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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk/sw/lib/source
    from Rev 47 to Rev 48
    ↔ Reverse comparison
  •

Rev 47 → Rev 48

/neorv32_cpu.c
60,9 → 60,8
**************************************************************************/
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel) {
 
if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) ||
(irq_sel == CSR_MIE_FIRQ0E) || (irq_sel == CSR_MIE_FIRQ1E) || (irq_sel == CSR_MIE_FIRQ2E) || (irq_sel == CSR_MIE_FIRQ3E) ||
(irq_sel == CSR_MIE_FIRQ4E) || (irq_sel == CSR_MIE_FIRQ5E) || (irq_sel == CSR_MIE_FIRQ6E) || (irq_sel == CSR_MIE_FIRQ7E)) {
if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) ||
((irq_sel >= CSR_MIE_FIRQ0E) && (irq_sel <= CSR_MIE_FIRQ15E))) {
return 0;
}
else {
/neorv32_rte.c
45,7 → 45,7
/**********************************************************************//**
* The >private< trap vector look-up table of the NEORV32 RTE.
**************************************************************************/
static uint32_t __neorv32_rte_vector_lut[21] __attribute__((unused)); // trap handler vector table
static uint32_t __neorv32_rte_vector_lut[29] __attribute__((unused)); // trap handler vector table
 
// private functions
static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused));
52,7 → 52,6
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
static void __neorv32_rte_print_hex_word(uint32_t num);
static int __neorv32_rte_check_exc_id(uint32_t id);
 
 
/**********************************************************************//**
94,7 → 93,7
int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) {
 
// id valid?
if (__neorv32_rte_check_exc_id(id) == 0) {
if ((id >= RTE_TRAP_I_MISALIGNED) && (id <= CSR_MIE_FIRQ15E)) {
__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler
return 0;
}
115,7 → 114,7
int neorv32_rte_exception_uninstall(uint8_t id) {
 
// id valid?
if (__neorv32_rte_check_exc_id(id) == 0) {
if ((id >= RTE_TRAP_I_MISALIGNED) && (id <= CSR_MIE_FIRQ15E)) {
__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered
return 0;
}
179,6 → 178,14
case TRAP_CODE_FIRQ_5: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_5]; break;
case TRAP_CODE_FIRQ_6: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_6]; break;
case TRAP_CODE_FIRQ_7: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_7]; break;
case TRAP_CODE_FIRQ_8: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_8]; break;
case TRAP_CODE_FIRQ_9: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_9]; break;
case TRAP_CODE_FIRQ_10: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_10]; break;
case TRAP_CODE_FIRQ_11: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_11]; break;
case TRAP_CODE_FIRQ_12: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_12]; break;
case TRAP_CODE_FIRQ_13: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break;
case TRAP_CODE_FIRQ_14: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break;
case TRAP_CODE_FIRQ_15: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break;
default: break;
}
 
195,11 → 202,20
**************************************************************************/
static void __neorv32_rte_debug_exc_handler(void) {
 
char tmp;
 
// intro
neorv32_uart_print("<RTE> ");
 
// cause
register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
tmp = (char)(trap_cause & 0xf);
if (tmp >= 10) {
tmp = 'a' + (tmp - 10);
}
else {
tmp = '0' + tmp;
}
switch (trap_cause) {
case TRAP_CODE_I_MISALIGNED: neorv32_uart_print("Instruction address misaligned"); break;
case TRAP_CODE_I_ACCESS: neorv32_uart_print("Instruction access fault"); break;
221,7 → 237,15
case TRAP_CODE_FIRQ_4:
case TRAP_CODE_FIRQ_5:
case TRAP_CODE_FIRQ_6:
case TRAP_CODE_FIRQ_7: neorv32_uart_print("Fast interrupt "); neorv32_uart_putc((char)('0' + (trap_cause & 0x7))); break;
case TRAP_CODE_FIRQ_7:
case TRAP_CODE_FIRQ_8:
case TRAP_CODE_FIRQ_9:
case TRAP_CODE_FIRQ_10:
case TRAP_CODE_FIRQ_11:
case TRAP_CODE_FIRQ_12:
case TRAP_CODE_FIRQ_13:
case TRAP_CODE_FIRQ_14:
case TRAP_CODE_FIRQ_15: neorv32_uart_print("Fast interrupt "); neorv32_uart_putc(tmp); break;
default: neorv32_uart_print("Unknown trap cause: "); __neorv32_rte_print_hex_word(trap_cause); break;
}
 
471,31 → 495,6
 
 
/**********************************************************************//**
* NEORV32 runtime environment: Private function to check exception id
* as 8-digit hexadecimal value (with "0x" suffix).
*
* @param[in] id Exception id (#NEORV32_RTE_TRAP_enum).
* @return Return 0 if id is valid
**************************************************************************/
static int __neorv32_rte_check_exc_id(uint32_t id) {
 
// id valid?
if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) ||
(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) || (id == RTE_TRAP_UENV_CALL) ||
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) ||
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3) ||
(id == RTE_TRAP_FIRQ_4) || (id == RTE_TRAP_FIRQ_5) || (id == RTE_TRAP_FIRQ_6) || (id == RTE_TRAP_FIRQ_7)) {
return 0;
}
else {
return 1;
}
}
 
 
 
/**********************************************************************//**
* NEORV32 runtime environment: Print the processor version in human-readable format.
**************************************************************************/
void neorv32_rte_print_hw_version(void) {
/neorv32_spi.c
67,9 → 67,8
* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
* @param[in] clk_polarity Idle clock polarity (0, 1).
* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
* @param[in] irq_en Enable transfer-done interrupt when 1.
**************************************************************************/
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size, uint8_t irq_en) {
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size) {
 
SPI_CT = 0; // reset
 
85,10 → 84,7
uint32_t ct_size = (uint32_t)(data_size & 0x03);
ct_size = ct_size << SPI_CT_SIZE0;
 
uint32_t ct_irq = (uint32_t)(irq_en & 0x01);
ct_irq = ct_irq << SPI_CT_IRQ_EN;
 
SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size | ct_irq;
SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size;
}
 
 
/neorv32_twi.c
65,10 → 65,9
* Enable and configure TWI controller. The TWI control register bits are listed in #NEORV32_TWI_CT_enum.
*
* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
* @param[in] irq_en Enable transfer-done interrupt when 1.
* @param[in] ckst_en Enable clock-stretching by peripherals when 1.
**************************************************************************/
void neorv32_twi_setup(uint8_t prsc, uint8_t irq_en, uint8_t ckst_en) {
void neorv32_twi_setup(uint8_t prsc, uint8_t ckst_en) {
 
TWI_CT = 0; // reset
 
78,13 → 77,10
uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
ct_prsc = ct_prsc << TWI_CT_PRSC0;
 
uint32_t ct_irq = (uint32_t)(irq_en & 0x01);
ct_irq = ct_irq << TWI_CT_IRQ_EN;
 
uint32_t ct_cksten = (uint32_t)(ckst_en & 0x01);
ct_cksten = ct_cksten << TWI_CT_CKSTEN;
 
TWI_CT = ct_enable | ct_prsc | ct_irq | ct_cksten;
TWI_CT = ct_enable | ct_prsc | ct_cksten;
}
 
 
93,7 → 89,7
**************************************************************************/
void neorv32_twi_disable(void) {
 
TWI_CT &= ~((uint32_t)(1 << TWI_CT_IRQ_EN));
TWI_CT &= ~((uint32_t)(1 << TWI_CT_EN));
}
 
 
/neorv32_uart.c
78,10 → 78,8
*
* @param[in] baudrate Targeted BAUD rate (e.g. 9600).
* @param[in] parity PArity configuration (00=off, 10=even, 11=odd).
* @param[in] rx_irq Enable RX interrupt (data received) when 1.
* @param[in] tx_irq Enable TX interrupt (transmission done) when 1.
**************************************************************************/
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity, uint8_t rx_irq, uint8_t tx_irq) {
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity) {
 
UART_CT = 0; // reset
 
123,12 → 121,6
uint32_t parity_config = (uint32_t)(parity & 3);
parity_config = parity_config << UART_CT_PMODE0;
 
uint32_t rx_irq_en = (uint32_t)(rx_irq & 1);
rx_irq_en = rx_irq_en << UART_CT_RX_IRQ;
 
uint32_t tx_irq_en = (uint32_t)(tx_irq & 1);
tx_irq_en = tx_irq_en << UART_CT_TX_IRQ;
 
/* Enable the UART for SIM mode. */
/* USE THIS ONLY FOR SIMULATION! */
#ifdef UART_SIM_MODE
138,7 → 130,7
uint32_t sim_mode = 0;
#endif
 
UART_CT = clk_prsc | baud_prsc | uart_en | parity_config | rx_irq_en | tx_irq_en | sim_mode;
UART_CT = clk_prsc | baud_prsc | uart_en | parity_config | sim_mode;
}
 
 

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