URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk/sw/lib/source
- from Rev 57 to Rev 58
- ↔ Reverse comparison
Rev 57 → Rev 58
/neorv32_cpu.c
331,6 → 331,11
**************************************************************************/ |
uint32_t neorv32_cpu_pmp_get_num_regions(void) { |
|
// PMP implemented at all? |
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_PMP)) == 0) { |
return 0; |
} |
|
uint32_t i = 0; |
|
// try setting R bit in all PMPCFG CSRs |
587,10 → 592,15
* |
* @warning This function overrides all available mhpmcounter* CSRs. |
* |
* @return Returns number of available HPM counters (..29). |
* @return Returns number of available HPM counters (0..29). |
**************************************************************************/ |
uint32_t neorv32_cpu_hpm_get_counters(void) { |
|
// HPMs implemented at all? |
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_HPM)) == 0) { |
return 0; |
} |
|
// inhibit all HPM counters |
uint32_t tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT); |
tmp |= 0xfffffff8; |
665,10 → 675,15
* |
* @warning This function overrides mhpmcounter3[h] CSRs. |
* |
* @return Size of HPM counter bits (1-64). |
* @return Size of HPM counter bits (1-64, 0 if not implemented at all). |
**************************************************************************/ |
uint32_t neorv32_cpu_hpm_get_size(void) { |
|
// HPMs implemented at all? |
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_HPM)) == 0) { |
return 0; |
} |
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// inhibt auto-update |
asm volatile ("csrwi %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTEREN_HPM3)); |
|
/neorv32_rte.c
45,7 → 45,7
/**********************************************************************//** |
* The >private< trap vector look-up table of the NEORV32 RTE. |
**************************************************************************/ |
static uint32_t __neorv32_rte_vector_lut[29] __attribute__((unused)); // trap handler vector table |
static uint32_t __neorv32_rte_vector_lut[NEORV32_RTE_NUM_TRAPS] __attribute__((unused)); // trap handler vector table |
|
// private functions |
static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused)); |
167,6 → 167,7
case TRAP_CODE_S_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break; |
case TRAP_CODE_UENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_UENV_CALL]; break; |
case TRAP_CODE_MENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break; |
case TRAP_CODE_NMI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_NMI]; break; |
case TRAP_CODE_MSI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break; |
case TRAP_CODE_MTI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break; |
case TRAP_CODE_MEI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break; |
273,9 → 274,9
|
// Processor - general stuff |
neorv32_uart_printf("\n=== << General >> ===\n"); |
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK); |
neorv32_uart_printf("User ID: 0x%x\n", SYSINFO_USER_CODE); |
neorv32_uart_printf("Dedicated HW reset: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_HW_RESET)); |
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK); |
neorv32_uart_printf("User ID: 0x%x\n", SYSINFO_USER_CODE); |
neorv32_uart_printf("Full HW reset: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_HW_RESET)); |
|
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// CPU configuration |
371,7 → 372,7
} |
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// check hardware performance monitors |
neorv32_uart_printf("HPM Counters: %ux, %u-bit wide\n", neorv32_cpu_hpm_get_counters(), neorv32_cpu_hpm_get_size()); |
neorv32_uart_printf("HPM Counters: %u counters, %u-bit wide\n", neorv32_cpu_hpm_get_counters(), neorv32_cpu_hpm_get_size()); |
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// Memory configuration |