URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/docs/figures/neorv32_overview.png
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+application/octet-stream
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Index: docs/figures/neorv32_processor.png
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Index: docs/NEORV32.pdf
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Index: docs/doxygen_makefile_sw
===================================================================
--- docs/doxygen_makefile_sw (revision 10)
+++ docs/doxygen_makefile_sw (revision 11)
@@ -38,7 +38,7 @@
# could be handy for archiving the generated documentation or if some version
# control system is used.
-PROJECT_NUMBER = 1.0
+PROJECT_NUMBER =
# Using the PROJECT_BRIEF tag one can provide an optional one line description
# for a project that appears at the top of each page and should give viewer a
/rtl/core/neorv32_application_image.vhd
1,5 → 1,5
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin> |
-- Auto-generated memory init file (for APPLICATION) from source file <cpu_test/main.bin> |
|
library ieee; |
use ieee.std_logic_1164.all; |
8,888 → 8,1146
|
type application_init_image_t is array (0 to 65535) of std_ulogic_vector(31 downto 0); |
constant application_init_image : application_init_image_t := ( |
00000000 => x"00000013", |
00000001 => x"00000093", |
00000002 => x"00008113", |
00000003 => x"00010193", |
00000004 => x"00018213", |
00000005 => x"00020293", |
00000006 => x"00028313", |
00000007 => x"00030393", |
00000008 => x"00038413", |
00000009 => x"00040493", |
00000010 => x"00048513", |
00000011 => x"00050593", |
00000012 => x"00058613", |
00000013 => x"00060693", |
00000014 => x"00068713", |
00000015 => x"00070793", |
00000016 => x"00078813", |
00000017 => x"00080893", |
00000018 => x"00088913", |
00000019 => x"00090993", |
00000020 => x"00098a13", |
00000021 => x"000a0a93", |
00000022 => x"000a8b13", |
00000023 => x"000b0b93", |
00000024 => x"000b8c13", |
00000025 => x"000c0c93", |
00000026 => x"000c8d13", |
00000027 => x"000d0d93", |
00000028 => x"000d8e13", |
00000029 => x"000e0e93", |
00000030 => x"000e8f13", |
00000031 => x"000f0f93", |
00000032 => x"00000013", |
00000033 => x"fc5025f3", |
00000034 => x"fc702673", |
00000035 => x"00c58133", |
00000036 => x"ffc10113", |
00000037 => x"00010413", |
00000038 => x"80000197", |
00000039 => x"7e818193", |
00000040 => x"00000597", |
00000041 => x"0b458593", |
00000042 => x"30559073", |
00000043 => x"fc5025f3", |
00000044 => x"00000617", |
00000045 => x"1f060613", |
00000046 => x"02000693", |
00000047 => x"00c5a023", |
00000048 => x"00458593", |
00000049 => x"fff68693", |
00000050 => x"fed01ae3", |
00000051 => x"f8000593", |
00000052 => x"0005a023", |
00000053 => x"00458593", |
00000054 => x"feb01ce3", |
00000055 => x"fff00593", |
00000056 => x"f8b02c23", |
00000057 => x"f8b02e23", |
00000058 => x"80000597", |
00000059 => x"f9858593", |
00000060 => x"80000617", |
00000061 => x"f9060613", |
00000062 => x"00c5d863", |
00000063 => x"00058023", |
00000064 => x"00158593", |
00000065 => x"ff5ff06f", |
00000066 => x"00001597", |
00000067 => x"cc058593", |
00000068 => x"80000617", |
00000069 => x"f7060613", |
00000070 => x"80000697", |
00000071 => x"f6868693", |
00000072 => x"00d65c63", |
00000073 => x"00058703", |
00000074 => x"00e60023", |
00000075 => x"00158593", |
00000076 => x"00160613", |
00000077 => x"fedff06f", |
00000078 => x"00000513", |
00000079 => x"00000593", |
00000080 => x"164000ef", |
00000081 => x"10500073", |
00000082 => x"30047073", |
00000083 => x"10500073", |
00000084 => x"0000006f", |
00000085 => x"f8810113", |
00000086 => x"00112023", |
00000087 => x"00312223", |
00000088 => x"00412423", |
00000089 => x"00512623", |
00000090 => x"00612823", |
00000091 => x"00712a23", |
00000092 => x"00812c23", |
00000093 => x"00912e23", |
00000094 => x"02a12023", |
00000095 => x"02b12223", |
00000096 => x"02c12423", |
00000097 => x"02d12623", |
00000098 => x"02e12823", |
00000099 => x"02f12a23", |
00000100 => x"03012c23", |
00000101 => x"03112e23", |
00000102 => x"05212023", |
00000103 => x"05312223", |
00000104 => x"05412423", |
00000105 => x"05512623", |
00000106 => x"05612823", |
00000107 => x"05712a23", |
00000108 => x"05812c23", |
00000109 => x"05912e23", |
00000110 => x"07a12023", |
00000111 => x"07b12223", |
00000112 => x"07c12423", |
00000113 => x"07d12623", |
00000114 => x"07e12823", |
00000115 => x"07f12a23", |
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00000117 => x"00f2f313", |
00000118 => x"00231313", |
00000119 => x"fc5020f3", |
00000120 => x"00130333", |
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00000122 => x"0002cc63", |
00000123 => x"34a022f3", |
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00000142 => x"01812403", |
00000143 => x"01c12483", |
00000144 => x"02012503", |
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00000146 => x"02812603", |
00000147 => x"02c12683", |
00000148 => x"03012703", |
00000149 => x"03412783", |
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00000152 => x"04012903", |
00000153 => x"04412983", |
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00000161 => x"06412d83", |
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00001139 => x"00008067", |
others => x"00000000" |
); |
|
/rtl/core/neorv32_bootloader_image.vhd
41,982 → 41,988
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00000757 => x"01e61613", |
00000758 => x"00c7e7b3", |
00000759 => x"01d59593", |
00000760 => x"00b7e7b3", |
00000761 => x"00e7e7b3", |
00000762 => x"10000737", |
00000763 => x"00e7e7b3", |
00000764 => x"faf02023", |
00000765 => x"00008067", |
00000766 => x"00170793", |
00000767 => x"01079713", |
00000768 => x"40a686b3", |
00000769 => x"01075713", |
00000770 => x"fadff06f", |
00000771 => x"ffe78513", |
00000772 => x"0fd57513", |
00000773 => x"00051a63", |
00000774 => x"00375713", |
00000775 => x"00178793", |
00000776 => x"0ff7f793", |
00000777 => x"fa1ff06f", |
00000778 => x"00175713", |
00000779 => x"ff1ff06f", |
00000780 => x"fa002783", |
00000781 => x"fe07cee3", |
00000782 => x"faa02223", |
00000783 => x"00008067", |
00000784 => x"fa402503", |
00000785 => x"fe055ee3", |
00000786 => x"0ff57513", |
00000787 => x"00008067", |
00000788 => x"ff010113", |
00000789 => x"00812423", |
00000790 => x"01212023", |
00000791 => x"00112623", |
00000792 => x"00912223", |
00000793 => x"00050413", |
00000794 => x"00a00913", |
00000795 => x"00044483", |
00000796 => x"00140413", |
00000797 => x"00049e63", |
00000798 => x"00c12083", |
00000799 => x"00812403", |
00000800 => x"00412483", |
00000801 => x"00012903", |
00000802 => x"01010113", |
00000803 => x"00008067", |
00000804 => x"01249663", |
00000805 => x"00d00513", |
00000806 => x"f99ff0ef", |
00000807 => x"00048513", |
00000808 => x"f91ff0ef", |
00000809 => x"fc9ff06f", |
00000810 => x"00757513", |
00000811 => x"00177793", |
00000812 => x"01079793", |
00000813 => x"0036f693", |
00000814 => x"00a51513", |
00000815 => x"00f56533", |
00000816 => x"00167613", |
00000817 => x"00e69793", |
00000818 => x"0015f593", |
00000819 => x"00f567b3", |
00000820 => x"00d61613", |
00000821 => x"00c7e7b3", |
00000822 => x"00959593", |
00000823 => x"fa800813", |
00000824 => x"00b7e7b3", |
00000825 => x"00082023", |
00000826 => x"1007e793", |
00000827 => x"00f82023", |
00000828 => x"00008067", |
00000829 => x"fa800713", |
00000830 => x"00072783", |
00000831 => x"eff7f793", |
00000832 => x"00f72023", |
00000833 => x"00008067", |
00000834 => x"fa800713", |
00000835 => x"00072683", |
00000836 => x"00757793", |
00000837 => x"00100513", |
00000838 => x"00f51533", |
00000839 => x"00d56533", |
00000840 => x"00a72023", |
00000841 => x"00008067", |
00000842 => x"fa800713", |
00000843 => x"00072683", |
00000844 => x"00757513", |
00000845 => x"00100793", |
00000846 => x"00a797b3", |
00000847 => x"fff7c793", |
00000848 => x"00d7f7b3", |
00000849 => x"00f72023", |
00000850 => x"00008067", |
00000851 => x"faa02623", |
00000852 => x"fa802783", |
00000853 => x"fe07cee3", |
00000854 => x"fac02503", |
00000855 => x"00008067", |
00000856 => x"f8400713", |
00000857 => x"00072683", |
00000858 => x"00f57793", |
00000859 => x"00100513", |
00000860 => x"00f51533", |
00000861 => x"00d54533", |
00000862 => x"00a72023", |
00000863 => x"00008067", |
00000864 => x"f8a02223", |
00000865 => x"00008067", |
00000866 => x"fb800713", |
00000867 => x"00072783", |
00000868 => x"ffe7f793", |
00000869 => x"00f72023", |
00000870 => x"00008067", |
00000871 => x"fb000713", |
00000872 => x"00072783", |
00000873 => x"ff77f793", |
00000874 => x"00f72023", |
00000875 => x"00008067", |
00000876 => x"f8800713", |
00000877 => x"00072783", |
00000878 => x"fef7f793", |
00000879 => x"00f72023", |
00000880 => x"00008067", |
00000881 => x"69617641", |
00000882 => x"6c62616c", |
00000883 => x"4d432065", |
00000884 => x"0a3a7344", |
00000885 => x"203a6820", |
00000886 => x"706c6548", |
00000887 => x"3a72200a", |
00000888 => x"73655220", |
00000889 => x"74726174", |
00000890 => x"3a75200a", |
00000891 => x"6c705520", |
00000892 => x"0a64616f", |
00000893 => x"203a7320", |
00000894 => x"726f7453", |
00000895 => x"6f742065", |
00000896 => x"616c6620", |
00000897 => x"200a6873", |
00000898 => x"4c203a6c", |
00000899 => x"2064616f", |
00000900 => x"6d6f7266", |
00000901 => x"616c6620", |
00000902 => x"200a6873", |
00000903 => x"45203a65", |
00000904 => x"75636578", |
00000905 => x"00006574", |
00000906 => x"65206f4e", |
00000907 => x"75636578", |
00000908 => x"6c626174", |
00000909 => x"76612065", |
00000910 => x"616c6961", |
00000911 => x"2e656c62", |
00000912 => x"00000000", |
00000913 => x"746f6f42", |
00000914 => x"2e676e69", |
00000915 => x"0a0a2e2e", |
00000916 => x"00000000", |
00000917 => x"52450a07", |
00000918 => x"00005f52", |
00000919 => x"6e6b6e75", |
00000920 => x"006e776f", |
00000921 => x"00007830", |
00000922 => x"58450a0a", |
00000923 => x"54504543", |
00000924 => x"3a4e4f49", |
00000925 => x"00000020", |
00000926 => x"30204020", |
00000927 => x"00000078", |
00000928 => x"69617741", |
00000929 => x"676e6974", |
00000930 => x"6f656e20", |
00000931 => x"32337672", |
00000932 => x"6578655f", |
00000933 => x"6e69622e", |
00000934 => x"202e2e2e", |
00000935 => x"00000000", |
00000936 => x"64616f4c", |
00000937 => x"2e676e69", |
00000938 => x"00202e2e", |
00000939 => x"00004b4f", |
00000940 => x"74697257", |
00000941 => x"78302065", |
00000942 => x"00000000", |
00000943 => x"74796220", |
00000944 => x"74207365", |
00000945 => x"5053206f", |
00000946 => x"6c662049", |
00000947 => x"20687361", |
00000948 => x"78302040", |
00000949 => x"00000000", |
00000950 => x"7928203f", |
00000951 => x"20296e2f", |
00000952 => x"00000000", |
00000953 => x"616c460a", |
00000954 => x"6e696873", |
00000955 => x"2e2e2e67", |
00000956 => x"00000020", |
00000957 => x"0a0a0a0a", |
00000958 => x"4e203c3c", |
00000959 => x"56524f45", |
00000960 => x"42203233", |
00000961 => x"6c746f6f", |
00000962 => x"6564616f", |
00000963 => x"3e3e2072", |
00000964 => x"4c420a0a", |
00000965 => x"203a5644", |
00000966 => x"206c754a", |
00000967 => x"32203920", |
00000968 => x"0a303230", |
00000969 => x"3a565748", |
00000970 => x"00002020", |
00000971 => x"4b4c430a", |
00000972 => x"0020203a", |
00000973 => x"0a7a4820", |
00000974 => x"4449484d", |
00000975 => x"0000203a", |
00000976 => x"53494d0a", |
00000977 => x"00203a41", |
00000978 => x"4e4f430a", |
00000979 => x"00203a46", |
00000980 => x"454d490a", |
00000981 => x"00203a4d", |
00000982 => x"74796220", |
00000983 => x"40207365", |
00000984 => x"00000020", |
00000985 => x"454d440a", |
00000986 => x"00203a4d", |
00000987 => x"75410a0a", |
00000988 => x"6f626f74", |
00000989 => x"6920746f", |
00000990 => x"7338206e", |
00000991 => x"7250202e", |
00000992 => x"20737365", |
00000993 => x"2079656b", |
00000994 => x"61206f74", |
00000995 => x"74726f62", |
00000996 => x"00000a2e", |
00000997 => x"0000000a", |
00000998 => x"726f6241", |
00000999 => x"2e646574", |
00001000 => x"00000a0a", |
00001001 => x"444d430a", |
00001002 => x"00203e3a", |
00001003 => x"53207962", |
00001004 => x"68706574", |
00001005 => x"4e206e61", |
00001006 => x"69746c6f", |
00001007 => x"0000676e", |
00001008 => x"61766e49", |
00001009 => x"2064696c", |
00001010 => x"00444d43", |
00001011 => x"33323130", |
00001012 => x"37363534", |
00001013 => x"42413938", |
00001014 => x"46454443", |
others => x"00000000" |
); |
|
/rtl/core/neorv32_cpu.vhd
88,20 → 88,23
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic; -- bus transfer error |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic; -- bus transfer error |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- external interrupts -- |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
); |
end neorv32_cpu; |
|
126,7 → 129,6
signal be_instr : std_ulogic; -- bus error on instruction access |
signal be_load : std_ulogic; -- bus error on load data access |
signal be_store : std_ulogic; -- bus error on store data access |
signal bus_exc_ack : std_ulogic; -- bus exception error acknowledge |
signal bus_busy : std_ulogic; -- bus unit is busy |
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch |
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction) |
201,6 → 203,8
-- external interrupt -- |
clic_irq_i => clic_irq_i, -- CLIC interrupt request |
mtime_irq_i => mtime_irq_i, -- machine timer interrupt |
-- system time input from MTIME -- |
time_i => time_i, -- current system time |
-- bus access exceptions -- |
mar_i => mar, -- memory address register |
ma_instr_i => ma_instr, -- misaligned instruction address |
209,7 → 213,6
be_instr_i => be_instr, -- bus error on instruction access |
be_load_i => be_load, -- bus error on load data access |
be_store_i => be_store, -- bus error on store data access |
bus_exc_ack_o => bus_exc_ack, -- bus exception error acknowledge |
bus_busy_i => bus_busy -- bus unit is busy |
); |
|
238,6 → 241,9
-- ALU ------------------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
neorv32_cpu_alu_inst: neorv32_cpu_alu |
generic map ( |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M -- implement muld/div extension? |
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
299,40 → 305,41
-- ------------------------------------------------------------------------------------------- |
neorv32_cpu_bus_inst: neorv32_cpu_bus |
generic map ( |
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout |
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
-- data input -- |
wdata_i => rs2, -- write data |
pc_i => fetch_pc, -- current PC for instruction fetch |
alu_i => alu_res, -- ALU result |
wdata_i => rs2, -- write data |
pc_i => fetch_pc, -- current PC for instruction fetch |
alu_i => alu_res, -- ALU result |
-- data output -- |
instr_o => instr, -- instruction |
rdata_o => rdata, -- read data |
instr_o => instr, -- instruction |
rdata_o => rdata, -- read data |
-- status -- |
mar_o => mar, -- current memory address register |
ma_instr_o => ma_instr, -- misaligned instruction address |
ma_load_o => ma_load, -- misaligned load data address |
ma_store_o => ma_store, -- misaligned store data address |
be_instr_o => be_instr, -- bus error on instruction access |
be_load_o => be_load, -- bus error on load data access |
be_store_o => be_store, -- bus error on store data access |
bus_wait_o => bus_wait, -- wait for bus operation to finish |
bus_busy_o => bus_busy, -- bus unit is busy |
exc_ack_i => bus_exc_ack, -- exception controller ACK |
mar_o => mar, -- current memory address register |
ma_instr_o => ma_instr, -- misaligned instruction address |
ma_load_o => ma_load, -- misaligned load data address |
ma_store_o => ma_store, -- misaligned store data address |
be_instr_o => be_instr, -- bus error on instruction access |
be_load_o => be_load, -- bus error on load data access |
be_store_o => be_store, -- bus error on store data access |
bus_wait_o => bus_wait, -- wait for bus operation to finish |
bus_busy_o => bus_busy, -- bus unit is busy |
-- bus system -- |
bus_addr_o => bus_addr_o, -- bus access address |
bus_rdata_i => bus_rdata_i, -- bus read data |
bus_wdata_o => bus_wdata_o, -- bus write data |
bus_ben_o => bus_ben_o, -- byte enable |
bus_we_o => bus_we_o, -- write enable |
bus_re_o => bus_re_o, -- read enable |
bus_ack_i => bus_ack_i, -- bus transfer acknowledge |
bus_err_i => bus_err_i -- bus transfer error |
bus_addr_o => bus_addr_o, -- bus access address |
bus_rdata_i => bus_rdata_i, -- bus read data |
bus_wdata_o => bus_wdata_o, -- bus write data |
bus_ben_o => bus_ben_o, -- byte enable |
bus_we_o => bus_we_o, -- write enable |
bus_re_o => bus_re_o, -- read enable |
bus_cancel_o => bus_cancel_o, -- cancel current bus transaction |
bus_ack_i => bus_ack_i, -- bus transfer acknowledge |
bus_err_i => bus_err_i -- bus transfer error |
); |
|
|
/rtl/core/neorv32_cpu_alu.vhd
42,6 → 42,9
use neorv32.neorv32_package.all; |
|
entity neorv32_cpu_alu is |
generic ( |
CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension? |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
200,7 → 203,7
cp_rb_ff0 <= '0'; |
cp_rb_ff1 <= '0'; |
elsif rising_edge(clk_i) then |
if (ctrl_i(ctrl_sys_m_ext_en_c) = '1') then -- FIXME add second cp (floating point stuff?) |
if (CPU_EXTENSION_RISCV_M = true) then -- FIXME add second cp (floating point stuff?) |
cp_cmd_ff <= ctrl_i(ctrl_cp_use_c); |
cp_rb_ff0 <= '0'; |
cp_rb_ff1 <= cp_rb_ff0; |
/rtl/core/neorv32_cpu_bus.vhd
43,40 → 43,41
|
entity neorv32_cpu_bus is |
generic ( |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- data input -- |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC |
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC |
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
-- data output -- |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
-- status -- |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data access |
bus_wait_o : out std_ulogic; -- wait for bus operation to finish |
bus_busy_o : out std_ulogic; -- bus unit is busy |
exc_ack_i : in std_ulogic; -- exception controller ACK |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data access |
bus_wait_o : out std_ulogic; -- wait for bus operation to finish |
bus_busy_o : out std_ulogic; -- bus unit is busy |
-- bus system -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
); |
end neorv32_cpu_bus; |
|
103,9 → 104,7
-- ------------------------------------------------------------------------------------------- |
mem_adr_reg: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
mar <= (others => '0'); |
elsif rising_edge(clk_i) then |
if rising_edge(clk_i) then |
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then |
mar <= alu_i; |
end if; |
113,7 → 112,7
end process mem_adr_reg; |
|
-- address output -- |
bus_addr_o <= pc_i when ((bus_if_req or ctrl_i(ctrl_bus_if_c)) = '1') else mar; -- is instruction fetch? |
bus_addr_o <= pc_i when ((bus_if_req or ctrl_i(ctrl_bus_if_c)) = '1') else mar; -- is instruction fetch? keep output at PC as long as IF request is active |
mar_o <= mar; |
|
-- write request output -- |
120,7 → 119,7
bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not misaligned_data); |
|
-- read request output (also used for instruction fetch) -- |
bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or ((bus_if_req or ctrl_i(ctrl_bus_if_c)) and (not misaligned_instr)); |
bus_re_o <= (ctrl_i(ctrl_bus_rd_c) and (not misaligned_data)) or (ctrl_i(ctrl_bus_if_c) and (not misaligned_instr)); -- FIXME i_reg and misaligned |
|
|
-- Write Data ----------------------------------------------------------------------------- |
223,7 → 222,7
align_err <= '0'; |
bus_timeout <= (others => '0'); |
elsif rising_edge(clk_i) then |
if (bus_busy = '0') then -- wait for new request |
if (bus_busy = '0') or (ctrl_i(ctrl_bus_reset_c) = '1') then -- wait for new request or reset |
bus_busy <= ctrl_i(ctrl_bus_if_c) or ctrl_i(ctrl_bus_rd_c) or ctrl_i(ctrl_bus_wr_c); -- any request at all? |
bus_if_req <= ctrl_i(ctrl_bus_if_c); -- instruction fetch |
bus_rd_req <= ctrl_i(ctrl_bus_rd_c); -- store access |
233,10 → 232,10
align_err <= '0'; |
else -- bus transfer in progress |
bus_timeout <= std_ulogic_vector(unsigned(bus_timeout) - 1); |
align_err <= (align_err or misaligned_data or misaligned_instr) and (not exc_ack_i); |
access_err <= (access_err or (not or_all_f(bus_timeout)) or bus_err_i) and (not exc_ack_i); |
align_err <= (align_err or misaligned_data or misaligned_instr) and (not ctrl_i(ctrl_bus_exc_ack_c)); |
access_err <= (access_err or (not or_all_f(bus_timeout)) or bus_err_i) and (not ctrl_i(ctrl_bus_exc_ack_c)); |
if (align_err = '1') or (access_err = '1') then |
if (exc_ack_i = '1') then -- wait for controller to ack exception |
if (ctrl_i(ctrl_bus_exc_ack_c) = '1') then -- wait for controller to ack exception |
bus_if_req <= '0'; |
bus_rd_req <= '0'; |
bus_wr_req <= '0'; |
262,6 → 261,9
ma_load_o <= bus_rd_req and align_err; |
ma_store_o <= bus_wr_req and align_err; |
|
-- terminate bus access -- |
bus_cancel_o <= (bus_busy and (align_err or access_err)) or ctrl_i(ctrl_bus_reset_c); |
|
-- wait for bus -- |
bus_busy_o <= bus_busy; |
bus_wait_o <= bus_busy and (not bus_ack_i); -- FIXME: 'async' ack |
291,10 → 293,10
begin |
-- check instruction access -- |
misaligned_instr <= '0'; -- default |
if (ctrl_i(ctrl_sys_c_ext_en_c) = '1') then -- 16-bit and 32-bit instruction accesses |
misaligned_instr <= '0'; |
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses |
misaligned_instr <= '0'; -- no alignment exceptions possible |
else -- 32-bit instruction accesses only |
if (pc_i(1 downto 0) /= "00") then |
if (pc_i(1) = '1') then -- PC(0) is always zero |
misaligned_instr <= '1'; |
end if; |
end if; |
/rtl/core/neorv32_cpu_control.vhd
104,6 → 104,8
-- external interrupt -- |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- bus access exceptions -- |
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register |
ma_instr_i : in std_ulogic; -- misaligned instruction address |
112,7 → 114,6
be_instr_i : in std_ulogic; -- bus error on instruction access |
be_load_i : in std_ulogic; -- bus error on load data access |
be_store_i : in std_ulogic; -- bus error on store data access |
bus_exc_ack_o : out std_ulogic; -- bus exception error acknowledge |
bus_busy_i : in std_ulogic -- bus unit is busy |
); |
end neorv32_cpu_control; |
140,6 → 141,7
ci_return_nxt : std_ulogic; |
reset : std_ulogic; |
bus_err_ack : std_ulogic; |
bus_reset : std_ulogic; |
end record; |
signal fetch_engine : fetch_engine_t; |
|
179,6 → 181,8
pc_nxt : std_ulogic_vector(data_width_c-1 downto 0); |
next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed |
last_pc : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction |
sleep : std_ulogic; -- CPU in sleep mode |
sleep_nxt : std_ulogic; -- CPU in sleep mode |
end record; |
signal execute_engine : execute_engine_t; |
|
212,8 → 216,6
|
-- fast bus access -- |
signal bus_fast_ir : std_ulogic; |
signal bus_fast_rd : std_ulogic; |
signal bus_fast_wr : std_ulogic; |
|
-- RISC-V control and status registers (CSRs) -- |
type csr_t is record |
228,21 → 230,19
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W) |
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W) |
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W) |
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/-) |
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W) |
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W) |
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/-) |
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W) |
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W) |
cycle : std_ulogic_vector(32 downto 0); -- cycle, mtime (R/-), plus carry bit |
instret : std_ulogic_vector(32 downto 0); -- instret (R/-), plus carry bit |
cycleh : std_ulogic_vector(31 downto 0); -- cycleh, mtimeh (R/-) |
instreth : std_ulogic_vector(31 downto 0); -- instreth (R/-) |
misa_c_en : std_ulogic; -- misa: C extension enable bit (R/W) |
misa_m_en : std_ulogic; -- misa: M extension enable bit (R/W) |
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit |
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit |
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W) |
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W) |
end record; |
signal csr : csr_t; |
|
signal cycle_msb : std_ulogic; |
signal instret_msb : std_ulogic; |
signal mcycle_msb : std_ulogic; |
signal minstret_msb : std_ulogic; |
|
-- illegal instruction check -- |
signal illegal_instruction : std_ulogic; |
330,6 → 330,7
fetch_engine.ci_reg_nxt <= fetch_engine.ci_reg; |
fetch_engine.ci_return_nxt <= fetch_engine.ci_return; |
fetch_engine.bus_err_ack <= '0'; |
fetch_engine.bus_reset <= '0'; |
|
-- instruction prefetch buffer interface -- |
ipb.we <= '0'; |
340,12 → 341,12
-- state machine -- |
case fetch_engine.state is |
|
when IFETCH_RESET => -- reset engine, prefetch buffer, get PC |
when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC |
-- ------------------------------------------------------------ |
fetch_engine.i_buf_state_nxt <= (others => '0'); |
fetch_engine.ci_return_nxt <= '0'; |
fetch_engine.bus_reset <= '1'; -- reset bus unit |
ipb.clear <= '1'; -- clear instruction prefetch buffer |
fetch_engine.bus_err_ack <= '1'; -- ack bus errors, the execute engine has to take care of them |
fetch_engine.state_nxt <= IFETCH_0; |
|
when IFETCH_0 => -- output current PC to bus system, request 32-bit word |
364,7 → 365,7
fetch_engine.i_buf_state_nxt(1) <= fetch_engine.i_buf_state(0); |
fetch_engine.state_nxt <= IFETCH_2; |
end if; |
|
|
fetch_engine.i_buf_state_nxt(0) <= '1'; |
if (be_instr_i = '1') or (ma_instr_i = '1') then -- any fetch exception? |
fetch_engine.bus_err_ack <= '1'; -- ack bus errors, the execute engine has to take care of them |
373,11 → 374,11
when IFETCH_2 => -- construct instruction and issue |
-- ------------------------------------------------------------ |
if (fetch_engine.i_buf_state(1) = '1') then |
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) or (csr.misa_c_en = '0') then -- 32-bit aligned |
if (fetch_engine.pc_fetch(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned |
fetch_engine.ci_reg_nxt <= fetch_engine.i_buf2(33 downto 32) & fetch_engine.i_buf2(15 downto 00); |
ipb.wdata <= fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0); |
|
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) or (csr.misa_c_en = '0') then -- uncompressed |
if (fetch_engine.i_buf2(01 downto 00) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed |
if (ipb.free = '1') then -- free entry in buffer? |
ipb.we <= '1'; |
fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c)); |
548,6 → 549,8
end if; |
execute_engine.state <= SYS_WAIT; |
execute_engine.state_prev <= SYS_WAIT; |
-- |
execute_engine.sleep <= '0'; |
elsif rising_edge(clk_i) then |
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0'; |
if (execute_engine.state = EXECUTE) then |
555,6 → 558,8
end if; |
execute_engine.state <= execute_engine.state_nxt; |
execute_engine.state_prev <= execute_engine.state; |
-- |
execute_engine.sleep <= execute_engine.sleep_nxt; |
end if; |
end process execute_engine_fsm_sync_rst; |
|
582,7 → 587,7
|
-- CPU Control Bus Output ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ctrl_output: process(ctrl, execute_engine, csr, bus_fast_ir, bus_fast_rd, bus_fast_wr) |
ctrl_output: process(ctrl, execute_engine, fetch_engine, trap_ctrl, csr, bus_fast_ir) |
begin |
ctrl_o <= ctrl; |
-- direct output of register addresses -- |
591,11 → 596,9
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c); |
-- bus access requests -- |
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir; |
ctrl_o(ctrl_bus_rd_c) <= ctrl(ctrl_bus_rd_c) or bus_fast_rd; |
ctrl_o(ctrl_bus_wr_c) <= ctrl(ctrl_bus_wr_c) or bus_fast_wr; |
-- cpu extension control -- |
ctrl_o(ctrl_sys_c_ext_en_c) <= csr.misa_c_en; -- C extension enabled |
ctrl_o(ctrl_sys_m_ext_en_c) <= csr.misa_m_en; -- M extension enabled |
-- bus control -- |
ctrl_o(ctrl_bus_exc_ack_c) <= trap_ctrl.env_start_ack or fetch_engine.bus_err_ack; |
ctrl_o(ctrl_bus_reset_c) <= fetch_engine.bus_reset; |
end process ctrl_output; |
|
|
614,6 → 617,7
execute_engine.is_jump_nxt <= '0'; |
execute_engine.is_ci_nxt <= execute_engine.is_ci; |
execute_engine.pc_nxt <= execute_engine.pc(data_width_c-1 downto 1) & '0'; |
execute_engine.sleep_nxt <= execute_engine.sleep; |
|
-- instruction dispatch -- |
fetch_engine.reset <= '0'; |
623,10 → 627,6
trap_ctrl.env_start_ack <= '0'; |
trap_ctrl.env_end <= '0'; |
|
-- bus access (fast) -- |
bus_fast_rd <= '0'; |
bus_fast_wr <= '0'; |
|
-- exception trigger -- |
trap_ctrl.instr_be <= '0'; |
trap_ctrl.instr_ma <= '0'; |
708,16 → 708,21
execute_engine.is_ci_nxt <= ipb.rdata(32); -- flag to indicate this is a compressed instruction beeing executed |
execute_engine.i_reg_nxt <= ipb.rdata(31 downto 0); |
execute_engine.pc_nxt <= ipb.raddr(data_width_c-1 downto 1) & '0'; -- the PC according to the current instruction |
execute_engine.state_nxt <= EXECUTE; |
if (execute_engine.sleep = '1') then |
execute_engine.state_nxt <= TRAP; |
else |
execute_engine.state_nxt <= EXECUTE; |
end if; |
end if; |
end if; |
|
when TRAP => -- Start trap environment (also used as sleep state) |
when TRAP => -- Start trap environment (also used as cpu sleep state) |
-- ------------------------------------------------------------ |
fetch_engine.reset <= '1'; |
if (trap_ctrl.env_start = '1') then |
trap_ctrl.env_start_ack <= '1'; |
execute_engine.sleep_nxt <= '0'; -- waky waky |
execute_engine.pc_nxt <= csr.mtvec(data_width_c-1 downto 1) & '0'; |
fetch_engine.reset <= '1'; |
execute_engine.state_nxt <= SYS_WAIT; |
end if; |
|
732,18 → 737,23
ctrl_nxt(ctrl_alu_opc_mux_c) <= not alu_immediate_v; |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result |
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and |
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV? |
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- muldiv CP |
-- multi cycle alu operation? -- |
if (alu_operation_v = alu_cmd_shift_c) or -- shift operation |
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and |
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001")) then -- MULDIV? |
execute_engine.state_nxt <= ALU_WAIT; |
elsif (alu_operation_v = alu_cmd_shift_c) then -- multi-cycle shift operation? |
execute_engine.state_nxt <= ALU_WAIT; |
else |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
execute_engine.state_nxt <= DISPATCH; |
end if; |
-- cp access? -- |
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and |
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV? |
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- muldiv CP |
end if; |
|
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC) |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 |
817,22 → 827,20
-- |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system |
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is |
when x"000" => -- ECALL |
when funct12_ecall_c => -- ECALL |
trap_ctrl.env_call <= '1'; |
execute_engine.state_nxt <= SYS_WAIT; |
when x"001" => -- EBREAK |
when funct12_ebreak_c => -- EBREAK |
trap_ctrl.break_point <= '1'; |
execute_engine.state_nxt <= SYS_WAIT; |
when x"302" => -- MRET |
trap_ctrl.env_end <= '1'; |
execute_engine.pc_nxt <= csr.mepc(data_width_c-1 downto 1) & '0'; |
fetch_engine.reset <= '1'; |
execute_engine.state_nxt <= SYS_WAIT; |
when x"105" => -- WFI |
execute_engine.state_nxt <= TRAP; |
when funct12_mret_c => -- MRET |
trap_ctrl.env_end <= '1'; |
execute_engine.pc_nxt <= csr.mepc(data_width_c-1 downto 1) & '0'; |
fetch_engine.reset <= '1'; |
when funct12_wfi_c => -- WFI = "CPU sleep" |
execute_engine.sleep_nxt <= '1'; -- good night |
when others => -- undefined |
NULL; |
end case; |
execute_engine.state_nxt <= SYS_WAIT; |
elsif (CPU_EXTENSION_RISCV_Zicsr = true) then -- CSR access |
execute_engine.state_nxt <= CSR_ACCESS; |
else |
892,7 → 900,7
-- RF write back -- |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output register |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in |
execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in |
|
when ALU_WAIT => -- wait for multi-cycle ALU operation to finish |
-- ------------------------------------------------------------ |
906,19 → 914,21
when BRANCH => -- update PC for taken branches and jumps |
-- ------------------------------------------------------------ |
if (execute_engine.is_jump = '1') or (execute_engine.branch_taken = '1') then |
execute_engine.pc_nxt <= alu_add_i(data_width_c-1 downto 1) & '0'; |
fetch_engine.reset <= '1'; |
execute_engine.pc_nxt <= alu_add_i(data_width_c-1 downto 1) & '0'; -- branch/jump destination |
fetch_engine.reset <= '1'; |
execute_engine.state_nxt <= SYS_WAIT; |
else |
execute_engine.state_nxt <= DISPATCH; |
end if; |
execute_engine.state_nxt <= SYS_WAIT; |
|
when LOAD => -- trigger memory read request |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_rd_c) <= '1';--bus_fast_rd <= '1'; -- fast read request |
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- fast read request |
execute_engine.state_nxt <= LOADSTORE_0; |
|
when STORE => -- trigger memory write request |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_wr_c) <= '1';--bus_fast_wr <= '1'; -- fast write request |
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- fast write request |
execute_engine.state_nxt <= LOADSTORE_0; |
|
when LOADSTORE_0 => -- memory latency |
951,6 → 961,8
-- ------------------------------------------------------------------------------------------- |
illegal_instruction_check: process(execute_engine, csr, ctrl_nxt, ci_illegal) |
begin |
-- illegal instructions are checked in the EXECUTE stage |
-- the execute engine will only commit valid instructions |
if (execute_engine.state = EXECUTE) then |
-- defaults -- |
illegal_instruction <= '0'; |
1023,7 → 1035,7
|
when opcode_alu_c => -- check ALU funct3 & funct7 |
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV |
if (CPU_EXTENSION_RISCV_M = false) or (csr.misa_m_en = '0') then -- not implemented or disabled |
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented |
illegal_instruction <= '1'; |
end if; |
elsif ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or |
1064,10 → 1076,10
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"344") or -- mip |
-- |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycle |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- time |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c01") and (IO_MTIME_USE = true)) or -- time |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c02") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instret |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c80") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- cycleh |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- timeh |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c81") and (IO_MTIME_USE = true)) or -- timeh |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"c82") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- instreth |
-- |
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = x"b00") and (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true)) or -- mcycle |
1092,10 → 1104,10
-- ecall, ebreak, mret, wfi -- |
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and |
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then |
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = "000000000000") or -- ECALL |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = "000000000001") or -- EBREAK |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = "001100000010") or -- MRET |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = "000100000101") then -- WFI |
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) or -- MRET |
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) then -- WFI |
illegal_instruction <= '0'; |
else |
illegal_instruction <= '1'; |
1108,7 → 1120,7
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode |
illegal_instruction <= '1'; |
else -- compressed instruction: illegal or disabled / not implemented |
illegal_compressed <= ci_illegal or (not csr.misa_c_en); |
illegal_compressed <= ci_illegal; |
end if; |
|
end case; |
1161,8 → 1173,8
|
-- trap control -- |
if (trap_ctrl.env_start = '0') then -- no started trap handler |
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and |
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- exception/IRQ detected! |
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected! |
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only |
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program |
trap_ctrl.exc_src <= trap_ctrl.exc_buf; -- capture exception source for hardware |
trap_ctrl.exc_ack <= '1'; -- clear execption |
1184,13 → 1196,7
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- classic exceptions (faults/traps) cannot be masked |
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- classic interrupts can be enabled/disabled |
|
-- exception acknowledge for bus unit -- |
bus_exc_ack_o <= trap_ctrl.env_start_ack or fetch_engine.bus_err_ack; |
|
-- exception/interrupt/status ID visible for program -- |
csr.mcause <= trap_ctrl.cause; |
|
|
-- Trap Priority Detector ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
trap_priority: process(trap_ctrl) |
1284,22 → 1290,14
-- Control and Status Registers (CSRs) |
-- **************************************************************************************************************************** |
|
-- CSR CPU Access ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
csr_cpu_acc: process(clk_i) |
begin |
if rising_edge(clk_i) then |
csr.we <= csr.we_nxt; |
csr.re <= csr.re_nxt; |
end if; |
end process csr_cpu_acc; |
|
|
-- Control and Status Registers Write Access ---------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
csr_write_access: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
csr.we <= '0'; |
csr.re <= '0'; |
-- |
csr.mstatus_mie <= '0'; |
csr.mstatus_mpie <= '0'; |
csr.mie_msie <= '0'; |
1309,55 → 1307,64
csr.mtval <= (others => '0'); |
csr.mepc <= (others => '0'); |
csr.mip_msip <= '0'; |
csr.misa_c_en <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension |
csr.misa_m_en <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension |
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
-- access -- |
csr.we <= csr.we_nxt; |
csr.re <= csr.re_nxt; |
|
-- defaults -- |
csr.mip_msip <= '0'; |
|
-- register that can be modified by user -- |
-- registers that can be modified by user -- |
if (csr.we = '1') then -- manual update |
|
-- machine trap setup -- |
if (execute_engine.i_reg(31 downto 24) = x"30") then |
if (execute_engine.i_reg(23 downto 20) = x"0") then -- R/W: mstatus - machine status register |
csr.mstatus_mie <= csr_wdata_i(03); |
csr.mstatus_mpie <= csr_wdata_i(07); |
-- Machine CSRs: Standard read/write |
if (execute_engine.i_reg(31 downto 28) = x"3") then |
-- machine trap setup -- |
if (execute_engine.i_reg(27 downto 24) = x"0") then |
case execute_engine.i_reg(23 downto 20) is |
when x"0" => -- R/W: mstatus - machine status register |
csr.mstatus_mie <= csr_wdata_i(03); |
csr.mstatus_mpie <= csr_wdata_i(07); |
when x"4" => -- R/W: mie - machine interrupt-enable register |
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable |
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable |
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable |
when x"5" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.mtvec <= csr_wdata_i; |
when others => |
NULL; |
end case; |
end if; |
if (execute_engine.i_reg(23 downto 20) = x"1") then -- R/W: misa - machine instruction set extensions |
csr.misa_c_en <= csr_wdata_i(02); -- C extension enable/disable during runtime |
csr.misa_m_en <= csr_wdata_i(12); -- M extension enable/disable during runtime |
-- machine trap handling -- |
if (execute_engine.i_reg(27 downto 24) = x"4") then |
case execute_engine.i_reg(23 downto 20) is |
when x"0" => -- R/W: mscratch - machine scratch register |
csr.mscratch <= csr_wdata_i; |
when x"1" => -- R/W: mepc - machine exception program counter |
csr.mepc <= csr_wdata_i; |
when x"2" => -- R/W: mcause - machine trap cause |
csr.mcause <= csr_wdata_i; |
when x"3" => -- R/W: mtval - machine bad address or instruction |
csr.mtval <= csr_wdata_i; |
when x"4" => -- R/W: mip - machine interrupt pending |
csr.mip_msip <= csr_wdata_i(03); -- manual SW IRQ trigger |
when others => |
NULL; |
end case; |
end if; |
if (execute_engine.i_reg(23 downto 20) = x"4") then -- R/W: mie - machine interrupt-enable register |
csr.mie_msie <= csr_wdata_i(03); -- SW IRQ enable |
csr.mie_mtie <= csr_wdata_i(07); -- TIMER IRQ enable |
csr.mie_meie <= csr_wdata_i(11); -- EXT IRQ enable |
end if; |
if (execute_engine.i_reg(23 downto 20) = x"5") then -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.mtvec <= csr_wdata_i; |
end if; |
end if; |
|
-- machine trap handling -- |
if (execute_engine.i_reg(31 downto 24) = x"34") then |
if (execute_engine.i_reg(23 downto 20) = x"0") then -- R/W: mscratch - machine scratch register |
csr.mscratch <= csr_wdata_i; |
end if; |
if (execute_engine.i_reg(23 downto 20) = x"1") then-- R/W: mepc - machine exception program counter |
csr.mepc <= csr_wdata_i; |
end if; |
if (execute_engine.i_reg(23 downto 20) = x"4") then -- R/W: mip - machine interrupt pending |
csr.mip_msip <= csr_wdata_i(03); -- manual SW IRQ trigger |
end if; |
end if; |
-- automatic update by hardware -- |
else |
|
else -- automatic update by hardware |
|
-- machine exception PC & exception value register -- |
if (trap_ctrl.env_start_ack = '1') then -- trap handler started? |
if (csr.mcause(data_width_c-1) = '1') then -- for INTERRUPTS only (mtval not defined for interrupts) |
csr.mcause <= trap_ctrl.cause; |
if (csr.mcause(data_width_c-1) = '1') then -- for INTERRUPTS only |
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction |
csr.mtval <= (others => '0'); |
csr.mtval <= (others => '0'); -- mtval not defined for interrupts |
else -- for EXCEPTIONS (according to their priority) |
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction |
if ((trap_ctrl.exc_src(exception_iaccess_c) or trap_ctrl.exc_src(exception_ialign_c)) = '1') then -- instruction access error OR misaligned instruction |
1392,91 → 1399,100
begin |
if rising_edge(clk_i) then |
csr_rdata_o <= (others => '0'); -- default |
if (CPU_EXTENSION_RISCV_Zicsr = true) then -- implement CSR access at all? |
if (csr.re = '1') then |
case execute_engine.i_reg(31 downto 20) is |
-- machine trap setup -- |
when x"300" => -- R/W: mstatus - machine status register |
csr_rdata_o(03) <= csr.mstatus_mie; -- MIE |
csr_rdata_o(07) <= csr.mstatus_mpie; -- MPIE |
csr_rdata_o(11) <= '1'; -- MPP low |
csr_rdata_o(12) <= '1'; -- MPP high |
when x"301" => -- R/W: misa - ISA and extensions |
csr_rdata_o(02) <= csr.misa_c_en; -- C CPU extension |
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension |
csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E) |
csr_rdata_o(12) <= csr.misa_m_en; -- M CPU extension |
csr_rdata_o(23) <= '1'; -- X CPU extension: non-standard extensions |
csr_rdata_o(25) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Z CPU extension |
csr_rdata_o(30) <= '1'; -- 32-bit architecture (MXL lo) |
csr_rdata_o(31) <= '0'; -- 32-bit architecture (MXL hi) |
when x"304" => -- R/W: mie - machine interrupt-enable register |
csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable |
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable |
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable |
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr_rdata_o <= csr.mtvec; |
-- machine trap handling -- |
when x"340" => -- R/W: mscratch - machine scratch register |
csr_rdata_o <= csr.mscratch; |
when x"341" => -- R/W: mepc - machine exception program counter |
csr_rdata_o <= csr.mepc; |
when x"342" => -- R/-: mcause - machine trap cause |
csr_rdata_o <= csr.mcause; |
when x"343" => -- R/-: mtval - machine bad address or instruction |
csr_rdata_o <= csr.mtval; |
when x"344" => -- R/W: mip - machine interrupt pending |
csr_rdata_o(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c); |
csr_rdata_o(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c); |
csr_rdata_o(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c); |
-- counter and timers -- |
when x"c00" | x"c01" | x"b00" => -- R/-: cycle/time/mcycle: Cycle counter LOW / Timer LOW |
csr_rdata_o <= csr.cycle(31 downto 0); |
when x"c02" | x"b02" => -- R/-: instret/minstret: Instructions-retired counter LOW |
csr_rdata_o <= csr.instret(31 downto 0); |
when x"c80" | x"c81" | x"b80" => -- R/-: cycleh/timeh/mcycleh: Cycle counter HIGH / Timer HIGH |
csr_rdata_o <= csr.cycleh; |
when x"c82" | x"b82" => -- R/-: instreth/minstreth: Instructions-retired counter HIGH |
csr_rdata_o <= csr.instreth; |
-- machine information registers -- |
when x"f13" => -- R/-: mimpid - implementation ID / version |
csr_rdata_o <= hw_version_c; |
when x"f14" => -- R/-: mhartid - hardware thread ID |
csr_rdata_o <= HART_ID; |
-- CUSTOM read-only machine CSRs -- |
when x"fc0" => -- R/-: mfeatures - implemented processor devices/features |
csr_rdata_o(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- implement processor-internal bootloader? |
csr_rdata_o(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- implement external memory bus interface? |
csr_rdata_o(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory? |
csr_rdata_o(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM? |
csr_rdata_o(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory? |
csr_rdata_o(05) <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- implement RISC-V (performance) counter? |
-- |
csr_rdata_o(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)? |
csr_rdata_o(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)? |
csr_rdata_o(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)? |
csr_rdata_o(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)? |
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)? |
csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)? |
csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)? |
csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)? |
csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)? |
csr_rdata_o(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)? |
when x"fc1" => -- R/-: mclock - processor clock speed |
csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32)); |
when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space |
csr_rdata_o <= MEM_ISPACE_BASE; |
when x"fc5" => -- R/-: mdspacebase - Base address of data memory space |
csr_rdata_o <= MEM_DSPACE_BASE; |
when x"fc6" => -- R/-: mispacesize - Total size of instruction memory space in byte |
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_ISPACE_SIZE, 32)); |
when x"fc7" => -- R/-: mdspacesize - Total size of data memory space in byte |
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_DSPACE_SIZE, 32)); |
-- undefined/unavailable -- |
when others => |
csr_rdata_o <= (others => '0'); -- not implemented (yet) |
end case; |
end if; |
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then |
case execute_engine.i_reg(31 downto 20) is |
|
-- machine trap setup -- |
when x"300" => -- R/W: mstatus - machine status register |
csr_rdata_o(03) <= csr.mstatus_mie; -- MIE |
csr_rdata_o(07) <= csr.mstatus_mpie; -- MPIE |
csr_rdata_o(11) <= '1'; -- MPP low |
csr_rdata_o(12) <= '1'; -- MPP high |
when x"301" => -- R/-: misa - ISA and extensions |
csr_rdata_o(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension |
csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension |
csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E) |
csr_rdata_o(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension |
csr_rdata_o(25) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Z CPU extension |
csr_rdata_o(30) <= '1'; -- 32-bit architecture (MXL lo) |
csr_rdata_o(31) <= '0'; -- 32-bit architecture (MXL hi) |
when x"304" => -- R/W: mie - machine interrupt-enable register |
csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable |
csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable |
csr_rdata_o(11) <= csr.mie_meie; -- external IRQ enable |
when x"305" => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr_rdata_o <= csr.mtvec; |
|
-- machine trap handling -- |
when x"340" => -- R/W: mscratch - machine scratch register |
csr_rdata_o <= csr.mscratch; |
when x"341" => -- R/W: mepc - machine exception program counter |
csr_rdata_o <= csr.mepc; |
when x"342" => -- R/W: mcause - machine trap cause |
csr_rdata_o <= csr.mcause; |
when x"343" => -- R/W: mtval - machine bad address or instruction |
csr_rdata_o <= csr.mtval; |
when x"344" => -- R/W: mip - machine interrupt pending |
csr_rdata_o(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c); |
csr_rdata_o(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c); |
csr_rdata_o(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c); |
|
-- counter and timers -- |
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW |
csr_rdata_o <= csr.mcycle(31 downto 0); |
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW |
csr_rdata_o <= csr.minstret(31 downto 0); |
when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH |
csr_rdata_o <= csr.mcycleh; |
when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH |
csr_rdata_o <= csr.minstreth; |
|
when x"c01" => -- R/-: time: System time LOW (from MTIME unit) |
csr_rdata_o <= time_i(31 downto 0); |
when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit) |
csr_rdata_o <= time_i(63 downto 32); |
|
-- machine information registers -- |
when x"f13" => -- R/-: mimpid - implementation ID / version |
csr_rdata_o <= hw_version_c; |
when x"f14" => -- R/-: mhartid - hardware thread ID |
csr_rdata_o <= HART_ID; |
|
-- CUSTOM read-only machine CSRs -- |
when x"fc0" => -- R/-: mfeatures - implemented processor devices/features |
csr_rdata_o(00) <= bool_to_ulogic_f(BOOTLOADER_USE); -- implement processor-internal bootloader? |
csr_rdata_o(01) <= bool_to_ulogic_f(MEM_EXT_USE); -- implement external memory bus interface? |
csr_rdata_o(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE); -- implement processor-internal instruction memory? |
csr_rdata_o(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM? |
csr_rdata_o(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory? |
csr_rdata_o(05) <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- implement RISC-V (performance) counter? |
-- |
csr_rdata_o(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)? |
csr_rdata_o(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)? |
csr_rdata_o(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)? |
csr_rdata_o(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)? |
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)? |
csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)? |
csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)? |
csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)? |
csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)? |
csr_rdata_o(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)? |
when x"fc1" => -- R/-: mclock - processor clock speed |
csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32)); |
when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space |
csr_rdata_o <= MEM_ISPACE_BASE; |
when x"fc5" => -- R/-: mdspacebase - Base address of data memory space |
csr_rdata_o <= MEM_DSPACE_BASE; |
when x"fc6" => -- R/-: mispacesize - Total size of instruction memory space in byte |
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_ISPACE_SIZE, 32)); |
when x"fc7" => -- R/-: mdspacesize - Total size of data memory space in byte |
csr_rdata_o <= std_ulogic_vector(to_unsigned(MEM_DSPACE_SIZE, 32)); |
|
-- undefined/unavailable -- |
when others => |
csr_rdata_o <= (others => '0'); -- not implemented |
|
end case; |
end if; |
end if; |
end process csr_read_access; |
1487,29 → 1503,47
csr_counters: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
csr.cycle <= (others => '0'); |
csr.instret <= (others => '0'); |
csr.cycleh <= (others => '0'); |
csr.instreth <= (others => '0'); |
cycle_msb <= '0'; |
instret_msb <= '0'; |
csr.mcycle <= (others => '0'); |
csr.minstret <= (others => '0'); |
csr.mcycleh <= (others => '0'); |
csr.minstreth <= (others => '0'); |
mcycle_msb <= '0'; |
minstret_msb <= '0'; |
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_E = false) and (CSR_COUNTERS_USE = true) then |
-- low word overflow buffers -- |
cycle_msb <= csr.cycle(csr.cycle'left); |
instret_msb <= csr.instret(csr.instret'left); |
-- low word counters -- |
csr.cycle <= std_ulogic_vector(unsigned(csr.cycle) + 1); |
if (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then |
csr.instret <= std_ulogic_vector(unsigned(csr.instret) + 1); |
|
-- mcycle (cycle) -- |
mcycle_msb <= csr.mcycle(csr.mcycle'left); |
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b00") then -- write access |
csr.mcycle(31 downto 0) <= csr_wdata_i; |
csr.mcycle(32) <= '0'; |
elsif (execute_engine.sleep = '0') then -- automatic update |
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1); |
end if; |
-- high word counters -- |
if ((cycle_msb xor csr.cycle(csr.cycle'left)) = '1') then |
csr.cycleh <= std_ulogic_vector(unsigned(csr.cycleh) + 1); |
|
-- mcycleh (cycleh) -- |
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access |
csr.mcycleh <= csr_wdata_i; |
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update |
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1); |
end if; |
if ((instret_msb xor csr.instret(csr.instret'left)) = '1') then |
csr.instreth <= std_ulogic_vector(unsigned(csr.instreth) + 1); |
|
-- minstret (instret) -- |
minstret_msb <= csr.minstret(csr.minstret'left); |
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access |
csr.minstret(31 downto 0) <= csr_wdata_i; |
csr.minstret(32) <= '0'; |
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update |
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1); |
end if; |
|
-- minstreth (instreth) -- |
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access |
csr.minstreth <= csr_wdata_i; |
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update |
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1); |
end if; |
|
end if; |
end if; |
end process csr_counters; |
/rtl/core/neorv32_mtime.vhd
7,6 → 7,7
-- # However, the achine time cannot issue a new interrupt until the mtimecmp.HI register is # |
-- # written again. # |
-- # Note: The 64-bit time and compare system is broken and de-coupled into two 32-bit systems. # |
-- # Note: The register of this unit can only be written in WORD MODE. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
58,6 → 59,8
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
-- time output for CPU -- |
time_o : out std_ulogic_vector(63 downto 0); -- current system time |
-- interrupt -- |
irq_o : out std_ulogic -- interrupt request |
); |
75,7 → 78,8
signal wren : std_ulogic; -- module access enable |
|
-- accessible regs -- |
signal mtimecmp : std_ulogic_vector(63 downto 0); |
signal mtimecmp_lo : std_ulogic_vector(31 downto 0); |
signal mtimecmp_hi : std_ulogic_vector(31 downto 0); |
signal mtime_lo : std_ulogic_vector(32 downto 0); |
signal mtime_lo_msb_ff : std_ulogic; |
signal mtime_hi : std_ulogic_vector(31 downto 0); |
85,8 → 89,6
signal cmp_lo_ff : std_ulogic; |
signal cmp_hi : std_ulogic; |
signal cmp_match_ff : std_ulogic; |
signal irq_flag : std_ulogic; |
signal irq_flag_ff : std_ulogic; |
|
begin |
|
94,52 → 96,38
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned |
wren <= acc_en and wren_i; |
wren <= acc_en and wren_i and and_all_f(ben_i); |
|
|
-- System Time Update --------------------------------------------------------------------- |
-- Write Access --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
system_time: process(clk_i) |
wr_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (rstn_i = '0') then |
mtime_lo <= (others => '0'); |
mtime_hi <= (others => '0'); |
else |
-- mtime low -- |
mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1); |
mtime_lo_msb_ff <= mtime_lo(mtime_lo'left); |
-- mtime high -- |
if ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry? |
mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1); |
-- mtimecmp -- |
if (wren = '1') then |
if (addr = mtime_cmp_lo_addr_c) then -- low |
mtimecmp_lo <= data_i; |
end if; |
if (addr = mtime_cmp_hi_addr_c) then -- high |
mtimecmp_hi <= data_i; |
end if; |
end if; |
end if; |
end process system_time; |
|
|
-- Write Access --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
wr_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
ack_o <= acc_en and (rden_i or wren_i); |
-- mtimecmp low -- |
if (wren = '1') and (addr = mtime_cmp_lo_addr_c) then |
for i in 0 to 3 loop |
if (ben_i(i) = '1') then |
mtimecmp(00+7+i*8 downto 00+0+i*8) <= data_i(7+i*8 downto 0+i*8); |
end if; |
end loop; -- byte enable |
-- mtime low -- |
if (wren = '1') and (addr = mtime_time_lo_addr_c) then |
mtime_lo_msb_ff <= '0'; |
mtime_lo <= '0' & data_i; |
else -- auto increment |
mtime_lo_msb_ff <= mtime_lo(mtime_lo'left); |
mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1); |
end if; |
|
-- mtimecmp high -- |
if (wren = '1') and (addr = mtime_cmp_hi_addr_c) then |
for i in 0 to 3 loop |
if (ben_i(i) = '1') then |
mtimecmp(32+7+i*8 downto 32+0+i*8) <= data_i(7+i*8 downto 0+i*8); |
end if; |
end loop; -- byte enable |
-- mtime high -- |
if (wren = '1') and (addr = mtime_time_hi_addr_c) then |
mtime_hi <= data_i; |
elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry? |
mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1); |
end if; |
end if; |
end process wr_access; |
150,6 → 138,7
rd_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
ack_o <= acc_en and (rden_i or wren_i); |
data_o <= (others => '0'); -- default |
if (rden_i = '1') and (acc_en = '1') then |
if (addr = mtime_time_lo_addr_c) then -- mtime LOW |
157,15 → 146,18
elsif (addr = mtime_time_hi_addr_c) then -- mtime HIGH |
data_o <= mtime_hi; |
elsif (addr = mtime_cmp_lo_addr_c) then -- mtimecmp LOW |
data_o <= mtimecmp(31 downto 00); |
data_o <= mtimecmp_lo; |
else -- (addr = mtime_cmp_hi_addr_c) then -- mtimecmp HIGH |
data_o <= mtimecmp(63 downto 32); |
data_o <= mtimecmp_hi; |
end if; |
end if; |
end if; |
end process rd_access; |
|
-- time output for cpu -- |
time_o <= mtime_hi & mtime_lo(31 downto 00); |
|
|
-- Comparator ----------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
cmp_sync: process(clk_i) |
173,38 → 165,13
if rising_edge(clk_i) then |
cmp_lo_ff <= cmp_lo; |
cmp_match_ff <= cmp_lo_ff and cmp_hi; |
irq_o <= cmp_lo_ff and cmp_hi and (not cmp_match_ff); |
end if; |
end process cmp_sync; |
|
-- test words -- |
cmp_lo <= '1' when (unsigned(mtime_lo(31 downto 00)) >= unsigned(mtimecmp(31 downto 00))) else '0'; |
cmp_hi <= '1' when (unsigned(mtime_hi(31 downto 00)) >= unsigned(mtimecmp(63 downto 32))) else '0'; |
cmp_lo <= '1' when (unsigned(mtime_lo(31 downto 00)) >= unsigned(mtimecmp_lo)) else '0'; |
cmp_hi <= '1' when (unsigned(mtime_hi(31 downto 00)) >= unsigned(mtimecmp_hi)) else '0'; |
|
|
-- Interrupt Logic ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
irq_ctrl: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (rstn_i = '0') then |
irq_flag_ff <= '0'; |
irq_flag <= '0'; |
else |
irq_flag_ff <= irq_flag; |
if (irq_flag = '0') then -- idle |
irq_flag <= '0'; |
if (cmp_match_ff = '1') then |
irq_flag <= '1'; |
end if; |
elsif (wren = '1') and (addr = mtime_cmp_hi_addr_c) then -- ACK |
irq_flag <= '0'; |
end if; |
end if; |
end if; |
end process irq_ctrl; |
|
-- irq output to CPU -- |
irq_o <= irq_flag and (not irq_flag_ff); -- rising edge detector |
|
|
end neorv32_mtime_rtl; |
/rtl/core/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - FIXED! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000100"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000600"; -- no touchy! |
|
-- Internal Functions --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
178,16 → 178,15
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable |
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable |
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load |
constant ctrl_bus_exc_ack_c : natural := 40; -- acknowledge bus exception |
constant ctrl_bus_reset_c : natural := 41; -- reset bus unit, terminate all actions |
-- co-processor -- |
constant ctrl_cp_use_c : natural := 40; -- is cp operation |
constant ctrl_cp_id_lsb_c : natural := 41; -- cp select lsb |
constant ctrl_cp_id_msb_c : natural := 42; -- cp select msb |
constant ctrl_cp_cmd0_c : natural := 43; -- cp command bit 0 |
constant ctrl_cp_cmd1_c : natural := 44; -- cp command bit 1 |
constant ctrl_cp_cmd2_c : natural := 45; -- cp command bit 2 |
-- system -- |
constant ctrl_sys_c_ext_en_c : natural := 46; -- CPU C extension enabled |
constant ctrl_sys_m_ext_en_c : natural := 47; -- CPU M extension enabled |
constant ctrl_cp_use_c : natural := 42; -- is cp operation |
constant ctrl_cp_id_lsb_c : natural := 43; -- cp select lsb |
constant ctrl_cp_id_msb_c : natural := 44; -- cp select msb |
constant ctrl_cp_cmd0_c : natural := 45; -- cp command bit 0 |
constant ctrl_cp_cmd1_c : natural := 46; -- cp command bit 1 |
constant ctrl_cp_cmd2_c : natural := 47; -- cp command bit 2 |
-- control bus size -- |
constant ctrl_width_c : natural := 48; -- control bus size |
|
277,6 → 276,14
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP) |
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync |
|
-- RISC-V Funct12 -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- system -- |
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL |
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK |
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET |
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI |
|
-- Co-Processor Operations ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- cp ids -- |
453,20 → 460,23
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
-- bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic; -- bus transfer error |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic; -- bus transfer error |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- external interrupts -- |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic -- machine timer interrupt |
); |
end component; |
|
533,6 → 543,8
-- external interrupt -- |
clic_irq_i : in std_ulogic; -- CLIC interrupt request |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- bus access exceptions -- |
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register |
ma_instr_i : in std_ulogic; -- misaligned instruction address |
541,7 → 553,6
be_instr_i : in std_ulogic; -- bus error on instruction access |
be_load_i : in std_ulogic; -- bus error on load data access |
be_store_i : in std_ulogic; -- bus error on store data access |
bus_exc_ack_o : out std_ulogic; -- bus exception error acknowledge |
bus_busy_i : in std_ulogic -- bus unit is busy |
); |
end component; |
570,6 → 581,9
-- Component: CPU ALU --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cpu_alu |
generic ( |
CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension? |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
616,40 → 630,41
-- ------------------------------------------------------------------------------------------- |
component neorv32_cpu_bus |
generic ( |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- data input -- |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC |
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data |
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC |
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
-- data output -- |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data |
-- status -- |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data |
bus_wait_o : out std_ulogic; -- wait for bus operation to finish |
bus_busy_o : out std_ulogic; -- bus unit is busy |
exc_ack_i : in std_ulogic; -- exception controller ACK |
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register |
ma_instr_o : out std_ulogic; -- misaligned instruction address |
ma_load_o : out std_ulogic; -- misaligned load data address |
ma_store_o : out std_ulogic; -- misaligned store data address |
be_instr_o : out std_ulogic; -- bus error on instruction access |
be_load_o : out std_ulogic; -- bus error on load data access |
be_store_o : out std_ulogic; -- bus error on store data |
bus_wait_o : out std_ulogic; -- wait for bus operation to finish |
bus_busy_o : out std_ulogic; -- bus unit is busy |
-- bus system -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
); |
end component; |
|
732,6 → 747,8
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
-- time output for CPU -- |
time_o : out std_ulogic_vector(63 downto 0); -- current system time |
-- interrupt -- |
irq_o : out std_ulogic -- interrupt request |
); |
940,6 → 957,7
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
cancel_i : in std_ulogic; -- cancel current bus transaction |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
-- wishbone interface -- |
/rtl/core/neorv32_top.vhd
52,9 → 52,9
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])? |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Memory configuration: Instruction memory -- |
142,14 → 142,18
signal pwm_cg_en : std_ulogic; |
|
-- cpu bus -- |
signal cpu_addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
signal cpu_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
signal cpu_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
signal cpu_ben : std_ulogic_vector(03 downto 0); -- byte enable |
signal cpu_we : std_ulogic; -- write enable |
signal cpu_re : std_ulogic; -- read enable |
signal cpu_ack : std_ulogic; -- bus transfer acknowledge |
signal cpu_err : std_ulogic; -- bus transfer error |
type cpu_bus_t is record |
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
ben : std_ulogic_vector(03 downto 0); -- byte enable |
we : std_ulogic; -- write enable |
re : std_ulogic; -- read enable |
cancel : std_ulogic; -- cancel current transfer |
ack : std_ulogic; -- bus transfer acknowledge |
err : std_ulogic; -- bus transfer error |
end record; |
signal cpu : cpu_bus_t; |
|
-- io space access -- |
signal io_acc : std_ulogic; |
198,6 → 202,9
signal spi_irq : std_ulogic; |
signal twi_irq : std_ulogic; |
|
-- misc -- |
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME |
|
begin |
|
-- Sanity Checks -------------------------------------------------------------------------- |
352,32 → 359,35
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
-- bus interface -- |
bus_addr_o => cpu_addr, -- bus access address |
bus_rdata_i => cpu_rdata, -- bus read data |
bus_wdata_o => cpu_wdata, -- bus write data |
bus_ben_o => cpu_ben, -- byte enable |
bus_we_o => cpu_we, -- write enable |
bus_re_o => cpu_re, -- read enable |
bus_ack_i => cpu_ack, -- bus transfer acknowledge |
bus_err_i => cpu_err, -- bus transfer error |
bus_addr_o => cpu.addr, -- bus access address |
bus_rdata_i => cpu.rdata, -- bus read data |
bus_wdata_o => cpu.wdata, -- bus write data |
bus_ben_o => cpu.ben, -- byte enable |
bus_we_o => cpu.we, -- write enable |
bus_re_o => cpu.re, -- read enable |
bus_cancel_o => cpu.cancel, -- cancel current bus transaction |
bus_ack_i => cpu.ack, -- bus transfer acknowledge |
bus_err_i => cpu.err, -- bus transfer error |
-- system time input from MTIME -- |
time_i => mtime_time, -- current system time |
-- external interrupts -- |
clic_irq_i => clic_irq, -- CLIC interrupt request |
mtime_irq_i => mtime_irq -- machine timer interrupt |
clic_irq_i => clic_irq, -- CLIC interrupt request |
mtime_irq_i => mtime_irq -- machine timer interrupt |
); |
|
-- CPU data input -- |
cpu_rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or |
cpu.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or |
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata); |
|
-- CPU ACK input -- |
cpu_ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or |
cpu.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or |
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack); |
|
-- CPU bus error input -- |
cpu_err <= wishbone_err; |
cpu.err <= wishbone_err; |
|
|
-- Processor-Internal Instruction Memory (IMEM) ------------------------------------------- |
393,12 → 403,12
) |
port map ( |
clk_i => clk_i, -- global clock line |
rden_i => cpu_re, -- read enable |
wren_i => cpu_we, -- write enable |
ben_i => cpu_ben, -- byte write enable |
rden_i => cpu.re, -- read enable |
wren_i => cpu.we, -- write enable |
ben_i => cpu.ben, -- byte write enable |
upen_i => '1', -- update enable |
addr_i => cpu_addr, -- address |
data_i => cpu_wdata, -- data in |
addr_i => cpu.addr, -- address |
data_i => cpu.wdata, -- data in |
data_o => imem_rdata, -- data out |
ack_o => imem_ack -- transfer acknowledge |
); |
422,11 → 432,11
) |
port map ( |
clk_i => clk_i, -- global clock line |
rden_i => cpu_re, -- read enable |
wren_i => cpu_we, -- write enable |
ben_i => cpu_ben, -- byte write enable |
addr_i => cpu_addr, -- address |
data_i => cpu_wdata, -- data in |
rden_i => cpu.re, -- read enable |
wren_i => cpu.we, -- write enable |
ben_i => cpu.ben, -- byte write enable |
addr_i => cpu.addr, -- address |
data_i => cpu.wdata, -- data in |
data_o => dmem_rdata, -- data out |
ack_o => dmem_ack -- transfer acknowledge |
); |
446,8 → 456,8
neorv32_boot_rom_inst: neorv32_boot_rom |
port map ( |
clk_i => clk_i, -- global clock line |
rden_i => cpu_re, -- read enable |
addr_i => cpu_addr, -- address |
rden_i => cpu.re, -- read enable |
addr_i => cpu.addr, -- address |
data_o => bootrom_rdata, -- data out |
ack_o => bootrom_ack -- transfer acknowledge |
); |
483,12 → 493,13
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active |
-- host access -- |
addr_i => cpu_addr, -- address |
rden_i => cpu_re, -- read enable |
wren_i => cpu_we, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
addr_i => cpu.addr, -- address |
rden_i => cpu.re, -- read enable |
wren_i => cpu.we, -- write enable |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => wishbone_rdata, -- data out |
cancel_i => cpu.cancel, -- cancel current transaction |
ack_o => wishbone_ack, -- transfer acknowledge |
err_o => wishbone_err, -- transfer error |
-- wishbone interface -- |
521,9 → 532,9
|
-- IO Access? ----------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
io_acc <= '1' when (cpu_addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0'; |
io_rden <= io_acc and cpu_re; |
io_wren <= io_acc and cpu_we; |
io_acc <= '1' when (cpu.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0'; |
io_rden <= io_acc and cpu.re; |
io_wren <= io_acc and cpu.we; |
|
|
-- General Purpose Input/Output Port (GPIO) ----------------------------------------------- |
534,11 → 545,11
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu_addr, -- address |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => gpio_rdata, -- data out |
ack_o => gpio_ack, -- transfer acknowledge |
-- parallel io -- |
568,9 → 579,9
clk_i => clk_i, -- global clock line |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
addr_i => cpu_addr, -- address |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
addr_i => cpu.addr, -- address |
data_i => cpu.wdata, -- data in |
data_o => clic_rdata, -- data out |
ack_o => clic_ack, -- transfer acknowledge |
-- cpu interrupt -- |
615,9 → 626,9
rstn_i => ext_rstn, -- global reset line, low-active |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
addr_i => cpu_addr, -- address |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
addr_i => cpu.addr, -- address |
data_i => cpu.wdata, -- data in |
data_o => wdt_rdata, -- data out |
ack_o => wdt_ack, -- transfer acknowledge |
-- clock generator -- |
648,13 → 659,15
-- host access -- |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset, low-active, async |
addr_i => cpu_addr, -- address |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => mtime_rdata, -- data out |
ack_o => mtime_ack, -- transfer acknowledge |
-- time output for CPU -- |
time_o => mtime_time, -- current system time |
-- interrupt -- |
irq_o => mtime_irq -- interrupt request |
); |
663,6 → 676,7
neorv32_mtime_inst_false: |
if (IO_MTIME_USE = false) generate |
mtime_rdata <= (others => '0'); |
mtime_time <= (others => '0'); |
mtime_ack <= '0'; |
mtime_irq <= '0'; |
end generate; |
676,11 → 690,11
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu_addr, -- address |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => uart_rdata, -- data out |
ack_o => uart_ack, -- transfer acknowledge |
-- clock generator -- |
712,11 → 726,11
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu_addr, -- address |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => spi_rdata, -- data out |
ack_o => spi_ack, -- transfer acknowledge |
-- clock generator -- |
752,11 → 766,11
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu_addr, -- address |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => twi_rdata, -- data out |
ack_o => twi_ack, -- transfer acknowledge |
-- clock generator -- |
789,11 → 803,11
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu_addr, -- address |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => pwm_rdata, -- data out |
ack_o => pwm_ack, -- transfer acknowledge |
-- clock generator -- |
821,11 → 835,11
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu_addr, -- address |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => trng_rdata, -- data out |
ack_o => trng_ack -- transfer acknowledge |
); |
846,11 → 860,11
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu_addr, -- address |
addr_i => cpu.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
ben_i => cpu.ben, -- byte write enable |
data_i => cpu.wdata, -- data in |
data_o => devnull_rdata, -- data out |
ack_o => devnull_ack -- transfer acknowledge |
); |
/rtl/core/neorv32_wishbone.vhd
72,6 → 72,7
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
cancel_i : in std_ulogic; -- cancel current bus transaction |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
-- wishbone interface -- |
108,7 → 109,7
-- ------------------------------------------------------------------------------------------- |
sanity_check: process(clk_i) |
begin |
if rising_edge(clk_i) then -- just for simulation |
if rising_edge(clk_i) then |
if (INTERFACE_REG_STAGES > 2) then |
assert false report "NEORV32 CONFIG ERROR! Number of external memory interface buffer stages must be 0, 1 or 2." severity error; |
end if; |
144,10 → 145,8
-- bus cycle -- |
if (INTERFACE_REG_STAGES = 0) then |
wb_cyc_ff <= '0'; -- unused |
elsif (INTERFACE_REG_STAGES = 1) then |
wb_cyc_ff <= wb_access and ((not wb_ack_i) or (not wb_err_i)); |
elsif (INTERFACE_REG_STAGES = 2) then |
wb_cyc_ff <= wb_access and ((not wb_ack_ff) or (not wb_err_ff)); |
else |
wb_cyc_ff <= (wb_cyc_ff or wb_access) and ((not wb_ack_i) or (not wb_err_i)) and (not cancel_i); |
end if; |
-- bus strobe -- |
wb_stb_ff1 <= wb_stb_ff0; |
188,10 → 187,12
buffer_stages_one: process(clk_i) |
begin |
if rising_edge(clk_i) then |
wb_adr_o <= addr_i; |
wb_dat_o <= data_i; |
wb_sel_o <= ben_i; |
wb_we_o <= wren_i; |
if (wb_cyc_ff = '0') then |
wb_adr_o <= addr_i; |
wb_dat_o <= data_i; |
wb_sel_o <= ben_i; |
wb_we_o <= wren_i; |
end if; |
end if; |
end process buffer_stages_one; |
data_o <= wb_dat_i; |
202,11 → 203,13
buffer_stages_two: process(clk_i) |
begin |
if rising_edge(clk_i) then |
wb_adr_o <= addr_i; |
wb_dat_o <= data_i; |
wb_sel_o <= ben_i; |
wb_we_o <= wren_i; |
data_o <= wb_dat_i; |
if (wb_cyc_ff = '0') then |
wb_adr_o <= addr_i; |
wb_dat_o <= data_i; |
wb_sel_o <= ben_i; |
wb_we_o <= wren_i; |
data_o <= wb_dat_i; |
end if; |
end if; |
end process buffer_stages_two; |
end generate; |
/rtl/top_templates/README.md
0,0 → 1,10
## Top Templates |
|
The top entity of the NEORV32 processor is `rtl/core/neorv32_top.vhd`. This folder provides additional |
top entities, that instantiate the processor's top entity and have a different top interface. |
|
### `neorv32_test_setup.vhd` |
|
This entity is intended as "FPGA hello world" example for playing with the NEORV32. It uses only some of the |
provided peripherals and provides a very simple and basic interface - only the clock, reset, UART and a subset |
of the GPIO output port are propagated to the outer world. |
/sim/vivado/neorv32_tb_behav.wcfg
12,15 → 12,15
</db_ref> |
</db_ref_list> |
<zoom_setting> |
<ZoomStartTime time="2538228050fs"></ZoomStartTime> |
<ZoomEndTime time="2538245251fs"></ZoomEndTime> |
<Cursor1Time time="2538353150fs"></Cursor1Time> |
<ZoomStartTime time="84997884fs"></ZoomStartTime> |
<ZoomEndTime time="85016285fs"></ZoomEndTime> |
<Cursor1Time time="85050184fs"></Cursor1Time> |
</zoom_setting> |
<column_width_setting> |
<NameColumnWidth column_width="178"></NameColumnWidth> |
<ValueColumnWidth column_width="127"></ValueColumnWidth> |
<ValueColumnWidth column_width="115"></ValueColumnWidth> |
</column_width_setting> |
<WVObjectSize size="156" /> |
<WVObjectSize size="157" /> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.FETCH</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
65,154 → 65,6
<obj_property name="ElementShortName">fetch_engine</obj_property> |
<obj_property name="ObjectShortName">fetch_engine</obj_property> |
<obj_property name="isExpanded"></obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
<obj_property name="CustomSignalColor">#FFD700</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf" type="array"> |
<obj_property name="ElementShortName">.i_buf[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2" type="array"> |
<obj_property name="ElementShortName">.i_buf2[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf2_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_reg" type="array"> |
<obj_property name="ElementShortName">.ci_reg[17:0]</obj_property> |
<obj_property name="ObjectShortName">.ci_reg[17:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.ci_reg_nxt[17:0]</obj_property> |
<obj_property name="ObjectShortName">.ci_reg_nxt[17:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state" type="array"> |
<obj_property name="ElementShortName">.i_buf_state[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_state_nxt[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state_nxt[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real" type="array"> |
<obj_property name="ElementShortName">.pc_real[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real_add" type="array"> |
<obj_property name="ElementShortName">.pc_real_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch" type="array"> |
<obj_property name="ElementShortName">.pc_fetch[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch_add" type="array"> |
<obj_property name="ElementShortName">.pc_fetch_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_return" type="logic"> |
<obj_property name="ElementShortName">.ci_return</obj_property> |
<obj_property name="ObjectShortName">.ci_return</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_return_nxt" type="logic"> |
<obj_property name="ElementShortName">.ci_return_nxt</obj_property> |
<obj_property name="ObjectShortName">.ci_return_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.reset" type="logic"> |
<obj_property name="ElementShortName">.reset</obj_property> |
<obj_property name="ObjectShortName">.reset</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.bus_err_ack" type="logic"> |
<obj_property name="ElementShortName">.bus_err_ack</obj_property> |
<obj_property name="ObjectShortName">.bus_err_ack</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf" type="array"> |
<obj_property name="ElementShortName">.i_buf[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2" type="array"> |
<obj_property name="ElementShortName">.i_buf2[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf2_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf2_nxt[33:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf2_nxt[33:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_reg" type="array"> |
<obj_property name="ElementShortName">.ci_reg[17:0]</obj_property> |
<obj_property name="ObjectShortName">.ci_reg[17:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.ci_reg_nxt[17:0]</obj_property> |
<obj_property name="ObjectShortName">.ci_reg_nxt[17:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state" type="array"> |
<obj_property name="ElementShortName">.i_buf_state[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.i_buf_state_nxt" type="array"> |
<obj_property name="ElementShortName">.i_buf_state_nxt[1:0]</obj_property> |
<obj_property name="ObjectShortName">.i_buf_state_nxt[1:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real" type="array"> |
<obj_property name="ElementShortName">.pc_real[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_real_add" type="array"> |
<obj_property name="ElementShortName">.pc_real_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_real_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch" type="array"> |
<obj_property name="ElementShortName">.pc_fetch[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.pc_fetch_add" type="array"> |
<obj_property name="ElementShortName">.pc_fetch_add[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_fetch_add[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_return" type="logic"> |
<obj_property name="ElementShortName">.ci_return</obj_property> |
<obj_property name="ObjectShortName">.ci_return</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.ci_return_nxt" type="logic"> |
<obj_property name="ElementShortName">.ci_return_nxt</obj_property> |
<obj_property name="ObjectShortName">.ci_return_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.reset" type="logic"> |
<obj_property name="ElementShortName">.reset</obj_property> |
<obj_property name="ObjectShortName">.reset</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine.bus_err_ack" type="logic"> |
<obj_property name="ElementShortName">.bus_err_ack</obj_property> |
<obj_property name="ObjectShortName">.bus_err_ack</obj_property> |
</wvobject> |
</wvobject> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.IPB</obj_property> |
287,10 → 139,6
<obj_property name="ElementShortName">be_store_i</obj_property> |
<obj_property name="ObjectShortName">be_store_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/bus_exc_ack_o" type="logic"> |
<obj_property name="ElementShortName">bus_exc_ack_o</obj_property> |
<obj_property name="ObjectShortName">bus_exc_ack_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ctrl" type="array"> |
<obj_property name="ElementShortName">ctrl[47:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl[47:0]</obj_property> |
299,14 → 147,6
<obj_property name="ElementShortName">ctrl_o[47:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_o[47:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/bus_fast_rd" type="logic"> |
<obj_property name="ElementShortName">bus_fast_rd</obj_property> |
<obj_property name="ObjectShortName">bus_fast_rd</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/bus_fast_wr" type="logic"> |
<obj_property name="ElementShortName">bus_fast_wr</obj_property> |
<obj_property name="ObjectShortName">bus_fast_wr</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ci_instr32" type="array"> |
<obj_property name="ElementShortName">ci_instr32[31:0]</obj_property> |
<obj_property name="ObjectShortName">ci_instr32[31:0]</obj_property> |
343,123 → 183,27
<obj_property name="ElementShortName">execute_engine</obj_property> |
<obj_property name="ObjectShortName">execute_engine</obj_property> |
<obj_property name="isExpanded"></obj_property> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
<obj_property name="CustomSignalColor">#FFD700</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_prev" type="other"> |
<obj_property name="ElementShortName">.state_prev</obj_property> |
<obj_property name="ObjectShortName">.state_prev</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg" type="array"> |
<obj_property name="ElementShortName">.i_reg[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.i_reg_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci" type="logic"> |
<obj_property name="ElementShortName">.is_ci</obj_property> |
<obj_property name="ObjectShortName">.is_ci</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_ci_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_ci_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump" type="logic"> |
<obj_property name="ElementShortName">.is_jump</obj_property> |
<obj_property name="ObjectShortName">.is_jump</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_jump_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_jump_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.branch_taken" type="logic"> |
<obj_property name="ElementShortName">.branch_taken</obj_property> |
<obj_property name="ObjectShortName">.branch_taken</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc" type="array"> |
<obj_property name="ElementShortName">.pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc_nxt" type="array"> |
<obj_property name="ElementShortName">.pc_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.next_pc" type="array"> |
<obj_property name="ElementShortName">.next_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.next_pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.last_pc" type="array"> |
<obj_property name="ElementShortName">.last_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.last_pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state" type="other"> |
<obj_property name="ElementShortName">.state</obj_property> |
<obj_property name="ObjectShortName">.state</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_nxt" type="other"> |
<obj_property name="ElementShortName">.state_nxt</obj_property> |
<obj_property name="ObjectShortName">.state_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.state_prev" type="other"> |
<obj_property name="ElementShortName">.state_prev</obj_property> |
<obj_property name="ObjectShortName">.state_prev</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg" type="array"> |
<obj_property name="ElementShortName">.i_reg[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.i_reg_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci" type="logic"> |
<obj_property name="ElementShortName">.is_ci</obj_property> |
<obj_property name="ObjectShortName">.is_ci</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_ci_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_ci_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_ci_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump" type="logic"> |
<obj_property name="ElementShortName">.is_jump</obj_property> |
<obj_property name="ObjectShortName">.is_jump</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.is_jump_nxt" type="logic"> |
<obj_property name="ElementShortName">.is_jump_nxt</obj_property> |
<obj_property name="ObjectShortName">.is_jump_nxt</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.branch_taken" type="logic"> |
<obj_property name="ElementShortName">.branch_taken</obj_property> |
<obj_property name="ObjectShortName">.branch_taken</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc" type="array"> |
<obj_property name="ElementShortName">.pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc_nxt" type="array"> |
<obj_property name="ElementShortName">.pc_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_nxt[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.next_pc" type="array"> |
<obj_property name="ElementShortName">.next_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.next_pc[31:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.last_pc" type="array"> |
<obj_property name="ElementShortName">.last_pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.last_pc[31:0]</obj_property> |
</wvobject> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/CPU_EXTENSION_RISCV_C" type="other"> |
<obj_property name="ElementShortName">CPU_EXTENSION_RISCV_C</obj_property> |
<obj_property name="ObjectShortName">CPU_EXTENSION_RISCV_C</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/CPU_EXTENSION_RISCV_E" type="other"> |
<obj_property name="ElementShortName">CPU_EXTENSION_RISCV_E</obj_property> |
<obj_property name="ObjectShortName">CPU_EXTENSION_RISCV_E</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/CPU_EXTENSION_RISCV_M" type="other"> |
<obj_property name="ElementShortName">CPU_EXTENSION_RISCV_M</obj_property> |
<obj_property name="ObjectShortName">CPU_EXTENSION_RISCV_M</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/CPU_EXTENSION_RISCV_Zicsr" type="other"> |
<obj_property name="ElementShortName">CPU_EXTENSION_RISCV_Zicsr</obj_property> |
<obj_property name="ObjectShortName">CPU_EXTENSION_RISCV_Zicsr</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/CPU_EXTENSION_RISCV_Zifencei" type="other"> |
<obj_property name="ElementShortName">CPU_EXTENSION_RISCV_Zifencei</obj_property> |
<obj_property name="ObjectShortName">CPU_EXTENSION_RISCV_Zifencei</obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider139"> |
<obj_property name="label">CPU: Control.TRAP</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
714,10 → 458,6
<obj_property name="ElementShortName">bus_wait_o</obj_property> |
<obj_property name="ObjectShortName">bus_wait_o</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/exc_ack_i" type="logic"> |
<obj_property name="ElementShortName">exc_ack_i</obj_property> |
<obj_property name="ObjectShortName">exc_ack_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/bus_addr_o" type="array"> |
<obj_property name="ElementShortName">bus_addr_o[31:0]</obj_property> |
<obj_property name="ObjectShortName">bus_addr_o[31:0]</obj_property> |
/sim/neorv32_tb.vhd
5,6 → 5,7
-- # signals. The received chars are shown in the simulator console and also written to a file # |
-- # ("neorv32.testbench_uart.out"). # |
-- # Futhermore, this testbench provides a simple RAM connected to the external Wishbone bus. # |
-- # The testbench configures the processor with all optional element enabled by default. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
159,7 → 160,7
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => true, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => true, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => false, -- implement true random number generator (TRNG)? |
IO_TRNG_USE => false, -- CANNOT BE SIMULATED! |
IO_DEVNULL_USE => true -- implement dummy device (DEVNULL)? |
) |
port map ( |
/sw/bootloader/bootloader.c
67,7 → 67,7
/** Bootloader status LED at GPIO output port (0..15) */ |
#define STATUS_LED (0) |
/** SPI flash boot image base address */ |
#define SPI_FLASH_BOOT_ADR (0x00040000) |
#define SPI_FLASH_BOOT_ADR (0x00800000) |
/** SPI flash chip select at spi_csn_o */ |
#define SPI_FLASH_CS (0) |
/** Default SPI flash clock prescaler for serial peripheral interface */ |
171,6 → 171,9
// Processor hardware initialization |
// ------------------------------------------------ |
|
// reset system time |
neorv32_mtime_set_time(0); |
|
// deactivate unused IO devices |
neorv32_clic_disable(); |
neorv32_pwm_disable(); |
/sw/common/crt0.S
218,10 → 218,10
// Go to endless sleep mode if main returns |
// ********************************************************* |
__crt0_this_is_the_end: |
wfi // in case Ziscr is not available -> processor should stall here |
csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE) |
csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE) |
wfi |
j . |
__crt0_this_is_the_end_end: |
j __crt0_this_is_the_end_end // in case Ziscr is not available |
|
|
// ********************************************************* |
/sw/example/cpu_test/main.c
119,6 → 119,12
int cnt_ok = 0; |
int cnt_test = 0; |
|
union { |
uint64_t uint64; |
uint32_t uint32[sizeof(uint64_t)/2]; |
} cpu_systime; |
|
|
// check if UART unit is implemented at all |
if (neorv32_uart_available() == 0) { |
return 0; |
139,6 → 145,7
neorv32_uart_setup(BAUD_RATE, 0, 0); |
|
|
neorv32_mtime_set_time(0); |
// set CMP of machine system timer MTIME to max to prevent an IRQ |
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFL; |
neorv32_mtime_set_timecmp(mtime_cmp_max); |
146,11 → 153,14
// intro |
neorv32_uart_printf("\n\n------ CPU TEST ------\n\n"); |
|
// show project credits |
neorv32_rte_print_credits(); |
|
// show full HW config report |
neorv32_rte_print_hw_config(); |
|
// intro2 |
neorv32_uart_printf("\n\nNEORV32 exceptions and interrupts test program\n\n"); |
neorv32_uart_printf("\n\nStarting tests...\n\n"); |
|
// install exception handler functions |
int install_err = 0; |
197,8 → 207,72
|
|
// ---------------------------------------------------------- |
// Test counter CSR access for mcycle[h] |
// ---------------------------------------------------------- |
neorv32_uart_printf("MCYCLE[H]: "); |
cnt_test++; |
|
neorv32_cpu_csr_write(CSR_MCYCLE, 0x1BCD1234); |
neorv32_cpu_csr_write(CSR_MCYCLEH, 0x22334455); |
|
if (((neorv32_cpu_csr_read(CSR_MCYCLE) & 0xffff0000L) == 0x1BCD0000) && |
(neorv32_cpu_csr_read(CSR_MCYCLEH) == 0x22334455)) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
|
|
// ---------------------------------------------------------- |
// Test counter CSR access for minstret[h] |
// ---------------------------------------------------------- |
neorv32_uart_printf("MINSTRET[H]: "); |
cnt_test++; |
|
neorv32_cpu_csr_write(CSR_MINSTRET, 0x11224499); |
neorv32_cpu_csr_write(CSR_MINSTRETH, 0x00110011); |
|
if (((neorv32_cpu_csr_read(CSR_MINSTRET) & 0xffff0000L) == 0x11220000) && |
(neorv32_cpu_csr_read(CSR_MINSTRETH) == 0x00110011)) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
|
|
// ---------------------------------------------------------- |
// Test time[h] (must be == MTIME) |
// ---------------------------------------------------------- |
neorv32_uart_printf("TIME[H]: "); |
cnt_test++; |
|
cpu_systime.uint32[0] = neorv32_cpu_csr_read(CSR_TIME); |
cpu_systime.uint32[1] = neorv32_cpu_csr_read(CSR_TIMEH); |
cpu_systime.uint64 &= 0xFFFFFFFFFFFF0000LL; |
|
uint64_t mtime_systime = neorv32_mtime_get_time() & 0xFFFFFFFFFFFF0000LL; |
|
if (cpu_systime.uint64 == mtime_systime) { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
else { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
|
|
// ---------------------------------------------------------- |
// Test fence instructions - make sure CPU does not crash here and throws no exception |
// a more complex test is provided by the RISC-V compliance test |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("FENCE(.I): "); |
cnt_test++; |
asm volatile ("fence"); |
212,12 → 286,12
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
exception_handler_answer = 0; |
|
|
// ---------------------------------------------------------- |
// Unaligned instruction address |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("EXC I_ALIGN: "); |
|
// skip if C-mode is not implemented |
237,11 → 311,10
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
} |
else { |
neorv32_uart_printf("skipped (no EXC I_ALIGN possible in C-mode)\n"); |
neorv32_uart_printf("skipped (not possible when C-EXT enabled)\n"); |
} |
|
|
248,6 → 321,7
// ---------------------------------------------------------- |
// Instruction access fault |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("EXC I_ACC: "); |
cnt_test++; |
|
263,7 → 337,6
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
270,6 → 343,7
// ---------------------------------------------------------- |
// Illegal instruction |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("EXC I_ILLEG: "); |
cnt_test++; |
|
291,7 → 365,6
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
298,6 → 371,7
// ---------------------------------------------------------- |
// Breakpoint instruction |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("EXC BREAK: "); |
cnt_test++; |
|
312,7 → 386,6
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
319,6 → 392,7
// ---------------------------------------------------------- |
// Unaligned load address |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("EXC L_ALIGN: "); |
cnt_test++; |
|
334,7 → 408,6
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
341,6 → 414,7
// ---------------------------------------------------------- |
// Load access fault |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("EXC L_ACC: "); |
cnt_test++; |
|
356,7 → 430,6
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
363,6 → 436,7
// ---------------------------------------------------------- |
// Unaligned store address |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("EXC S_ALIGN: "); |
cnt_test++; |
|
378,7 → 452,6
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
385,6 → 458,7
// ---------------------------------------------------------- |
// Store access fault |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("EXC S_ACC: "); |
cnt_test++; |
|
400,7 → 474,6
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
407,6 → 480,7
// ---------------------------------------------------------- |
// Environment call |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("EXC ENVCALL: "); |
cnt_test++; |
|
421,7 → 495,6
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
428,6 → 501,7
// ---------------------------------------------------------- |
// Machine software interrupt |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("IRQ MSI: "); |
cnt_test++; |
|
443,7 → 517,6
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
450,6 → 523,7
// ---------------------------------------------------------- |
// Machine timer interrupt (MTIME) |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("IRQ MTI: "); |
cnt_test++; |
|
471,13 → 545,16
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
// no more mtime interrupts |
neorv32_mtime_set_timecmp(-1); |
|
|
// ---------------------------------------------------------- |
// Machine external interrupt (via CLIC) |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("IRQ MEI: "); |
cnt_test++; |
|
499,10 → 576,36
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
exception_handler_answer = 0; |
#endif |
|
|
// ---------------------------------------------------------- |
// Test WFI ("sleep") instructions |
// ---------------------------------------------------------- |
exception_handler_answer = 0; |
neorv32_uart_printf("WFI: "); |
cnt_test++; |
|
// program timer to wake up |
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + 1000); |
|
// put CPU into sleep mode |
asm volatile ("wfi"); |
|
if (exception_handler_answer != ANSWER_MTI) { |
neorv32_uart_printf("fail\n"); |
cnt_fail++; |
} |
else { |
neorv32_uart_printf("ok\n"); |
cnt_ok++; |
} |
|
|
|
|
|
|
// error report |
neorv32_uart_printf("\n\nTests: %i\nOK: %i\nFAIL: %i\n\n", cnt_test, cnt_ok, cnt_fail); |
|
/sw/lib/include/neorv32.h
71,17 → 71,17
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/-): Machine bad address or instruction */ |
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */ |
|
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/-): Machine cycle counter low word */ |
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/-): Machine instructions-retired counter low word */ |
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/-): Machine cycle counter high word */ |
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/-): Machine instructions-retired counter high word */ |
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */ |
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */ |
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */ |
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */ |
|
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word */ |
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word*/ |
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME) */ |
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word */ |
|
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word */ |
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word*/ |
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME) */ |
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word */ |
|
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */ |
129,10 → 129,10
* CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MISA_enum { |
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/w), can be switched on/off */ |
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-), can be switched on/off */ |
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */ |
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */ |
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/w), can be switched on/off */ |
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-), can be switched on/off */ |
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */ |
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension(s) available (r/-) */ |
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */ |
324,17 → 324,17
* @name IO Device: Machine System Timer (MTIME) |
**************************************************************************/ |
/**@{*/ |
/** MTIME (time register) low word (r/-) */ |
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90UL)) |
/** MTIME (time register) high word (r/-) */ |
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94UL)) |
/** MTIME (time register) low word (r/w) */ |
#define MTIME_LO (*(IO_REG32 0xFFFFFF90UL)) |
/** MTIME (time register) high word (r/w) */ |
#define MTIME_HI (*(IO_REG32 0xFFFFFF94UL)) |
/** MTIMECMP (time compare register) low word (r/w) */ |
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL)) |
/** MTIMECMP (time register) high word (r/w) */ |
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL)) |
|
/** MTIME (time register) 64-bit access (r/-) */ |
#define MTIME (*(IO_ROM64 (&MTIME_LO))) |
/** MTIME (time register) 64-bit access (r/w) */ |
#define MTIME (*(IO_REG64 (&MTIME_LO))) |
/** MTIMECMP (time compare register) low word (r/w) */ |
#define MTIMECMP (*(IO_REG64 (&MTIMECMP_LO))) |
/**@}*/ |
/sw/lib/include/neorv32_cpu.h
43,7 → 43,6
#define neorv32_cpu_h |
|
// prototypes |
int neorv32_cpu_switch_extension(int sel, int state); |
int neorv32_cpu_irq_enable(uint8_t irq_sel); |
int neorv32_cpu_irq_disable(uint8_t irq_sel); |
void neorv32_cpu_delay_ms(uint32_t time_ms); |
/sw/lib/include/neorv32_mtime.h
46,6 → 46,7
|
// prototypes |
int neorv32_mtime_available(void); |
void neorv32_mtime_set_time(uint64_t time); |
uint64_t neorv32_mtime_get_time(void); |
void neorv32_mtime_set_timecmp(uint64_t timecmp); |
uint64_t neorv32_mtime_get_timecmp(void); |
/sw/lib/include/neorv32_rte.h
46,6 → 46,8
void neorv32_rte_enable_debug_mode(void); |
int neorv32_rte_exception_install(uint8_t exc_id, void (*handler)(void)); |
int neorv32_rte_exception_uninstall(uint8_t exc_id); |
|
void neorv32_rte_print_hw_config(void); |
void neorv32_rte_print_credits(void); |
|
#endif // neorv32_rte_h |
/sw/lib/source/neorv32_cpu.c
44,54 → 44,6
|
|
/**********************************************************************//** |
* Enable/disable CPU extension during runtime via the 'misa' CSR. |
* |
* @warning This is still highly experimental! This function requires the Zicsr + Zifencei CPU extensions. |
* |
* @param[in] sel Bit to be set in misa CSR / extension to be enabled. See #NEORV32_CPU_MISA_enum. |
* @param[in] state Set 1 to enable the selected extension, set 0 to disable it; |
* return 0 if success, 1 if error (invalid sel or extension cannot be enabled). |
**************************************************************************/ |
int neorv32_cpu_switch_extension(int sel, int state) { |
|
// get current misa setting |
uint32_t misa_curr = neorv32_cpu_csr_read(CSR_MISA); |
uint32_t misa_prev = misa_curr; |
|
// abort if misa.z is cleared |
if ((misa_curr & (1 << CPU_MISA_Z_EXT)) == 0) { |
return 1; |
} |
|
// out of range? |
if (sel > 25) { |
return 1; |
} |
|
// enable/disable selected extension |
if (state & 1) { |
misa_curr |= (1 << sel); |
} |
else { |
misa_curr &= ~(1 << sel); |
} |
|
// try updating misa |
neorv32_cpu_csr_write(CSR_MISA, misa_curr); |
asm volatile("fence.i"); // required to flush prefetch buffers |
asm volatile("nop"); |
|
// dit it work? |
if (neorv32_cpu_csr_read(CSR_MISA) == misa_prev) { |
return 1; // nope |
} |
else { |
return 0; // fine |
} |
} |
|
|
/**********************************************************************//** |
* Enable specific CPU interrupt. |
* |
* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too. |
/sw/lib/source/neorv32_mtime.c
62,10 → 62,23
|
|
/**********************************************************************//** |
* Get current system time since reset. |
* Set current system time. |
* |
* @note The MTIME timer increments with the primary processor clock. |
* |
* @param[in] time New system time (uint64_t) |
**************************************************************************/ |
void neorv32_mtime_set_time(uint64_t time) { |
|
MTIME = time; |
} |
|
|
/**********************************************************************//** |
* Get current system time. |
* |
* @note The MTIME timer increments with the primary processor clock. |
* |
* @return Current system time (uint64_t) |
**************************************************************************/ |
uint64_t neorv32_mtime_get_time(void) { |
/sw/lib/source/neorv32_rte.c
373,3 → 373,16
} |
} |
} |
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Print project credits |
**************************************************************************/ |
void neorv32_rte_print_credits(void) { |
|
neorv32_uart_print("\n\nThe NEORV32 Processor Project\n" |
"by Stephan Nolting\n" |
"https://github.com/stnolting/neorv32\n" |
"made in Hannover, Germany\n\n"); |
} |
|
/README.md
1,4 → 1,4
# [The NEORV32 Processor](https://github.com/stnolting/neorv32) |
# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V-compliant) |
|
[](https://travis-ci.com/stnolting/neorv32) |
[](https://github.com/stnolting/neorv32/blob/master/LICENSE) |
20,23 → 20,24
|
## Introduction |
|
The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional |
`M`, `C`, `Zicsr` and `Zifencei` extensions. The CPU was built from scratch and is compliant to the **Unprivileged |
ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended |
as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller. |
The NEORV32 is a customizable full-scale mikrocontroller-like processor system based on a [RISC-V-compliant](https://github.com/stnolting/neorv32_riscv_compliance) |
`rv32i` CPU with optional `E`, `C`, `M`, `Zicsr` and `Zifencei` extensions. The CPU was built from scratch and is compliant to the **Unprivileged |
ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12-draft**. |
|
The NEORV32 is intended as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller. |
Its top entity can be directly synthesized for any FPGA without modifications and provides a full-scale RISC-V based microcontroller. |
|
The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI, |
interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a |
Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled and configured via VHDL generics. |
|
This project comes with a complete software ecosystem that features core libraries for high-level usage of the |
provided functions and peripherals, application makefiles and example programs. All software source files |
provide a doxygen-based documentary. The deployed doxygen-based software documentation can be found on the |
project's [Github pages](https://stnolting.github.io/neorv32/files.html). |
provided functions and peripherals, application makefiles, a runtime environment and several example programs. All software source files |
provide a doxygen-based [documentary](https://stnolting.github.io/neorv32/files.html). |
|
The project is intended to work "out of the box". Just synthesize the test setup from this project, upload |
it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) |
by yourself, you can also download [pre-compiled toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux. |
by yourself, you can also download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux. |
|
For more information take a look a the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
57,16 → 58,17
|
The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance). |
|
| Project | Status | Misc | |
|:--------------------------------------------------------------------------------|:-------|:---------| |
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) | |
| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | | |
| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | | |
| Project component | CI status | Note | |
|:--------------------------------------------------------------------------------|:----------|:---------| |
| [NEORV32 processor](https://github.com/stnolting/neorv32) | [](https://travis-ci.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32/files.html) | |
| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | | |
| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | | |
|
|
### Limitations to be fixed |
|
* No exception is triggered in `E`-mode when using registers above `x15` yet |
* `misa` CSR is read-only; no dynamic enabling/disabling of implemented CPU extensions during runtime |
|
|
### To-Do / Wish List |
83,14 → 85,15
|
## Features |
|
 |
|
### Processor Features |
|
 |
|
- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M`, `Zicsr` and `rv32Zifencei` extensions |
- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt)) |
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available [@Github pages](https://stnolting.github.io/neorv32/files.html) |
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html) |
- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf) |
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc. |
- Fully synchronous design, no latches, no gated clocks |
- Small hardware footprint and high operating frequency |
109,12 → 112,23
- _Optional_ core-local interrupt controller with 8 channels (CLIC) |
- _Optional_ dummy device (DEVNULL) (can be used for *fast* simulation console output) |
|
|
### CPU Features |
|
The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the |
 |
|
The CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the |
[official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the |
[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf). |
|
More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in |
the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
|
**General**: |
* No hardware support of unaligned accesses - they will trigger and exception |
* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme |
|
|
**RV32I base instruction set** (`I` extension): |
* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND` |
* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU` |
140,7 → 154,7
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI` |
* System instructions: `MRET` `WFI` |
* Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth` |
* Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid` |
* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid` |
* Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize` |
* Supported exceptions and interrupts: |
* Misaligned instruction address |
152,7 → 166,7
* Store address misaligned |
* Store access fault |
* Environment call from M-mode (via `ecall` instruction) |
* Machine software instrrupt `msi` |
* Machine software interrupt `msi` |
* Machine timer interrupt `mti` (via MTIME unit) |
* Machine external interrupt `mei` (via CLIC unit) |
|
159,15 → 173,7
**Privileged architecture / FENCE.I** (`Zifencei` extension): |
* System instructions: `FENCE.I` |
|
**General**: |
* No hardware support of unaligned accesses - they will trigger and exception |
* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle execution |
|
More information including a detailed list of the available CSRs can be found in |
the [ NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
|
|
## FPGA Implementation Results |
|
This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on |
175,10 → 181,10
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration |
of the processor's generics is assumed. No constraints were used. |
|
### CPU |
|
Results generated for hardware version: `1.0.0.0` |
|
### CPU |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max | |
|:--------------------|:----------:|:--------:|:-----------:|:------:|:-------:| |
| `rv32i` | 1027 | 474 | 2048 | 0 (0%) | 111 MHz | |
189,6 → 195,8
|
### Processor-Internal Peripherals and Memories |
|
Results generated for hardware version: `1.0.5.0` |
|
| Module | Description | LEs | FFs | Memory bits | DSPs | |
|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:| |
| BOOT ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 | |
196,7 → 204,7
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 | |
| GPIO | General purpose input/output ports | 38 | 33 | 0 | 0 | |
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 | |
| MTIME | Machine system timer | 270 | 167 | 0 | 0 | |
| MTIME | Machine system timer | 269 | 166 | 0 | 0 | |
| PWM | Pulse-width modulation controller | 76 | 69 | 0 | 0 | |
| SPI | Serial peripheral interface | 206 | 125 | 0 | 0 | |
| TRNG | True random number generator | 104 | 93 | 0 | 0 | |
204,32 → 212,30
| UART | Universal asynchronous receiver/transmitter | 151 | 108 | 0 | 0 | |
| WDT | Watchdog timer | 57 | 45 | 0 | 0 | |
|
### CPU + Peripheral |
|
The following table shows the implementation results for an _Intel Cyclone IV EP4CE22F17C6N_ FPGA. |
The design was synthesized using Intel Quartus Prime Lite 19.1 (“balanced implementation”). |
IMEM uses 16kB and DMEM uses 8kB memory space. |
### Exemplary FPGA Setups |
|
| CPU Configuration | LEs | REGs | DSPs | Memory Bits | f_max | |
|:--------------------|:----------:|:---------:|:------:|:------------:|:-------:| |
| `rv32imc` + `Zicsr` | 3724 (17%) | 1899 (9%) | 0 (0%) | 231424 (38%) | 103 MHz | |
Exemplary implementation results for different FPGA platforms. The processor setup uses *all provided peripherals*, |
all CPU extensions (`rv32imc` + `Zicsr` + `Zifencei`, no `E` extension), no external memory interface and only internal |
instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup top entity connects most of the |
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals |
to FPGA pins - except for the Wishbone bus and the external interrupt signals. |
|
Results generated for hardware version: `1.0.1.1` |
|
### Lattice iCE40 UltraPlus 5k |
| Vendor | FPGA | Board | Toolchain | Impl. strategy | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency | |
|:--------|:----------------------------------|:-----------------|:------------------------|:---------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|------------:| |
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | 3841 (17%) | 1866 (8%) | 0 (0%) | 231424 (38%) | - | - | 103 MHz | |
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (LSE) | default | 5014 (95%) | 1952 (37%) | 0 (0%) | - | 12 (40%) | 4 (100%) | c 20.25 MHz | |
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | 2312 (11%) | 1924 (5%) | 0 (0%) | - | 8 (16%) | - | c 100 MHz | |
|
The following table shows the hardware utilization for a [iCE40 UP5K](http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) FPGA. |
The setup uses all provided peripherals, all CPU extensions (except for the `E` extension), no external memory interface and internal |
instruction and data memories (each 64kB) based on SPRAM primitives. The FPGA-specific memory components can be found in the |
[`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder. |
**Notes** |
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DEMEM (each 64kb). |
The FPGA-specific memory components can be found in the [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder. |
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are `f_max` results from the place and route timing reports. |
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32 |
bootloader to store and automatically boot an application program after reset (both tested successfully). |
|
Place & route reports generated with **Lattice Radiant 2.1** using Lattice LSE. The clock frequency |
is constrained and generated via the PLL from the internal HF oscillator running at 12 MHz. |
|
| CPU Configuration | LUTs | REGs | DSPs | SPRAM | EBR | f | |
|:--------------------|:----------:|:----------:|:------:|:--------:|:--------:|:---------:| |
| `rv32imc` + `Zicsr` | 4985 (94%) | 1982 (38%) | 0 (0%) | 4 (100%) | 12 (40%) | 20.25 MHz | |
|
|
## Performance |
|
### CoreMark Benchmark |
245,7 → 251,7
Hardware: 32kB IMEM, 16kb DMEM, 100MHz clock |
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK |
CPU extensions: `rv32i` or `rv32im` or `rv32imc` |
Used peripherals: MTIME for time measurement, UART for printing the results |
Used peripherals: UART for printing the results |
~~~ |
|
| __Configuration__ | __Optimization__ | __Executable Size__ | __CoreMark Score__ | __CoreMarks/MHz__ | |
260,7 → 266,7
|
### Instruction Cycles |
|
The NEORV32 CPU is based on two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence, |
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence, |
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions). |
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available |
CPU extensions. |
411,7 → 417,7
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt) |
|
|
### Dowload the NEORV32 Project and Create a Hardware Project |
### Dowload the NEORV32 and Create a Hardware Project |
|
Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using |
`git` from the command line (suggested for easy project updates via `git pull`): |
418,13 → 424,14
|
$ git clone https://github.com/stnolting/neorv32.git |
|
Create a new HW project with your FPGA design tool of choice. Add all files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl) |
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl) |
folder to this project and add them to a **new library** called `neorv32`. |
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in you own project, or you |
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity. This test |
setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are |
propagated: |
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you |
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's |
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity. |
This test setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are |
propagated (basically, its a FPGA "hello world" example): |
|
```vhdl |
entity neorv32_test_setup is |
441,12 → 448,10
end neorv32_test_setup; |
``` |
|
This test setup is intended as quick and easy "hello world" test setup to get into the NEORV32. |
|
|
### Compiling and Uploading One of the Example Projects |
|
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain, navigate to an example project like |
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like |
`sw/example/blink_led` and run: |
|
neorv32/sw/example/blink_led$ make check |
513,19 → 518,17
|
|
|
## Citation |
## Legal |
|
This is project is released under the BSD 3-Clause license. No copyright infringement intended. |
Other implied or used projects might have different licensing - see their documentation to get more information. |
|
#### Citation |
|
If you are using the NEORV32 Processor in some kind of publication, please cite it as follows: |
|
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32 |
|
|
|
## Legal |
|
This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended. |
Other implied/used projects might have different licensing - see their documentation to get more information. |
|
#### BSD 3-Clause License |
|
Copyright (c) 2020, Stephan Nolting. All rights reserved. |
564,21 → 567,25
link in question. |
|
|
#### Propretary Notice |
#### Proprietary Notice |
|
"Windows" is a trademark of Microsoft Corporation. |
|
"Artix" and "Vivado" are trademarks of Xilinx Inc. |
|
"Cyclone", "Quartus Prime" and "Avalon Bus" are trademarks of Intel Corporation. |
"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation. |
|
"Artix" and "Vivado" are trademarks of Xilinx, Inc. |
|
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation. |
|
"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc. |
|
|
#### Misc |
## Acknowledgement |
|
[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free :heart: |
|
[](https://travis-ci.com/stnolting/neorv32) |
|
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl). |
588,5 → 595,6
|
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org). |
|
\ |
|
Made with :coffee: in Hannover, Germany. |