URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/.ci/hw_check.sh
16,6 → 16,8
ghdl -v |
|
# List files |
echo "" |
echo "Simulation source files:" |
ls -al $srcdir_core |
ls -al $srcdir_top_templates |
ls -al $srcdir_sim |
34,6 → 36,7
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_cp_muldiv.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_decompressor.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_regfile.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_devnull.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_dmem.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_gpio.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_imem.vhd |
51,17 → 54,21
# |
ghdl -a --work=neorv32 $srcdir_sim/*.vhd |
|
# Prepare UART tx output log file and run simulation |
touch neorv32.sim_uart.out |
chmod 777 neorv32.sim_uart.out |
# Prepare simulation output files |
touch neorv32.testbench_uart.out |
chmod 777 neorv32.testbench_uart.out |
touch neorv32.devnull.out |
chmod 777 neorv32.devnull.out |
|
# Run simulation |
ghdl -e --work=neorv32 neorv32_tb |
ghdl -r --work=neorv32 neorv32_tb --stop-time=100ms --ieee-asserts=disable-at-0 --assert-level=error |
ghdl -r --work=neorv32 neorv32_tb --stop-time=5ms --ieee-asserts=disable --assert-level=error |
|
# Check output |
echo "Checking UART output. Should contain:"; cat $homedir/reference.out |
echo "Checking NEORV32.DEVNULL output. Should contain:"; cat $homedir/check_reference.out |
echo "" |
echo "Checking UART output. UART output is:" |
cat neorv32.sim_uart.out |
echo "Checking NEORV32.DEVNULL output. NEORV32.DEVNULL output is:" |
cat neorv32.devnull.out |
|
# Compare output with reference |
grep -qf $homedir/reference.out neorv32.sim_uart.out |
# Check if reference can be found in output |
grep -qf $homedir/check_reference.out neorv32.devnull.out |
/.ci/sw_check.sh
20,16 → 20,17
make -C $test_app_dir check |
|
# Compile all example projects |
make -C $srcdir_examples clean_all info compile |
make -C $srcdir_examples clean_all compile |
|
# Compile and install bootloader |
make -C $srcdir_bootloader clean_all info bootloader |
|
# Compile and install test application |
# Redirect UART TX to DEVNULL.simulation_output via <DEVNULL_UART_OVERRIDE> user flag |
echo "Installing test application" |
make -C $test_app_dir clean_all MARCH=-march=rv32imc info all |
make -C $test_app_dir clean_all USER_FLAGS+=-DDEVNULL_UART_OVERRIDE MARCH=-march=rv32imc info all |
|
# Verification reference string |
touch $homedir/reference.out |
chmod 777 $homedir/reference.out |
echo "TEST OK!" > $homedir/reference.out |
touch $homedir/check_reference.out |
chmod 777 $homedir/check_reference.out |
echo "TEST OK!" > $homedir/check_reference.out |
/docs/NEORV32.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/rtl/core/neorv32_application_image.vhd
1,5 → 1,5
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin> |
-- Auto-generated memory init file (for APPLICATION) from source file <test_exceptions/main.bin> |
|
library ieee; |
use ieee.std_logic_1164.all; |
8,883 → 8,718
|
type application_init_image_t is array (0 to 65535) of std_ulogic_vector(31 downto 0); |
constant application_init_image : application_init_image_t := ( |
00000000 => x"00000013", |
00000001 => x"00000093", |
00000002 => x"00008113", |
00000003 => x"00010193", |
00000004 => x"00018213", |
00000005 => x"00020293", |
00000006 => x"00028313", |
00000007 => x"00030393", |
00000008 => x"00038413", |
00000009 => x"00040493", |
00000010 => x"00048513", |
00000011 => x"00050593", |
00000012 => x"00058613", |
00000013 => x"00060693", |
00000014 => x"00068713", |
00000015 => x"00070793", |
00000016 => x"00078813", |
00000017 => x"00080893", |
00000018 => x"00088913", |
00000019 => x"00090993", |
00000020 => x"00098a13", |
00000021 => x"000a0a93", |
00000022 => x"000a8b13", |
00000023 => x"000b0b93", |
00000024 => x"000b8c13", |
00000025 => x"000c0c93", |
00000026 => x"000c8d13", |
00000027 => x"000d0d93", |
00000028 => x"000d8e13", |
00000029 => x"000e0e93", |
00000030 => x"000e8f13", |
00000031 => x"000f0f93", |
00000032 => x"00000013", |
00000033 => x"fc5015f3", |
00000034 => x"fc701673", |
00000035 => x"00c58133", |
00000036 => x"ffc10113", |
00000037 => x"00010413", |
00000038 => x"80000197", |
00000039 => x"7e818193", |
00000040 => x"00000597", |
00000041 => x"0b458593", |
00000042 => x"30559073", |
00000043 => x"fc5015f3", |
00000044 => x"00000617", |
00000045 => x"1f460613", |
00000046 => x"02000693", |
00000047 => x"00c5a023", |
00000048 => x"00458593", |
00000049 => x"fff68693", |
00000050 => x"fed01ae3", |
00000051 => x"f8000593", |
00000052 => x"0005a023", |
00000053 => x"00458593", |
00000054 => x"feb01ce3", |
00000055 => x"fff00593", |
00000056 => x"f8b02c23", |
00000057 => x"f8b02e23", |
00000058 => x"80000597", |
00000059 => x"f9858593", |
00000060 => x"80000617", |
00000061 => x"f9060613", |
00000062 => x"00c5d863", |
00000063 => x"00058023", |
00000064 => x"00158593", |
00000065 => x"ff5ff06f", |
00000066 => x"00001597", |
00000067 => x"cac58593", |
00000068 => x"80000617", |
00000069 => x"f7060613", |
00000070 => x"80000697", |
00000071 => x"f6868693", |
00000072 => x"00d65c63", |
00000073 => x"00058703", |
00000074 => x"00e60023", |
00000075 => x"00158593", |
00000076 => x"00160613", |
00000077 => x"fedff06f", |
00000078 => x"00000513", |
00000079 => x"00000593", |
00000080 => x"168000ef", |
00000081 => x"10500073", |
00000082 => x"30047073", |
00000083 => x"10500073", |
00000084 => x"0000006f", |
00000085 => x"f8810113", |
00000086 => x"00112023", |
00000087 => x"00312223", |
00000088 => x"00412423", |
00000089 => x"00512623", |
00000090 => x"00612823", |
00000091 => x"00712a23", |
00000092 => x"00812c23", |
00000093 => x"00912e23", |
00000094 => x"02a12023", |
00000095 => x"02b12223", |
00000096 => x"02c12423", |
00000097 => x"02d12623", |
00000098 => x"02e12823", |
00000099 => x"02f12a23", |
00000100 => x"03012c23", |
00000101 => x"03112e23", |
00000102 => x"05212023", |
00000103 => x"05312223", |
00000104 => x"05412423", |
00000105 => x"05512623", |
00000106 => x"05612823", |
00000107 => x"05712a23", |
00000108 => x"05812c23", |
00000109 => x"05912e23", |
00000110 => x"07a12023", |
00000111 => x"07b12223", |
00000112 => x"07c12423", |
00000113 => x"07d12623", |
00000114 => x"07e12823", |
00000115 => x"07f12a23", |
00000116 => x"342012f3", |
00000117 => x"00f2f313", |
00000118 => x"00231313", |
00000119 => x"fc5010f3", |
00000120 => x"00130333", |
00000121 => x"341010f3", |
00000122 => x"0002cc63", |
00000123 => x"34a012f3", |
00000124 => x"0022f293", |
00000125 => x"00208093", |
00000126 => x"005080b3", |
00000127 => x"0080006f", |
00000128 => x"04030313", |
00000129 => x"00032283", |
00000130 => x"ffc10113", |
00000131 => x"00112023", |
00000132 => x"34009073", |
00000133 => x"000280e7", |
00000134 => x"00012083", |
00000135 => x"00410113", |
00000136 => x"34109073", |
00000137 => x"00012083", |
00000138 => x"00412183", |
00000139 => x"00812203", |
00000140 => x"00c12283", |
00000141 => x"01012303", |
00000142 => x"01412383", |
00000143 => x"01812403", |
00000144 => x"01c12483", |
00000145 => x"02012503", |
00000146 => x"02412583", |
00000147 => x"02812603", |
00000148 => x"02c12683", |
00000149 => x"03012703", |
00000150 => x"03412783", |
00000151 => x"03812803", |
00000152 => x"03c12883", |
00000153 => x"04012903", |
00000154 => x"04412983", |
00000155 => x"04812a03", |
00000156 => x"04c12a83", |
00000157 => x"05012b03", |
00000158 => x"05412b83", |
00000159 => x"05812c03", |
00000160 => x"05c12c83", |
00000161 => x"06012d03", |
00000162 => x"06412d83", |
00000163 => x"06812e03", |
00000164 => x"06c12e83", |
00000165 => x"07012f03", |
00000166 => x"07412f83", |
00000167 => x"07810113", |
00000168 => x"30200073", |
00000169 => x"00008067", |
00000170 => x"ff010113", |
00000171 => x"00112623", |
00000172 => x"00812423", |
00000173 => x"6ac000ef", |
00000174 => x"04050663", |
00000175 => x"2a8000ef", |
00000176 => x"00005537", |
00000177 => x"00000613", |
00000178 => x"00000593", |
00000179 => x"b0050513", |
00000180 => x"3e8000ef", |
00000181 => x"00001537", |
00000182 => x"ac050513", |
00000183 => x"478000ef", |
00000184 => x"00000513", |
00000185 => x"68c000ef", |
00000186 => x"00000413", |
00000187 => x"0ff47513", |
00000188 => x"680000ef", |
00000189 => x"0c800513", |
00000190 => x"6b0000ef", |
00000191 => x"00140413", |
00000192 => x"fedff06f", |
00000193 => x"00c12083", |
00000194 => x"00812403", |
00000195 => x"01010113", |
00000196 => x"00008067", |
00000197 => x"00001537", |
00000198 => x"ff010113", |
00000199 => x"adc50513", |
00000200 => x"00112623", |
00000201 => x"00812423", |
00000202 => x"484000ef", |
00000203 => x"c81015f3", |
00000204 => x"c0101673", |
00000205 => x"00001537", |
00000206 => x"b0450513", |
00000207 => x"470000ef", |
00000208 => x"34201473", |
00000209 => x"04045663", |
00000210 => x"00001537", |
00000211 => x"b1c50513", |
00000212 => x"45c000ef", |
00000213 => x"341015f3", |
00000214 => x"00001537", |
00000215 => x"b3450513", |
00000216 => x"44c000ef", |
00000217 => x"00001537", |
00000218 => x"b5450513", |
00000219 => x"440000ef", |
00000220 => x"00b00793", |
00000221 => x"0287e463", |
00000222 => x"00001737", |
00000223 => x"00241793", |
00000224 => x"d6870713", |
00000225 => x"00e787b3", |
00000226 => x"0007a783", |
00000227 => x"00078067", |
00000228 => x"00001537", |
00000229 => x"b2850513", |
00000230 => x"fb9ff06f", |
00000231 => x"800007b7", |
00000232 => x"00778713", |
00000233 => x"10e40c63", |
00000234 => x"00b78713", |
00000235 => x"10e40e63", |
00000236 => x"00378793", |
00000237 => x"0ef40e63", |
00000238 => x"00001537", |
00000239 => x"00040593", |
00000240 => x"cb850513", |
00000241 => x"3e8000ef", |
00000242 => x"0100006f", |
00000243 => x"00001537", |
00000244 => x"b5c50513", |
00000245 => x"3d8000ef", |
00000246 => x"00001537", |
00000247 => x"d5450513", |
00000248 => x"0240006f", |
00000249 => x"00001537", |
00000250 => x"b7c50513", |
00000251 => x"fe9ff06f", |
00000252 => x"00001537", |
00000253 => x"b9850513", |
00000254 => x"3b4000ef", |
00000255 => x"00001537", |
00000256 => x"bac50513", |
00000257 => x"3a8000ef", |
00000258 => x"343015f3", |
00000259 => x"00001537", |
00000260 => x"cc850513", |
00000261 => x"398000ef", |
00000262 => x"34a01473", |
00000263 => x"00001537", |
00000264 => x"00040593", |
00000265 => x"cd050513", |
00000266 => x"00247413", |
00000267 => x"380000ef", |
00000268 => x"0a040263", |
00000269 => x"00001537", |
00000270 => x"cec50513", |
00000271 => x"370000ef", |
00000272 => x"340015f3", |
00000273 => x"00001537", |
00000274 => x"d0450513", |
00000275 => x"360000ef", |
00000276 => x"00812403", |
00000277 => x"00c12083", |
00000278 => x"00001537", |
00000279 => x"d2c50513", |
00000280 => x"01010113", |
00000281 => x"3480006f", |
00000282 => x"00001537", |
00000283 => x"bc450513", |
00000284 => x"f65ff06f", |
00000285 => x"00001537", |
00000286 => x"bd850513", |
00000287 => x"f59ff06f", |
00000288 => x"00001537", |
00000289 => x"bf050513", |
00000290 => x"f4dff06f", |
00000291 => x"00001537", |
00000292 => x"c0450513", |
00000293 => x"f41ff06f", |
00000294 => x"00001537", |
00000295 => x"c2050513", |
00000296 => x"f35ff06f", |
00000297 => x"00001537", |
00000298 => x"c3450513", |
00000299 => x"f29ff06f", |
00000300 => x"00001537", |
00000301 => x"c5050513", |
00000302 => x"f1dff06f", |
00000303 => x"00001537", |
00000304 => x"c6c50513", |
00000305 => x"f11ff06f", |
00000306 => x"00001537", |
00000307 => x"c9050513", |
00000308 => x"f05ff06f", |
00000309 => x"00001537", |
00000310 => x"cf850513", |
00000311 => x"f61ff06f", |
00000312 => x"ff010113", |
00000313 => x"00812423", |
00000314 => x"00912223", |
00000315 => x"00112623", |
00000316 => x"00700793", |
00000317 => x"00050413", |
00000318 => x"00058493", |
00000319 => x"02a7fc63", |
00000320 => x"00b00793", |
00000321 => x"02f50863", |
00000322 => x"01300793", |
00000323 => x"02f50063", |
00000324 => x"01700793", |
00000325 => x"04f50463", |
00000326 => x"01b00793", |
00000327 => x"00100513", |
00000328 => x"02f41463", |
00000329 => x"00b00513", |
00000330 => x"0080006f", |
00000331 => x"00300513", |
00000332 => x"448000ef", |
00000333 => x"fc501573", |
00000334 => x"00241413", |
00000335 => x"00a40433", |
00000336 => x"00942023", |
00000337 => x"00000513", |
00000338 => x"00c12083", |
00000339 => x"00812403", |
00000340 => x"00412483", |
00000341 => x"01010113", |
00000342 => x"00008067", |
00000343 => x"00700513", |
00000344 => x"fd1ff06f", |
00000345 => x"ff010113", |
00000346 => x"00812423", |
00000347 => x"00912223", |
00000348 => x"01212023", |
00000349 => x"00112623", |
00000350 => x"00000413", |
00000351 => x"02000493", |
00000352 => x"00040513", |
00000353 => x"00140413", |
00000354 => x"31400593", |
00000355 => x"0ff47413", |
00000356 => x"f51ff0ef", |
00000357 => x"fe9416e3", |
00000358 => x"00c12083", |
00000359 => x"00812403", |
00000360 => x"00412483", |
00000361 => x"00012903", |
00000362 => x"01010113", |
00000363 => x"00008067", |
00000364 => x"fd010113", |
00000365 => x"02812423", |
00000366 => x"02912223", |
00000367 => x"03212023", |
00000368 => x"01312e23", |
00000369 => x"01412c23", |
00000370 => x"02112623", |
00000371 => x"01512a23", |
00000372 => x"00001a37", |
00000373 => x"00050493", |
00000374 => x"00058413", |
00000375 => x"00058523", |
00000376 => x"00000993", |
00000377 => x"00410913", |
00000378 => x"d98a0a13", |
00000379 => x"00a00593", |
00000380 => x"00048513", |
00000381 => x"468000ef", |
00000382 => x"00aa0533", |
00000383 => x"00054783", |
00000384 => x"01390ab3", |
00000385 => x"00048513", |
00000386 => x"00fa8023", |
00000387 => x"00a00593", |
00000388 => x"404000ef", |
00000389 => x"00198993", |
00000390 => x"00a00793", |
00000391 => x"00050493", |
00000392 => x"fcf996e3", |
00000393 => x"00090693", |
00000394 => x"00900713", |
00000395 => x"03000613", |
00000396 => x"0096c583", |
00000397 => x"00070793", |
00000398 => x"fff70713", |
00000399 => x"01071713", |
00000400 => x"01075713", |
00000401 => x"00c59a63", |
00000402 => x"000684a3", |
00000403 => x"fff68693", |
00000404 => x"fe0710e3", |
00000405 => x"00000793", |
00000406 => x"00f907b3", |
00000407 => x"00000593", |
00000408 => x"0007c703", |
00000409 => x"00070c63", |
00000410 => x"00158693", |
00000411 => x"00b405b3", |
00000412 => x"00e58023", |
00000413 => x"01069593", |
00000414 => x"0105d593", |
00000415 => x"fff78713", |
00000416 => x"02f91863", |
00000417 => x"00b40433", |
00000418 => x"00040023", |
00000419 => x"02c12083", |
00000420 => x"02812403", |
00000421 => x"02412483", |
00000422 => x"02012903", |
00000423 => x"01c12983", |
00000424 => x"01812a03", |
00000425 => x"01412a83", |
00000426 => x"03010113", |
00000427 => x"00008067", |
00000428 => x"00070793", |
00000429 => x"fadff06f", |
00000430 => x"fa002023", |
00000431 => x"fc1016f3", |
00000432 => x"00000713", |
00000433 => x"00151513", |
00000434 => x"04a6f263", |
00000435 => x"000016b7", |
00000436 => x"00000793", |
00000437 => x"ffe68693", |
00000438 => x"04e6e463", |
00000439 => x"00167613", |
00000440 => x"0015f593", |
00000441 => x"01879793", |
00000442 => x"01e61613", |
00000443 => x"00c7e7b3", |
00000444 => x"01d59593", |
00000445 => x"00b7e7b3", |
00000446 => x"00e7e7b3", |
00000447 => x"10000737", |
00000448 => x"00e7e7b3", |
00000449 => x"faf02023", |
00000450 => x"00008067", |
00000451 => x"00170793", |
00000452 => x"01079713", |
00000453 => x"40a686b3", |
00000454 => x"01075713", |
00000455 => x"fadff06f", |
00000456 => x"ffe78513", |
00000457 => x"0fd57513", |
00000458 => x"00051a63", |
00000459 => x"00375713", |
00000460 => x"00178793", |
00000461 => x"0ff7f793", |
00000462 => x"fa1ff06f", |
00000463 => x"00175713", |
00000464 => x"ff1ff06f", |
00000465 => x"fa002783", |
00000466 => x"fe07cee3", |
00000467 => x"faa02223", |
00000468 => x"00008067", |
00000469 => x"ff010113", |
00000470 => x"00812423", |
00000471 => x"01212023", |
00000472 => x"00112623", |
00000473 => x"00912223", |
00000474 => x"00050413", |
00000475 => x"00a00913", |
00000476 => x"00044483", |
00000477 => x"00140413", |
00000478 => x"00049e63", |
00000479 => x"00c12083", |
00000480 => x"00812403", |
00000481 => x"00412483", |
00000482 => x"00012903", |
00000483 => x"01010113", |
00000484 => x"00008067", |
00000485 => x"01249663", |
00000486 => x"00d00513", |
00000487 => x"fa9ff0ef", |
00000488 => x"00048513", |
00000489 => x"fa1ff0ef", |
00000490 => x"fc9ff06f", |
00000491 => x"fa010113", |
00000492 => x"02912a23", |
00000493 => x"04f12a23", |
00000494 => x"000014b7", |
00000495 => x"04410793", |
00000496 => x"02812c23", |
00000497 => x"03212823", |
00000498 => x"03412423", |
00000499 => x"03512223", |
00000500 => x"03612023", |
00000501 => x"01712e23", |
00000502 => x"02112e23", |
00000503 => x"03312623", |
00000504 => x"01812c23", |
00000505 => x"00050413", |
00000506 => x"04b12223", |
00000507 => x"04c12423", |
00000508 => x"04d12623", |
00000509 => x"04e12823", |
00000510 => x"05012c23", |
00000511 => x"05112e23", |
00000512 => x"00f12023", |
00000513 => x"02500a13", |
00000514 => x"00a00a93", |
00000515 => x"07300913", |
00000516 => x"07500b13", |
00000517 => x"07800b93", |
00000518 => x"da448493", |
00000519 => x"00044c03", |
00000520 => x"020c0463", |
00000521 => x"134c1263", |
00000522 => x"00144783", |
00000523 => x"00240993", |
00000524 => x"09278c63", |
00000525 => x"04f96263", |
00000526 => x"06300713", |
00000527 => x"0ae78463", |
00000528 => x"06900713", |
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00000744 => x"74736e69", |
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00000759 => x"64646120", |
00000760 => x"73736572", |
00000761 => x"73696d20", |
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00000764 => x"64616f4c", |
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00000766 => x"20737365", |
00000767 => x"6c756166", |
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00000769 => x"726f7453", |
00000770 => x"64612065", |
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00000788 => x"6863614d", |
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00000798 => x"6e692072", |
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00000802 => x"49544d20", |
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00000824 => x"3a6e6f69", |
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00000830 => x"6d6f6328", |
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00000674 => x"00000020", |
00000675 => x"20515249", |
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00000677 => x"20202020", |
00000678 => x"00000020", |
00000679 => x"20515249", |
00000680 => x"3a49544d", |
00000681 => x"20202020", |
00000682 => x"00000020", |
00000683 => x"20515249", |
00000684 => x"3a49454d", |
00000685 => x"20202020", |
00000686 => x"00000020", |
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00000690 => x"203a4b4f", |
00000691 => x"25202020", |
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00000694 => x"0a692520", |
00000695 => x"0000000a", |
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00000697 => x"214b4f20", |
00000698 => x"0000000a", |
00000699 => x"54534554", |
00000700 => x"49414620", |
00000701 => x"2144454c", |
00000702 => x"0000000a", |
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00000704 => x"37363534", |
00000705 => x"00003938", |
00000706 => x"33323130", |
00000707 => x"37363534", |
00000708 => x"62613938", |
00000709 => x"66656463", |
00000710 => x"0000007f", |
00000711 => x"00008067", |
others => x"00000000" |
); |
|
/rtl/core/neorv32_bootloader_image.vhd
982,7 → 982,7
00000971 => x"4c420a0a", |
00000972 => x"203a5644", |
00000973 => x"206e754a", |
00000974 => x"32203432", |
00000974 => x"32203532", |
00000975 => x"0a303230", |
00000976 => x"3a565748", |
00000977 => x"00002020", |
/rtl/core/neorv32_cpu.vhd
81,7 → 81,8
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true -- implement true random number generator (TRNG)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- global control -- |
168,7 → 169,8
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => IO_TRNG_USE -- implement true random number generator (TRNG)? |
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)? |
) |
port map ( |
-- global control -- |
/rtl/core/neorv32_cpu_alu.vhd
165,7 → 165,7
shifter_unit: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
shift_sreg <= (others => '-'); |
shift_sreg <= (others => '0'); |
shift_cnt <= (others => '0'); |
shift_cmd_ff <= '0'; |
elsif rising_edge(clk_i) then |
241,7 → 241,7
when alu_cmd_and_c => alu_res <= opa and opb; |
when alu_cmd_shift_c => alu_res <= shift_sreg; |
when alu_cmd_slt_c => alu_res <= (others => '0'); alu_res(0) <= cmp_less; |
when others => alu_res <= (others => '-'); -- undefined |
when others => alu_res <= (others => '0'); -- undefined |
end case; |
end process alu_function_mux; |
|
/rtl/core/neorv32_cpu_control.vhd
75,7 → 75,8
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true -- implement true random number generator (TRNG)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- global control -- |
388,7 → 389,7
when funct3_sr_c => alu_operation_v := alu_cmd_shift_c; -- SRL(I) / SRA(I) |
when funct3_or_c => alu_operation_v := alu_cmd_or_c; -- OR(I) |
when funct3_and_c => alu_operation_v := alu_cmd_and_c; -- AND(I) |
when others => alu_operation_v := (others => '-'); -- undefined |
when others => alu_operation_v := (others => '0'); -- undefined |
end case; |
|
-- is rs1 = r0? -- |
903,10 → 904,10
irq_buf <= (others => '0'); |
exc_ack <= (others => '0'); |
irq_ack <= (others => '0'); |
exc_src <= (others => '-'); |
exc_src <= (others => '0'); |
exc_cpu_start <= '0'; |
exc_cause <= (others => '0'); |
mtinst <= (others => '-'); |
mtinst <= (others => '0'); |
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
-- exception buffer: misaligned load/store/instruction address |
1092,10 → 1093,10
mie_msie <= '0'; |
mie_meie <= '0'; |
mie_mtie <= '0'; |
mtvec <= (others => '-'); |
mtval <= (others => '-'); |
mepc <= (others => '-'); |
mip_msip <= '-'; |
mtvec <= (others => '0'); |
mtval <= (others => '0'); |
mepc <= (others => '0'); |
mip_msip <= '0'; |
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
mip_msip <= '0'; |
1134,7 → 1135,7
if (exc_cpu_ack = '1') then -- exception start? |
if (exc_cause(exc_cause_nxt'left) = '1') then -- for INTERRUPTs: mepc = address of next (unclompeted) instruction |
mepc <= pc_reg; |
mtval <= (others => '-'); -- not specified |
mtval <= (others => '0'); -- not specified |
else -- for EXCEPTIONs: mepc = address of next (unclompeted) instruction |
mepc <= pc_backup2_reg; |
if ((exc_src(exception_iaccess_c) or exc_src(exception_ialign_c)) = '1') then -- instruction access error OR misaligned instruction |
1243,15 → 1244,16
csr_rdata_o(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- implement processor-internal instruction memory as ROM |
csr_rdata_o(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- implement processor-internal data memory |
-- |
csr_rdata_o(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)? |
csr_rdata_o(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)? |
csr_rdata_o(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)? |
csr_rdata_o(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)? |
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)? |
csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)? |
csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)? |
csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)? |
csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)? |
csr_rdata_o(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- implement general purpose input/output port unit (GPIO)? |
csr_rdata_o(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- implement machine system timer (MTIME)? |
csr_rdata_o(18) <= bool_to_ulogic_f(IO_UART_USE); -- implement universal asynchronous receiver/transmitter (UART)? |
csr_rdata_o(19) <= bool_to_ulogic_f(IO_SPI_USE); -- implement serial peripheral interface (SPI)? |
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)? |
csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)? |
csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)? |
csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)? |
csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)? |
csr_rdata_o(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)? |
when x"fc1" => -- R/-: mclock - processor clock speed |
csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32)); |
when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space |
/rtl/core/neorv32_cpu_cp_muldiv.vhd
95,12 → 95,12
if (rstn_i = '0') then |
state <= IDLE; |
cp_op <= (others => '0'); |
opx <= (others => '-'); |
opy <= (others => '-'); |
cnt <= (others => '-'); |
start <= '-'; |
opx <= (others => '0'); |
opy <= (others => '0'); |
cnt <= (others => '0'); |
start <= '0'; |
valid_o <= '0'; |
div_res_corr <= '-'; |
div_res_corr <= '0'; |
elsif rising_edge(clk_i) then |
-- defaults -- |
start <= '0'; |
254,7 → 254,7
when cp_op_remu_c => |
res_o <= remainder; |
when others => -- undefined |
res_o <= (others => '-'); |
res_o <= (others => '0'); |
end case; |
end if; |
end process operation_result; |
/rtl/core/neorv32_devnull.vhd
0,0 → 1,115
-- ################################################################################################# |
-- # << NEORV32 - /DEV/NULL (DEVNULL) Dummy Device with Simulation Output >> # |
-- # ********************************************************************************************* # |
-- # In simulation: This unit will output the lowest 8 bit of the written data as ASCII chars # |
-- # to the simulator console and to a text file ("neorv32.devnull.out"). # |
-- # In real hardware: This unit implements a "/dev/null" device. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
use std.textio.all; |
|
entity neorv32_devnull is |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
); |
end neorv32_devnull; |
|
architecture neorv32_devnull_rtl of neorv32_devnull is |
|
-- configuration -- |
constant sim_output_en_c : boolean := true; -- output lowest byte as char to simulator |
|
-- text.io -- |
file file_devnull_out : text open write_mode is "neorv32.devnull.out"; |
|
-- IO space: module base address -- |
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(devnull_size_c); -- low address boundary bit |
|
-- access control -- |
signal acc_en : std_ulogic; -- module access enable |
|
begin |
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = devnull_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
|
|
-- Read/Write Access ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
rw_access: process(clk_i) |
variable i : integer; |
variable la, lb : line; -- we need to variables here since "writeline" seems to flush the source variable |
begin |
if rising_edge(clk_i) then |
ack_o <= acc_en and (wren_i or rden_i); |
if ((acc_en and wren_i and ben_i(0)) = '1') then |
-- print lowest byte as ASCII to console -- |
if (sim_output_en_c = true) then |
i := to_integer(unsigned(data_i(7 downto 0))); |
if (i >= 128) then -- out of range? |
i := 0; |
end if; |
if (i /= 10) and (i /= 13) then -- skip linebreaks |
write(la, character'val(i)); |
write(lb, character'val(i)); |
end if; |
if (i = 10) then -- line break: write to screen and file |
writeline(output, la); |
writeline(file_devnull_out, lb); |
end if; |
end if; |
end if; |
end if; |
end process rw_access; |
|
-- output -- |
data_o <= (others => '0'); |
|
|
end neorv32_devnull_rtl; |
/rtl/core/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - FIXED! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"00000203"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"00000204"; -- no touchy! |
|
-- Internal Functions --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
125,8 → 125,13
|
-- RESERVED -- |
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed! |
--constant ???_size_c : natural := 14*4; -- bytes, fixed! |
--constant ???_size_c : natural := 13*4; -- bytes, fixed! |
|
-- Dummy Device (with SIM output) (DEVNULL) -- |
constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFFC"; -- base address, fixed! |
constant devnull_size_c : natural := 1*4; -- bytes, fixed! |
constant devnull_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(devnull_base_c) + x"00000000"); |
|
-- Main Control Bus ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- register file -- |
361,7 → 366,8
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := false -- implement true random number generator (TRNG)? |
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- Global control -- |
434,7 → 440,8
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true -- implement true random number generator (TRNG)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- global control -- |
631,7 → 638,8
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := true -- implement true random number generator (TRNG)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- global control -- |
941,6 → 949,22
); |
end component; |
|
-- Component: Dummy Device with SIM Output (DEVNULL) ------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_devnull |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic -- transfer acknowledge |
); |
end component; |
|
end neorv32_package; |
|
package body neorv32_package is |
/rtl/core/neorv32_top.vhd
79,7 → 79,8
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := false -- implement true random number generator (TRNG)? |
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- Global control -- |
181,6 → 182,8
signal clic_ack : std_ulogic; |
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal trng_ack : std_ulogic; |
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal devnull_ack : std_ulogic; |
|
-- IRQs -- |
signal mtime_irq : std_ulogic; |
340,7 → 343,8
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => IO_TRNG_USE -- implement true random number generator (TRNG)? |
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)? |
) |
port map ( |
-- global control -- |
362,11 → 366,11
|
-- CPU data input -- |
cpu_rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or |
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata); |
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata); |
|
-- CPU ACK input -- |
cpu_ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or |
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack); |
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack); |
|
-- CPU bus error input -- |
cpu_err <= wishbone_err; |
827,4 → 831,29
end generate; |
|
|
-- Dummy Device (DEVNULL) ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_devnull_inst_true: |
if (IO_DEVNULL_USE = true) generate |
neorv32_devnull_inst: neorv32_devnull |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
addr_i => cpu_addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
ben_i => cpu_ben, -- byte write enable |
data_i => cpu_wdata, -- data in |
data_o => devnull_rdata, -- data out |
ack_o => devnull_ack -- transfer acknowledge |
); |
end generate; |
|
neorv32_devnull_inst_false: |
if (IO_DEVNULL_USE = false) generate |
devnull_rdata <= (others => '0'); |
devnull_ack <= '0'; |
end generate; |
|
|
end neorv32_top_rtl; |
/rtl/core/neorv32_trng.vhd
250,7 → 250,7
case tmp_v is |
when "101" => db_enable <= '1'; db_data <= '1'; -- rising edge -> '1' |
when "110" => db_enable <= '1'; db_data <= '0'; -- falling edge -> '0' |
when others => db_enable <= '0'; db_data <= '-'; -- invalid |
when others => db_enable <= '0'; db_data <= '0'; -- invalid |
end case; |
end process debiasing; |
|
/rtl/top_templates/neorv32_test_setup.vhd
101,7 → 101,8
IO_PWM_USE => false, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => true, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => true, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => false -- implement true random number generator (TRNG)? |
IO_TRNG_USE => false, -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE => true -- implement dummy device (DEVNULL)? |
) |
port map ( |
-- Global control -- |
/sim/ghdl/ghdl_sim.sh
0,0 → 1,60
#!/bin/bash |
|
# Abort if any command returns != 0 |
set -e |
|
# Project home folder |
homedir="$( cd "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )" |
homedir=$homedir/../.. |
|
# The directories of the hw source files |
srcdir_core=$homedir/rtl/core |
srcdir_sim=$homedir/sim |
|
# Show GHDL version |
ghdl -v |
|
# List files |
echo "Simulation source files:" |
ls -al $srcdir_core |
ls -al $srcdir_sim |
|
# Analyse sources; libs and images at first! |
ghdl -a --work=neorv32 $srcdir_core/neorv32_package.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_application_image.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_bootloader_image.vhd |
# |
ghdl -a --work=neorv32 $srcdir_core/neorv32_boot_rom.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_clic.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_alu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_bus.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_control.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_cp_muldiv.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_decompressor.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_regfile.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_devnull.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_dmem.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_gpio.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_imem.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_mtime.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_pwm.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_spi.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_top.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_trng.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_twi.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_uart.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_wdt.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_wishbone.vhd |
# |
ghdl -a --work=neorv32 $srcdir_sim/*.vhd |
|
# Prepare simulation output files |
touch neorv32.testbench_uart.out |
chmod 777 neorv32.testbench_uart.out |
touch neorv32.devnull.out |
chmod 777 neorv32.devnull.out |
|
# Run simulation |
ghdl -e --work=neorv32 neorv32_tb |
ghdl -r --work=neorv32 neorv32_tb --stop-time=4ms --ieee-asserts=disable --assert-level=error |
/sim/neorv32_tb.vhd
1,6 → 1,11
-- ################################################################################################# |
-- # << NEORV32 - Simple Testbench with UART-to-Console module >> # |
-- # << NEORV32 - Simple Testbench >> # |
-- # ********************************************************************************************* # |
-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o # |
-- # signals. The received chars are shown in the simulator console and also written to a file # |
-- # ("neorv32.testbench_uart.out"). # |
-- # Futhermore, this testbench provides a simple RAM connected to the external Wishbone bus. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
52,25 → 57,17
constant f_clock_c : real := 100000000.0; -- main clock in Hz |
constant f_clock_nat_c : natural := 100000000; -- main clock in Hz |
constant baud_rate_c : real := 19200.0; -- standard UART baudrate |
constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address |
constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes |
constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address |
-- ------------------------------------------------------------------------------------------- |
|
-- textio -- |
file file_uart_tx_out : text open write_mode is "neorv32.sim_uart.out"; |
-- text.io -- |
file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out"; |
|
-- internal configuration -- |
constant baud_val_c : real := f_clock_c / baud_rate_c; |
constant f_clk_c : natural := natural(f_clock_c); |
|
-- reduced ASCII table -- |
type ascii_t is array (0 to 94) of character; |
constant ascii_lut : ascii_t := (' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', |
'.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', ';', '<', '=', '>', '?', '@', 'A', |
'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', |
'V', 'W', 'X', 'Y', 'Z', '[', '\', ']', '^', '_', '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', |
'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z', '{', '|', '}', '~'); |
|
-- generators -- |
signal clk_gen, rst_gen : std_ulogic := '0'; |
|
106,12 → 103,14
signal wb_cpu : wishbone_t; |
|
|
-- Wishbone memory -- |
-- Wishbone memory, SimCom -- |
type wb_mem_file_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0); |
signal wb_mem_file : wb_mem_file_t := (others => (others => '0')); |
signal rb_en : std_ulogic; |
signal r_data : std_ulogic_vector(31 downto 0); |
signal wb_acc_en : std_ulogic; |
signal wb_mem_file : wb_mem_file_t := (others => (others => '0')); |
signal rb_en : std_ulogic; |
signal r_data : std_ulogic_vector(31 downto 0); |
signal wb_acc_en : std_ulogic; |
signal wb_mem_rdata : std_ulogic_vector(31 downto 0); |
signal wb_mem_ack : std_ulogic; |
|
begin |
|
158,7 → 157,8
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => true, -- implement watch dog timer (WDT)? |
IO_CLIC_USE => true, -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE => false -- implement true random number generator (TRNG)? |
IO_TRNG_USE => false, -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE => true -- implement dummy device (DEVNULL)? |
) |
port map ( |
-- Global control -- |
195,18 → 195,22
ext_ack_o => open -- external interrupt request acknowledge |
); |
|
-- twi termination -- |
-- TWI termination -- |
twi_scl <= 'H'; |
twi_sda <= 'H'; |
|
-- Wishbone read-back -- |
wb_cpu.rdata <= wb_mem_rdata; |
wb_cpu.ack <= wb_mem_ack; |
wb_cpu.err <= '0'; |
|
|
-- Console UART Receiver ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
uart_rx_console: process(clk_gen) |
variable i, j : integer; |
variable line_tmp : line; |
variable i : integer; |
variable l : line; |
begin |
|
-- "UART" -- |
if rising_edge(clk_gen) then |
-- synchronizer -- |
221,7 → 225,6
end if; |
else |
if (uart_rx_baud_cnt = 0.0) then |
-- adapt to the inter-frame pause - which is not implemented in the neo430 uart ;) |
if (uart_rx_bitcnt = 1) then |
uart_rx_baud_cnt <= round(0.5 * baud_val_c); |
else |
230,21 → 233,17
if (uart_rx_bitcnt = 0) then |
uart_rx_busy <= '0'; -- done |
i := to_integer(unsigned(uart_rx_sreg(8 downto 1))); |
j := i - 32; |
if (j < 0) or (j > 95) then |
j := 0; -- undefined = SPACE |
end if; |
|
if (i < 32) or (j > 32+95) then |
report "UART TX: (" & integer'image(i) & ")"; -- print code |
if (i < 32) or (i > 32+95) then -- printable char? |
report "SIM_UART TX: (" & integer'image(i) & ")"; -- print code |
else |
report "UART TX: " & ascii_lut(j); -- print ASCII |
report "SIM_UART TX: " & character'val(i); -- print ASCII |
end if; |
|
if (i = 10) then -- Linux line break |
writeline(file_uart_tx_out, line_tmp); |
writeline(file_uart_tx_out, l); |
elsif (i /= 13) then -- Remove additional carriage return |
write(line_tmp, ascii_lut(j)); |
write(l, character'val(i)); |
end if; |
else |
uart_rx_sreg <= uart_rx_sync(4) & uart_rx_sreg(8 downto 1); |
264,7 → 263,7
begin |
if rising_edge(clk_gen) then |
rb_en <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en and (not wb_cpu.we); -- read-back control |
wb_cpu.ack <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en; -- wishbone acknowledge |
wb_mem_ack <= wb_cpu.cyc and wb_cpu.stb and wb_acc_en; -- wishbone acknowledge |
if ((wb_cpu.cyc and wb_cpu.stb and wb_acc_en and wb_cpu.we) = '1') then -- valid write access |
for i in 0 to 3 loop |
if (wb_cpu.sel(i) = '1') then |
280,7 → 279,7
wb_acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0'; |
|
-- output gate -- |
wb_cpu.rdata <= r_data when (rb_en = '1') else (others=> '0'); |
wb_cpu.err <= '0'; |
wb_mem_rdata <= r_data when (rb_en = '1') else (others=> '0'); |
|
|
end neorv32_tb_rtl; |
/sw/common/crt0.S
84,6 → 84,8
addi x15, x14, 0 |
|
// the following registers do not exist in rv32e |
// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when |
// compiling for a rv32e architecture |
#ifndef __RISCV_EMBEDDED_CPU__ |
addi x16, x15, 0 |
addi x17, x16, 0 |
/sw/example/hw_analysis/main.c
150,33 → 150,36
neorv32_uart_printf("\n-- Peripherals --\n"); |
tmp = neorv32_cpu_csr_read(CSR_MFEATURES); |
|
neorv32_uart_printf("GPIO: "); |
neorv32_uart_printf("GPIO: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO)); |
|
neorv32_uart_printf("MTIME: "); |
neorv32_uart_printf("MTIME: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME)); |
|
neorv32_uart_printf("UART: "); |
neorv32_uart_printf("UART: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART)); |
|
neorv32_uart_printf("SPI: "); |
neorv32_uart_printf("SPI: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI)); |
|
neorv32_uart_printf("TWI: "); |
neorv32_uart_printf("TWI: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI)); |
|
neorv32_uart_printf("PWM: "); |
neorv32_uart_printf("PWM: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM)); |
|
neorv32_uart_printf("WDT: "); |
neorv32_uart_printf("WDT: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT)); |
|
neorv32_uart_printf("CLIC: "); |
neorv32_uart_printf("CLIC: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC)); |
|
neorv32_uart_printf("TRNG: "); |
neorv32_uart_printf("TRNG: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG)); |
|
neorv32_uart_printf("DEVNULL: "); |
print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL)); |
|
return 0; |
} |
|
/sw/example/test_exceptions/main.c
143,13 → 143,11
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFL; |
neorv32_mtime_set_timecmp(mtime_cmp_max); |
|
#if (DETAILED_EXCEPTION_DEBUG==1) |
// detailed intro |
neorv32_uart_printf("NEORV32 exceptions and interrupts test program: "); |
#endif |
neorv32_uart_printf("NEORV32 EXC TESTS\n"); |
|
// intro |
neorv32_uart_printf("\nNEORV32 exceptions and interrupts test program\n\n"); |
|
|
// install exception handler functions |
int install_err = 0; |
install_err += neorv32_rte_exception_install(EXCID_I_MISALIGNED, exc_handler_i_misalign); |
197,7 → 195,7
// ---------------------------------------------------------- |
// Unaligned instruction address |
// ---------------------------------------------------------- |
neorv32_uart_printf("I_ALIGN: "); |
neorv32_uart_printf("EXC I_ALIGN: "); |
cnt_test++; |
|
// call unaligned address |
219,7 → 217,7
// ---------------------------------------------------------- |
// Instruction access fault |
// ---------------------------------------------------------- |
neorv32_uart_printf("I_ACC: "); |
neorv32_uart_printf("EXC I_ACC: "); |
cnt_test++; |
|
// call unreachable aligned address |
241,7 → 239,7
// ---------------------------------------------------------- |
// Illegal instruction |
// ---------------------------------------------------------- |
neorv32_uart_printf("I_ILLEG: "); |
neorv32_uart_printf("EXC I_ILLEG: "); |
cnt_test++; |
|
// create mini program in RAM |
269,7 → 267,7
// ---------------------------------------------------------- |
// Breakpoint instruction |
// ---------------------------------------------------------- |
neorv32_uart_printf("BREAK: "); |
neorv32_uart_printf("EXC BREAK: "); |
cnt_test++; |
|
asm volatile("EBREAK"); |
290,7 → 288,7
// ---------------------------------------------------------- |
// Unaligned load address |
// ---------------------------------------------------------- |
neorv32_uart_printf("L_ALIGN: "); |
neorv32_uart_printf("EXC L_ALIGN: "); |
cnt_test++; |
|
// load from unaligned address |
312,7 → 310,7
// ---------------------------------------------------------- |
// Load access fault |
// ---------------------------------------------------------- |
neorv32_uart_printf("L_ACC: "); |
neorv32_uart_printf("EXC L_ACC: "); |
cnt_test++; |
|
// load from unreachable aligned address |
334,7 → 332,7
// ---------------------------------------------------------- |
// Unaligned store address |
// ---------------------------------------------------------- |
neorv32_uart_printf("S_ALIGN: "); |
neorv32_uart_printf("EXC S_ALIGN: "); |
cnt_test++; |
|
// store to unaligned address |
356,7 → 354,7
// ---------------------------------------------------------- |
// Store access fault |
// ---------------------------------------------------------- |
neorv32_uart_printf("S_ACC: "); |
neorv32_uart_printf("EXC S_ACC: "); |
cnt_test++; |
|
// store to unreachable aligned address |
378,7 → 376,7
// ---------------------------------------------------------- |
// Environment call |
// ---------------------------------------------------------- |
neorv32_uart_printf("ENVCALL: "); |
neorv32_uart_printf("EXC ENVCALL: "); |
cnt_test++; |
|
asm volatile("ECALL"); |
399,7 → 397,7
// ---------------------------------------------------------- |
// Machine software interrupt |
// ---------------------------------------------------------- |
neorv32_uart_printf("MSI: "); |
neorv32_uart_printf("IRQ MSI: "); |
cnt_test++; |
|
// trigger machine software interrupt |
421,7 → 419,7
// ---------------------------------------------------------- |
// Machine timer interrupt (MTIME) |
// ---------------------------------------------------------- |
neorv32_uart_printf("MTI: "); |
neorv32_uart_printf("IRQ MTI: "); |
cnt_test++; |
|
// force MTIME IRQ |
449,7 → 447,7
// ---------------------------------------------------------- |
// Machine external interrupt (via CLIC) |
// ---------------------------------------------------------- |
neorv32_uart_printf("MEI: "); |
neorv32_uart_printf("IRQ MEI: "); |
cnt_test++; |
|
// manually trigger CLIC channel (watchdog interrupt) |
474,10 → 472,8
#endif |
|
|
#if (DETAILED_EXCEPTION_DEBUG==1) |
// error report |
neorv32_uart_printf("\n\nTests: %i\nOK: %i\nFAIL: %i\n\n", cnt_test, cnt_ok, cnt_fail); |
#endif |
|
// final result |
if (cnt_fail == 0) { |
/sw/lib/include/neorv32.h
144,7 → 144,8
CPU_MFEATURES_IO_PWM = 21, /**< CPU mfeatures CSR (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_USE generic) */ |
CPU_MFEATURES_IO_WDT = 22, /**< CPU mfeatures CSR (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_USE generic) */ |
CPU_MFEATURES_IO_CLIC = 23, /**< CPU mfeatures CSR (23) (r/-): Core-local interrupt controller implemented when 1 (via IO_CLIC_USE generic) */ |
CPU_MFEATURES_IO_TRNG = 24 /**< CPU mfeatures CSR (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */ |
CPU_MFEATURES_IO_TRNG = 24, /**< CPU mfeatures CSR (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_USE generic) */ |
CPU_MFEATURES_IO_DEVNULL = 25 /**< CPU mfeatures CSR (24) (r/-): Dummy device implemented when 1 (via IO_DEVNULL_USE generic) */ |
}; |
|
|
491,6 → 492,15
/**@}*/ |
|
|
/**********************************************************************//** |
* @name IO Device: Dummy Device (DEVNULL) |
**************************************************************************/ |
/**@{*/ |
/** TRNG data register (r/w) */ |
#define DEVNULL_DATA (*(IO_REG32 0xFFFFFFFC)) |
/**@}*/ |
|
|
// ---------------------------------------------------------------------------- |
// Include all IO driver headers |
// ---------------------------------------------------------------------------- |
/sw/lib/source/neorv32_uart.c
130,14 → 130,21
* Send single char via UART. |
* |
* @note This function is blocking. |
* @warning The 'SIMCOM_UART_OVERRIDE' compiler user flag will forward all UART TX data to the SIMCOM simulation console output. |
* |
* @param[in] c Char to be send. |
**************************************************************************/ |
void neorv32_uart_putc(char c) { |
|
#ifdef DEVNULL_UART_OVERRIDE |
#warning UART OVERRIDE! Sending all UART.TX data to DEVNULL simulation output instead of UART transmitter. Use this for simulations only! |
DEVNULL_DATA = (uint32_t)c; |
#else |
// wait for previous transfer to finish |
while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0); |
UART_DATA = ((uint32_t)c) << UART_DATA_LSB; |
#endif |
|
} |
|
|
/.gitignore
10,6 → 10,7
|
# no executables |
sw/image_gen/image_gen |
sw/image_gen/image_gen.exe |
|
# no temp/legacy files/folders |
~* |
/CODE_OF_CONDUCT.md
0,0 → 1,76
# Contributor Covenant Code of Conduct |
|
## Our Pledge |
|
In the interest of fostering an open and welcoming environment, we as |
contributors and maintainers pledge to making participation in our project and |
our community a harassment-free experience for everyone, regardless of age, body |
size, disability, ethnicity, sex characteristics, gender identity and expression, |
level of experience, education, socio-economic status, nationality, personal |
appearance, race, religion, or sexual identity and orientation. |
|
## Our Standards |
|
Examples of behavior that contributes to creating a positive environment |
include: |
|
* Using welcoming and inclusive language |
* Being respectful of differing viewpoints and experiences |
* Gracefully accepting constructive criticism |
* Focusing on what is best for the community |
* Showing empathy towards other community members |
|
Examples of unacceptable behavior by participants include: |
|
* The use of sexualized language or imagery and unwelcome sexual attention or |
advances |
* Trolling, insulting/derogatory comments, and personal or political attacks |
* Public or private harassment |
* Publishing others' private information, such as a physical or electronic |
address, without explicit permission |
* Other conduct which could reasonably be considered inappropriate in a |
professional setting |
|
## Our Responsibilities |
|
Project maintainers are responsible for clarifying the standards of acceptable |
behavior and are expected to take appropriate and fair corrective action in |
response to any instances of unacceptable behavior. |
|
Project maintainers have the right and responsibility to remove, edit, or |
reject comments, commits, code, wiki edits, issues, and other contributions |
that are not aligned to this Code of Conduct, or to ban temporarily or |
permanently any contributor for other behaviors that they deem inappropriate, |
threatening, offensive, or harmful. |
|
## Scope |
|
This Code of Conduct applies both within project spaces and in public spaces |
when an individual is representing the project or its community. Examples of |
representing a project or community include using an official project e-mail |
address, posting via an official social media account, or acting as an appointed |
representative at an online or offline event. Representation of a project may be |
further defined and clarified by project maintainers. |
|
## Enforcement |
|
Instances of abusive, harassing, or otherwise unacceptable behavior may be |
reported by contacting the project team at stnolting@gmail.com. All |
complaints will be reviewed and investigated and will result in a response that |
is deemed necessary and appropriate to the circumstances. The project team is |
obligated to maintain confidentiality with regard to the reporter of an incident. |
Further details of specific enforcement policies may be posted separately. |
|
Project maintainers who do not follow or enforce the Code of Conduct in good |
faith may face temporary or permanent repercussions as determined by other |
members of the project's leadership. |
|
## Attribution |
|
This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, |
available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html |
|
[homepage]: https://www.contributor-covenant.org |
|
For answers to common questions about this code of conduct, see |
https://www.contributor-covenant.org/faq |
/README.md
27,7 → 27,7
|
The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional |
`M`, `C` and `Zicsr` extensions. The CPU was built from scratch and is compliant to the **Unprivileged |
ISA Specification Version 2.1** and the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended |
ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended |
as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller. |
|
The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI, |
55,8 → 55,10
|
|
### Status |
|
 |
|
The processor is synthesizable (tested with Intel Quartus Prime and Lattice Radiant/Synplify) and can successfully execute all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example). |
|
## Features |
|
66,8 → 68,8
|
- RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M` and `Zicsr` extensions |
- GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt)) |
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/Makefile) |
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doygen_makefile_sw) documentation of the software framework |
- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework |
- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc. |
- Fully synchronous design, no latches, no gated clocks |
- Small hardware footprint and high operating frequency |
84,6 → 86,7
- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (PWM) |
- Optional GARO-based true random number generator (TRNG) |
- Optional core-local interrupt controller with 8 channels (CLIC) |
- Optional dummy device (DEVNULL) (can be used for *fast* simulation console output) |
|
|
### CPU Features |
91,26 → 94,26
The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the |
[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf). |
|
RV32I base instruction set (**`I` extension**): |
**RV32I base instruction set** (`I` extension): |
* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND` |
* Branches instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU` |
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW` |
|
Compressed instructions (**`C` extension**): |
**Compressed instructions** (`C` extension): |
* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP` |
* Branches instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ` |
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP` |
* Misc instructions: `C.EBREAK` (only with `Zicsr` extension) |
|
Embedded CPU version (**`E` extension**): |
**Embedded CPU version** (`E` extension): |
* Reduced register file (only the 16 lowest registers) |
* No performance counter CSRs |
|
Integer multiplication and division hardware (**`M` extension**): |
**Integer multiplication and division hardware** (`M` extension): |
* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU` |
* Division instructions: `DIV` `DIVU` `REM` `REMU` |
|
Privileged architecture (**`Zicsr` extension**): |
**Privileged architecture** (`Zicsr` extension): |
* Privilege levels: `M-mode` (Machine mode) |
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI` |
* System instructions: `ECALL` `EBREAK` `MRET` `WFI` |
131,7 → 134,7
* Machine timer interrupt (from MTIME) |
* Machine external interrupt (via CLIC) |
|
General: |
**General**: |
* No hardware support of unaligned accesses (except for instructions in `C` extension that still have to be aligned on 16-bit boundaries) |
* Multi-cycle in-order instruction execution |
|
179,6 → 182,7
| Module | Description | LEs | FFs | Memory bits | DSPs | |
|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:| |
| Boot ROM | Bootloader ROM (4kB) | 3 | 1 | 32 768 | 0 | |
| DEVNULL | Dummy device | 2 | 1 | 0 | 0 | |
| DMEM | Processor-internal data memory (8kB) | 12 | 2 | 65 536 | 0 | |
| GPIO | General purpose input/output ports | 37 | 33 | 0 | 0 | |
| IMEM | Processor-internal instruction memory (16kb) | 7 | 2 | 131 072 | 0 | |
317,7 → 321,8
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)? |
IO_TRNG_USE : boolean := false -- implement true random number generator (TRNG)? |
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)? |
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)? |
); |
port ( |
-- Global control -- |
487,7 → 492,7
|
## Contact |
|
If you have any questions, bug reports, ideas or if you are facing problems with the NEORV32 or want to give some kinf of feedback, open a |
If you have any questions, bug reports, ideas or if you are facing problems with the NEORV32 or want to give some kind of feedback, open a |
[new issue](https://github.com/stnolting/neorv32/issues) or directly drop me a line: |
|
stnolting@gmail.com |