URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk
- from Rev 35 to Rev 36
- ↔ Reverse comparison
Rev 35 → Rev 36
/.ci/hw_check.sh
17,4 → 17,4
cat neorv32.uart.sim_mode.text.out |
|
# Check if reference can be found in output |
grep -qf $homedir/check_reference.out neorv32.uart.sim_mode.text.out && echo "Test successfully completed!" |
grep -qf $homedir/check_reference.out neorv32.uart.sim_mode.text.out && echo "Hardware test completed successfully!" |
/.ci/sw_check.sh
33,4 → 33,4
# Verification reference string |
touch $homedir/check_reference.out |
chmod 777 $homedir/check_reference.out |
echo "TEST OK!" > $homedir/check_reference.out |
echo "CPU TEST COMPLETED SUCCESSFULLY!" > $homedir/check_reference.out |
/docs/figures/neorv32_processor.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/docs/NEORV32.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/rtl/core/neorv32_application_image.vhd
1,5 → 1,5
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin> |
-- Auto-generated memory init file (for APPLICATION) from source file <cpu_test/main.bin> |
|
library ieee; |
use ieee.std_logic_1164.all; |
6,7 → 6,7
|
package neorv32_application_image is |
|
type application_init_image_t is array (0 to 669) of std_ulogic_vector(31 downto 0); |
type application_init_image_t is array (0 to 3656) of std_ulogic_vector(31 downto 0); |
constant application_init_image : application_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
35,648 → 35,3635
00000024 => x"00000e93", |
00000025 => x"00000f13", |
00000026 => x"00000f93", |
00000027 => x"00002537", |
00000028 => x"80050513", |
00000029 => x"30051073", |
00000030 => x"30401073", |
00000031 => x"80002117", |
00000032 => x"f8010113", |
00000033 => x"ffc17113", |
00000034 => x"00010413", |
00000035 => x"80000197", |
00000036 => x"77418193", |
00000037 => x"00000597", |
00000038 => x"08058593", |
00000039 => x"30559073", |
00000040 => x"f8000593", |
00000041 => x"0005a023", |
00000042 => x"00458593", |
00000043 => x"feb01ce3", |
00000044 => x"80000597", |
00000045 => x"f5058593", |
00000046 => x"84018613", |
00000047 => x"00c5d863", |
00000048 => x"00058023", |
00000049 => x"00158593", |
00000050 => x"ff5ff06f", |
00000051 => x"00001597", |
00000052 => x"9a858593", |
00000053 => x"80000617", |
00000054 => x"f2c60613", |
00000055 => x"80000697", |
00000056 => x"f2468693", |
00000057 => x"00d65c63", |
00000058 => x"00058703", |
00000059 => x"00e60023", |
00000060 => x"00158593", |
00000061 => x"00160613", |
00000062 => x"fedff06f", |
00000063 => x"00000513", |
00000064 => x"00000593", |
00000065 => x"05c000ef", |
00000066 => x"30047073", |
00000067 => x"10500073", |
00000068 => x"0000006f", |
00000069 => x"ff810113", |
00000070 => x"00812023", |
00000071 => x"00912223", |
00000072 => x"34202473", |
00000073 => x"02044663", |
00000074 => x"34102473", |
00000075 => x"00041483", |
00000076 => x"0034f493", |
00000077 => x"00240413", |
00000078 => x"34141073", |
00000079 => x"00300413", |
00000080 => x"00941863", |
00000081 => x"34102473", |
00000082 => x"00240413", |
00000083 => x"34141073", |
00000084 => x"00012483", |
00000085 => x"00412403", |
00000086 => x"00810113", |
00000087 => x"30200073", |
00000088 => x"00005537", |
00000089 => x"ff010113", |
00000090 => x"00000613", |
00000091 => x"00000593", |
00000092 => x"b0050513", |
00000093 => x"00112623", |
00000094 => x"00812423", |
00000095 => x"478000ef", |
00000096 => x"568000ef", |
00000097 => x"02050a63", |
00000098 => x"410000ef", |
00000099 => x"78800513", |
00000100 => x"500000ef", |
00000101 => x"00000513", |
00000102 => x"560000ef", |
00000103 => x"00000413", |
00000104 => x"0ff47513", |
00000105 => x"554000ef", |
00000106 => x"0c800513", |
00000107 => x"554000ef", |
00000108 => x"00140413", |
00000109 => x"fedff06f", |
00000110 => x"76400513", |
00000111 => x"4d4000ef", |
00000112 => x"00c12083", |
00000113 => x"00812403", |
00000114 => x"00000513", |
00000115 => x"01010113", |
00000116 => x"00008067", |
00000117 => x"00000000", |
00000118 => x"00000000", |
00000119 => x"00000000", |
00000120 => x"fc010113", |
00000121 => x"02112e23", |
00000122 => x"02512c23", |
00000123 => x"02612a23", |
00000124 => x"02712823", |
00000125 => x"02a12623", |
00000126 => x"02b12423", |
00000127 => x"02c12223", |
00000128 => x"02d12023", |
00000129 => x"00e12e23", |
00000130 => x"00f12c23", |
00000131 => x"01012a23", |
00000132 => x"01112823", |
00000133 => x"01c12623", |
00000134 => x"01d12423", |
00000135 => x"01e12223", |
00000136 => x"01f12023", |
00000137 => x"34102773", |
00000138 => x"34071073", |
00000139 => x"342027f3", |
00000140 => x"0807c663", |
00000141 => x"00071683", |
00000142 => x"00300593", |
00000143 => x"0036f693", |
00000144 => x"00270613", |
00000145 => x"00b69463", |
00000146 => x"00470613", |
00000147 => x"34161073", |
00000148 => x"00b00713", |
00000149 => x"04f77a63", |
00000150 => x"3e800793", |
00000151 => x"000780e7", |
00000152 => x"03c12083", |
00000153 => x"03812283", |
00000154 => x"03412303", |
00000155 => x"03012383", |
00000156 => x"02c12503", |
00000157 => x"02812583", |
00000158 => x"02412603", |
00000159 => x"02012683", |
00000160 => x"01c12703", |
00000161 => x"01812783", |
00000162 => x"01412803", |
00000163 => x"01012883", |
00000164 => x"00c12e03", |
00000165 => x"00812e83", |
00000166 => x"00412f03", |
00000167 => x"00012f83", |
00000168 => x"04010113", |
00000169 => x"30200073", |
00000170 => x"00279793", |
00000171 => x"7a400713", |
00000172 => x"00e787b3", |
00000173 => x"0007a783", |
00000174 => x"00078067", |
00000175 => x"80000737", |
00000176 => x"ffd74713", |
00000177 => x"00e787b3", |
00000178 => x"01000713", |
00000179 => x"f8f766e3", |
00000180 => x"00279793", |
00000181 => x"7d400713", |
00000182 => x"00e787b3", |
00000183 => x"0007a783", |
00000184 => x"00078067", |
00000185 => x"800007b7", |
00000186 => x"0007a783", |
00000187 => x"f71ff06f", |
00000188 => x"800007b7", |
00000189 => x"0047a783", |
00000190 => x"f65ff06f", |
00000191 => x"800007b7", |
00000192 => x"0087a783", |
00000193 => x"f59ff06f", |
00000194 => x"800007b7", |
00000195 => x"00c7a783", |
00000196 => x"f4dff06f", |
00000197 => x"8101a783", |
00000198 => x"f45ff06f", |
00000199 => x"8141a783", |
00000200 => x"f3dff06f", |
00000201 => x"8181a783", |
00000202 => x"f35ff06f", |
00000203 => x"81c1a783", |
00000204 => x"f2dff06f", |
00000205 => x"8201a783", |
00000206 => x"f25ff06f", |
00000207 => x"8241a783", |
00000208 => x"f1dff06f", |
00000209 => x"8281a783", |
00000210 => x"f15ff06f", |
00000211 => x"82c1a783", |
00000212 => x"f0dff06f", |
00000213 => x"8301a783", |
00000214 => x"f05ff06f", |
00000215 => x"8341a783", |
00000216 => x"efdff06f", |
00000217 => x"8381a783", |
00000218 => x"ef5ff06f", |
00000219 => x"83c1a783", |
00000220 => x"eedff06f", |
00000221 => x"00000000", |
00000222 => x"fe010113", |
00000223 => x"01212823", |
00000224 => x"00050913", |
00000225 => x"00001537", |
00000226 => x"00912a23", |
00000227 => x"81850513", |
00000228 => x"000014b7", |
00000229 => x"00812c23", |
00000230 => x"01312623", |
00000231 => x"00112e23", |
00000232 => x"01c00413", |
00000233 => x"2ec000ef", |
00000234 => x"a6448493", |
00000235 => x"ffc00993", |
00000236 => x"008957b3", |
00000237 => x"00f7f793", |
00000238 => x"00f487b3", |
00000239 => x"0007c503", |
00000240 => x"ffc40413", |
00000241 => x"2bc000ef", |
00000242 => x"ff3414e3", |
00000243 => x"01c12083", |
00000244 => x"01812403", |
00000245 => x"01412483", |
00000246 => x"01012903", |
00000247 => x"00c12983", |
00000248 => x"02010113", |
00000249 => x"00008067", |
00000250 => x"00001537", |
00000251 => x"ff010113", |
00000252 => x"81c50513", |
00000253 => x"00112623", |
00000254 => x"00812423", |
00000255 => x"294000ef", |
00000256 => x"34202473", |
00000257 => x"00b00793", |
00000258 => x"0487f463", |
00000259 => x"800007b7", |
00000260 => x"ffd7c793", |
00000261 => x"00f407b3", |
00000262 => x"01000713", |
00000263 => x"00f77e63", |
00000264 => x"00001537", |
00000265 => x"99050513", |
00000266 => x"268000ef", |
00000267 => x"00040513", |
00000268 => x"f49ff0ef", |
00000269 => x"0400006f", |
00000270 => x"00001737", |
00000271 => x"00279793", |
00000272 => x"9bc70713", |
00000273 => x"00e787b3", |
00000274 => x"0007a783", |
00000275 => x"00078067", |
00000276 => x"00001737", |
00000277 => x"00241793", |
00000278 => x"a0070713", |
00000279 => x"00e787b3", |
00000280 => x"0007a783", |
00000281 => x"00078067", |
00000282 => x"00001537", |
00000283 => x"82450513", |
00000284 => x"220000ef", |
00000285 => x"00001537", |
00000286 => x"9a850513", |
00000287 => x"214000ef", |
00000288 => x"34002573", |
00000289 => x"ef5ff0ef", |
00000290 => x"00001537", |
00000291 => x"9b050513", |
00000292 => x"200000ef", |
00000293 => x"34302573", |
00000294 => x"ee1ff0ef", |
00000295 => x"00812403", |
00000296 => x"00c12083", |
00000297 => x"00001537", |
00000298 => x"a5c50513", |
00000299 => x"01010113", |
00000300 => x"1e00006f", |
00000301 => x"00001537", |
00000302 => x"84450513", |
00000303 => x"fb5ff06f", |
00000304 => x"00001537", |
00000305 => x"86050513", |
00000306 => x"fa9ff06f", |
00000307 => x"00001537", |
00000308 => x"87450513", |
00000309 => x"f9dff06f", |
00000310 => x"00001537", |
00000311 => x"88050513", |
00000312 => x"f91ff06f", |
00000313 => x"00001537", |
00000314 => x"89850513", |
00000315 => x"f85ff06f", |
00000316 => x"00001537", |
00000317 => x"8ac50513", |
00000318 => x"f79ff06f", |
00000319 => x"00001537", |
00000320 => x"8c850513", |
00000321 => x"f6dff06f", |
00000322 => x"00001537", |
00000323 => x"8dc50513", |
00000324 => x"f61ff06f", |
00000325 => x"00001537", |
00000326 => x"8f050513", |
00000327 => x"f55ff06f", |
00000328 => x"00001537", |
00000329 => x"90c50513", |
00000330 => x"f49ff06f", |
00000331 => x"00001537", |
00000332 => x"92450513", |
00000333 => x"f3dff06f", |
00000334 => x"00001537", |
00000335 => x"94050513", |
00000336 => x"f31ff06f", |
00000337 => x"00001537", |
00000338 => x"95450513", |
00000339 => x"f25ff06f", |
00000340 => x"00001537", |
00000341 => x"96850513", |
00000342 => x"f19ff06f", |
00000343 => x"00001537", |
00000344 => x"97c50513", |
00000345 => x"f0dff06f", |
00000346 => x"00f00793", |
00000347 => x"02a7e263", |
00000348 => x"800007b7", |
00000349 => x"00078793", |
00000350 => x"00251513", |
00000351 => x"00a78533", |
00000352 => x"3e800793", |
00000353 => x"00f52023", |
00000354 => x"00000513", |
00000355 => x"00008067", |
00000356 => x"00100513", |
00000357 => x"00008067", |
00000358 => x"ff010113", |
00000359 => x"00112623", |
00000360 => x"00812423", |
00000361 => x"00912223", |
00000362 => x"301027f3", |
00000363 => x"00079863", |
00000364 => x"00001537", |
00000365 => x"a3050513", |
00000366 => x"0d8000ef", |
00000367 => x"1e000793", |
00000368 => x"30579073", |
00000369 => x"00000413", |
00000370 => x"01000493", |
00000371 => x"00040513", |
00000372 => x"00140413", |
00000373 => x"0ff47413", |
00000374 => x"f91ff0ef", |
00000375 => x"fe9418e3", |
00000376 => x"00c12083", |
00000377 => x"00812403", |
00000378 => x"00412483", |
00000379 => x"01010113", |
00000380 => x"00008067", |
00000381 => x"fa002023", |
00000382 => x"fe002683", |
00000383 => x"00151513", |
00000384 => x"00000713", |
00000385 => x"04a6f263", |
00000386 => x"000016b7", |
00000387 => x"00000793", |
00000388 => x"ffe68693", |
00000389 => x"04e6e463", |
00000390 => x"00167613", |
00000391 => x"0015f593", |
00000392 => x"01879793", |
00000393 => x"01e61613", |
00000394 => x"00c7e7b3", |
00000395 => x"01d59593", |
00000396 => x"00b7e7b3", |
00000397 => x"00e7e7b3", |
00000398 => x"10000737", |
00000399 => x"00e7e7b3", |
00000400 => x"faf02023", |
00000401 => x"00008067", |
00000402 => x"00170793", |
00000403 => x"01079713", |
00000404 => x"40a686b3", |
00000405 => x"01075713", |
00000406 => x"fadff06f", |
00000407 => x"ffe78513", |
00000408 => x"0fd57513", |
00000409 => x"00051a63", |
00000410 => x"00375713", |
00000411 => x"00178793", |
00000412 => x"0ff7f793", |
00000413 => x"fa1ff06f", |
00000414 => x"00175713", |
00000415 => x"ff1ff06f", |
00000416 => x"fa002783", |
00000417 => x"fe07cee3", |
00000418 => x"faa02223", |
00000419 => x"00008067", |
00000420 => x"ff010113", |
00000421 => x"00812423", |
00000422 => x"01212023", |
00000423 => x"00112623", |
00000424 => x"00912223", |
00000425 => x"00050413", |
00000426 => x"00a00913", |
00000427 => x"00044483", |
00000428 => x"00140413", |
00000429 => x"00049e63", |
00000430 => x"00c12083", |
00000431 => x"00812403", |
00000432 => x"00412483", |
00000433 => x"00012903", |
00000434 => x"01010113", |
00000435 => x"00008067", |
00000436 => x"01249663", |
00000437 => x"00d00513", |
00000438 => x"fa9ff0ef", |
00000439 => x"00048513", |
00000440 => x"fa1ff0ef", |
00000441 => x"fc9ff06f", |
00000442 => x"fe802503", |
00000443 => x"01055513", |
00000444 => x"00157513", |
00000445 => x"00008067", |
00000446 => x"f8a02223", |
00000447 => x"00008067", |
00000448 => x"00050593", |
00000449 => x"fe002503", |
00000450 => x"ff010113", |
00000451 => x"00112623", |
00000452 => x"00f55513", |
00000453 => x"02c000ef", |
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00000456 => x"01010113", |
00000457 => x"00008067", |
00000458 => x"00000013", |
00000459 => x"00000013", |
00000460 => x"00000013", |
00000461 => x"00000013", |
00000462 => x"fff50513", |
00000463 => x"fddff06f", |
00000464 => x"00050613", |
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00000483 => x"676e696b", |
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00000486 => x"7270206f", |
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00000501 => x"0000033c", |
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00000508 => x"00000258", |
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00000510 => x"00000258", |
00000511 => x"00000258", |
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00000521 => x"74736e49", |
00000522 => x"74637572", |
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00000531 => x"206e6f69", |
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00000590 => x"75727265", |
00000591 => x"00007470", |
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00000595 => x"30207470", |
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00000600 => x"31207470", |
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00000610 => x"33207470", |
00000611 => x"00000000", |
00000612 => x"6e6b6e55", |
00000613 => x"206e776f", |
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00003547 => x"202c5954", |
00003548 => x"54454857", |
00003549 => x"20524548", |
00003550 => x"43204e49", |
00003551 => x"52544e4f", |
00003552 => x"2c544341", |
00003553 => x"52545320", |
00003554 => x"20544349", |
00003555 => x"4241494c", |
00003556 => x"54494c49", |
00003557 => x"4f202c59", |
00003558 => x"4f542052", |
00003559 => x"28205452", |
00003560 => x"4c434e49", |
00003561 => x"4e494455", |
00003562 => x"454e0a47", |
00003563 => x"47494c47", |
00003564 => x"45434e45", |
00003565 => x"20524f20", |
00003566 => x"4548544f", |
00003567 => x"53495752", |
00003568 => x"41202945", |
00003569 => x"49534952", |
00003570 => x"4920474e", |
00003571 => x"4e41204e", |
00003572 => x"41572059", |
00003573 => x"554f2059", |
00003574 => x"464f2054", |
00003575 => x"45485420", |
00003576 => x"45535520", |
00003577 => x"20464f20", |
00003578 => x"53494854", |
00003579 => x"464f5320", |
00003580 => x"52415754", |
00003581 => x"45202c45", |
00003582 => x"204e4556", |
00003583 => x"41204649", |
00003584 => x"53495644", |
00003585 => x"4f0a4445", |
00003586 => x"48542046", |
00003587 => x"4f502045", |
00003588 => x"42495353", |
00003589 => x"54494c49", |
00003590 => x"464f2059", |
00003591 => x"43555320", |
00003592 => x"41442048", |
00003593 => x"4547414d", |
00003594 => x"540a0a2e", |
00003595 => x"4e206568", |
00003596 => x"56524f45", |
00003597 => x"50203233", |
00003598 => x"65636f72", |
00003599 => x"726f7373", |
00003600 => x"68202d20", |
00003601 => x"73707474", |
00003602 => x"672f2f3a", |
00003603 => x"75687469", |
00003604 => x"6f632e62", |
00003605 => x"74732f6d", |
00003606 => x"746c6f6e", |
00003607 => x"2f676e69", |
00003608 => x"726f656e", |
00003609 => x"20323376", |
00003610 => x"20296328", |
00003611 => x"70657453", |
00003612 => x"206e6168", |
00003613 => x"746c6f4e", |
00003614 => x"0a676e69", |
00003615 => x"00000a0a", |
00003616 => x"33323130", |
00003617 => x"37363534", |
00003618 => x"42413938", |
00003619 => x"46454443", |
00003620 => x"00001e38", |
00003621 => x"00001d14", |
00003622 => x"00001d14", |
00003623 => x"00001d14", |
00003624 => x"00001d14", |
00003625 => x"00001d14", |
00003626 => x"00001df4", |
00003627 => x"00001d14", |
00003628 => x"00001d14", |
00003629 => x"00001d14", |
00003630 => x"00001d14", |
00003631 => x"00001d14", |
00003632 => x"00001d14", |
00003633 => x"00001d14", |
00003634 => x"00001d14", |
00003635 => x"00001d14", |
00003636 => x"00001dc8", |
00003637 => x"00001d14", |
00003638 => x"00001d94", |
00003639 => x"00001d14", |
00003640 => x"00001d14", |
00003641 => x"00001d44", |
00003642 => x"33323130", |
00003643 => x"37363534", |
00003644 => x"00003938", |
00003645 => x"33323130", |
00003646 => x"37363534", |
00003647 => x"62613938", |
00003648 => x"66656463", |
00003649 => x"00000000", |
00003650 => x"00006073", |
00003651 => x"00008067", |
00003652 => x"3407d073", |
00003653 => x"00008067", |
00003654 => x"00000001", |
00003655 => x"00008067", |
others => x"00000000" |
); |
|
/rtl/core/neorv32_bootloader_image.vhd
6,7 → 6,7
|
package neorv32_bootloader_image is |
|
type bootloader_init_image_t is array (0 to 1022) of std_ulogic_vector(31 downto 0); |
type bootloader_init_image_t is array (0 to 1018) of std_ulogic_vector(31 downto 0); |
constant bootloader_init_image : bootloader_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
44,7 → 44,7
00000033 => x"00158593", |
00000034 => x"ff5ff06f", |
00000035 => x"00001597", |
00000036 => x"f6c58593", |
00000036 => x"f5c58593", |
00000037 => x"80010617", |
00000038 => x"f6c60613", |
00000039 => x"80010697", |
94,942 → 94,938
00000083 => x"01712623", |
00000084 => x"01812423", |
00000085 => x"9ff78793", |
00000086 => x"00000713", |
00000087 => x"00000693", |
00000088 => x"00000613", |
00000089 => x"00000593", |
00000090 => x"00200513", |
00000091 => x"0087f463", |
00000092 => x"00400513", |
00000093 => x"3b5000ef", |
00000094 => x"00005537", |
00000095 => x"00000613", |
00000096 => x"00000593", |
00000097 => x"b0050513", |
00000098 => x"291000ef", |
00000099 => x"249000ef", |
00000100 => x"00245793", |
00000101 => x"00a78533", |
00000102 => x"00f537b3", |
00000103 => x"00b785b3", |
00000104 => x"261000ef", |
00000105 => x"ffff07b7", |
00000106 => x"49478793", |
00000107 => x"30579073", |
00000108 => x"08000793", |
00000109 => x"30479073", |
00000110 => x"30046073", |
00000111 => x"00100513", |
00000112 => x"429000ef", |
00000113 => x"ffff1537", |
00000114 => x"800007b7", |
00000115 => x"f1450513", |
00000116 => x"0007a023", |
00000117 => x"2fd000ef", |
00000118 => x"159000ef", |
00000119 => x"ffff1537", |
00000120 => x"f4c50513", |
00000121 => x"2ed000ef", |
00000122 => x"fe002503", |
00000123 => x"238000ef", |
00000124 => x"ffff1537", |
00000125 => x"f5450513", |
00000126 => x"2d9000ef", |
00000127 => x"fe402503", |
00000128 => x"224000ef", |
00000129 => x"ffff1537", |
00000130 => x"f6050513", |
00000131 => x"2c5000ef", |
00000132 => x"30102573", |
00000133 => x"210000ef", |
00000134 => x"ffff1537", |
00000135 => x"f6850513", |
00000136 => x"2b1000ef", |
00000137 => x"fe802503", |
00000138 => x"ffff14b7", |
00000139 => x"00341413", |
00000140 => x"1f4000ef", |
00000141 => x"ffff1537", |
00000142 => x"f7050513", |
00000143 => x"295000ef", |
00000144 => x"ff802503", |
00000145 => x"1e0000ef", |
00000146 => x"f7848513", |
00000147 => x"285000ef", |
00000148 => x"ff002503", |
00000149 => x"1d0000ef", |
00000150 => x"ffff1537", |
00000151 => x"f8450513", |
00000152 => x"271000ef", |
00000153 => x"ffc02503", |
00000154 => x"1bc000ef", |
00000155 => x"f7848513", |
00000156 => x"261000ef", |
00000157 => x"ff402503", |
00000158 => x"1ac000ef", |
00000159 => x"ffff1537", |
00000160 => x"f8c50513", |
00000161 => x"24d000ef", |
00000162 => x"14d000ef", |
00000163 => x"00a404b3", |
00000164 => x"0084b433", |
00000165 => x"00b40433", |
00000166 => x"fa402783", |
00000167 => x"0207d263", |
00000168 => x"ffff1537", |
00000169 => x"fb450513", |
00000170 => x"229000ef", |
00000171 => x"219000ef", |
00000172 => x"02300793", |
00000173 => x"02f51263", |
00000174 => x"00000513", |
00000175 => x"0180006f", |
00000176 => x"115000ef", |
00000177 => x"fc85eae3", |
00000178 => x"00b41463", |
00000179 => x"fc9566e3", |
00000180 => x"00100513", |
00000181 => x"5b4000ef", |
00000182 => x"0b4000ef", |
00000183 => x"ffff1937", |
00000184 => x"ffff19b7", |
00000185 => x"02300a13", |
00000186 => x"07200a93", |
00000187 => x"06800b13", |
00000188 => x"07500b93", |
00000189 => x"ffff14b7", |
00000190 => x"ffff1c37", |
00000191 => x"fc090513", |
00000192 => x"1d1000ef", |
00000193 => x"1b1000ef", |
00000194 => x"00050413", |
00000195 => x"199000ef", |
00000196 => x"ecc98513", |
00000197 => x"1bd000ef", |
00000198 => x"fb4400e3", |
00000199 => x"01541863", |
00000200 => x"ffff02b7", |
00000201 => x"00028067", |
00000202 => x"fd5ff06f", |
00000203 => x"01641663", |
00000204 => x"05c000ef", |
00000205 => x"fc9ff06f", |
00000206 => x"00000513", |
00000207 => x"03740063", |
00000208 => x"07300793", |
00000209 => x"00f41663", |
00000210 => x"66c000ef", |
00000211 => x"fb1ff06f", |
00000212 => x"06c00793", |
00000213 => x"00f41863", |
00000214 => x"00100513", |
00000215 => x"3f0000ef", |
00000216 => x"f9dff06f", |
00000217 => x"06500793", |
00000218 => x"00f41663", |
00000219 => x"02c000ef", |
00000220 => x"f8dff06f", |
00000221 => x"03f00793", |
00000222 => x"fc8c0513", |
00000223 => x"00f40463", |
00000224 => x"fdc48513", |
00000225 => x"14d000ef", |
00000226 => x"f75ff06f", |
00000227 => x"ffff1537", |
00000228 => x"df050513", |
00000229 => x"13d0006f", |
00000230 => x"800007b7", |
00000231 => x"0007a783", |
00000232 => x"00079863", |
00000233 => x"ffff1537", |
00000234 => x"e5450513", |
00000235 => x"1250006f", |
00000236 => x"ff010113", |
00000237 => x"00112623", |
00000238 => x"30047073", |
00000239 => x"ffff1537", |
00000240 => x"e7050513", |
00000241 => x"10d000ef", |
00000242 => x"fa002783", |
00000243 => x"fe07cee3", |
00000244 => x"b0001073", |
00000245 => x"b8001073", |
00000246 => x"b0201073", |
00000247 => x"b8201073", |
00000248 => x"ff002783", |
00000249 => x"00078067", |
00000250 => x"0000006f", |
00000251 => x"ff010113", |
00000252 => x"00812423", |
00000253 => x"00050413", |
00000254 => x"ffff1537", |
00000255 => x"e8050513", |
00000256 => x"00112623", |
00000257 => x"0cd000ef", |
00000258 => x"03040513", |
00000259 => x"0ff57513", |
00000260 => x"095000ef", |
00000261 => x"30047073", |
00000262 => x"00100513", |
00000263 => x"1cd000ef", |
00000264 => x"0000006f", |
00000265 => x"fe010113", |
00000266 => x"01212823", |
00000267 => x"00050913", |
00000268 => x"ffff1537", |
00000269 => x"00912a23", |
00000270 => x"e9850513", |
00000271 => x"ffff14b7", |
00000272 => x"00812c23", |
00000273 => x"01312623", |
00000274 => x"00112e23", |
00000275 => x"01c00413", |
00000276 => x"081000ef", |
00000277 => x"fe848493", |
00000278 => x"ffc00993", |
00000279 => x"008957b3", |
00000280 => x"00f7f793", |
00000281 => x"00f487b3", |
00000282 => x"0007c503", |
00000283 => x"ffc40413", |
00000284 => x"035000ef", |
00000285 => x"ff3414e3", |
00000286 => x"01c12083", |
00000287 => x"01812403", |
00000288 => x"01412483", |
00000289 => x"01012903", |
00000290 => x"00c12983", |
00000291 => x"02010113", |
00000292 => x"00008067", |
00000293 => x"fb010113", |
00000294 => x"04112623", |
00000295 => x"04512423", |
00000296 => x"04612223", |
00000297 => x"04712023", |
00000298 => x"02812e23", |
00000299 => x"02a12c23", |
00000300 => x"02b12a23", |
00000301 => x"02c12823", |
00000302 => x"02d12623", |
00000303 => x"02e12423", |
00000304 => x"02f12223", |
00000305 => x"03012023", |
00000306 => x"01112e23", |
00000307 => x"01c12c23", |
00000308 => x"01d12a23", |
00000309 => x"01e12823", |
00000310 => x"01f12623", |
00000311 => x"34202473", |
00000312 => x"800007b7", |
00000313 => x"00778793", |
00000314 => x"06f41a63", |
00000315 => x"00000513", |
00000316 => x"0dd000ef", |
00000317 => x"6e0000ef", |
00000318 => x"fe002783", |
00000319 => x"0027d793", |
00000320 => x"00a78533", |
00000321 => x"00f537b3", |
00000322 => x"00b785b3", |
00000323 => x"6f4000ef", |
00000324 => x"03c12403", |
00000325 => x"04c12083", |
00000326 => x"04812283", |
00000327 => x"04412303", |
00000328 => x"04012383", |
00000329 => x"03812503", |
00000330 => x"03412583", |
00000331 => x"03012603", |
00000332 => x"02c12683", |
00000333 => x"02812703", |
00000334 => x"02412783", |
00000335 => x"02012803", |
00000336 => x"01c12883", |
00000337 => x"01812e03", |
00000338 => x"01412e83", |
00000339 => x"01012f03", |
00000340 => x"00c12f83", |
00000341 => x"05010113", |
00000342 => x"30200073", |
00000343 => x"00700793", |
00000344 => x"00100513", |
00000345 => x"02f40863", |
00000346 => x"ffff1537", |
00000347 => x"e8c50513", |
00000348 => x"760000ef", |
00000349 => x"00040513", |
00000350 => x"eadff0ef", |
00000351 => x"ffff1537", |
00000352 => x"e9450513", |
00000353 => x"74c000ef", |
00000354 => x"34102573", |
00000355 => x"e99ff0ef", |
00000356 => x"00500513", |
00000357 => x"e59ff0ef", |
00000358 => x"ff010113", |
00000359 => x"00000513", |
00000360 => x"00112623", |
00000361 => x"00812423", |
00000362 => x"7cc000ef", |
00000363 => x"00500513", |
00000364 => x"009000ef", |
00000365 => x"00000513", |
00000366 => x"001000ef", |
00000367 => x"00050413", |
00000368 => x"00000513", |
00000369 => x"7d0000ef", |
00000370 => x"00c12083", |
00000371 => x"0ff47513", |
00000372 => x"00812403", |
00000373 => x"01010113", |
00000374 => x"00008067", |
00000375 => x"ff010113", |
00000376 => x"00000513", |
00000377 => x"00112623", |
00000378 => x"00812423", |
00000379 => x"788000ef", |
00000380 => x"09e00513", |
00000381 => x"7c4000ef", |
00000382 => x"00000513", |
00000383 => x"7bc000ef", |
00000384 => x"00050413", |
00000385 => x"00000513", |
00000386 => x"78c000ef", |
00000387 => x"00c12083", |
00000388 => x"0ff47513", |
00000389 => x"00812403", |
00000390 => x"01010113", |
00000391 => x"00008067", |
00000392 => x"ff010113", |
00000393 => x"00000513", |
00000394 => x"00112623", |
00000395 => x"748000ef", |
00000396 => x"00600513", |
00000397 => x"784000ef", |
00000398 => x"00c12083", |
00000399 => x"00000513", |
00000400 => x"01010113", |
00000401 => x"7500006f", |
00000402 => x"ff010113", |
00000403 => x"00812423", |
00000404 => x"00050413", |
00000405 => x"01055513", |
00000406 => x"0ff57513", |
00000407 => x"00112623", |
00000408 => x"758000ef", |
00000409 => x"00845513", |
00000410 => x"0ff57513", |
00000411 => x"74c000ef", |
00000412 => x"0ff47513", |
00000413 => x"00812403", |
00000414 => x"00c12083", |
00000415 => x"01010113", |
00000416 => x"7380006f", |
00000417 => x"ff010113", |
00000418 => x"00812423", |
00000419 => x"00050413", |
00000420 => x"00000513", |
00000421 => x"00112623", |
00000422 => x"6dc000ef", |
00000423 => x"00300513", |
00000424 => x"718000ef", |
00000425 => x"00040513", |
00000426 => x"fa1ff0ef", |
00000427 => x"00000513", |
00000428 => x"708000ef", |
00000429 => x"00050413", |
00000430 => x"00000513", |
00000431 => x"6d8000ef", |
00000432 => x"00c12083", |
00000433 => x"0ff47513", |
00000434 => x"00812403", |
00000435 => x"01010113", |
00000436 => x"00008067", |
00000437 => x"fd010113", |
00000438 => x"02812423", |
00000439 => x"02912223", |
00000440 => x"03212023", |
00000441 => x"01312e23", |
00000442 => x"01412c23", |
00000443 => x"02112623", |
00000444 => x"00050913", |
00000445 => x"00058993", |
00000446 => x"00c10493", |
00000447 => x"00000413", |
00000448 => x"00400a13", |
00000449 => x"02091e63", |
00000450 => x"5ac000ef", |
00000451 => x"00a481a3", |
00000452 => x"00140413", |
00000453 => x"fff48493", |
00000454 => x"ff4416e3", |
00000455 => x"02c12083", |
00000456 => x"02812403", |
00000457 => x"00c12503", |
00000458 => x"02412483", |
00000459 => x"02012903", |
00000460 => x"01c12983", |
00000461 => x"01812a03", |
00000462 => x"03010113", |
00000463 => x"00008067", |
00000464 => x"00898533", |
00000465 => x"f41ff0ef", |
00000466 => x"fc5ff06f", |
00000467 => x"fe802783", |
00000468 => x"fd010113", |
00000469 => x"02812423", |
00000470 => x"02112623", |
00000471 => x"02912223", |
00000472 => x"03212023", |
00000473 => x"01312e23", |
00000474 => x"01412c23", |
00000475 => x"01512a23", |
00000476 => x"01612823", |
00000477 => x"01712623", |
00000478 => x"0087f793", |
00000479 => x"00050413", |
00000480 => x"00078a63", |
00000481 => x"fe802783", |
00000482 => x"00400513", |
00000483 => x"0047f793", |
00000484 => x"04079663", |
00000485 => x"02041863", |
00000486 => x"ffff1537", |
00000487 => x"e9c50513", |
00000488 => x"530000ef", |
00000489 => x"008005b7", |
00000490 => x"00040513", |
00000491 => x"f29ff0ef", |
00000492 => x"4788d7b7", |
00000493 => x"afe78793", |
00000494 => x"02f50463", |
00000495 => x"00000513", |
00000496 => x"01c0006f", |
00000497 => x"ffff1537", |
00000498 => x"ebc50513", |
00000499 => x"504000ef", |
00000500 => x"e0dff0ef", |
00000501 => x"fc0518e3", |
00000502 => x"00300513", |
00000503 => x"c11ff0ef", |
00000504 => x"008009b7", |
00000505 => x"00498593", |
00000506 => x"00040513", |
00000507 => x"ee9ff0ef", |
00000508 => x"00050a13", |
00000509 => x"00898593", |
00000510 => x"00040513", |
00000511 => x"ed9ff0ef", |
00000512 => x"ff002b83", |
00000513 => x"00050a93", |
00000514 => x"ffca7b13", |
00000515 => x"00000913", |
00000516 => x"00000493", |
00000517 => x"00c98993", |
00000518 => x"013905b3", |
00000519 => x"052b1863", |
00000520 => x"015484b3", |
00000521 => x"00200513", |
00000522 => x"fa049ae3", |
00000523 => x"ffff1537", |
00000524 => x"ec850513", |
00000525 => x"49c000ef", |
00000526 => x"02c12083", |
00000527 => x"02812403", |
00000528 => x"800007b7", |
00000529 => x"0147a023", |
00000530 => x"02412483", |
00000531 => x"02012903", |
00000532 => x"01c12983", |
00000533 => x"01812a03", |
00000534 => x"01412a83", |
00000535 => x"01012b03", |
00000536 => x"00c12b83", |
00000537 => x"03010113", |
00000538 => x"00008067", |
00000539 => x"00040513", |
00000540 => x"e65ff0ef", |
00000541 => x"012b87b3", |
00000542 => x"00a484b3", |
00000543 => x"00a7a023", |
00000544 => x"00490913", |
00000545 => x"f95ff06f", |
00000546 => x"ff010113", |
00000547 => x"00112623", |
00000548 => x"ebdff0ef", |
00000549 => x"ffff1537", |
00000550 => x"ecc50513", |
00000551 => x"434000ef", |
00000552 => x"af9ff0ef", |
00000553 => x"0000006f", |
00000554 => x"ff010113", |
00000555 => x"00112623", |
00000556 => x"00812423", |
00000557 => x"00912223", |
00000558 => x"00058413", |
00000559 => x"00050493", |
00000560 => x"d61ff0ef", |
00000561 => x"00000513", |
00000562 => x"4ac000ef", |
00000563 => x"00200513", |
00000564 => x"4e8000ef", |
00000565 => x"00048513", |
00000566 => x"d71ff0ef", |
00000567 => x"00040513", |
00000568 => x"4d8000ef", |
00000569 => x"00000513", |
00000570 => x"4ac000ef", |
00000571 => x"cadff0ef", |
00000572 => x"00157513", |
00000573 => x"fe051ce3", |
00000574 => x"00c12083", |
00000575 => x"00812403", |
00000576 => x"00412483", |
00000577 => x"01010113", |
00000578 => x"00008067", |
00000579 => x"fe010113", |
00000580 => x"00812c23", |
00000581 => x"00912a23", |
00000582 => x"01212823", |
00000583 => x"00112e23", |
00000584 => x"00b12623", |
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00001014 => x"0000676e", |
00001015 => x"61766e49", |
00001016 => x"2064696c", |
00001017 => x"00444d43", |
00001018 => x"33323130", |
00001019 => x"37363534", |
00001020 => x"42413938", |
00001021 => x"46454443", |
00000924 => x"52450a07", |
00000925 => x"5f524f52", |
00000926 => x"00000000", |
00000927 => x"58450a0a", |
00000928 => x"00282043", |
00000929 => x"20402029", |
00000930 => x"00007830", |
00000931 => x"69617741", |
00000932 => x"676e6974", |
00000933 => x"6f656e20", |
00000934 => x"32337672", |
00000935 => x"6578655f", |
00000936 => x"6e69622e", |
00000937 => x"202e2e2e", |
00000938 => x"00000000", |
00000939 => x"64616f4c", |
00000940 => x"2e676e69", |
00000941 => x"00202e2e", |
00000942 => x"00004b4f", |
00000943 => x"0000000a", |
00000944 => x"74697257", |
00000945 => x"78302065", |
00000946 => x"00000000", |
00000947 => x"74796220", |
00000948 => x"74207365", |
00000949 => x"5053206f", |
00000950 => x"6c662049", |
00000951 => x"20687361", |
00000952 => x"78302040", |
00000953 => x"00000000", |
00000954 => x"7928203f", |
00000955 => x"20296e2f", |
00000956 => x"00000000", |
00000957 => x"616c460a", |
00000958 => x"6e696873", |
00000959 => x"2e2e2e67", |
00000960 => x"00000020", |
00000961 => x"0a0a0a0a", |
00000962 => x"4e203c3c", |
00000963 => x"56524f45", |
00000964 => x"42203233", |
00000965 => x"6c746f6f", |
00000966 => x"6564616f", |
00000967 => x"3e3e2072", |
00000968 => x"4c420a0a", |
00000969 => x"203a5644", |
00000970 => x"20766f4e", |
00000971 => x"32203320", |
00000972 => x"0a303230", |
00000973 => x"3a565748", |
00000974 => x"00002020", |
00000975 => x"4b4c430a", |
00000976 => x"0020203a", |
00000977 => x"0a7a4820", |
00000978 => x"52455355", |
00000979 => x"0000203a", |
00000980 => x"53494d0a", |
00000981 => x"00203a41", |
00000982 => x"4f52500a", |
00000983 => x"00203a43", |
00000984 => x"454d490a", |
00000985 => x"00203a4d", |
00000986 => x"74796220", |
00000987 => x"40207365", |
00000988 => x"00000020", |
00000989 => x"454d440a", |
00000990 => x"00203a4d", |
00000991 => x"75410a0a", |
00000992 => x"6f626f74", |
00000993 => x"6920746f", |
00000994 => x"7338206e", |
00000995 => x"7250202e", |
00000996 => x"20737365", |
00000997 => x"2079656b", |
00000998 => x"61206f74", |
00000999 => x"74726f62", |
00001000 => x"00000a2e", |
00001001 => x"726f6241", |
00001002 => x"2e646574", |
00001003 => x"00000a0a", |
00001004 => x"444d430a", |
00001005 => x"00203e3a", |
00001006 => x"53207962", |
00001007 => x"68706574", |
00001008 => x"4e206e61", |
00001009 => x"69746c6f", |
00001010 => x"0000676e", |
00001011 => x"61766e49", |
00001012 => x"2064696c", |
00001013 => x"00444d43", |
00001014 => x"33323130", |
00001015 => x"37363534", |
00001016 => x"42413938", |
00001017 => x"46454443", |
others => x"00000000" |
); |
|
/rtl/core/neorv32_busswitch.vhd
72,6 → 72,7
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus -- |
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B |
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
188,6 → 189,8
arbiter.bus_sel <= '0'; |
arbiter.we_trig <= '0'; |
arbiter.re_trig <= '0'; |
-- |
p_bus_src_o <= '0'; |
|
-- state machine -- |
case arbiter.state is |
194,6 → 197,7
|
when IDLE => -- Controller a has full bus access |
-- ------------------------------------------------------------ |
p_bus_src_o <= '0'; -- access from port A |
if (ca_req_current = '1') then -- current request? |
arbiter.bus_sel <= '0'; |
arbiter.state_nxt <= BUSY; |
210,6 → 214,7
|
when BUSY => -- transaction in progress |
-- ------------------------------------------------------------ |
p_bus_src_o <= '0'; -- access from port A |
arbiter.bus_sel <= '0'; |
if (ca_bus_cancel_i = '1') or -- controller cancels access |
(p_bus_err_i = '1') or -- peripheral cancels access |
219,6 → 224,7
|
when RETIRE => -- retire pending access |
-- ------------------------------------------------------------ |
p_bus_src_o <= '0'; -- access from port A |
arbiter.bus_sel <= '0'; |
if (PORT_CA_READ_ONLY = false) then |
arbiter.we_trig <= ca_wr_req_buf; |
228,6 → 234,7
|
when BUSY_SWITCHED => -- switched transaction in progress |
-- ------------------------------------------------------------ |
p_bus_src_o <= '1'; -- access from port B |
arbiter.bus_sel <= '1'; |
if (cb_bus_cancel_i = '1') or -- controller cancels access |
(p_bus_err_i = '1') or -- peripheral cancels access |
237,6 → 244,7
|
when RETIRE_SWITCHED => -- retire pending switched access |
-- ------------------------------------------------------------ |
p_bus_src_o <= '1'; -- access from port B |
arbiter.bus_sel <= '1'; |
if (PORT_CB_READ_ONLY = false) then |
arbiter.we_trig <= cb_wr_req_buf; |
250,14 → 258,14
|
-- Peripheral Bus Switch ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
p_bus_addr_o <= ca_bus_addr_i when (arbiter.bus_sel = '0') else cb_bus_addr_i; |
p_bus_wdata_o <= cb_bus_wdata_i when (PORT_CA_READ_ONLY = true) else ca_bus_wdata_i when (PORT_CB_READ_ONLY = true) else |
ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i; |
p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else |
ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i; |
p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i; |
p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i; |
p_bus_cancel_o <= ca_bus_cancel_i when (arbiter.bus_sel = '0') else cb_bus_cancel_i; |
p_bus_addr_o <= ca_bus_addr_i when (arbiter.bus_sel = '0') else cb_bus_addr_i; |
p_bus_wdata_o <= cb_bus_wdata_i when (PORT_CA_READ_ONLY = true) else ca_bus_wdata_i when (PORT_CB_READ_ONLY = true) else |
ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i; |
p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else |
ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i; |
p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i; |
p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i; |
p_bus_cancel_o <= ca_bus_cancel_i when (arbiter.bus_sel = '0') else cb_bus_cancel_i; |
p_bus_we_o <= (p_bus_we or arbiter.we_trig); |
p_bus_re_o <= (p_bus_re or arbiter.re_trig); |
|
/rtl/core/neorv32_cpu.vhd
2,13 → 2,13
-- # << NEORV32 - CPU Top Entity >> # |
-- # ********************************************************************************************* # |
-- # NEORV32 CPU: # |
-- # * neorv32_cpu.vhd : CPU top entity # |
-- # * neorv32_cpu_alu.vhd : Arithmetic/logic unit # |
-- # * neorv32_cpu_bus.vhd : Instruction and data bus interface unit # |
-- # * neorv32_cpu_cp_muldiv.vhd : MULDIV co-processor # |
-- # * neorv32_cpu_ctrl.vhd : CPU control and CSR system # |
-- # * neorv32_cpu_decompressor.vhd : Compressed instructions decoder # |
-- # * neorv32_cpu_regfile.vhd : Data register file # |
-- # * neorv32_cpu.vhd - CPU top entity # |
-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit # |
-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit # |
-- # * neorv32_cpu_cp_muldiv.vhd - MULDIV co-processor # |
-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system # |
-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder # |
-- # * neorv32_cpu_regfile.vhd - Data register file # |
-- # # |
-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf # |
-- # ********************************************************************************************* # |
117,7 → 117,9
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction |
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers |
signal alu_opb : std_ulogic_vector(data_width_c-1 downto 0); -- ALU operand b |
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result |
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result |
signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data |
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit |
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch |
135,14 → 137,13
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next to-be-executed instruction) |
|
-- co-processor interface -- |
signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0); |
signal cp0_valid, cp1_valid : std_ulogic; |
signal cp0_start, cp1_start : std_ulogic; |
signal cp0_data, cp1_data, cp2_data, cp3_data : std_ulogic_vector(data_width_c-1 downto 0); |
signal cp0_valid, cp1_valid, cp2_valid, cp3_valid : std_ulogic; |
signal cp0_start, cp1_start, cp2_start, cp3_start : std_ulogic; |
|
-- pmp interface -- |
signal pmp_addr : pmp_addr_if_t; |
signal pmp_ctrl : pmp_ctrl_if_t; |
signal priv_mode : std_ulogic_vector(1 downto 0); -- current CPU privilege level |
|
begin |
|
149,7 → 150,7
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- CSR system -- |
assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning; |
assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning; |
-- U-extension requires Zicsr extension -- |
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr extension." severity error; |
-- PMP requires Zicsr extension -- |
157,7 → 158,7
-- PMP regions -- |
assert not ((PMP_NUM_REGIONS > pmp_max_r_c) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions out of valid range." severity error; |
-- PMP granulartiy -- |
assert not (((PMP_GRANULARITY < 1) or (PMP_GRANULARITY > 32)) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Invalid PMP granulartiy (0 < G < 33)." severity error; |
assert not (((PMP_GRANULARITY < 1) or (PMP_GRANULARITY > 32)) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Invalid PMP granulartiy (0 < PMP_GRANULARITY < 33)." severity error; |
|
|
-- Control Unit --------------------------------------------------------------------------- |
191,7 → 192,8
-- data input -- |
instr_i => instr, -- instruction |
cmp_i => alu_cmp, -- comparator status |
alu_res_i => alu_res, -- ALU processing result |
alu_add_i => alu_add, -- ALU address result |
rs1_i => rs1, -- rf source 1 |
-- data output -- |
imm_o => imm, -- immediate |
fetch_pc_o => fetch_pc, -- PC for instruction fetch |
209,7 → 211,6
-- physical memory protection -- |
pmp_addr_o => pmp_addr, -- addresses |
pmp_ctrl_o => pmp_ctrl, -- configs |
priv_mode_o => priv_mode, -- current CPU privilege level |
-- bus access exceptions -- |
mar_i => mar, -- memory address register |
ma_instr_i => ma_instr, -- misaligned instruction address |
262,6 → 263,8
-- data output -- |
cmp_o => alu_cmp, -- comparator status |
res_o => alu_res, -- ALU result |
add_o => alu_add, -- address computation result |
opb_o => alu_opb, -- ALU operand B |
-- co-processor interface -- |
cp0_start_o => cp0_start, -- trigger co-processor 0 |
cp0_data_i => cp0_data, -- co-processor 0 result |
269,6 → 272,12
cp1_start_o => cp1_start, -- trigger co-processor 1 |
cp1_data_i => cp1_data, -- co-processor 1 result |
cp1_valid_i => cp1_valid, -- co-processor 1 result valid |
cp2_start_o => cp2_start, -- trigger co-processor 2 |
cp2_data_i => cp2_data, -- co-processor 2 result |
cp2_valid_i => cp2_valid, -- co-processor 2 result valid |
cp3_start_o => cp3_start, -- trigger co-processor 3 |
cp3_data_i => cp3_data, -- co-processor 3 result |
cp3_valid_i => cp3_valid, -- co-processor 3 result valid |
-- status -- |
wait_o => alu_wait -- busy due to iterative processing units |
); |
287,8 → 296,8
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
start_i => cp0_start, -- trigger operation |
-- data input -- |
start_i => cp0_start, -- trigger operation |
rs1_i => rs1, -- rf source 1 |
rs2_i => rs2, -- rf source 2 |
-- result and status -- |
304,12 → 313,30
end generate; |
|
|
-- Co-Processor 1: Not Implemented Yet ---------------------------------------------------- |
-- Co-Processor 1: Not implemented yet ---------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- control: ctrl cp1_start |
-- inputs: rs1 rs2 alu_cmp alu_opb |
cp1_data <= (others => '0'); |
cp1_valid <= '0'; |
|
|
-- Co-Processor 2: Not implemented yet ---------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- control: ctrl cp2_start |
-- inputs: rs1 rs2 alu_cmp alu_opb |
cp2_data <= (others => '0'); |
cp2_valid <= '0'; |
|
|
-- Co-Processor 3: Not implemented yet ---------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- control: ctrl cp3_start |
-- inputs: rs1 rs2 alu_cmp alu_opb |
cp3_data <= (others => '0'); |
cp3_valid <= '0'; |
|
|
-- Bus Interface Unit --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cpu_bus_inst: neorv32_cpu_bus |
323,7 → 350,6
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
ctrl_i => ctrl, -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i => fetch_pc, -- PC for instruction fetch |
346,7 → 372,6
-- physical memory protection -- |
pmp_addr_i => pmp_addr, -- addresses |
pmp_ctrl_i => pmp_ctrl, -- configs |
priv_mode_i => priv_mode, -- current CPU privilege level |
-- instruction bus -- |
i_bus_addr_o => i_bus_addr_o, -- bus access address |
i_bus_rdata_i => i_bus_rdata_i, -- bus read data |
372,8 → 397,8
); |
|
-- current privilege level -- |
i_bus_priv_o <= priv_mode; |
d_bus_priv_o <= priv_mode; |
i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c); |
d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c); |
|
|
end neorv32_cpu_rtl; |
/rtl/core/neorv32_cpu_alu.vhd
2,7 → 2,6
-- # << NEORV32 - Arithmetical/Logical Unit >> # |
-- # ********************************************************************************************* # |
-- # Main data and address ALU. Includes comparator unit and co-processor interface/arbiter. # |
-- # The shifter sub-unit uses an iterative approach. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
60,6 → 59,8
-- data output -- |
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status |
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result |
opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU operand B |
-- co-processor interface -- |
cp0_start_o : out std_ulogic; -- trigger co-processor 0 |
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result |
67,6 → 68,12
cp1_start_o : out std_ulogic; -- trigger co-processor 1 |
cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result |
cp1_valid_i : in std_ulogic; -- co-processor 1 result valid |
cp2_start_o : out std_ulogic; -- trigger co-processor 2 |
cp2_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 2 result |
cp2_valid_i : in std_ulogic; -- co-processor 2 result valid |
cp3_start_o : out std_ulogic; -- trigger co-processor 3 |
cp3_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 3 result |
cp3_valid_i : in std_ulogic; -- co-processor 3 result valid |
-- status -- |
wait_o : out std_ulogic -- busy due to iterative processing units |
); |
78,14 → 85,13
signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- results -- |
signal addsub_res : std_ulogic_vector(data_width_c-1 downto 0); |
signal addsub_res : std_ulogic_vector(data_width_c downto 0); |
signal cp_res : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- comparator -- |
signal cmp_opx : std_ulogic_vector(data_width_c downto 0); |
signal cmp_opy : std_ulogic_vector(data_width_c downto 0); |
signal cmp_sub : std_ulogic_vector(data_width_c downto 0); |
signal cmp_less : std_ulogic; |
signal cmp_opx : std_ulogic_vector(data_width_c downto 0); |
signal cmp_opy : std_ulogic_vector(data_width_c downto 0); |
signal cmp_sub : std_ulogic_vector(data_width_c downto 0); |
|
-- shifter -- |
type shifter_t is record |
116,8 → 122,10
|
-- Operand Mux ---------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand) |
opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops |
opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand) |
-- |
opb_o <= opb; |
|
|
-- Comparator Unit ------------------------------------------------------------------------ |
147,24 → 155,22
if (ctrl_i(ctrl_alu_addsub_c) = '1') then -- subtraction |
op_y_v := not op_b_v; |
cin_v(0) := '1'; |
else-- addition |
else -- addition |
op_y_v := op_b_v; |
cin_v(0) := '0'; |
end if; |
|
-- adder core -- |
res_v := std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0))); |
|
-- output -- |
cmp_less <= res_v(32); |
addsub_res <= res_v(31 downto 0); |
addsub_res <= res_v(31 downto 0); |
-- adder core (result + carry/borrow) -- |
addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0))); |
end process binary_arithmetic_core; |
|
-- direct output of address result -- |
add_o <= addsub_res(data_width_c-1 downto 0); |
|
|
-- Shifter Unit --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
shifter_unit: process(rstn_i, clk_i) |
shifter_unit: process(clk_i) |
variable bs_input_v : std_ulogic_vector(data_width_c-1 downto 0); |
variable bs_level_4_v : std_ulogic_vector(data_width_c-1 downto 0); |
variable bs_level_3_v : std_ulogic_vector(data_width_c-1 downto 0); |
172,15 → 178,7
variable bs_level_1_v : std_ulogic_vector(data_width_c-1 downto 0); |
variable bs_level_0_v : std_ulogic_vector(data_width_c-1 downto 0); |
begin |
if (rstn_i = '0') then |
shifter.sreg <= (others => '0'); |
shifter.cnt <= (others => '0'); |
shifter.cmd_ff <= '0'; |
if (FAST_SHIFT_EN = true) then |
shifter.bs_d_in <= (others => '0'); |
shifter.bs_a_in <= (others => '0'); |
end if; |
elsif rising_edge(clk_i) then |
if rising_edge(clk_i) then |
shifter.cmd_ff <= shifter.cmd; |
|
-- -------------------------------------------------------------------------------- |
189,7 → 187,7
if (FAST_SHIFT_EN = false) then |
|
if (shifter.start = '1') then -- trigger new shift |
shifter.sreg <= opa; -- shift operand |
shifter.sreg <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc) |
shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount |
elsif (shifter.run = '1') then -- running shift |
-- coarse shift: multiples of 4 -- |
221,7 → 219,7
|
-- operands and cycle control -- |
if (shifter.start = '1') then -- trigger new shift |
shifter.bs_d_in <= opa; -- shift data |
shifter.bs_d_in <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc) |
shifter.bs_a_in <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount |
shifter.cnt <= (others => '0'); |
end if; |
298,7 → 296,7
cp_ctrl.cmd_ff <= cp_ctrl.cmd; |
if (cp_ctrl.start = '1') then |
cp_ctrl.busy <= '1'; |
elsif ((cp0_valid_i or cp1_valid_i) = '1') then -- cp computation done? |
elsif ((cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i) = '1') then -- cp computation done? |
cp_ctrl.busy <= '0'; |
end if; |
else -- no co-processor(s) implemented |
311,29 → 309,31
-- is co-processor operation? -- |
cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_cp_c) else '0'; |
cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0'; |
cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) else '0'; -- MULDIV CP |
cp1_start_o <= '0'; -- not yet implemented |
cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0'; -- CP0: MULDIV CP |
cp1_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0'; -- CP1: not implemented yet |
cp2_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0'; -- CP2: not implemented yet |
cp3_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0'; -- CP3: not implemented yet |
|
-- co-processor operation running? -- |
cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start; |
|
-- co-processor result -- |
cp_res <= cp0_data_i or cp1_data_i; -- only the **actaully selected** co-processor should output data != 0 |
cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0 |
|
|
-- ALU Function Select -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
alu_function_mux: process(ctrl_i, opa, opb, addsub_res, cp_res, cmp_less, shifter.sreg) |
alu_function_mux: process(ctrl_i, rs1_i, opb, addsub_res, cp_res, shifter.sreg) |
begin |
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is |
when alu_cmd_xor_c => res_o <= opa xor opb; |
when alu_cmd_or_c => res_o <= opa or opb; |
when alu_cmd_and_c => res_o <= opa and opb; |
when alu_cmd_xor_c => res_o <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc) |
when alu_cmd_or_c => res_o <= rs1_i or opb; |
when alu_cmd_and_c => res_o <= rs1_i and opb; |
when alu_cmd_movb_c => res_o <= opb; |
when alu_cmd_addsub_c => res_o <= addsub_res; |
when alu_cmd_addsub_c => res_o <= addsub_res(data_width_c-1 downto 0); |
when alu_cmd_cp_c => res_o <= cp_res; |
when alu_cmd_shift_c => res_o <= shifter.sreg; |
when alu_cmd_slt_c => res_o <= (others => '0'); res_o(0) <= cmp_less; |
when alu_cmd_slt_c => res_o <= (others => '0'); res_o(0) <= addsub_res(addsub_res'left); -- => carry/borrow |
when others => res_o <= opb; -- undefined |
end case; |
end process alu_function_mux; |
/rtl/core/neorv32_cpu_bus.vhd
52,7 → 52,6
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
75,7 → 74,6
-- physical memory protection -- |
pmp_addr_i : in pmp_addr_if_t; -- addresses |
pmp_ctrl_i : in pmp_ctrl_if_t; -- configs |
priv_mode_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level |
-- instruction bus -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
105,8 → 103,8
|
-- PMP modes -- |
constant pmp_off_mode_c : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled) |
constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range |
constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region |
--constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range |
--constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region |
constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes) |
|
-- PMP configuration register bits -- |
163,7 → 161,7
|
-- Data Interface: Access Address --------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
mem_adr_reg: process(rstn_i, clk_i) |
mem_adr_reg: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then |
201,7 → 199,7
begin |
if rising_edge(clk_i) then |
if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then |
mdo <= wdata_i; |
mdo <= wdata_i; -- memory data out register (MDO) |
end if; |
end if; |
end process mem_do_reg; |
215,8 → 213,12
d_bus_wdata(15 downto 08) <= mdo(07 downto 00); |
d_bus_wdata(23 downto 16) <= mdo(07 downto 00); |
d_bus_wdata(31 downto 24) <= mdo(07 downto 00); |
d_bus_ben <= (others => '0'); |
d_bus_ben(to_integer(unsigned(mar(1 downto 0)))) <= '1'; |
case mar(1 downto 0) is |
when "00" => d_bus_ben <= "0001"; |
when "01" => d_bus_ben <= "0010"; |
when "10" => d_bus_ben <= "0100"; |
when others => d_bus_ben <= "1000"; |
end case; |
when "01" => -- half-word |
d_bus_wdata(31 downto 16) <= mdo(15 downto 00); |
d_bus_wdata(15 downto 00) <= mdo(15 downto 00); |
237,9 → 239,8
mem_out_buf: process(clk_i) |
begin |
if rising_edge(clk_i) then |
-- memory data in register (MDI) -- |
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then |
mdi <= d_bus_rdata; |
mdi <= d_bus_rdata; -- memory data in register (MDI) |
end if; |
end if; |
end process mem_out_buf; |
246,33 → 247,24
|
-- input data alignment and sign extension -- |
read_align: process(mdi, mar, ctrl_i) |
variable signed_v : std_ulogic; |
variable byte_in_v : std_ulogic_vector(07 downto 0); |
variable hword_in_v : std_ulogic_vector(15 downto 0); |
begin |
signed_v := not ctrl_i(ctrl_bus_unsigned_c); |
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is -- data size |
-- sub-word input -- |
case mar(1 downto 0) is |
when "00" => byte_in_v := mdi(07 downto 00); hword_in_v := mdi(15 downto 00); -- byte 0 / half-word 0 |
when "01" => byte_in_v := mdi(15 downto 08); hword_in_v := mdi(15 downto 00); -- byte 1 / half-word 0 |
when "10" => byte_in_v := mdi(23 downto 16); hword_in_v := mdi(31 downto 16); -- byte 2 / half-word 1 |
when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1 |
end case; |
-- actual data size -- |
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is |
when "00" => -- byte |
case mar(1 downto 0) is |
when "00" => |
rdata_o(31 downto 08) <= (others => (signed_v and mdi(07))); |
rdata_o(07 downto 00) <= mdi(07 downto 00); -- byte 0 |
when "01" => |
rdata_o(31 downto 08) <= (others => (signed_v and mdi(15))); |
rdata_o(07 downto 00) <= mdi(15 downto 08); -- byte 1 |
when "10" => |
rdata_o(31 downto 08) <= (others => (signed_v and mdi(23))); |
rdata_o(07 downto 00) <= mdi(23 downto 16); -- byte 2 |
when others => |
rdata_o(31 downto 08) <= (others => (signed_v and mdi(31))); |
rdata_o(07 downto 00) <= mdi(31 downto 24); -- byte 3 |
end case; |
rdata_o(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension |
rdata_o(07 downto 00) <= byte_in_v; |
when "01" => -- half-word |
if (mar(1) = '0') then |
rdata_o(31 downto 16) <= (others => (signed_v and mdi(15))); |
rdata_o(15 downto 00) <= mdi(15 downto 00); -- low half-word |
else |
rdata_o(31 downto 16) <= (others => (signed_v and mdi(31))); |
rdata_o(15 downto 00) <= mdi(31 downto 16); -- high half-word |
end if; |
rdata_o(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension |
rdata_o(15 downto 00) <= hword_in_v; -- high half-word |
when others => -- word |
rdata_o <= mdi; -- full word |
end case; |
297,17 → 289,9
|
-- Instruction Fetch Arbiter -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ifetch_arbiter: process(rstn_i, clk_i) |
ifetch_arbiter: process(clk_i) |
begin |
if (rstn_i = '0') then |
i_arbiter.rd_req <= '0'; |
i_arbiter.wr_req <= '0'; |
i_arbiter.err_align <= '0'; |
i_arbiter.err_bus <= '0'; |
i_arbiter.timeout <= (others => '0'); |
elsif rising_edge(clk_i) then |
i_arbiter.wr_req <= '0'; -- instruction fetch is read-only |
|
if rising_edge(clk_i) then |
-- instruction fetch request -- |
if (i_arbiter.rd_req = '0') then -- idle |
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c); |
318,10 → 302,6
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1); |
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
--if (i_arbiter.err_align = '1') or (i_arbiter.err_bus = '1') then -- any error? |
-- if (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for controller to acknowledge error |
-- i_arbiter.rd_req <= '0'; |
-- end if; |
if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort |
i_arbiter.rd_req <= '0'; |
end if; |
329,6 → 309,8
end if; |
end process ifetch_arbiter; |
|
i_arbiter.wr_req <= '0'; -- instruction fetch is read-only |
|
-- cancel bus access -- |
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c); |
|
351,16 → 333,9
|
-- Data Access Arbiter -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
data_access_arbiter: process(rstn_i, clk_i) |
data_access_arbiter: process(clk_i) |
begin |
if (rstn_i = '0') then |
d_arbiter.rd_req <= '0'; |
d_arbiter.wr_req <= '0'; |
d_arbiter.err_align <= '0'; |
d_arbiter.err_bus <= '0'; |
d_arbiter.timeout <= (others => '0'); |
elsif rising_edge(clk_i) then |
|
if rising_edge(clk_i) then |
-- data access request -- |
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle |
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c); |
372,11 → 347,6
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1); |
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
--if (d_arbiter.err_align = '1') or (d_arbiter.err_bus = '1') then -- any error? |
-- if (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for controller to acknowledge error |
-- d_arbiter.wr_req <= '0'; |
-- d_arbiter.rd_req <= '0'; |
-- end if; |
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
456,11 → 426,11
|
|
-- check access type and regions's permissions -- |
pmp_check_permission: process(pmp, pmp_ctrl_i, priv_mode_i) |
pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i) |
begin |
for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions |
if ((priv_mode_i = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode |
(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry |
if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode |
(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry |
pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission |
pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission |
pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission |
/rtl/core/neorv32_cpu_control.vhd
73,7 → 73,8
-- data input -- |
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status |
alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU processing result |
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 |
-- data output -- |
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
91,7 → 92,6
-- physical memory protection -- |
pmp_addr_o : out pmp_addr_if_t; -- addresses |
pmp_ctrl_o : out pmp_ctrl_if_t; -- configs |
priv_mode_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level |
-- bus access exceptions -- |
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register |
ma_instr_i : in std_ulogic; -- misaligned instruction address |
269,6 → 269,7
signal minstret_msb : std_ulogic; |
|
-- illegal instruction check -- |
signal illegal_opcode_lsbs : std_ulogic; -- if opcode != rv32 |
signal illegal_instruction : std_ulogic; |
signal illegal_register : std_ulogic; -- only for E-extension |
signal illegal_compressed : std_ulogic; -- only fir C-extension |
359,12 → 360,9
|
-- Instruction Prefetch Buffer (FIFO) ----------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
instr_prefetch_buffer_ctrl: process(rstn_i, clk_i) |
instr_prefetch_buffer: process(clk_i) |
begin |
if (rstn_i = '0') then |
ipb.w_pnt <= (others => '0'); |
ipb.r_pnt <= (others => '0'); |
elsif rising_edge(clk_i) then |
if rising_edge(clk_i) then |
-- write port -- |
if (ipb.clear = '1') then |
ipb.w_pnt <= (others => '0'); |
371,7 → 369,10
elsif (ipb.we = '1') then |
ipb.w_pnt <= std_ulogic_vector(unsigned(ipb.w_pnt) + 1); |
end if; |
-- read ports -- |
if (ipb.we = '1') then -- write port |
ipb.data(to_integer(unsigned(ipb.w_pnt(ipb.w_pnt'left-1 downto 0)))) <= ipb.wdata; |
end if; |
-- read port -- |
if (ipb.clear = '1') then |
ipb.r_pnt <= (others => '0'); |
elsif (ipb.re = '1') then |
378,17 → 379,8
ipb.r_pnt <= std_ulogic_vector(unsigned(ipb.r_pnt) + 1); |
end if; |
end if; |
end process instr_prefetch_buffer_ctrl; |
end process instr_prefetch_buffer; |
|
instr_prefetch_buffer_data: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (ipb.we = '1') then -- write port |
ipb.data(to_integer(unsigned(ipb.w_pnt(ipb.w_pnt'left-1 downto 0)))) <= ipb.wdata; |
end if; |
end if; |
end process instr_prefetch_buffer_data; |
|
-- async read -- |
ipb.rdata <= ipb.data(to_integer(unsigned(ipb.r_pnt(ipb.r_pnt'left-1 downto 0)))); |
|
450,6 → 442,7
|
-- instruction buffer interface defaults -- |
i_buf.we <= '0'; |
-- i_buf = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word> |
i_buf.wdata <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); |
|
-- state machine -- |
461,15 → 454,14
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word |
if (i_buf.free = '1') then |
i_buf.we <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned" |
ipb.re <= '1'; |
i_buf.wdata <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); |
i_buf.we <= '1'; |
else -- compressed |
ipb.re <= '1'; |
i_buf.wdata <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
i_buf.we <= '1'; |
issue_engine.align_nxt <= '1'; |
end if; |
end if; |
476,15 → 468,14
|
else -- begin check in HIGH instruction half-word |
if (i_buf.free = '1') then |
i_buf.we <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned" |
ipb.re <= '1'; |
i_buf.wdata <= '0' & issue_engine.buf(17 downto 16) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0)); |
i_buf.we <= '1'; |
else -- compressed |
--ipb.re <= '1'; |
-- do not read from ipb here! |
i_buf.wdata <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
i_buf.we <= '1'; |
issue_engine.align_nxt <= '0'; |
end if; |
end if; |
533,11 → 524,9
|
-- Instruction Buffer --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
instruction_buffer_ctrl: process(rstn_i, clk_i) |
instruction_buffer: process(clk_i) |
begin |
if (rstn_i = '0') then |
i_buf.status <= '0'; |
elsif rising_edge(clk_i) then |
if rising_edge(clk_i) then |
if (i_buf.clear = '1') then |
i_buf.status <= '0'; |
elsif (i_buf.we = '1') then |
545,17 → 534,11
elsif (i_buf.re = '1') then |
i_buf.status <= '0'; |
end if; |
end if; |
end process instruction_buffer_ctrl; |
|
instruction_buffer_data: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (i_buf.we = '1') then |
i_buf.rdata <= i_buf.wdata; |
end if; |
end if; |
end process instruction_buffer_data; |
end process instruction_buffer; |
|
-- status -- |
i_buf.free <= not i_buf.status; |
598,9 → 581,6
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21); |
imm_o(00) <= '0'; |
when opcode_syscsr_c => -- CSR-immediate (uimm5) |
imm_o(31 downto 05) <= (others => '0'); |
imm_o(04 downto 00) <= execute_engine.i_reg(19 downto 15); |
when others => -- I-immediate |
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
680,16 → 660,24
|
-- CPU Control Bus Output ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, bus_fast_ir, execute_engine) |
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, bus_fast_ir, execute_engine, csr.privilege) |
begin |
-- signals from execute engine -- |
ctrl_o <= ctrl; |
-- current privilege level -- |
ctrl_o(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) <= csr.privilege; |
-- register addresses -- |
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c); |
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c); |
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c); |
-- fast bus access requests -- |
ctrl_o(ctrl_bus_if_c) <= ctrl(ctrl_bus_if_c) or bus_fast_ir; |
ctrl_o(ctrl_bus_if_c) <= bus_fast_ir; |
-- bus error control -- |
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack; |
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack; |
-- co-processor operation -- |
ctrl_o(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); |
-- instruction's function blocks (for co-processors) -- |
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c); |
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); |
end process ctrl_output; |
|
|
696,9 → 684,10
-- Execute Engine FSM Comb ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
execute_engine_fsm_comb: process(execute_engine, fetch_engine, i_buf, trap_ctrl, csr, ctrl, csr_acc_valid, |
alu_res_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i) |
alu_add_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i) |
variable alu_immediate_v : std_ulogic; |
variable rs1_is_r0_v : std_ulogic; |
variable opcode_v : std_ulogic_vector(6 downto 0); |
begin |
-- arbiter defaults -- |
execute_engine.state_nxt <= execute_engine.state; |
731,11 → 720,11
csr.re_nxt <= '0'; |
|
-- control defaults -- |
ctrl_nxt <= (others => '0'); -- all off at first |
ctrl_nxt <= (others => '0'); -- default: all off |
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation (SLTIU, SLTU) |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU) |
else -- branches |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches (BLTU, BGEU) |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU) |
end if; |
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU) |
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right) |
742,9 → 731,6
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- default ALU operation: ADD(I) |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 (=MULDIV) implemented yet |
ctrl_nxt(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= ctrl(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c); -- keep rd addr |
ctrl_nxt(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= ctrl(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- keep rs1 addr |
ctrl_nxt(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= ctrl(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- keep rs2 addr |
ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size |
|
-- is immediate ALU operation? -- |
761,31 → 747,24
-- ------------------------------------------------------------ |
-- set reg_file's r0 to zero -- |
if (rf_r0_is_reg_c = true) then -- is r0 implemented as physical register, which has to be set to zero? |
ctrl_nxt(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= (others => '0'); -- rd addr = r0 |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output (hacky! results zero since there is no valid CSR_read request) |
ctrl_nxt(ctrl_rf_r0_we_c) <= '1'; -- allow write access to r0 |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
ctrl_nxt(ctrl_rf_r0_we_c) <= '1'; -- force RF write access and force rd=r0 |
end if; |
-- |
execute_engine.state_nxt <= DISPATCH; |
|
when DISPATCH => -- Get new command from instruction buffer (I_BUF) |
when DISPATCH => -- Get new command from instruction buffer (i_buf) |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= i_buf.rdata(instr_rd_msb_c downto instr_rd_lsb_c); -- rd addr |
ctrl_nxt(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= i_buf.rdata(instr_rs1_msb_c downto instr_rs1_lsb_c); -- rs1 addr |
ctrl_nxt(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= i_buf.rdata(instr_rs2_msb_c downto instr_rs2_lsb_c); -- rs2 addr |
-- |
if (i_buf.avail = '1') then -- instruction available? |
i_buf.re <= '1'; |
-- |
execute_engine.is_ci_nxt <= i_buf.rdata(32); -- flag to indicate this is a de-compressed instruction beeing executed |
execute_engine.i_reg_nxt <= i_buf.rdata(31 downto 0); |
execute_engine.is_ci_nxt <= i_buf.rdata(32); -- flag to indicate this is a de-compressed instruction beeing executed |
execute_engine.i_reg_nxt <= i_buf.rdata(31 downto 0); |
trap_ctrl.instr_ma <= i_buf.rdata(33); -- misaligned instruction fetch address |
trap_ctrl.instr_be <= i_buf.rdata(34); -- bus access fault during instrucion fetch |
illegal_compressed <= i_buf.rdata(35); -- invalid decompressed instruction |
-- |
execute_engine.if_rst_nxt <= '0'; |
-- |
trap_ctrl.instr_ma <= i_buf.rdata(33); -- misaligned instruction fetch address |
trap_ctrl.instr_be <= i_buf.rdata(34); -- bus access fault during instrucion fetch |
illegal_compressed <= i_buf.rdata(35); -- invalid decompressed instruction |
-- |
if (execute_engine.if_rst = '0') then -- if there was NO non-linear PC modification |
execute_engine.pc_nxt <= execute_engine.next_pc; |
end if; |
814,7 → 793,8
-- ------------------------------------------------------------ |
execute_engine.last_pc_nxt <= execute_engine.pc; -- store address of current instruction for commit |
-- |
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is |
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32 |
case opcode_v is |
|
when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation |
-- ------------------------------------------------------------ |
901,7 → 881,8
|
when opcode_fence_c => -- fence operations |
-- ------------------------------------------------------------ |
-- for simplicity: internally, fence and fence.i perform the same operations (flush and reload of instruction prefetch buffer) |
execute_engine.state_nxt <= SYS_WAIT; |
-- for simplicity: internally, fence and fence.i perform the same operations (clear and reload instruction prefetch buffer) |
-- FENCE.I -- |
if (CPU_EXTENSION_RISCV_Zifencei = true) then |
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction |
915,13 → 896,9
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then |
ctrl_nxt(ctrl_bus_fence_c) <= '1'; |
end if; |
-- |
execute_engine.state_nxt <= SYS_WAIT; |
|
when opcode_syscsr_c => -- system/csr access |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= ctrl(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- copy rs1_addr to rs2_addr (for CSR mod) |
-- |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system |
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is |
when funct12_ecall_c => -- ECALL |
933,7 → 910,7
execute_engine.pc_nxt <= csr.mepc; |
fetch_engine.reset <= '1'; |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
when funct12_wfi_c => -- WFI (CPU sleep) |
when funct12_wfi_c => -- WFI |
execute_engine.sleep_nxt <= '1'; -- good night |
when others => -- undefined |
NULL; |
952,8 → 929,6
|
when CSR_ACCESS => -- write CSR data to RF, write ALU.res to CSR |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_alu_opb_mux_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- OPB = rs2 (which is rs1 here) / immediate |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_movb_c; -- actual ALU operation = MOVB |
-- CSR write access -- |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is |
when funct3_csrrw_c | funct3_csrrwi_c => -- CSRRW(I) |
986,7 → 961,7
when BRANCH => -- update PC for taken branches and jumps |
-- ------------------------------------------------------------ |
if (execute_engine.is_jump = '1') or (execute_engine.branch_taken = '1') then |
execute_engine.pc_nxt <= alu_res_i; -- branch/jump destination |
execute_engine.pc_nxt <= alu_add_i; -- branch/jump destination |
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
execute_engine.state_nxt <= SYS_WAIT; |
1016,7 → 991,7
execute_engine.state_nxt <= SYS_WAIT; |
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (keep writing back all the time) |
end if; |
execute_engine.state_nxt <= DISPATCH; |
end if; |
1111,16 → 1086,25
-- Illegal Instruction Check -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
illegal_instruction_check: process(execute_engine, csr_acc_valid) |
variable opcode_v : std_ulogic_vector(6 downto 0); |
begin |
-- illegal instructions are checked in the EXECUTE stage |
-- the execute engine will only commit valid instructions |
-- the execute engine should not commit any illegal instruction |
if (execute_engine.state = EXECUTE) then |
-- defaults -- |
illegal_instruction <= '0'; |
illegal_register <= '0'; |
|
-- check opcode for rv32 -- |
if (execute_engine.i_reg(instr_opcode_lsb_c+1 downto instr_opcode_lsb_c) = "11") then |
illegal_opcode_lsbs <= '0'; |
else |
illegal_opcode_lsbs <= '1'; |
end if; |
|
-- check instructions -- |
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is |
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; |
case opcode_v is |
|
-- OPCODE check sufficient: LUI, UIPC, JAL -- |
when opcode_lui_c | opcode_auipc_c | opcode_jal_c => |
1266,13 → 1250,12
illegal_instruction <= '1'; |
end if; |
|
when others => -- compressed instruction or undefined instruction |
if (execute_engine.i_reg(1 downto 0) = "11") then -- undefined/unimplemented opcode |
illegal_instruction <= '1'; |
end if; |
when others => -- undefined instruction -> illegal! |
illegal_instruction <= '1'; |
|
end case; |
else |
illegal_opcode_lsbs <= '0'; |
illegal_instruction <= '0'; |
illegal_register <= '0'; |
end if; |
1279,7 → 1262,7
end process illegal_instruction_check; |
|
-- any illegal condition? -- |
trap_ctrl.instr_il <= illegal_instruction or illegal_register or illegal_compressed; |
trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed; |
|
|
-- **************************************************************************************************************************** |
1451,13 → 1434,21
|
-- Control and Status Registers Write Data ------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
csr_write_data: process(execute_engine.i_reg, csr.rdata, alu_res_i) |
csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i) |
variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0); |
begin |
-- CSR operand source -- |
if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate |
csr_operand_v := (others => '0'); |
csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); |
else -- register |
csr_operand_v := rs1_i; |
end if; |
-- "mini ALU" for CSR update operations -- |
case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is |
when "10" => csr.wdata <= csr.rdata or alu_res_i; -- CSRRS(I) |
when "11" => csr.wdata <= csr.rdata and (not alu_res_i); -- CSRRC(I) |
when others => csr.wdata <= alu_res_i; -- CSRRW(I) |
when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I) |
when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I) |
when others => csr.wdata <= csr_operand_v; -- CSRRW(I) |
end case; |
end process csr_write_data; |
|
1478,7 → 1469,7
csr.mie_mtie <= '0'; |
csr.mie_firqe <= (others => '0'); |
csr.mtvec <= (others => '0'); |
csr.mscratch <= (others => '0'); |
csr.mscratch <= x"19880704"; -- :) |
csr.mepc <= (others => '0'); |
csr.mcause <= (others => '0'); |
csr.mtval <= (others => '0'); |
1492,21 → 1483,26
mcycle_msb <= '0'; |
minstret_msb <= '0'; |
elsif rising_edge(clk_i) then |
|
-- write access? -- |
csr.we <= csr.we_nxt; |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
|
-- -------------------------------------------------------------------------------- |
-- CSRs that can be written by application software only |
-- -------------------------------------------------------------------------------- |
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.we = '1') then -- manual update |
|
-- machine CSRs -- |
if (execute_engine.i_reg(31 downto 28) = csr_mie_c(11 downto 8)) then |
|
-- machine trap setup -- |
if (execute_engine.i_reg(27 downto 24) = csr_mie_c(7 downto 4)) then |
if (execute_engine.i_reg(23 downto 20) = csr_mie_c(3 downto 0)) then -- R/W: mie - machine interrupt-enable register |
-- -------------------------------------------------------------------------------- |
-- CSR access by application software |
-- -------------------------------------------------------------------------------- |
if (csr.we = '1') then -- manual update |
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is |
|
-- machine trap setup -- |
-- -------------------------------------------------------------------- |
when csr_mstatus_c => -- R/W: mstatus - machine status register |
csr.mstatus_mie <= csr.wdata(03); |
csr.mstatus_mpie <= csr.wdata(07); |
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented |
csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12); |
csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12); |
end if; |
when csr_mie_c => -- R/W: mie - machine interrupt-enable register |
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable |
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable |
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable |
1515,172 → 1511,145
csr.mie_firqe(1) <= csr.wdata(17); -- fast interrupt channel 1 |
csr.mie_firqe(2) <= csr.wdata(18); -- fast interrupt channel 2 |
csr.mie_firqe(3) <= csr.wdata(19); -- fast interrupt channel 3 |
end if; |
if (execute_engine.i_reg(23 downto 20) = csr_mtvec_c(3 downto 0)) then -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
end if; |
end if; |
|
-- machine trap handling -- |
if (execute_engine.i_reg(27 downto 20) = csr_mscratch_c(7 downto 0)) then -- R/W: mscratch - machine scratch register |
csr.mscratch <= csr.wdata; |
end if; |
-- machine trap handling -- |
-- -------------------------------------------------------------------- |
when csr_mscratch_c => -- R/W: mscratch - machine scratch register |
csr.mscratch <= csr.wdata; |
when csr_mepc_c => -- R/W: mepc - machine exception program counter |
csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0'; |
when csr_mcause_c => -- R/W: mcause - machine trap cause |
csr.mcause <= (others => '0'); |
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception |
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier |
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction |
csr.mtval <= csr.wdata; |
|
-- machine physical memory protection (pmp) -- |
if (PMP_USE = true) then |
-- pmpcfg -- |
if (execute_engine.i_reg(27 downto 24) = csr_pmpcfg0_c(7 downto 4)) then |
if (PMP_NUM_REGIONS >= 1) then |
if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg0_c(3 downto 0)) then -- pmpcfg0 |
for j in 0 to 3 loop -- bytes in pmpcfg CSR |
if ((j+1) <= PMP_NUM_REGIONS) then |
if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access |
csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R (rights.read) |
csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W (rights.write) |
csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute) |
csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L |
csr.pmpcfg(0+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only |
csr.pmpcfg(0+j)(5) <= '0'; -- reserved |
csr.pmpcfg(0+j)(6) <= '0'; -- reserved |
csr.pmpcfg(0+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode) |
end if; |
-- physical memory protection - configuration -- |
-- -------------------------------------------------------------------- |
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - PMP configuration register 0 |
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 1) then |
for j in 0 to 3 loop -- bytes in pmpcfg CSR |
if ((j+1) <= PMP_NUM_REGIONS) then |
if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access |
csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R (rights.read) |
csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W (rights.write) |
csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute) |
csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L |
csr.pmpcfg(0+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only |
csr.pmpcfg(0+j)(5) <= '0'; -- reserved |
csr.pmpcfg(0+j)(6) <= '0'; -- reserved |
csr.pmpcfg(0+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode) |
end if; |
end loop; -- j (bytes in CSR) |
end if; |
end if; |
end loop; -- j (bytes in CSR) |
end if; |
if (PMP_NUM_REGIONS >= 5) then |
if (execute_engine.i_reg(23 downto 20) = csr_pmpcfg1_c(3 downto 0)) then -- pmpcfg1 |
for j in 0 to 3 loop -- bytes in pmpcfg CSR |
if ((j+1+4) <= PMP_NUM_REGIONS) then |
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access |
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R (rights.read) |
csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W (rights.write) |
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute) |
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L |
csr.pmpcfg(4+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only |
csr.pmpcfg(4+j)(5) <= '0'; -- reserved |
csr.pmpcfg(4+j)(6) <= '0'; -- reserved |
csr.pmpcfg(4+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode) |
end if; |
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - PMP configuration register 1 |
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 5) then |
for j in 0 to 3 loop -- bytes in pmpcfg CSR |
if ((j+1+4) <= PMP_NUM_REGIONS) then |
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access |
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R (rights.read) |
csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W (rights.write) |
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute) |
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L |
csr.pmpcfg(4+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only |
csr.pmpcfg(4+j)(5) <= '0'; -- reserved |
csr.pmpcfg(4+j)(6) <= '0'; -- reserved |
csr.pmpcfg(4+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode) |
end if; |
end loop; -- j (bytes in CSR) |
end if; |
end if; |
end loop; -- j (bytes in CSR) |
end if; |
end if; |
-- pmpaddr -- |
if (execute_engine.i_reg(27 downto 24) = csr_pmpaddr0_c(7 downto 4)) then |
for i in 0 to PMP_NUM_REGIONS-1 loop |
if (execute_engine.i_reg(23 downto 20) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access |
csr.pmpaddr(i) <= csr.wdata(31 downto 1) & '0'; -- min granularity is 8 bytes -> bit zero cannot be configured |
end if; |
end loop; -- i (CSRs) |
end if; |
end if; -- implement PMP at all? |
end if; |
|
end if; |
-- physical memory protection - addresses -- |
-- -------------------------------------------------------------------- |
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | |
csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c => -- R/W: pmpaddr0..7 - PMP address register 0..7 |
if (PMP_USE = true) then |
for i in 0 to PMP_NUM_REGIONS-1 loop |
if (execute_engine.i_reg(23 downto 20) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access |
csr.pmpaddr(i) <= csr.wdata(31 downto 1) & '0'; -- min granularity is 8 bytes -> bit zero cannot be configured |
end if; |
end loop; -- i (CSRs) |
end if; |
|
-- -------------------------------------------------------------------------------- |
-- CSRs that can be written by application and hardware (application access) |
-- -------------------------------------------------------------------------------- |
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.we = '1') then -- manual update |
-- undefined -- |
-- -------------------------------------------------------------------- |
when others => |
NULL; |
|
-- machine CSRs -- |
if (execute_engine.i_reg(31 downto 28) = csr_mstatus_c(11 downto 8)) then |
end case; |
|
-- machine trap setup -- |
if (execute_engine.i_reg(27 downto 20) = csr_mstatus_c(7 downto 0)) then -- R/W: mstatus - machine status register |
csr.mstatus_mie <= csr.wdata(03); |
csr.mstatus_mpie <= csr.wdata(07); |
-- |
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented |
csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12); |
csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12); |
-- -------------------------------------------------------------------------------- |
-- CSR access by hardware |
-- -------------------------------------------------------------------------------- |
else |
|
-- mepc & mtval: machine exception PC & machine trap value register -- |
-- -------------------------------------------------------------------- |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting? |
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS |
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction |
csr.mtval <= (others => '0'); -- mtval is zero for interrupts |
else -- for EXCEPTIONS (according to their priority) |
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction |
if (trap_ctrl.cause(4 downto 0) = trap_iba_c(4 downto 0)) or -- instruction access error OR |
(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction address OR |
(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR |
(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- environment call |
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction |
elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction |
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself |
else -- load/store misalignments/access errors |
csr.mtval <= mar_i; -- faulting data access address |
end if; |
end if; |
end if; |
|
-- machine trap handling -- |
if (execute_engine.i_reg(27 downto 24) = csr_mepc_c(7 downto 4)) then |
if (execute_engine.i_reg(23 downto 20) = csr_mepc_c(3 downto 0)) then -- R/W: mepc - machine exception program counter |
csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0'; |
-- mstatus: context switch -- |
-- -------------------------------------------------------------------- |
if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting? |
-- trap ID code -- |
csr.mcause <= (others => '0'); |
csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception |
csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier |
-- |
csr.mstatus_mie <= '0'; -- disable interrupts |
csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state |
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode |
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode |
csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode |
end if; |
if (execute_engine.i_reg(23 downto 20) = csr_mcause_c(3 downto 0)) then -- R/W: mcause - machine trap cause |
csr.mcause <= (others => '0'); |
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception |
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier |
elsif (trap_ctrl.env_end = '1') then -- EXIT: return from exception |
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag |
csr.mstatus_mpie <= '1'; |
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode |
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode |
csr.mstatus_mpp <= priv_mode_u_c; |
end if; |
if (execute_engine.i_reg(23 downto 20) = csr_mtval_c(3 downto 0)) then -- R/W: mtval - machine bad address or instruction |
csr.mtval <= csr.wdata; |
end if; |
end if; |
|
end if; |
|
-- -------------------------------------------------------------------------------- |
-- CSRs that can be written by application and hardware (hardware access) |
-- -------------------------------------------------------------------------------- |
else -- hardware update |
|
-- mepc & mtval: machine exception PC & machine trap value register -- |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting? |
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (is mcause(31)) |
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction |
csr.mtval <= (others => '0'); -- mtval is zero for interrupts |
else -- for EXCEPTIONS (according to their priority) |
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction |
if (trap_ctrl.cause(4 downto 0) = trap_iba_c(4 downto 0)) or -- instruction access error OR |
(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction address OR |
(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR |
(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- environment call |
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction |
elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction |
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself |
else -- load/store misalignments/access errors |
csr.mtval <= mar_i; -- faulting data access address |
end if; |
-- user mode NOT implemented -- |
if (CPU_EXTENSION_RISCV_U = false) then |
csr.privilege <= priv_mode_m_c; |
csr.mstatus_mpp <= priv_mode_m_c; |
end if; |
end if; |
|
-- mstatus: context switch -- |
if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting? |
-- trap ID code -- |
csr.mcause <= (others => '0'); |
csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception |
csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier |
-- |
csr.mstatus_mie <= '0'; -- disable interrupts |
csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state |
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode |
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode |
csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode |
end if; |
elsif (trap_ctrl.env_end = '1') then -- EXIT: return from exception |
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag |
csr.mstatus_mpie <= '1'; |
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode |
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode |
csr.mstatus_mpp <= priv_mode_u_c; |
end if; |
end if; |
-- user mode NOT implemented -- |
if (CPU_EXTENSION_RISCV_U = false) then |
csr.privilege <= priv_mode_m_c; |
csr.mstatus_mpp <= priv_mode_m_c; |
end if; |
end if; |
end if; -- hardware csr access |
|
-- -------------------------------------------------------------------------------- |
-- Counter CSRs |
-- -------------------------------------------------------------------------------- |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
|
-- mcycle (cycle) -- |
mcycle_msb <= csr.mcycle(csr.mcycle'left); |
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycle_c) then -- write access |
csr.mcycle(31 downto 0) <= csr.wdata; |
csr.mcycle(32) <= '0'; |
csr.mcycle <= '0' & csr.wdata; |
mcycle_msb <= '0'; |
elsif (execute_engine.sleep = '0') then -- automatic update (if CPU is not in sleep mode) |
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1); |
mcycle_msb <= csr.mcycle(csr.mcycle'left); |
end if; |
|
-- mcycleh (cycleh) -- |
1691,12 → 1660,12
end if; |
|
-- minstret (instret) -- |
minstret_msb <= csr.minstret(csr.minstret'left); |
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstret_c) then -- write access |
csr.minstret(31 downto 0) <= csr.wdata; |
csr.minstret(32) <= '0'; |
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update |
csr.minstret <= '0' & csr.wdata; |
minstret_msb <= '0'; |
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update (if CPU commits an instruction) |
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1); |
minstret_msb <= csr.minstret(csr.minstret'left); |
end if; |
|
-- minstreth (instreth) -- |
1705,14 → 1674,12
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update |
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1); |
end if; |
|
end if; |
end if; |
end process csr_write_access; |
|
-- CPU's current privilege level -- |
priv_mode_o <= csr.privilege; |
|
-- PMP output -- |
-- PMP configuration output to bus unit -- |
pmp_output: process(csr) |
begin |
pmp_addr_o <= (others => (others => '0')); |
1743,6 → 1710,8
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low |
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high |
when csr_misa_c => -- R/-: misa - ISA and extensions |
csr.rdata(00) <= '0'; -- A CPU extension |
csr.rdata(01) <= '0'; -- B CPU extension |
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension |
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension |
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E) |
/rtl/core/neorv32_cpu_cp_muldiv.vhd
4,6 → 4,7
-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. # |
-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency # |
-- # Divider core (unsigned) uses serial algorithm. -> 32+6 cycles latency # |
-- # Multiplications can be mapped to DSP block when FAST_MUL_EN = true. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
52,8 → 53,8
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
start_i : in std_ulogic; -- trigger operation |
-- data input -- |
start_i : in std_ulogic; -- trigger operation |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 |
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 |
-- result and status -- |
106,7 → 107,6
begin |
if (rstn_i = '0') then |
state <= IDLE; |
cp_op <= (others => '0'); |
opx <= (others => '0'); |
opy <= (others => '0'); |
cnt <= (others => '0'); |
125,7 → 125,6
opx <= rs1_i; |
opy <= rs2_i; |
if (start_i = '1') then |
cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c); |
state <= DECODE; |
end if; |
|
189,6 → 188,9
end if; |
end process coprocessor_ctrl; |
|
-- co-processor command -- |
cp_op <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c); |
|
-- operation -- |
operation <= '1' when (cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c) or (cp_op = cp_op_rem_c) or (cp_op = cp_op_remu_c) else '0'; |
|
199,11 → 201,12
opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0'; |
|
|
-- Multiplier Core (signed) --------------------------------------------------------------- |
-- Multiplier Core (signed/unsigned) ------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
multiplier_core: process(clk_i) |
begin |
if rising_edge(clk_i) then |
-- --------------------------------------------------------- |
if (FAST_MUL_EN = false) then -- use small iterative computation |
if (start = '1') then -- start new multiplication |
mul_product(63 downto 32) <= (others => '0'); |
212,6 → 215,7
mul_product(63 downto 31) <= mul_do_add(32 downto 0); |
mul_product(30 downto 00) <= mul_product(31 downto 1); |
end if; |
-- --------------------------------------------------------- |
else -- use direct approach using (several!) DSP blocks |
if (start = '1') then |
mul_op_x <= signed((opx(opx'left) and opx_is_signed) & opx); |
/rtl/core/neorv32_cpu_decompressor.vhd
116,10 → 116,10
|
when "000" => -- Illegal_instruction, C.ADDI4SPN |
-- ---------------------------------------------------------------------------------------------------------- |
if (ci_instr16_i(12 downto 2) = "00000000000") then -- "official" illegal instruction |
if (ci_instr16_i(12 downto 2) = "00000000000") then -- "official illegal instruction" |
ci_illegal_o <= '1'; |
|
else -- C.ADDI4SPN |
else |
-- C.ADDI4SPN |
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c; |
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer |
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rd_3_msb_c downto ci_rd_3_lsb_c); |
/rtl/core/neorv32_cpu_regfile.vhd
1,10 → 1,11
-- ################################################################################################# |
-- # << NEORV32 - CPU Register File >> # |
-- # << NEORV32 - CPU Data Register File >> # |
-- # ********************************************************************************************* # |
-- # General purpose data registers. 32 entries for normal mode, 16 entries for embedded mode when # |
-- # RISC-V "E" extension is enabled. Register zero (r0/x0) is a normal physical registers, that # |
-- # has to be initialized to zero by the CPU control system. For normal operations, x0 cannot be # |
-- # written. # |
-- # General purpose data register file. 32 entries for normal mode (I), 16 entries for embedded # |
-- # mode (E) when RISC-V "E" extension is enabled. Register zero (r0) is a normal physical # |
-- # registers, that has to be initialized to zero by the CPU control system. For normal # |
-- # operations r0 cannot be written. The register file uses synchronous reads. Hence it can be # |
-- # mapped to FPGA block RAM. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
71,22 → 72,10
signal reg_file : reg_file_t; |
signal reg_file_emb : reg_file_emb_t; |
signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data |
signal valid_wr : std_ulogic; -- writing not to r0 |
signal rd_is_r0 : std_ulogic; -- writing to r0? |
signal rf_we : std_ulogic; |
signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address |
|
|
-- attributes - these are *NOT mandatory*; just for footprint / timing optimization -- |
-- -------------------------------------------------------------------------------- -- |
|
-- lattice radiant -- |
attribute syn_ramstyle : string; |
attribute syn_ramstyle of reg_file : signal is "no_rw_check"; |
attribute syn_ramstyle of reg_file_emb : signal is "no_rw_check"; |
|
-- intel quartus prime -- |
attribute ramstyle : string; |
attribute ramstyle of reg_file : signal is "no_rw_check"; |
attribute ramstyle of reg_file_emb : signal is "no_rw_check"; |
|
begin |
|
-- Input mux ------------------------------------------------------------------------------ |
101,11 → 90,17
end case; |
end process input_mux; |
|
-- only write if destination is not x0; except we are forcing a r0 write access -- |
valid_wr <= or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) or ctrl_i(ctrl_rf_r0_we_c) when (CPU_EXTENSION_RISCV_E = false) else |
or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)) or ctrl_i(ctrl_rf_r0_we_c); |
-- check if we are writing to x0 -- |
rd_is_r0 <= not or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else |
not or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)); |
|
-- valid RF write access -- |
rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c); |
|
-- destination address -- |
dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0? |
|
|
-- Register file read/write access -------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
rf_access: process(clk_i) |
112,21 → 107,19
begin |
if rising_edge(clk_i) then -- sync read and write |
if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries |
-- write -- |
if (ctrl_i(ctrl_rf_wb_en_c) = '1') and ((valid_wr = '1') or (rf_r0_is_reg_c = false)) then -- valid write-back |
reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data; |
if (rf_we = '1') then |
reg_file(to_integer(unsigned(dst_addr(4 downto 0)))) <= rf_write_data; |
else -- read |
rs1_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c)))); |
rs2_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c)))); |
end if; |
-- read -- |
rs1_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c)))); |
rs2_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c)))); |
else -- embedded register file with 16 entries |
-- write -- |
if (ctrl_i(ctrl_rf_wb_en_c) = '1') and ((valid_wr = '1') or (rf_r0_is_reg_c = false)) then -- valid write-back |
reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data; |
if (rf_we = '1') then |
reg_file_emb(to_integer(unsigned(dst_addr(3 downto 0)))) <= rf_write_data; |
else -- read |
rs1_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c)))); |
rs2_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c)))); |
end if; |
-- read -- |
rs1_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c)))); |
rs2_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c)))); |
end if; |
end if; |
end process rf_access; |
/rtl/core/neorv32_package.vhd
38,22 → 38,22
|
package neorv32_package is |
|
-- Architecture Configuration ------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address |
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address |
constant bus_timeout_c : natural := 127; -- cycles after which a valid bus access will timeout and trigger an access exception |
constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode |
constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2 |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW |
|
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040600"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040606"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
|
-- Architecture Configuration ------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant ispace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"00000000"; -- default instruction memory address space base address |
constant dspace_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"80000000"; -- default data memory address space base address |
constant bus_timeout_c : natural := 127; -- cycles after which a valid bus access will timeout and triggers an access exception |
constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode (better timing) |
constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2 |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW |
|
-- Helper Functions ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
function index_size_f(input : natural) return natural; |
66,6 → 66,7
function xnor_all_f(a : std_ulogic_vector) return std_ulogic; |
function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character; |
function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector; |
function is_power_of_two_f(input : natural) return boolean; |
|
-- Internal Types ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
160,57 → 161,73
-- Main Control Bus ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- register file -- |
constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (00=ALU, 01=MEM) |
constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (10=PC, 11=CSR) |
constant ctrl_rf_rs1_adr0_c : natural := 2; -- source register 1 address bit 0 |
constant ctrl_rf_rs1_adr1_c : natural := 3; -- source register 1 address bit 1 |
constant ctrl_rf_rs1_adr2_c : natural := 4; -- source register 1 address bit 2 |
constant ctrl_rf_rs1_adr3_c : natural := 5; -- source register 1 address bit 3 |
constant ctrl_rf_rs1_adr4_c : natural := 6; -- source register 1 address bit 4 |
constant ctrl_rf_rs2_adr0_c : natural := 7; -- source register 2 address bit 0 |
constant ctrl_rf_rs2_adr1_c : natural := 8; -- source register 2 address bit 1 |
constant ctrl_rf_rs2_adr2_c : natural := 9; -- source register 2 address bit 2 |
constant ctrl_rf_rs2_adr3_c : natural := 10; -- source register 2 address bit 3 |
constant ctrl_rf_rs2_adr4_c : natural := 11; -- source register 2 address bit 4 |
constant ctrl_rf_rd_adr0_c : natural := 12; -- destiantion register address bit 0 |
constant ctrl_rf_rd_adr1_c : natural := 13; -- destiantion register address bit 1 |
constant ctrl_rf_rd_adr2_c : natural := 14; -- destiantion register address bit 2 |
constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3 |
constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4 |
constant ctrl_rf_wb_en_c : natural := 17; -- write back enable |
constant ctrl_rf_r0_we_c : natural := 18; -- allow write access to r0 (zero) |
constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (00=ALU, 01=MEM) |
constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (10=PC, 11=CSR) |
constant ctrl_rf_rs1_adr0_c : natural := 2; -- source register 1 address bit 0 |
constant ctrl_rf_rs1_adr1_c : natural := 3; -- source register 1 address bit 1 |
constant ctrl_rf_rs1_adr2_c : natural := 4; -- source register 1 address bit 2 |
constant ctrl_rf_rs1_adr3_c : natural := 5; -- source register 1 address bit 3 |
constant ctrl_rf_rs1_adr4_c : natural := 6; -- source register 1 address bit 4 |
constant ctrl_rf_rs2_adr0_c : natural := 7; -- source register 2 address bit 0 |
constant ctrl_rf_rs2_adr1_c : natural := 8; -- source register 2 address bit 1 |
constant ctrl_rf_rs2_adr2_c : natural := 9; -- source register 2 address bit 2 |
constant ctrl_rf_rs2_adr3_c : natural := 10; -- source register 2 address bit 3 |
constant ctrl_rf_rs2_adr4_c : natural := 11; -- source register 2 address bit 4 |
constant ctrl_rf_rd_adr0_c : natural := 12; -- destiantion register address bit 0 |
constant ctrl_rf_rd_adr1_c : natural := 13; -- destiantion register address bit 1 |
constant ctrl_rf_rd_adr2_c : natural := 14; -- destiantion register address bit 2 |
constant ctrl_rf_rd_adr3_c : natural := 15; -- destiantion register address bit 3 |
constant ctrl_rf_rd_adr4_c : natural := 16; -- destiantion register address bit 4 |
constant ctrl_rf_wb_en_c : natural := 17; -- write back enable |
constant ctrl_rf_r0_we_c : natural := 18; -- force write access and force rd=r0 |
-- alu -- |
constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0 |
constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1 |
constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2 |
constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB |
constant ctrl_alu_opa_mux_c : natural := 23; -- operand A select (0=rs1, 1=PC) |
constant ctrl_alu_opb_mux_c : natural := 24; -- operand B select (0=rs2, 1=IMM) |
constant ctrl_alu_unsigned_c : natural := 25; -- is unsigned ALU operation |
constant ctrl_alu_shift_dir_c : natural := 26; -- shift direction (0=left, 1=right) |
constant ctrl_alu_shift_ar_c : natural := 27; -- is arithmetic shift |
constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0 |
constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1 |
constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2 |
constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB |
constant ctrl_alu_opa_mux_c : natural := 23; -- operand A select (0=rs1, 1=PC) |
constant ctrl_alu_opb_mux_c : natural := 24; -- operand B select (0=rs2, 1=IMM) |
constant ctrl_alu_unsigned_c : natural := 25; -- is unsigned ALU operation |
constant ctrl_alu_shift_dir_c : natural := 26; -- shift direction (0=left, 1=right) |
constant ctrl_alu_shift_ar_c : natural := 27; -- is arithmetic shift |
-- bus interface -- |
constant ctrl_bus_size_lsb_c : natural := 28; -- transfer size lsb (00=byte, 01=half-word) |
constant ctrl_bus_size_msb_c : natural := 29; -- transfer size msb (10=word, 11=?) |
constant ctrl_bus_rd_c : natural := 30; -- read data request |
constant ctrl_bus_wr_c : natural := 31; -- write data request |
constant ctrl_bus_if_c : natural := 32; -- instruction fetch request |
constant ctrl_bus_mar_we_c : natural := 33; -- memory address register write enable |
constant ctrl_bus_mdo_we_c : natural := 34; -- memory data out register write enable |
constant ctrl_bus_mdi_we_c : natural := 35; -- memory data in register write enable |
constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load |
constant ctrl_bus_ierr_ack_c : natural := 37; -- acknowledge instruction fetch bus exceptions |
constant ctrl_bus_derr_ack_c : natural := 38; -- acknowledge data access bus exceptions |
constant ctrl_bus_fence_c : natural := 39; -- executed fence operation |
constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation |
constant ctrl_bus_size_lsb_c : natural := 28; -- transfer size lsb (00=byte, 01=half-word) |
constant ctrl_bus_size_msb_c : natural := 29; -- transfer size msb (10=word, 11=?) |
constant ctrl_bus_rd_c : natural := 30; -- read data request |
constant ctrl_bus_wr_c : natural := 31; -- write data request |
constant ctrl_bus_if_c : natural := 32; -- instruction fetch request |
constant ctrl_bus_mar_we_c : natural := 33; -- memory address register write enable |
constant ctrl_bus_mdo_we_c : natural := 34; -- memory data out register write enable |
constant ctrl_bus_mdi_we_c : natural := 35; -- memory data in register write enable |
constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load |
constant ctrl_bus_ierr_ack_c : natural := 37; -- acknowledge instruction fetch bus exceptions |
constant ctrl_bus_derr_ack_c : natural := 38; -- acknowledge data access bus exceptions |
constant ctrl_bus_fence_c : natural := 39; -- executed fence operation |
constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation |
-- co-processors -- |
constant ctrl_cp_id_lsb_c : natural := 41; -- cp select ID lsb |
constant ctrl_cp_id_msb_c : natural := 42; -- cp select ID msb |
constant ctrl_cp_cmd0_c : natural := 43; -- cp command bit 0 |
constant ctrl_cp_cmd1_c : natural := 44; -- cp command bit 1 |
constant ctrl_cp_cmd2_c : natural := 45; -- cp command bit 2 |
constant ctrl_cp_id_lsb_c : natural := 41; -- cp select ID lsb |
constant ctrl_cp_id_msb_c : natural := 42; -- cp select ID msb |
-- current privilege level -- |
constant ctrl_priv_lvl_lsb_c : natural := 43; -- privilege level lsb |
constant ctrl_priv_lvl_msb_c : natural := 44; -- privilege level msb |
-- instruction's control blocks -- |
constant ctrl_ir_funct3_0_c : natural := 45; -- funct3 bit 0 |
constant ctrl_ir_funct3_1_c : natural := 46; -- funct3 bit 1 |
constant ctrl_ir_funct3_2_c : natural := 47; -- funct3 bit 2 |
constant ctrl_ir_funct12_0_c : natural := 48; -- funct12 bit 0 |
constant ctrl_ir_funct12_1_c : natural := 49; -- funct12 bit 1 |
constant ctrl_ir_funct12_2_c : natural := 50; -- funct12 bit 2 |
constant ctrl_ir_funct12_3_c : natural := 51; -- funct12 bit 3 |
constant ctrl_ir_funct12_4_c : natural := 52; -- funct12 bit 4 |
constant ctrl_ir_funct12_5_c : natural := 53; -- funct12 bit 5 |
constant ctrl_ir_funct12_6_c : natural := 54; -- funct12 bit 6 |
constant ctrl_ir_funct12_7_c : natural := 55; -- funct12 bit 7 |
constant ctrl_ir_funct12_8_c : natural := 56; -- funct12 bit 8 |
constant ctrl_ir_funct12_9_c : natural := 57; -- funct12 bit 9 |
constant ctrl_ir_funct12_10_c : natural := 58; -- funct12 bit 10 |
constant ctrl_ir_funct12_11_c : natural := 59; -- funct12 bit 11 |
-- control bus size -- |
constant ctrl_width_c : natural := 46; -- control bus size |
constant ctrl_width_c : natural := 60; -- control bus size |
|
-- ALU Comparator Bus --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
308,63 → 325,66
|
-- RISC-V CSR Addresses ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus |
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; -- misa |
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; -- mie |
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305"; -- mtvec |
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus |
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; -- misa |
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; -- mie |
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305"; -- mtvec |
-- |
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340"; -- mscratch |
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341"; -- mepc |
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342"; -- mcause |
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343"; -- mtval |
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344"; -- mip |
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340"; -- mscratch |
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341"; -- mepc |
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342"; -- mcause |
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343"; -- mtval |
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344"; -- mip |
-- |
constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := x"3a0"; -- pmpcfg0 |
constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := x"3a1"; -- pmpcfg1 |
constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := x"3a0"; -- pmpcfg0 |
constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := x"3a1"; -- pmpcfg1 |
-- |
constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := x"3b0"; -- pmpaddr0 |
constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := x"3b1"; -- pmpaddr1 |
constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := x"3b2"; -- pmpaddr2 |
constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := x"3b3"; -- pmpaddr3 |
constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := x"3b4"; -- pmpaddr4 |
constant csr_pmpaddr5_c : std_ulogic_vector(11 downto 0) := x"3b5"; -- pmpaddr5 |
constant csr_pmpaddr6_c : std_ulogic_vector(11 downto 0) := x"3b6"; -- pmpaddr6 |
constant csr_pmpaddr7_c : std_ulogic_vector(11 downto 0) := x"3b7"; -- pmpaddr7 |
constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := x"3b0"; -- pmpaddr0 |
constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := x"3b1"; -- pmpaddr1 |
constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := x"3b2"; -- pmpaddr2 |
constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := x"3b3"; -- pmpaddr3 |
constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := x"3b4"; -- pmpaddr4 |
constant csr_pmpaddr5_c : std_ulogic_vector(11 downto 0) := x"3b5"; -- pmpaddr5 |
constant csr_pmpaddr6_c : std_ulogic_vector(11 downto 0) := x"3b6"; -- pmpaddr6 |
constant csr_pmpaddr7_c : std_ulogic_vector(11 downto 0) := x"3b7"; -- pmpaddr7 |
-- |
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00"; -- mcycle |
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02"; -- minstret |
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00"; -- mcycle |
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02"; -- minstret |
-- |
constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := x"b80"; -- mcycleh |
constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := x"b82"; -- minstreth |
constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := x"b80"; -- mcycleh |
constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := x"b82"; -- minstreth |
-- |
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00"; -- cycle |
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01"; -- time |
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02"; -- instret |
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00"; -- cycle |
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01"; -- time |
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02"; -- instret |
-- |
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80"; -- cycleh |
constant csr_timeh_c : std_ulogic_vector(11 downto 0) := x"c81"; -- timeh |
constant csr_instreth_c : std_ulogic_vector(11 downto 0) := x"c82"; -- instreth |
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80"; -- cycleh |
constant csr_timeh_c : std_ulogic_vector(11 downto 0) := x"c81"; -- timeh |
constant csr_instreth_c : std_ulogic_vector(11 downto 0) := x"c82"; -- instreth |
-- |
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11"; -- mvendorid |
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12"; -- marchid |
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13"; -- mimpid |
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; -- mhartid |
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11"; -- mvendorid |
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12"; -- marchid |
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13"; -- mimpid |
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; -- mhartid |
-- |
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0"; -- mzext |
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0"; -- mzext (custom) |
|
-- Co-Processor Operations ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- cp ids -- |
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV CP |
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV |
constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "01"; -- BITMANIP |
--constant cp_sel_reserved_c : std_ulogic_vector(1 downto 0) := "10"; -- reserved |
--constant cp_sel_reserved_c : std_ulogic_vector(1 downto 0) := "11"; -- reserved |
-- muldiv cp -- |
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul |
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh |
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu |
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu |
constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"; -- div |
constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"; -- divu |
constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem |
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu |
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul |
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh |
constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu |
constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu |
constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"; -- div |
constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"; -- divu |
constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem |
constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu |
|
-- ALU Function Codes --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
448,6 → 468,7
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
488,6 → 509,7
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
-- Wishbone bus interface -- |
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
498,7 → 520,6
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
priv_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
-- GPIO -- |
529,8 → 550,8
component neorv32_cpu |
generic ( |
-- General -- |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address |
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
616,7 → 637,8
-- data input -- |
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction |
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status |
alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU processing result |
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 |
-- data output -- |
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
634,7 → 656,6
-- physical memory protection -- |
pmp_addr_o : out pmp_addr_if_t; -- addresses |
pmp_ctrl_o : out pmp_ctrl_if_t; -- configs |
priv_mode_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level |
-- bus access exceptions -- |
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register |
ma_instr_i : in std_ulogic; -- misaligned instruction address |
687,6 → 708,8
-- data output -- |
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status |
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result |
opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU operand B |
-- co-processor interface -- |
cp0_start_o : out std_ulogic; -- trigger co-processor 0 |
cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result |
694,6 → 717,12
cp1_start_o : out std_ulogic; -- trigger co-processor 1 |
cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result |
cp1_valid_i : in std_ulogic; -- co-processor 1 result valid |
cp2_start_o : out std_ulogic; -- trigger co-processor 2 |
cp2_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 2 result |
cp2_valid_i : in std_ulogic; -- co-processor 2 result valid |
cp3_start_o : out std_ulogic; -- trigger co-processor 3 |
cp3_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 3 result |
cp3_valid_i : in std_ulogic; -- co-processor 3 result valid |
-- status -- |
wait_o : out std_ulogic -- busy due to iterative processing units |
); |
710,8 → 739,8
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
start_i : in std_ulogic; -- trigger operation |
-- data input -- |
start_i : in std_ulogic; -- trigger operation |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1 |
rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2 |
-- result and status -- |
733,7 → 762,6
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
-- cpu instruction fetch interface -- |
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
756,7 → 784,6
-- physical memory protection -- |
pmp_addr_i : in pmp_addr_if_t; -- addresses |
pmp_ctrl_i : in pmp_ctrl_if_t; -- configs |
priv_mode_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level |
-- instruction bus -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
814,6 → 841,7
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus -- |
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B |
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
1080,6 → 1108,7
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
-- host access -- |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
1089,7 → 1118,9
cancel_i : in std_ulogic; -- cancel current bus transaction |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level |
-- wishbone interface -- |
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
1326,4 → 1357,15
return output_v; |
end function bit_rev_f; |
|
-- Function: Test if input number is a power of two --------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
function is_power_of_two_f(input : natural) return boolean is |
begin |
if ((input / 2) /= 0) and ((input mod 2) = 0) then |
return true; |
else |
return false; |
end if; |
end function is_power_of_two_f; |
|
end neorv32_package; |
/rtl/core/neorv32_spi.vhd
1,8 → 1,9
-- ################################################################################################# |
-- # << NEORV32 - Serial Peripheral Interface Controller (SPI) >> # |
-- # ********************************************************************************************* # |
-- # Frame format: 8/16/24/32-bit RTX, MSB or LSB first, 2 clock modes, 8 clock speeds, # |
-- # 8 dedicated CS lines (low-active). Interrupt: SPI_transfer_done # |
-- # Frame format: 8/16/24/32-bit receive/transmit data, always MSB first, 2 clock modes, # |
-- # 8 clock speeds (derived from system clock), 8 dedicated chip-select lines (low-active). # |
-- # Interrupt: SPI_transfer_done # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
86,12 → 87,10
constant ctrl_spi_prsc0_c : natural := 10; -- r/w: spi prescaler select bit 0 |
constant ctrl_spi_prsc1_c : natural := 11; -- r/w: spi prescaler select bit 1 |
constant ctrl_spi_prsc2_c : natural := 12; -- r/w: spi prescaler select bit 2 |
constant ctrl_spi_dir_c : natural := 13; -- r/w: shift direction (0: MSB first, 1: LSB first) |
constant ctrl_spi_size0_c : natural := 14; -- r/w: data size (00: 8-bit, 01: 16-bit) |
constant ctrl_spi_size1_c : natural := 15; -- r/w: data size (10: 24-bit, 11: 32-bit) |
constant ctrl_spi_size0_c : natural := 13; -- r/w: data size (00: 8-bit, 01: 16-bit) |
constant ctrl_spi_size1_c : natural := 14; -- r/w: data size (10: 24-bit, 11: 32-bit) |
constant ctrl_spi_irq_en_c : natural := 15; -- r/w: spi transmission done interrupt enable |
-- |
constant ctrl_spi_irq_en_c : natural := 16; -- r/w: spi transmission done interrupt enable |
-- |
constant ctrl_spi_busy_c : natural := 31; -- r/-: spi transceiver is busy |
|
-- access control -- |
101,22 → 100,24
signal rden : std_ulogic; -- read enable |
|
-- accessible regs -- |
signal ctrl : std_ulogic_vector(16 downto 0); |
signal tx_data : std_ulogic_vector(31 downto 0); |
signal ctrl : std_ulogic_vector(15 downto 0); |
signal tx_data_reg : std_ulogic_vector(31 downto 0); |
signal rx_data : std_ulogic_vector(31 downto 0); |
|
-- clock generator -- |
signal spi_clk : std_ulogic; |
|
-- spi transceiver -- |
signal spi_start : std_ulogic; |
signal spi_busy : std_ulogic; |
signal spi_state0 : std_ulogic; |
signal spi_state1 : std_ulogic; |
signal spi_rtx_sreg : std_ulogic_vector(31 downto 0); |
signal spi_rx_data : std_ulogic_vector(31 downto 0); |
signal spi_bitcnt : std_ulogic_vector(05 downto 0); |
signal spi_sdi_ff0 : std_ulogic; |
signal spi_sdi_ff1 : std_ulogic; |
signal spi_start : std_ulogic; |
signal spi_busy : std_ulogic; |
signal spi_state0 : std_ulogic; |
signal spi_state1 : std_ulogic; |
signal spi_rtx_sreg : std_ulogic_vector(31 downto 0); |
signal spi_rx_data : std_ulogic_vector(31 downto 0); |
signal spi_bitcnt : std_ulogic_vector(05 downto 0); |
signal spi_bitcnt_max : std_ulogic_vector(05 downto 0); |
signal spi_sdi_ff0 : std_ulogic; |
signal spi_sdi_ff1 : std_ulogic; |
|
begin |
|
134,17 → 135,15
begin |
if rising_edge(clk_i) then |
ack_o <= acc_en and (rden_i or wren_i); |
-- write access -- |
spi_start <= '0'; |
-- write access -- |
if (wren = '1') then |
-- control regsiter -- |
if (addr = spi_ctrl_addr_c) then |
if (addr = spi_ctrl_addr_c) then -- control |
ctrl <= data_i(ctrl'left downto 0); |
end if; |
-- data regsiter -- |
if (addr = spi_rtx_addr_c) then |
tx_data <= data_i; |
spi_start <= '1'; |
if (addr = spi_rtx_addr_c) then -- tx data |
tx_data_reg <= data_i; |
spi_start <= '1'; |
end if; |
end if; |
-- read access -- |
165,29 → 164,20
data_o(ctrl_spi_prsc0_c) <= ctrl(ctrl_spi_prsc0_c); |
data_o(ctrl_spi_prsc1_c) <= ctrl(ctrl_spi_prsc1_c); |
data_o(ctrl_spi_prsc2_c) <= ctrl(ctrl_spi_prsc2_c); |
data_o(ctrl_spi_dir_c) <= ctrl(ctrl_spi_dir_c); |
data_o(ctrl_spi_size0_c) <= ctrl(ctrl_spi_size0_c); |
data_o(ctrl_spi_size1_c) <= ctrl(ctrl_spi_size1_c); |
-- |
data_o(ctrl_spi_irq_en_c) <= ctrl(ctrl_spi_irq_en_c); |
-- |
data_o(ctrl_spi_busy_c) <= spi_busy; |
else -- spi_rtx_addr_c |
data_o <= spi_rx_data; |
data_o <= rx_data; |
end if; |
end if; |
end if; |
end process rw_access; |
|
-- direct CS (output is low-active) -- |
spi_csn_o(0) <= '0' when (ctrl(ctrl_spi_cs0_c) = '1') else '1'; |
spi_csn_o(1) <= '0' when (ctrl(ctrl_spi_cs1_c) = '1') else '1'; |
spi_csn_o(2) <= '0' when (ctrl(ctrl_spi_cs2_c) = '1') else '1'; |
spi_csn_o(3) <= '0' when (ctrl(ctrl_spi_cs3_c) = '1') else '1'; |
spi_csn_o(4) <= '0' when (ctrl(ctrl_spi_cs4_c) = '1') else '1'; |
spi_csn_o(5) <= '0' when (ctrl(ctrl_spi_cs5_c) = '1') else '1'; |
spi_csn_o(6) <= '0' when (ctrl(ctrl_spi_cs6_c) = '1') else '1'; |
spi_csn_o(7) <= '0' when (ctrl(ctrl_spi_cs7_c) = '1') else '1'; |
-- direct chip-select (CS) (output is low-active) -- |
spi_csn_o(7 downto 0) <= not ctrl(ctrl_spi_cs7_c downto ctrl_spi_cs0_c); |
|
|
-- Clock Selection ------------------------------------------------------------------------ |
211,61 → 201,50
-- serial engine -- |
spi_irq_o <= '0'; |
if (spi_state0 = '0') or (ctrl(ctrl_spi_en_c) = '0') then -- idle or disabled |
case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is |
when "00" => spi_bitcnt <= "001000"; -- 8-bit mode |
when "01" => spi_bitcnt <= "010000"; -- 16-bit mode |
when "10" => spi_bitcnt <= "011000"; -- 24-bit mode |
when others => spi_bitcnt <= "100000"; -- 32-bit mode |
end case; |
-- -------------------------------------------------------------- |
spi_bitcnt <= (others => '0'); |
spi_state1 <= '0'; |
spi_sdo_o <= '0'; |
spi_sck_o <= '0'; |
spi_sdo_o <= '0'; |
spi_sck_o <= '0'; |
if (ctrl(ctrl_spi_en_c) = '0') then -- disabled |
spi_busy <= '0'; |
elsif (spi_start = '1') then -- start new transmission |
case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is |
when "00" => spi_rtx_sreg <= tx_data(07 downto 0) & x"000000"; -- 8-bit mode |
when "01" => spi_rtx_sreg <= tx_data(15 downto 0) & x"0000"; -- 16-bit mode |
when "10" => spi_rtx_sreg <= tx_data(23 downto 0) & x"00"; -- 24-bit mode |
when others => spi_rtx_sreg <= tx_data(31 downto 0); -- 32-bit mode |
end case; |
spi_busy <= '1'; |
spi_rtx_sreg <= tx_data_reg; |
spi_busy <= '1'; |
end if; |
spi_state0 <= spi_busy and spi_clk; -- start with next new clock pulse |
|
else -- transmission in progress |
-- -------------------------------------------------------------- |
if (spi_state1 = '0') then -- first half of transmission |
-- -------------------------------------------------------------- |
spi_sck_o <= ctrl(ctrl_spi_cpha_c); |
|
spi_sck_o <= ctrl(ctrl_spi_cpha_c); |
if (ctrl(ctrl_spi_dir_c) = '0') then |
spi_sdo_o <= spi_rtx_sreg(31); -- MSB first |
else |
spi_sdo_o <= spi_rtx_sreg(0); -- LSB first |
end if; |
case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is |
when "00" => spi_sdo_o <= spi_rtx_sreg(07); -- 8-bit mode |
when "01" => spi_sdo_o <= spi_rtx_sreg(15); -- 16-bit mode |
when "10" => spi_sdo_o <= spi_rtx_sreg(23); -- 24-bit mode |
when others => spi_sdo_o <= spi_rtx_sreg(31); -- 32-bit mode |
end case; |
|
if (spi_clk = '1') then |
spi_state1 <= '1'; |
if (ctrl(ctrl_spi_cpha_c) = '0') then |
if (ctrl(ctrl_spi_dir_c) = '0') then |
spi_rtx_sreg <= spi_rtx_sreg(30 downto 0) & spi_sdi_ff1; -- MSB first |
else |
spi_rtx_sreg <= spi_sdi_ff1 & spi_rtx_sreg(31 downto 1); -- LSB first |
end if; |
spi_rtx_sreg <= spi_rtx_sreg(30 downto 0) & spi_sdi_ff1; |
end if; |
spi_bitcnt <= std_ulogic_vector(unsigned(spi_bitcnt) - 1); |
spi_bitcnt <= std_ulogic_vector(unsigned(spi_bitcnt) + 1); |
end if; |
|
else -- second half of transmission |
-- -------------------------------------------------------------- |
spi_sck_o <= not ctrl(ctrl_spi_cpha_c); |
|
spi_sck_o <= not ctrl(ctrl_spi_cpha_c); |
if (spi_clk = '1') then |
spi_state1 <= '0'; |
if (ctrl(ctrl_spi_cpha_c) = '1') then |
if (ctrl(ctrl_spi_dir_c) = '0') then |
spi_rtx_sreg <= spi_rtx_sreg(30 downto 0) & spi_sdi_ff1; -- MSB first |
else |
spi_rtx_sreg <= spi_sdi_ff1 & spi_rtx_sreg(31 downto 1); -- LSB first |
end if; |
spi_rtx_sreg <= spi_rtx_sreg(30 downto 0) & spi_sdi_ff1; |
end if; |
if (spi_bitcnt = "000000") then |
if (spi_bitcnt = spi_bitcnt_max) then |
spi_state0 <= '0'; |
spi_busy <= '0'; |
spi_irq_o <= ctrl(ctrl_spi_irq_en_c); |
276,16 → 255,31
end if; |
end process spi_rtx_unit; |
|
-- SPI receiver output -- |
spi_rx_output: process(ctrl, spi_rtx_sreg) |
|
-- RTX Data size ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
data_size: process(ctrl) |
begin |
case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is |
when "00" => spi_rx_data <= x"000000" & spi_rtx_sreg(7 downto 0); -- 8-bit mode |
when "01" => spi_rx_data <= x"0000" & spi_rtx_sreg(15 downto 0); -- 16-bit mode |
when "10" => spi_rx_data <= x"00" & spi_rtx_sreg(23 downto 0); -- 24-bit mode |
when others => spi_rx_data <= spi_rtx_sreg(31 downto 0); -- 32-bit mode |
when "00" => spi_bitcnt_max <= "001000"; -- 8-bit mode |
when "01" => spi_bitcnt_max <= "010000"; -- 16-bit mode |
when "10" => spi_bitcnt_max <= "011000"; -- 24-bit mode |
when others => spi_bitcnt_max <= "100000"; -- 32-bit mode |
end case; |
end process spi_rx_output; |
end process data_size; |
|
|
-- RX-Data Masking ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
rx_mapping: process(ctrl, spi_rtx_sreg) |
begin |
case ctrl(ctrl_spi_size1_c downto ctrl_spi_size0_c) is |
when "00" => rx_data <= x"000000" & spi_rtx_sreg(07 downto 0); -- 8-bit mode |
when "01" => rx_data <= x"0000" & spi_rtx_sreg(15 downto 0); -- 16-bit mode |
when "10" => rx_data <= x"00" & spi_rtx_sreg(23 downto 0); -- 24-bit mode |
when others => rx_data <= spi_rtx_sreg(31 downto 0); -- 32-bit mode |
end case; |
end process rx_mapping; |
|
|
end neorv32_spi_rtl; |
/rtl/core/neorv32_top.vhd
51,6 → 51,7
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
91,6 → 92,7
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
-- Wishbone bus interface (available if MEM_EXT_USE = true) -- |
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
101,7 → 103,6
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
priv_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
-- GPIO (available if IO_GPIO_USE = true) -- |
170,6 → 171,7
err : std_ulogic; -- bus transfer error |
fence : std_ulogic; -- fence(i) instruction executed |
priv : std_ulogic_vector(1 downto 0); -- current privilege level |
src : std_ulogic; -- access source |
end record; |
signal cpu_i, cpu_d, p_bus : bus_interface_t; |
|
227,6 → 229,8
|
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- clock -- |
assert not (CLOCK_FREQUENCY = 0) report "NEORV32 PROCESSOR CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error; |
-- internal bootloader ROM -- |
assert not ((BOOTLOADER_USE = true) and (boot_rom_size_c > boot_rom_max_size_c)) report "NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range." severity error; |
assert not ((BOOTLOADER_USE = true) and (MEM_INT_IMEM_ROM = true)) report "NEORV32 PROCESSOR CONFIG WARNING! IMEM is configured as read-only. Bootloader will not be able to load new executables." severity warning; |
233,17 → 237,18
-- memory system - data/instruction fetch -- |
assert not ((MEM_EXT_USE = false) and (MEM_INT_DMEM_USE = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal data memory." severity error; |
assert not ((MEM_EXT_USE = false) and (MEM_INT_IMEM_USE = false) and (BOOTLOADER_USE = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch instructions without external memory interface, internal data memory and bootloader." severity error; |
-- memory system - size -- |
assert not ((MEM_INT_DMEM_USE = true) and (is_power_of_two_f(MEM_INT_IMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_IMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning; |
assert not ((MEM_INT_IMEM_USE = true) and (is_power_of_two_f(MEM_INT_DMEM_SIZE) = false)) report "NEORV32 PROCESSOR CONFIG WARNING! MEM_INT_DMEM_SIZE should be a power of 2 to allow optimal hardware mapping." severity warning; |
-- memory system - alignment -- |
assert not (ispace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address must be 4-byte-aligned." severity error; |
assert not (dspace_base_c(1 downto 0) /= "00") report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address must be 4-byte-aligned." severity error; |
assert not ((ispace_base_c(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) /= imem_align_check_c) and (MEM_INT_IMEM_USE = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Instruction memory space base address has to be aligned to IMEM size." severity error; |
assert not ((dspace_base_c(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) /= dmem_align_check_c) and (MEM_INT_DMEM_USE = true)) report "NEORV32 PROCESSOR CONFIG ERROR! Data memory space base address has to be aligned to DMEM size." severity error; |
-- clock -- |
assert not (CLOCK_FREQUENCY = 0) report "NEORV32 PROCESSOR CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error; |
-- memory layout warning -- |
-- memory system - layout warning -- |
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning; |
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning; |
-- memory latency notifier (warning) -- |
-- (external) memory latency notifier (warning) -- |
assert not (MEM_EXT_USE = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning; |
-- external memory iterface protocol notifier (warning) -- |
assert not ((MEM_EXT_USE = true) and (wb_pipe_mode_c = false)) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol." severity warning; |
313,7 → 318,7
neorv32_cpu_inst: neorv32_cpu |
generic map ( |
-- General -- |
HW_THREAD_ID => (others => '0'), -- hardware thread id |
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id |
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
368,8 → 373,11
firq_i => fast_irq |
); |
|
-- misc -- |
cpu_i.src <= '1'; |
cpu_d.src <= '0'; |
|
-- advanced memory control -- |
priv_o <= cpu_i.priv; -- is the same as "cpu_d.priv" |
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation |
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation |
|
412,6 → 420,7
cb_bus_ack_o => cpu_i.ack, -- bus transfer acknowledge |
cb_bus_err_o => cpu_i.err, -- bus transfer error |
-- peripheral bus -- |
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions) |
p_bus_addr_o => p_bus.addr, -- bus access address |
p_bus_rdata_i => p_bus.rdata, -- bus read data |
p_bus_wdata_o => p_bus.wdata, -- bus write data |
434,7 → 443,10
-- processor bus: CPU data bus error input -- |
p_bus.err <= wishbone_err; |
|
-- current CPU privilege level -- |
p_bus.priv <= cpu_i.priv; -- cpu_i.priv == cpu_d.priv |
|
|
-- Processor-Internal Instruction Memory (IMEM) ------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_int_imem_inst_true: |
538,6 → 550,7
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active |
-- host access -- |
src_i => p_bus.src, -- access type (0: data, 1:instruction) |
addr_i => p_bus.addr, -- address |
rden_i => p_bus.re, -- read enable |
wren_i => p_bus.we, -- write enable |
547,7 → 560,9
cancel_i => p_bus.cancel, -- cancel current transaction |
ack_o => wishbone_ack, -- transfer acknowledge |
err_o => wishbone_err, -- transfer error |
priv_i => p_bus.priv, -- current CPU privilege level |
-- wishbone interface -- |
wb_tag_o => wb_tag_o, -- tag |
wb_adr_o => wb_adr_o, -- address |
wb_dat_i => wb_dat_i, -- read data |
wb_dat_o => wb_dat_o, -- write data |
572,6 → 587,7
wb_sel_o <= (others => '0'); |
wb_stb_o <= '0'; |
wb_cyc_o <= '0'; |
wb_tag_o <= (others => '0'); |
end generate; |
|
|
/rtl/core/neorv32_wishbone.vhd
64,6 → 64,7
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
-- host access -- |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
73,7 → 74,9
cancel_i : in std_ulogic; -- cancel current bus transaction |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level |
-- wishbone interface -- |
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
112,11 → 115,13
ack : std_ulogic; |
err : std_ulogic; |
timeout : std_ulogic_vector(index_size_f(wb_timeout_c)-1 downto 0); |
src : std_ulogic; |
priv : std_ulogic_vector(1 downto 0); |
end record; |
signal ctrl : ctrl_t; |
signal ctrl : ctrl_t; |
signal stb_int : std_ulogic; |
signal cyc_int : std_ulogic; |
|
signal stb_int, cyc_int : std_ulogic; |
|
begin |
|
-- Sanity Checks -------------------------------------------------------------------------- |
157,6 → 162,8
ctrl.timeout <= (others => '0'); |
ctrl.ack <= '0'; |
ctrl.err <= '0'; |
ctrl.src <= '0'; |
ctrl.priv <= "00"; |
elsif rising_edge(clk_i) then |
-- defaults -- |
ctrl.state_prev <= ctrl.state; |
177,6 → 184,8
ctrl.adr <= addr_i; |
ctrl.wdat <= data_i; |
ctrl.sel <= ben_i; |
ctrl.src <= src_i; |
ctrl.priv <= priv_i; |
-- valid read/write access -- |
if ((wb_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then |
ctrl.state <= BUSY; |
214,7 → 223,6
end if; |
end process bus_arbiter; |
|
|
-- host access -- |
data_o <= ctrl.rdat; |
ack_o <= ctrl.ack; |
221,6 → 229,10
err_o <= ctrl.err; |
|
-- wishbone interface -- |
wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode |
wb_tag_o(1) <= '0'; -- 0=secure, 1=non-secure |
wb_tag_o(2) <= ctrl.src; -- 0=data access, 1=instruction access |
|
wb_adr_o <= ctrl.adr; |
wb_dat_o <= ctrl.wdat; |
wb_we_o <= ctrl.we; |
/rtl/top_templates/neorv32_test_setup.vhd
72,6 → 72,7
CLOCK_FREQUENCY => 100000000, -- clock frequency of clk_i in Hz |
BOOTLOADER_USE => true, -- implement processor-internal bootloader? |
USER_CODE => x"00000000", -- custom user code |
HW_THREAD_ID => x"00000000", -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? |
112,6 → 113,7
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
-- Wishbone bus interface -- |
wb_tag_o => open, -- tag |
wb_adr_o => open, -- address |
wb_dat_i => (others => '0'), -- read data |
wb_dat_o => open, -- write data |
122,7 → 124,6
wb_ack_i => '0', -- transfer acknowledge |
wb_err_i => '0', -- transfer error |
-- Advanced memory control signals -- |
priv_o => open, -- current CPU privilege level |
fence_o => open, -- indicates an executed FENCE operation |
fencei_o => open, -- indicates an executed FENCEI operation |
-- GPIO -- |
/rtl/top_templates/neorv32_top_axi4lite.vhd
46,7 → 46,8
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
USER_CODE : std_logic_vector(31 downto 0) := x"00000000"; -- custom user code |
HW_THREAD_ID : std_logic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
136,7 → 137,8
architecture neorv32_top_axi4lite_rtl of neorv32_top_axi4lite is |
|
-- type conversion -- |
constant USER_CODE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(USER_CODE); |
constant USER_CODE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(USER_CODE); |
constant HW_THREAD_ID_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(HW_THREAD_ID); |
-- |
signal clk_i_int : std_ulogic; |
signal rstn_i_int : std_ulogic; |
144,8 → 146,6
signal gpio_o_int : std_ulogic_vector(31 downto 0); |
signal gpio_i_int : std_ulogic_vector(31 downto 0); |
-- |
signal priv_level : std_ulogic_vector(1 downto 0); |
-- |
signal uart_txd_o_int : std_ulogic; |
signal uart_rxd_i_int : std_ulogic; |
-- |
171,6 → 171,7
cyc : std_ulogic; -- valid cycle |
ack : std_ulogic; -- transfer acknowledge |
err : std_ulogic; -- transfer error |
tag : std_ulogic_vector(2 downto 0); -- tag |
end record; |
signal wb_core : wb_bus_t; |
|
200,6 → 201,7
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz |
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader? |
USER_CODE => USER_CODE_INT, -- custom user code |
HW_THREAD_ID => HW_THREAD_ID_INT, -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
240,6 → 242,7
clk_i => clk_i_int, -- global clock, rising edge |
rstn_i => rstn_i_int, -- global reset, low-active, async |
-- Wishbone bus interface -- |
wb_tag_o => wb_core.tag, -- tag |
wb_adr_o => wb_core.adr, -- address |
wb_dat_i => wb_core.di, -- read data |
wb_dat_o => wb_core.do, -- write data |
250,7 → 253,6
wb_ack_i => wb_core.ack, -- transfer acknowledge |
wb_err_i => wb_core.err, -- transfer error |
-- Advanced memory control signals -- |
priv_o => priv_level, -- current CPU privilege level |
fence_o => open, -- indicates an executed FENCE operation |
fencei_o => open, -- indicates an executed FENCEI operation |
-- GPIO -- |
340,7 → 342,10
-- AXI4-Lite Read Address Channel -- |
m_axi_araddr <= std_logic_vector(wb_core.adr); |
m_axi_arvalid <= std_logic((wb_core.cyc and (not wb_core.we)) and (not ctrl.radr_received)); |
m_axi_arprot <= "000"; -- recommended by Xilinx -- "001" when (priv_level = priv_mode_m_c) else "000"; -- always: data-access, secure; privileged only when CPU is in machine mode |
--m_axi_arprot <= "000"; -- recommended by Xilinx |
m_axi_arprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access |
m_axi_arprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access |
m_axi_arprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access |
|
-- AXI4-Lite Read Data Channel -- |
m_axi_rready <= std_logic(wb_core.cyc and (not wb_core.we)); |
352,7 → 357,10
-- AXI4-Lite Write Address Channel -- |
m_axi_awaddr <= std_logic_vector(wb_core.adr); |
m_axi_awvalid <= std_logic((wb_core.cyc and wb_core.we) and (not ctrl.wadr_received)); |
m_axi_awprot <= "000"; -- recommended by Xilinx -- "001" when (priv_level = priv_mode_m_c) else "000"; -- always: data-access, secure; privileged only when CPU is in machine mode |
--m_axi_awprot <= "000"; -- recommended by Xilinx |
m_axi_awprot(0) <= wb_core.tag(0); -- 0:unprivileged access, 1:privileged access |
m_axi_awprot(1) <= wb_core.tag(1); -- 0:secure access, 1:non-secure access |
m_axi_awprot(2) <= wb_core.tag(2); -- 0:data access, 1:instruction access |
|
-- AXI4-Lite Write Data Channel -- |
m_axi_wdata <= std_logic_vector(wb_core.do); |
/rtl/top_templates/neorv32_top_stdlogic.vhd
45,6 → 45,7
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_logic_vector(31 downto 0) := x"00000000"; -- custom user code |
HW_THREAD_ID : std_logic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
85,6 → 86,7
clk_i : in std_logic := '0'; -- global clock, rising edge |
rstn_i : in std_logic := '0'; -- global reset, low-active, async |
-- Wishbone bus interface (available if MEM_EXT_USE = true) -- |
wb_tag_o : out std_logic_vector(2 downto 0); -- tag |
wb_adr_o : out std_logic_vector(31 downto 0); -- address |
wb_dat_i : in std_logic_vector(31 downto 0) := (others => '0'); -- read data |
wb_dat_o : out std_logic_vector(31 downto 0); -- write data |
95,7 → 97,6
wb_ack_i : in std_logic := '0'; -- transfer acknowledge |
wb_err_i : in std_logic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
priv_o : out std_logic_vector(1 downto 0); -- current CPU privilege level |
fence_o : out std_logic; -- indicates an executed FENCE operation |
fencei_o : out std_logic; -- indicates an executed FENCEI operation |
-- GPIO (available if IO_GPIO_USE = true) -- |
124,11 → 125,13
architecture neorv32_top_stdlogic_rtl of neorv32_top_stdlogic is |
|
-- type conversion -- |
constant USER_CODE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(USER_CODE); |
constant USER_CODE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(USER_CODE); |
constant HW_THREAD_ID_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(HW_THREAD_ID); |
-- |
signal clk_i_int : std_ulogic; |
signal rstn_i_int : std_ulogic; |
-- |
signal wb_tag_o_int : std_ulogic_vector(2 downto 0); |
signal wb_adr_o_int : std_ulogic_vector(31 downto 0); |
signal wb_dat_i_int : std_ulogic_vector(31 downto 0); |
signal wb_dat_o_int : std_ulogic_vector(31 downto 0); |
139,7 → 142,6
signal wb_ack_i_int : std_ulogic; |
signal wb_err_i_int : std_ulogic; |
-- |
signal priv_o_int : std_ulogic_vector(1 downto 0); |
signal fence_o_int : std_ulogic; |
signal fencei_o_int : std_ulogic; |
-- |
170,6 → 172,7
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz |
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader? |
USER_CODE => USER_CODE_INT, -- custom user code |
HW_THREAD_ID => HW_THREAD_ID_INT, -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
210,6 → 213,7
clk_i => clk_i_int, -- global clock, rising edge |
rstn_i => rstn_i_int, -- global reset, low-active, async |
-- Wishbone bus interface -- |
wb_tag_o => wb_tag_o_int, -- tag |
wb_adr_o => wb_adr_o_int, -- address |
wb_dat_i => wb_dat_i_int, -- read data |
wb_dat_o => wb_dat_o_int, -- write data |
220,7 → 224,6
wb_ack_i => wb_ack_i_int, -- transfer acknowledge |
wb_err_i => wb_err_i_int, -- transfer error |
-- Advanced memory control signals -- |
priv_o => priv_o_int, -- current CPU privilege level |
fence_o => fence_o_int, -- indicates an executed FENCE operation |
fencei_o => fencei_o_int, -- indicates an executed FENCEI operation |
-- GPIO -- |
249,6 → 252,7
clk_i_int <= std_ulogic(clk_i); |
rstn_i_int <= std_ulogic(rstn_i); |
|
wb_tag_o <= std_logic_vector(wb_tag_o_int); |
wb_adr_o <= std_logic_vector(wb_adr_o_int); |
wb_dat_i_int <= std_ulogic_vector(wb_dat_i); |
wb_dat_o <= std_logic_vector(wb_dat_o_int); |
259,7 → 263,6
wb_ack_i_int <= std_ulogic(wb_ack_i); |
wb_err_i_int <= std_ulogic(wb_err_i); |
|
priv_o <= std_logic_vector(priv_o_int); |
fence_o <= std_logic(fence_o_int); |
fencei_o <= std_logic(fencei_o_int); |
|
/sim/neorv32_tb.vhd
1,11 → 1,11
-- ################################################################################################# |
-- # << NEORV32 - Simple Testbench >> # |
-- # << NEORV32 - Default Testbench >> # |
-- # ********************************************************************************************* # |
-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o # |
-- # signals. The received chars are shown in the simulator console and also written to a file # |
-- # ("neorv32.testbench_uart.out"). # |
-- # Futhermore, this testbench provides a simple RAM connected to the external Wishbone bus. # |
-- # The testbench configures the processor with all optional element enabled by default. # |
-- # signal. The received chars are shown in the simulator console and also written to a file # |
-- # ("neorv32.testbench_uart.out"). Futhermore, this testbench provides a simple RAM connected # |
-- # to the external Wishbone bus. The testbench configures the processor with all optional # |
-- # elements enabled by default. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
103,6 → 103,7
cyc : std_ulogic; -- valid cycle |
ack : std_ulogic; -- transfer acknowledge |
err : std_ulogic; -- transfer error |
tag : std_ulogic_vector(2 downto 0); -- tag |
end record; |
signal wb_cpu : wishbone_t; |
|
126,8 → 127,8
-- How to simulate a boot from an external memory -- |
-- ---------------------------------------------- -- |
-- The simulated Wishbone memory can be initialized with the compiled application init. |
-- 1. Uncomment the init_wbmen function below; this will initialize the simulated wishbone memory with the neorv32_application_image.vhd image |
-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB) |
-- 1. Uncomment the init_wbmem function below; this will initialize the simulated wishbone memory with the neorv32_application_image.vhd image |
-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB -> 16*1024) |
-- 3. Disable the processor-internal IMEM in the processor instantiation below (MEM_INT_IMEM_USE => false) |
-- 4. Set the Wishbone memory base address wb_mem_base_addr_c (above) to zero (constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000";) |
-- 5. Simulate! |
157,7 → 158,8
-- General -- |
CLOCK_FREQUENCY => f_clock_nat_c, -- clock frequency of clk_i in Hz |
BOOTLOADER_USE => false, -- implement processor-internal bootloader? |
USER_CODE => x"19880704", -- custom user code |
USER_CODE => x"12345678", -- custom user code |
HW_THREAD_ID => x"00000000", -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? |
198,6 → 200,7
clk_i => clk_gen, -- global clock, rising edge |
rstn_i => rst_gen, -- global reset, low-active, async |
-- Wishbone bus interface -- |
wb_tag_o => wb_cpu.tag, -- tag |
wb_adr_o => wb_cpu.addr, -- address |
wb_dat_i => wb_cpu.rdata, -- read data |
wb_dat_o => wb_cpu.wdata, -- write data |
232,7 → 235,7
mext_irq_i => '0' -- machine external interrupt |
); |
|
-- TWI termination -- |
-- TWI termination (pull-ups) -- |
twi_scl <= 'H'; |
twi_sda <= 'H'; |
|
/sw/bootloader/bootloader.c
189,12 → 189,12
// get clock speed (in Hz) |
uint32_t clock_speed = SYSINFO_CLK; |
|
// init SPI for 8-bit, clock-mode 0, MSB-first, no interrupt |
// init SPI for 8-bit, clock-mode 0, no interrupt |
if (clock_speed < 40000000) { |
neorv32_spi_setup(SPI_FLASH_CLK_PRSC, 0, 0, 0, 0); |
neorv32_spi_setup(SPI_FLASH_CLK_PRSC, 0, 0, 0); |
} |
else { |
neorv32_spi_setup(CLK_PRSC_128, 0, 0, 0, 0); |
neorv32_spi_setup(CLK_PRSC_128, 0, 0, 0); |
} |
|
// init UART (no interrupts) |
/sw/bootloader/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/common/neorv32.ld
44,7 → 44,7
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv") |
OUTPUT_ARCH(riscv) |
ENTRY(_start) |
SEARCH_DIR("=/opt/riscv/riscv64-unknown-linux-gnu/lib"); SEARCH_DIR("=/usr/local/lib"); SEARCH_DIR("=/lib"); SEARCH_DIR("=/usr/lib"); |
SEARCH_DIR("/opt/riscv/riscv32-unknown-elf/lib"); SEARCH_DIR("=/opt/riscv/riscv64-unknown-linux-gnu/lib"); SEARCH_DIR("=/usr/local/lib"); SEARCH_DIR("=/lib"); SEARCH_DIR("=/usr/lib"); |
|
/* ************************************************************************* */ |
/* NEORV32 memory configuration. */ |
/sw/example/blink_led/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/example/coremark/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/example/cpu_test/main.c
867,7 → 867,7
cnt_test++; |
|
// configure SPI, enable transfer-done IRQ |
neorv32_spi_setup(CLK_PRSC_2, 0, 0, 0, 1); |
neorv32_spi_setup(CLK_PRSC_2, 0, 0, 1); |
|
// trigger SPI IRQ |
neorv32_spi_trans(0); |
1200,10 → 1200,10
|
// final result |
if (cnt_fail == 0) { |
neorv32_uart_printf("%c[1m[TEST OK!]%c[0m\n", 27, 27); |
neorv32_uart_printf("%c[1m[CPU TEST COMPLETED SUCCESSFULLY!]%c[0m\n", 27, 27); |
} |
else { |
neorv32_uart_printf("%c[1m[TEST FAILED!]%c[0m\n", 27, 27); |
neorv32_uart_printf("%c[1m[CPU TEST FAILED!]%c[0m\n", 27, 27); |
} |
|
return 0; |
/sw/example/cpu_test/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/example/demo_freeRTOS/full_demo/RegTest.s
0,0 → 1,266
/* |
* FreeRTOS Kernel V10.3.0 |
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy of |
* this software and associated documentation files (the "Software"), to deal in |
* the Software without restriction, including without limitation the rights to |
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of |
* the Software, and to permit persons to whom the Software is furnished to do so, |
* subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in all |
* copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS |
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR |
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER |
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
* http://www.FreeRTOS.org |
* http://aws.amazon.com/freertos |
* |
* 1 tab == 4 spaces! |
*/ |
|
.extern ulRegTest1LoopCounter |
.extern ulRegTest2LoopCounter |
|
.global vRegTest1Implementation |
.global vRegTest2Implementation |
|
/*-----------------------------------------------------------*/ |
|
/* |
* The register check tasks are described in the comments at the top of |
* main_full.c. |
*/ |
|
.align( 4 ) |
vRegTest1Implementation: |
|
/* Fill the core registers with known values. */ |
li x5, 0x5 |
li x6, 0x6 |
li x7, 0x7 |
li x8, 0x8 |
li x9, 0x9 |
li x10, 0xa |
li x11, 0xb |
li x12, 0xc |
li x13, 0xd |
li x14, 0xe |
li x15, 0xf |
li x16, 0x10 |
li x17, 0x11 |
li x18, 0x12 |
li x19, 0x13 |
li x20, 0x14 |
li x21, 0x15 |
li x22, 0x16 |
li x23, 0x17 |
li x24, 0x18 |
li x25, 0x19 |
li x26, 0x1a |
li x27, 0x1b |
li x28, 0x1c |
li x29, 0x1d |
li x30, 0x1e |
|
reg1_loop: |
|
/* Check each register still contains the expected known value. |
vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation |
uses x5 as the temporary. */ |
li x31, 0x5 |
bne x31, x5, reg1_error_loop |
li x31, 0x6 |
bne x31, x6, reg1_error_loop |
li x31, 0x7 |
bne x31, x7, reg1_error_loop |
li x31, 0x8 |
bne x31, x8, reg1_error_loop |
li x31, 0x9 |
bne x31, x9, reg1_error_loop |
li x31, 0xa |
bne x31, x10, reg1_error_loop |
li x31, 0xb |
bne x31, x11, reg1_error_loop |
li x31, 0xc |
bne x31, x12, reg1_error_loop |
li x31, 0xd |
bne x31, x13, reg1_error_loop |
li x31, 0xe |
bne x31, x14, reg1_error_loop |
li x31, 0xf |
bne x31, x15, reg1_error_loop |
li x31, 0x10 |
bne x31, x16, reg1_error_loop |
li x31, 0x11 |
bne x31, x17, reg1_error_loop |
li x31, 0x12 |
bne x31, x18, reg1_error_loop |
li x31, 0x13 |
bne x31, x19, reg1_error_loop |
li x31, 0x14 |
bne x31, x20, reg1_error_loop |
li x31, 0x15 |
bne x31, x21, reg1_error_loop |
li x31, 0x16 |
bne x31, x22, reg1_error_loop |
li x31, 0x17 |
bne x31, x23, reg1_error_loop |
li x31, 0x18 |
bne x31, x24, reg1_error_loop |
li x31, 0x19 |
bne x31, x25, reg1_error_loop |
li x31, 0x1a |
bne x31, x26, reg1_error_loop |
li x31, 0x1b |
bne x31, x27, reg1_error_loop |
li x31, 0x1c |
bne x31, x28, reg1_error_loop |
li x31, 0x1d |
bne x31, x29, reg1_error_loop |
li x31, 0x1e |
bne x31, x30, reg1_error_loop |
|
/* Everything passed, increment the loop counter. */ |
lw x31, ulRegTest1LoopCounterConst |
lw x30, 0(x31) |
addi x30, x30, 1 |
sw x30, 0(x31) |
|
/* Restore clobbered register reading for next loop. */ |
li x30, 0x1e |
|
/* Yield to increase code coverage. */ |
ecall |
|
/* Start again. */ |
jal reg1_loop |
|
reg1_error_loop: |
/* Jump here if a register contains an uxpected value. This stops the loop |
counter being incremented so the check task knows an error was found. */ |
ebreak |
jal reg1_error_loop |
|
.align( 4 ) |
ulRegTest1LoopCounterConst: .word ulRegTest1LoopCounter |
|
/*-----------------------------------------------------------*/ |
|
.align( 4 ) |
vRegTest2Implementation: |
|
/* Fill the core registers with known values. */ |
li x6, 0x61 |
li x7, 0x71 |
li x8, 0x81 |
li x9, 0x91 |
li x10, 0xa1 |
li x11, 0xb1 |
li x12, 0xc1 |
li x13, 0xd1 |
li x14, 0xe1 |
li x15, 0xf1 |
li x16, 0x20 |
li x17, 0x21 |
li x18, 0x22 |
li x19, 0x23 |
li x20, 0x24 |
li x21, 0x25 |
li x22, 0x26 |
li x23, 0x27 |
li x24, 0x28 |
li x25, 0x29 |
li x26, 0x2a |
li x27, 0x2b |
li x28, 0x2c |
li x29, 0x2d |
li x30, 0x2e |
li x31, 0x2f |
|
Reg2_loop: |
|
/* Check each register still contains the expected known value. |
vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation |
uses x31 as the temporary. */ |
li x5, 0x61 |
bne x5, x6, reg2_error_loop |
li x5, 0x71 |
bne x5, x7, reg2_error_loop |
li x5, 0x81 |
bne x5, x8, reg2_error_loop |
li x5, 0x91 |
bne x5, x9, reg2_error_loop |
li x5, 0xa1 |
bne x5, x10, reg2_error_loop |
li x5, 0xb1 |
bne x5, x11, reg2_error_loop |
li x5, 0xc1 |
bne x5, x12, reg2_error_loop |
li x5, 0xd1 |
bne x5, x13, reg2_error_loop |
li x5, 0xe1 |
bne x5, x14, reg2_error_loop |
li x5, 0xf1 |
bne x5, x15, reg2_error_loop |
li x5, 0x20 |
bne x5, x16, reg2_error_loop |
li x5, 0x21 |
bne x5, x17, reg2_error_loop |
li x5, 0x22 |
bne x5, x18, reg2_error_loop |
li x5, 0x23 |
bne x5, x19, reg2_error_loop |
li x5, 0x24 |
bne x5, x20, reg2_error_loop |
li x5, 0x25 |
bne x5, x21, reg2_error_loop |
li x5, 0x26 |
bne x5, x22, reg2_error_loop |
li x5, 0x27 |
bne x5, x23, reg2_error_loop |
li x5, 0x28 |
bne x5, x24, reg2_error_loop |
li x5, 0x29 |
bne x5, x25, reg2_error_loop |
li x5, 0x2a |
bne x5, x26, reg2_error_loop |
li x5, 0x2b |
bne x5, x27, reg2_error_loop |
li x5, 0x2c |
bne x5, x28, reg2_error_loop |
li x5, 0x2d |
bne x5, x29, reg2_error_loop |
li x5, 0x2e |
bne x5, x30, reg2_error_loop |
li x5, 0x2f |
bne x5, x31, reg2_error_loop |
|
/* Everything passed, increment the loop counter. */ |
lw x5, ulRegTest2LoopCounterConst |
lw x6, 0(x5) |
addi x6, x6, 1 |
sw x6, 0(x5) |
|
/* Restore clobbered register reading for next loop. */ |
li x6, 0x61 |
|
/* Start again. */ |
jal Reg2_loop |
|
reg2_error_loop: |
/* Jump here if a register contains an uxpected value. This stops the loop |
counter being incremented so the check task knows an error was found. */ |
ebreak |
jal reg2_error_loop |
|
.align( 4 ) |
ulRegTest2LoopCounterConst: .word ulRegTest2LoopCounter |
|
|
/sw/example/demo_freeRTOS/full_demo/main_full.c
0,0 → 1,328
/* |
* FreeRTOS Kernel V10.3.0 |
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a copy of |
* this software and associated documentation files (the "Software"), to deal in |
* the Software without restriction, including without limitation the rights to |
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of |
* the Software, and to permit persons to whom the Software is furnished to do so, |
* subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included in all |
* copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS |
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR |
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER |
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
* http://www.FreeRTOS.org |
* http://aws.amazon.com/freertos |
* |
* 1 tab == 4 spaces! |
*/ |
|
/****************************************************************************** |
* NOTE 1: This project provides two demo applications. A simple blinky style |
* project, and a more comprehensive test and demo application. The |
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select |
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY |
* in main.c. This file implements the comprehensive test and demo version. |
* |
* NOTE 2: This file only contains the source code that is specific to the |
* full demo. Generic functions, such FreeRTOS hook functions, and functions |
* required to configure the hardware, are defined in main.c. |
* |
****************************************************************************** |
* |
* main_full() creates all the demo application tasks and software timers, then |
* starts the scheduler. The web documentation provides more details of the |
* standard demo application tasks, which provide no particular functionality, |
* but do provide a good example of how to use the FreeRTOS API. |
* |
* In addition to the standard demo tasks, the following tasks and tests are |
* defined and/or created within this file: |
* |
* "Reg test" tasks - These fill both the core registers with known values, then |
* check that each register maintains its expected value for the lifetime of the |
* task. Each task uses a different set of values. The reg test tasks execute |
* with a very low priority, so get preempted very frequently. A register |
* containing an unexpected value is indicative of an error in the context |
* switching mechanism. |
* |
* "Check" task - The check executes every three seconds. It checks that all |
* the standard demo tasks, and the register check tasks, are not only still |
* executing, but are executing without reporting any errors. The check task |
* toggles the LED every three seconds if all the standard demo tasks are |
* executing as expected, or every 500ms if a potential error is discovered in |
* any task. |
*/ |
|
/* Standard includes. */ |
#include <string.h> |
#include <unistd.h> |
|
/* NEORV32*/ |
#include <neorv32.h> |
|
/* Kernel includes. */ |
#include <FreeRTOS.h> |
#include <task.h> |
#include <timers.h> |
#include <semphr.h> |
|
/* Standard demo application includes. */ |
#include <dynamic.h> |
#include <blocktim.h> |
#include <GenQTest.h> |
#include <TimerDemo.h> |
#include <TaskNotify.h> |
|
/* Priorities for the demo application tasks. */ |
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) |
|
/* The period of the check task, in ms, converted to ticks using the |
pdMS_TO_TICKS() macro. mainNO_ERROR_CHECK_TASK_PERIOD is used if no errors have |
been found, mainERROR_CHECK_TASK_PERIOD is used if an error has been found. */ |
#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 2000UL ) |
#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 100UL ) |
|
/* Parameters that are passed into the register check tasks solely for the |
purpose of ensuring parameters are passed into tasks correctly. */ |
#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) |
#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) |
|
/* The base period used by the timer test tasks. */ |
#define mainTIMER_TEST_PERIOD ( 50 ) |
|
/* The size of the stack allocated to the check task (as described in the |
comments at the top of this file. */ |
#define mainCHECK_TASK_STACK_SIZE_WORDS 160 |
|
/* Size of the stacks to allocated for the register check tasks. */ |
#define mainREG_TEST_STACK_SIZE_WORDS 90 |
|
/*-----------------------------------------------------------*/ |
|
/* |
* Called by main() to run the full demo (as opposed to the blinky demo) when |
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. |
*/ |
void main_full( void ); |
|
/* |
* The check task, as described at the top of this file. |
*/ |
static void prvCheckTask( void *pvParameters ); |
|
/* |
* Register check tasks as described at the top of this file. The nature of |
* these files necessitates that they are written in an assembly file, but the |
* entry points are kept in the C file for the convenience of checking the task |
* parameter. |
*/ |
static void prvRegTestTaskEntry1( void *pvParameters ); |
extern void vRegTest1Implementation( void ); |
static void prvRegTestTaskEntry2( void *pvParameters ); |
extern void vRegTest2Implementation( void ); |
|
/* |
* IO |
*/ |
extern void vSendString( const char * pcString ); |
extern void vToggleLED( void ); |
|
/* |
* Tick hook used by the full demo, which includes code that interacts with |
* some of the tests. |
*/ |
void vFullDemoTickHook( void ); |
|
/*-----------------------------------------------------------*/ |
|
/* The following two variables are used to communicate the status of the |
register check tasks to the check task. If the variables keep incrementing, |
then the register check tasks have not discovered any errors. If a variable |
stops incrementing, then an error has been found. */ |
uint32_t ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; |
volatile uint32_t *pulRegTest1LoopCounter = &ulRegTest1LoopCounter; |
volatile uint32_t *pulRegTest2LoopCounter = &ulRegTest2LoopCounter; |
/*-----------------------------------------------------------*/ |
|
void main_full( void ) |
{ |
|
vSendString("FreeRTOS: Creating tasks...\n"); |
|
/* Start all the other standard demo/test tasks. They have no particular |
functionality, but do demonstrate how to use the FreeRTOS API and test the |
kernel port. */ |
|
vSendString("FreeRTOS: Starting <vStartDynamicPriorityTasks>...\n"); |
vStartDynamicPriorityTasks(); |
|
vSendString("FreeRTOS: Starting <vStartGenericQueueTasks>...\n"); |
vStartGenericQueueTasks( tskIDLE_PRIORITY ); |
|
vSendString("FreeRTOS: Starting <vStartTimerDemoTask>...\n"); |
vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); |
|
vSendString("FreeRTOS: Starting <vStartTaskNotifyTask>...\n"); |
vStartTaskNotifyTask(); |
|
|
/* Create the register check tasks, as described at the top of this file. |
Use xTaskCreateStatic() to create a task using only statically allocated |
memory. */ |
vSendString("FreeRTOS: Creating tasks <prvRegTestTaskEntry1>...\n"); |
xTaskCreate( prvRegTestTaskEntry1, /* The function that implements the task. */ |
"Reg1", /* The name of the task. */ |
mainREG_TEST_STACK_SIZE_WORDS, /* Size of stack to allocate for the task - in words not bytes!. */ |
mainREG_TEST_TASK_1_PARAMETER, /* Parameter passed into the task. */ |
tskIDLE_PRIORITY, /* Priority of the task. */ |
NULL ); /* Can be used to pass out a handle to the created task. */ |
vSendString("FreeRTOS: Creating tasks <prvRegTestTaskEntry2>...\n"); |
xTaskCreate( prvRegTestTaskEntry2, "Reg2", mainREG_TEST_STACK_SIZE_WORDS, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); |
|
/* Create the task that performs the 'check' functionality, as described at |
the top of this file. */ |
xTaskCreate( prvCheckTask, "Check", mainCHECK_TASK_STACK_SIZE_WORDS, NULL, mainCHECK_TASK_PRIORITY, NULL ); |
|
|
/* Start the scheduler. */ |
vSendString("\nFreeRTOS: Starting scheduler...\n\n"); |
vTaskStartScheduler(); |
|
/* If all is well, the scheduler will now be running, and the following |
line will never be reached. If the following line does execute, then |
there was insufficient FreeRTOS heap memory available for the Idle and/or |
timer tasks to be created. See the memory management section on the |
FreeRTOS web site for more details on the FreeRTOS heap |
http://www.freertos.org/a00111.html. */ |
for( ;; ); |
} |
/*-----------------------------------------------------------*/ |
|
static void prvCheckTask( void *pvParameters ) |
{ |
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; |
TickType_t xLastExecutionTime; |
uint32_t ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; |
char * const pcPassMessage = "."; |
char * pcStatusMessage = pcPassMessage; |
|
/* Just to stop compiler warnings. */ |
( void ) pvParameters; |
|
/* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() |
works correctly. */ |
xLastExecutionTime = xTaskGetTickCount(); |
|
/* Cycle for ever, delaying then checking all the other tasks are still |
operating without error. The onboard LED is toggled on each iteration. |
If an error is detected then the delay period is decreased from |
mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the |
effect of increasing the rate at which the onboard LED toggles, and in so |
doing gives visual feedback of the system status. */ |
for( ;; ) |
{ |
/* Delay until it is time to execute again. */ |
vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); |
|
/* Check all the demo tasks (other than the flash tasks) to ensure |
that they are all still running, and that none have detected an error. */ |
if( xAreDynamicPriorityTasksStillRunning() == pdFALSE ) |
{ |
pcStatusMessage = "ERROR: Dynamic priority demo/tests.\n"; |
} |
|
if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) == pdFALSE ) |
{ |
pcStatusMessage = "ERROR: Timer demo/tests.\n"; |
} |
|
if( xAreGenericQueueTasksStillRunning() == pdFALSE ) |
{ |
pcStatusMessage = "ERROR: Generic queue demo/tests.\n"; |
} |
|
if( xAreTaskNotificationTasksStillRunning() == pdFALSE ) |
{ |
pcStatusMessage = "ERROR: Task notification demo/tests.\n"; |
} |
|
if( ulLastRegTest1Value == ulRegTest1LoopCounter ) |
{ |
pcStatusMessage = "ERROR: Register test 1.\n"; |
} |
ulLastRegTest1Value = ulRegTest1LoopCounter; |
|
if( ulLastRegTest2Value == ulRegTest2LoopCounter ) |
{ |
pcStatusMessage = "ERROR: Register test 2.\n"; |
} |
ulLastRegTest2Value = ulRegTest2LoopCounter; |
|
/* Write the status message to the UART. */ |
vSendString( pcStatusMessage ); |
|
/* Toggle the LED to show the system status */ |
vToggleLED(); |
|
/* If an error has been found then increase the LED toggle rate by |
increasing the cycle frequency. */ |
if( pcStatusMessage != pcPassMessage ) |
{ |
xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; |
} |
} |
} |
/*-----------------------------------------------------------*/ |
|
static void prvRegTestTaskEntry1( void *pvParameters ) |
{ |
/* Although the regtest task is written in assembler, its entry point is |
written in C for convenience of checking the task parameter is being passed |
in correctly. */ |
if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) |
{ |
/* Start the part of the test that is written in assembler. */ |
vRegTest1Implementation(); |
} |
|
/* The following line will only execute if the task parameter is found to |
be incorrect. The check task will detect that the regtest loop counter is |
not being incremented and flag an error. */ |
vTaskDelete( NULL ); |
} |
/*-----------------------------------------------------------*/ |
|
static void prvRegTestTaskEntry2( void *pvParameters ) |
{ |
/* Although the regtest task is written in assembler, its entry point is |
written in C for convenience of checking the task parameter is being passed |
in correctly. */ |
if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) |
{ |
/* Start the part of the test that is written in assembler. */ |
vRegTest2Implementation(); |
} |
|
/* The following line will only execute if the task parameter is found to |
be incorrect. The check task will detect that the regtest loop counter is |
not being incremented and flag an error. */ |
vTaskDelete( NULL ); |
} |
/*-----------------------------------------------------------*/ |
|
void vFullDemoTickHook( void ) |
{ |
/* Called from vApplicationTickHook() when the project is configured to |
build the full test/demo applications. */ |
|
/* Use task notifications from an interrupt. */ |
xNotifyTaskFromISR(); |
} |
/sw/example/demo_freeRTOS/FreeRTOSConfig.h
97,10 → 97,11
#define configCPU_CLOCK_HZ 100000000 |
#define configTICK_RATE_HZ ( ( TickType_t ) 100 ) |
#define configMAX_PRIORITIES ( 5 ) |
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */ |
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */ |
#define configSUPPORT_DYNAMIC_ALLOCATION 1 |
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7 * 1024 ) ) |
#define configMAX_TASK_NAME_LEN ( 16 ) |
#define configUSE_TRACE_FACILITY 0 |
#define configUSE_TRACE_FACILITY 1 |
#define configUSE_16_BIT_TICKS 0 |
#define configIDLE_SHOULD_YIELD 0 |
#define configUSE_MUTEXES 1 |
111,6 → 112,8
#define configUSE_APPLICATION_TASK_TAG 0 |
#define configUSE_COUNTING_SEMAPHORES 1 |
#define configGENERATE_RUN_TIME_STATS 0 |
#define configTASK_NOTIFICATION_ARRAY_ENTRIES 4 |
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 |
|
/* Co-routine definitions. */ |
#define configUSE_CO_ROUTINES 0 |
142,15 → 145,8
#define INCLUDE_xTaskGetHandle 1 |
#define INCLUDE_xSemaphoreGetMutexHolder 1 |
|
// get runtime stats |
#define configGENERATE_RUN_TIME_STATS 0 |
|
/* Normal assert() semantics without relying on the provision of an assert.h |
header file. */ |
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); } |
|
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 |
#define configKERNEL_INTERRUPT_PRIORITY 7 |
|
|
#endif /* FREERTOS_CONFIG_H */ |
/sw/example/demo_freeRTOS/README.md
1,7 → 1,8
# FreeRTOS Demo for the NEORV32 Processor |
# FreeRTOS Demo for the NEORV32 Processor |
|
This is simple example shows the usage of [FreeRTOS](https://www.freertos.org/) on the NEORV32 processor. It uses the default *blink* |
demo application (`blinky_demo/main_blinky.c`). See the comments in that source file for more information. |
This example shows how to run [FreeRTOS](https://www.freertos.org/) on the NEORV32 processor. It features the default |
"blinky_demo" and the more sophisticated "full_demo" demo applications. See the comments in `main.c` and the according |
source files for more information. |
|
The chip-specific extensions folder (`chip_specific_extensions/neorv32`) should be in `$(FREERTOS_HOME)/Source/portable/GCC/RISC-V/chip_specific_extensions`, |
but is placed in this source directory for simplicity. |
9,20 → 10,20
|
## Hardware Requirements |
|
* 8kB DMEM and 16kB IMEM |
* MTIME (machine timer) |
* DMEM/IMEM requriements depend on the actual application (for example: 8kB DMEM and 16kB IMEM for *blinky_demo*) |
* MTIME (machine timer) + UART + GPIO |
* `Zicsr` CPU extension |
|
|
## Instructions |
|
Download FreeRTOS from the [official GitHub repository](https://github.com/FreeRTOS/FreeRTOS). |
Download FreeRTOS from the [official GitHub repository](https://github.com/FreeRTOS/FreeRTOS) or from the its official homepage. |
|
$ git clone https://github.com/FreeRTOS/FreeRTOS.git |
|
Open the makefile from this example folder and configure the `FREERTOS_HOME` variable to point to the `FreeRTOS/FreeRTOS` home folder. |
Open the makefile from this example folder and configure the `FREERTOS_HOME` variable to point to your FreeRTOS home folder. |
|
FREERTOS_HOME ?= /mnt/n/Projects/FreeRTOS/FreeRTOS |
FREERTOS_HOME ?= /mnt/n/Projects/FreeRTOSv10.4.1 |
|
Compile the NEORV32 executable. Do not forget the `RUN_FREERTOS_DEMO` switch. |
|
38,15 → 39,26
CMD:> e |
Booting... |
|
FreeRTOS V10.3.1 |
FreeRTOS V10.4.1 |
Blink |
Blink |
Blink |
``` |
|
## FreeRTOS Plus |
|
## Note |
To automatically add source and include files from FreeRTOS plus extensions add one (or more) of the following arguments when invoking `make`: |
|
* FreeRTOS-Plus-CLI: `USER_FLAGS+=-FREERTOS_PLUS_CLI` |
* FreeRTOS-Plus-TCP: `USER_FLAGS+=-FREERTOS_PLUS_TCP` |
|
Example: |
|
$ make USER_FLAGS+=-DRUN_FREERTOS_DEMO USER_FLAGS+=-FREERTOS_PLUS_TCP clean_all exe |
|
|
## Notes |
|
The onfiguration of the FreeRTOS home folder (via `FREERTOS_HOME`) is corrupted if the compiler shows the following error: |
|
``` |
/sw/example/demo_freeRTOS/main.c
25,6 → 25,23
* 1 tab == 4 spaces! |
*/ |
|
/****************************************************************************** |
* This project provides two demo applications. A simple blinky style project, |
* and a more comprehensive test and demo application. The |
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to |
* select between the two. The simply blinky demo is implemented and described |
* in main_blinky.c. The more comprehensive test and demo application is |
* implemented and described in main_full.c. |
* |
* This file implements the code that is not demo specific, including the |
* hardware setup and standard FreeRTOS hook functions. |
* |
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON |
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO |
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! |
* |
*/ |
|
/* |
* Modified for the NEORV32 processor by Stephan Nolting. |
*/ |
31,40 → 48,45
|
#ifdef RUN_FREERTOS_DEMO |
|
#include <stdint.h> |
|
/* FreeRTOS kernel includes. */ |
#include <FreeRTOS.h> |
#include <semphr.h> |
#include <queue.h> |
#include <task.h> |
|
/* NEORV32 includes. */ |
#include <neorv32.h> |
|
/* misc */ |
//#include "driver_wrapper/uart_serial.h" |
|
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, |
or 0 to run the more comprehensive test and demo application. */ |
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 |
|
/* UART hardware constants. */ |
#define BAUD_RATE 19200 |
|
/*-----------------------------------------------------------*/ |
|
/****************************************************************************** |
* This project provides two demo applications. A simple blinky style project, |
* and a more comprehensive test and demo application. The |
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to |
* select between the two. The simply blinky demo is implemented and described |
* in main_blinky.c. The more comprehensive test and demo application is |
* implemented and described in main_full.c. |
* |
* This file implements the code that is not demo specific, including the |
* hardware setup and standard FreeRTOS hook functions. |
* |
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON |
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO |
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! |
* |
/* |
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. |
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. |
*/ |
#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 |
extern void main_blinky( void ); |
#else |
extern void main_full( void ); |
#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ |
|
extern void main_blinky( void ); |
extern void freertos_risc_v_trap_handler( void ); |
|
/* Prototypes for the standard FreeRTOS callback/hook functions implemented |
within this file. See https://www.freertos.org/a00016.html */ |
/* |
* Prototypes for the standard FreeRTOS callback/hook functions implemented |
* within this file. See https://www.freertos.org/a00016.html |
*/ |
void vApplicationMallocFailedHook( void ); |
void vApplicationIdleHook( void ); |
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); |
73,8 → 95,9
/* Prepare hardware to run the demo. */ |
static void prvSetupHardware( void ); |
|
/* Send a message to the UART initialised in prvSetupHardware. */ |
void vSendString( const char * const pcString ); |
/* System */ |
void vToggleLED( void ); |
void vSendString( const char * pcString ); |
|
/*-----------------------------------------------------------*/ |
|
82,9 → 105,16
{ |
prvSetupHardware(); |
|
neorv32_uart_printf("FreeRTOS %s\n", tskKERNEL_VERSION_NUMBER); |
/* say hi */ |
neorv32_uart_printf("FreeRTOS %s on NEORV32 Demo\n\n", tskKERNEL_VERSION_NUMBER); |
|
main_blinky(); |
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top |
of this file. */ |
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) |
main_blinky(); |
#else |
main_full(); |
#endif |
} |
|
/*-----------------------------------------------------------*/ |
94,6 → 124,9
// configure trap handler entry point |
neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)&freertos_risc_v_trap_handler); |
|
// clear GPIO.out port |
neorv32_gpio_port_set(0); |
|
// configure UART for default baud rate, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0, 0); |
} |
107,9 → 140,9
|
/*-----------------------------------------------------------*/ |
|
void vSendString( const char * const pcString ) |
void vSendString( const char * pcString ) |
{ |
neorv32_uart_print( (char *)pcString ); |
neorv32_uart_print( ( const char * ) pcString ); |
} |
|
/*-----------------------------------------------------------*/ |
127,7 → 160,7
to query the size of free heap space that remains (although it does not |
provide information on how the remaining heap might be fragmented). */ |
taskDISABLE_INTERRUPTS(); |
neorv32_uart_print("FreeRTOS_FAULT: vApplicationMallocFailedHook\n"); |
neorv32_uart_print("FreeRTOS_FAULT: vApplicationMallocFailedHook (solution: increase 'configTOTAL_HEAP_SIZE' in FreeRTOSConfig.h)\n"); |
__asm volatile( "ebreak" ); |
for( ;; ); |
} |
167,7 → 200,13
|
void vApplicationTickHook( void ) |
{ |
|
/* The tests in the full demo expect some interaction with interrupts. */ |
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 ) |
{ |
extern void vFullDemoTickHook( void ); |
vFullDemoTickHook(); |
} |
#endif |
} |
|
/*-----------------------------------------------------------*/ |
/sw/example/demo_freeRTOS/makefile
73,22 → 73,31
# ----------------------------------------------------------------------------- |
ifneq (,$(findstring RUN_FREERTOS_DEMO,$(USER_FLAGS))) |
# FreeRTOS home folder (adapt this!) |
FREERTOS_HOME ?= /mnt/n/Projects/FreeRTOS/FreeRTOS |
FREERTOS_HOME ?= /mnt/n/Projects/FreeRTOSv10.4.1 |
|
# Application |
APP_SRC += blinky_demo/main_blinky.c |
# FreeRTOS RISC-V specific |
APP_SRC += $(wildcard $(FREERTOS_HOME)/FreeRTOS/Source/portable/GCC/RISC-V/*.c) |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S |
|
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS/Source/portable/GCC/RISC-V |
|
# FreeRTOS core |
APP_SRC += $(wildcard $(FREERTOS_HOME)/Source/*.c) |
APP_SRC += $(wildcard $(FREERTOS_HOME)/Source/portable/MemMang/heap_1.c) |
APP_SRC += $(wildcard $(FREERTOS_HOME)/FreeRTOS/Source/*.c) |
APP_SRC += $(wildcard $(FREERTOS_HOME)/FreeRTOS/Source/portable/MemMang/heap_4.c) |
|
APP_INC += -I $(FREERTOS_HOME)/Source/include |
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS/Source/include |
|
# FreeRTOS RISC-V specific |
APP_SRC += $(wildcard $(FREERTOS_HOME)/Source/portable/GCC/RISC-V/*.c) |
APP_SRC += $(FREERTOS_HOME)/Source/portable/GCC/RISC-V/portASM.S |
# FreeRTOS sources for the full_demo |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/blocktim.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/dynamic.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/GenQTest.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/recmutex.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/TaskNotify.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/TaskNotifyArray.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/TimerDemo.c |
|
APP_INC += -I $(FREERTOS_HOME)/Source/portable/GCC/RISC-V |
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS/Demo/Common/include |
|
# NEORV32 specific |
ASM_INC += -DportasmHANDLE_INTERRUPT=SystemIrqHandler |
96,10 → 105,42
APP_INC += -I chip_specific_extensions/neorv32 |
|
ASM_INC += -I chip_specific_extensions/neorv32 |
|
# Demo application |
APP_SRC += blinky_demo/main_blinky.c |
APP_SRC += full_demo/main_full.c |
APP_SRC += full_demo/RegTest.s |
endif |
|
# ----------------- |
# FreeRTOS-Plus-CLI |
# ----------------- |
ifneq (,$(findstring FREERTOS_PLUS_CLI,$(USER_FLAGS))) |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/FreeRTOS_CLI.c |
|
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI |
endif |
|
# ----------------- |
# FreeRTOS-Plus-TCP |
# ----------------- |
ifneq (,$(findstring FREERTOS_PLUS_TCP,$(USER_FLAGS))) |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c |
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c |
|
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include |
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC |
endif |
|
|
|
# ----------------------------------------------------------------------------- |
# NEORV32 framework |
# ----------------------------------------------------------------------------- |
219,7 → 260,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/example/demo_pwm/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/example/demo_trng/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/example/demo_twi/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/example/demo_wdt/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/example/game_of_life/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/example/hex_viewer/makefile
57,7 → 57,7
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
187,7 → 187,7
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -D -S -z $< > $@ |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
/sw/lib/include/neorv32.h
393,12 → 393,10
SPI_CT_PRSC0 = 10, /**< UART control register(10) (r/w): Clock prescaler select bit 0 */ |
SPI_CT_PRSC1 = 11, /**< UART control register(11) (r/w): Clock prescaler select bit 1 */ |
SPI_CT_PRSC2 = 12, /**< UART control register(12) (r/w): Clock prescaler select bit 2 */ |
SPI_CT_DIR = 13, /**< UART control register(13) (r/w): Shift direction (0: MSB first, 1: LSB first) */ |
SPI_CT_SIZE0 = 14, /**< UART control register(14) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ |
SPI_CT_SIZE1 = 15, /**< UART control register(15) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ |
SPI_CT_SIZE0 = 13, /**< UART control register(13) (r/w): Transfer data size lsb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ |
SPI_CT_SIZE1 = 14, /**< UART control register(14) (r/w): Transfer data size msb (00: 8-bit, 01: 16-bit, 10: 24-bit, 11: 32-bit) */ |
SPI_CT_IRQ_EN = 15, /**< UART control register(15) (r/w): Transfer done interrupt enable */ |
|
SPI_CT_IRQ_EN = 16, /**< UART control register(16) (r/w): Transfer done interrupt enable */ |
|
SPI_CT_BUSY = 31 /**< UART control register(31) (r/-): SPI busy flag */ |
}; |
/**@}*/ |
/sw/lib/include/neorv32_spi.h
46,7 → 46,7
|
// prototypes |
int neorv32_spi_available(void); |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t dir, uint8_t data_size, uint8_t irq_en); |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size, uint8_t irq_en); |
void neorv32_spi_disable(void); |
void neorv32_spi_cs_en(uint8_t cs); |
void neorv32_spi_cs_dis(uint8_t cs); |
/sw/lib/source/neorv32_spi.c
66,11 → 66,10
* |
* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum. |
* @param[in] clk_polarity Idle clock polarity (0, 1). |
* @param[in] dir Shift direction (0: MSB first, 1: LSB first). |
* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit). |
* @param[in] irq_en Enable transfer-done interrupt when 1. |
**************************************************************************/ |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t dir, uint8_t data_size, uint8_t irq_en) { |
void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size, uint8_t irq_en) { |
|
SPI_CT = 0; // reset |
|
83,9 → 82,6
uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01); |
ct_polarity = ct_polarity << SPI_CT_CPHA; |
|
uint32_t ct_dir = (uint32_t)(dir & 0x01); |
ct_dir = ct_dir << SPI_CT_DIR; |
|
uint32_t ct_size = (uint32_t)(data_size & 0x03); |
ct_size = ct_size << SPI_CT_SIZE0; |
|
92,7 → 88,7
uint32_t ct_irq = (uint32_t)(irq_en & 0x01); |
ct_irq = ct_irq << SPI_CT_IRQ_EN; |
|
SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_dir | ct_size | ct_irq; |
SPI_CT = ct_enable | ct_prsc | ct_polarity | ct_size | ct_irq; |
} |
|
|
138,6 → 134,8
/**********************************************************************//** |
* Initiate SPI transfer. |
* |
* @warning The SPI always sends MSB first. |
* |
* @note This function is blocking. |
* |
* @param tx_data Transmit data (8/16/24/32-bit, LSB-aligned). |
/sw/lib/source/neorv32_uart.c
71,7 → 71,7
/**********************************************************************//** |
* Enable and configure UART. |
* |
* @warning The 'UART_SIM_MODE' compiler flag will redirect all UART TX data to the simulation output. Use this for simulations only! |
* @warning The 'UART_SIM_MODE' compiler flag will configure UART for simulation mode: all UART TX data will be redirected to simulation output. Use this for simulations only! |
* @warning To enable simulation mode add <USER_FLAGS+=-DUART_SIM_MODE> when compiling. |
* |
* @param[in] baudrate Targeted BAUD rate (e.g. 9600). |
82,14 → 82,21
|
UART_CT = 0; // reset |
|
// raw baud rate prescaler |
uint32_t clock = SYSINFO_CLK; |
uint16_t i = 0; // BAUD rate divisor |
uint8_t p = 0; // prsc = CLK/2 |
uint8_t p = 0; // initial prsc = CLK/2 |
|
// raw clock prescaler |
#ifdef __riscv_div |
// use div instructions |
i = (uint16_t)(clock / (2*baudrate)); |
#else |
// division via repeated subtraction |
while (clock >= 2*baudrate) { |
clock -= 2*baudrate; |
i++; |
} |
#endif |
|
// find clock prsc |
while (i >= 0x0fff) { |
/CHANGELOG.md
14,6 → 14,11
|
| Date (*dd.mm.yyyy*) | Version | Comment | |
|:----------:|:-------:|:--------| |
| 03.11.2020 | 1.4.6.6 | Removed SPI module's *buggy* "LSB-first mode", SPI module now always sends data MSB-first; removed SPI.CTRL `SPI_CT_DIR` bit; modfied bit order in SPI CTRL register; updated SPI SW library | |
| 02.11.2020 | 1.4.6.5 | :warning: Fixed bug in CPU's illegal instruction detection logic; CPU rtl code optimizations - further reduced hardware footprint; rtl code clean-ups | |
| 01.11.2020 | 1.4.6.4 | :warning: Fixed bug in `[m]instret[h]` and `[m]cycle[h]` carry logic; CPU hardware optimizations (area reduction, shortend critical path) | |
| 29.10.2020 | 1.4.6.3 | rtl code clean-up; made preparations for additional co-processors | |
| 25.10.2020 | 1.4.6.2 | Added tag signal (`wb_tag_o`) to processor's Wishbone bus; removed processors's `priv_o` - privilege level is now encoded in Wishbone *tag* signal; added a more sophisticated **FreeRTOS** example ("full_demo") | |
| 24.10.2020 | [**:rocket:1.4.6.0**](https://github.com/stnolting/neorv32/releases/tag/v1.4.6.0) | Completely reworked external memory interface (WISHBONE), removed now-obsolete processor generic `MEM_EXT_REG_STAGES`; added processor wrapper with **AXI4-Lite master interface** | |
| 22.10.2020 | 1.4.5.11 | TWI: Added new control register flag to enable/disable SCL clock stretching by peripheral devices | |
| 22.10.2020 | 1.4.5.10 | Added `i_bus_priv_o` and `d_bus_priv_o` signals to CPU_top and `priv_o` to Processor_top to show privilege level of bus access (from `mstatus` MPP); :warning: Fixed bug in external memory interface [WISHBONE] (non-standard Wishbone components were able to corrupt processor-internal ACK/ERR signal logic) | |
/README.md
19,63 → 19,43
## Overview |
|
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based |
on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts: |
on the RISC-V-compliant NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC |
designs or as stand-alone custom microcontroller. Its top entity can be directly synthesized for *any* target technology without modifications. |
|
|
### [NEORV32 CPU](#CPU-Features) |
|
The CPU implements a `rv32i RISC-V` core with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and |
`PMP` (physical memory protection) extensions. It passes the official [RISC-V compliance tests](https://github.com/stnolting/neorv32_riscv_compliance) |
and is compliant to the *Unprivileged ISA Specification [Version 2.2](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)* |
and a subset of the *Privileged Architecture Specification [Version 1.12-draft](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)*. |
|
If you do not want to use the NEORV32 Processor setup, you can also use the CPU in |
stand-alone mode and build your own SoC around it. |
|
|
### [NEORV32 Processor](#Processor-Features) |
|
Based on the NEORV32 CPU, the NEORV32 Processor is a full-scale RISC-V microcontroller system (**SoC**) |
that already provides common peripherals like GPIO, serial interfaces, timers, embedded |
memories and an external bus interface for connectivity and custom extension. |
All optional features and modules beyond the base CPU can be enabled and configured via |
[VHDL generics](#Top-Entities). |
|
The processor is intended as ready-to-use auxiliary processor within a larger SoC |
designs or as stand-alone custom microcontroller. Its top entity can be directly |
synthesized for any target technology without modifications. |
|
This project comes with a complete software ecosystem that features core |
libraries for high-level usage of the provided functions and peripherals, |
makefiles, a runtime environment, several example programs to start with - including a free RTOS demo - and |
even a builtin bootloader for easy program upload via UART. |
|
|
### [How to get started?](#Getting-Started) |
|
The processor is intended to work "out of the box". Just synthesize the |
[test setup](#Create-a-new-Hardware-Project), upload it to your FPGA board of choice and start playing |
with the NEORV32. For more information take a look at the [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf). |
|
The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository. |
To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases). |
|
|
### Key Features |
|
* RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and `PMP` (physical memory protection) extensions |
* GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt)) |
* Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
* [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html) |
* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features) |
* Compliant to *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf) |
* Compliant to *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf) |
* Optional CPU extensions |
* `C` - compressed instructions (16-bit) |
* `E` - embedded CPU (reduced register file) |
* `M` - integer multiplication and division hardware |
* `U` - less-privileged *user mode* |
* `Zicsr` - control and status register access instructions (+ exception/irq system) |
* `Zifencei` - instruction stream synchronization |
* `PMP` - physical memory protection |
* Software framework |
* Core libraries for high-level usage of the provided functions and peripherals |
* Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt)) |
* runtime environment |
* several example programs |
* [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html) |
* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available |
* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf) |
* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc. |
* Fully synchronous design, no latches, no gated clocks |
* Small hardware footprint and high operating frequency |
* Highly configurable CPU and processor setup |
* [AXI4-Lite connectivity](#AXI4-Connectivity) - compatible with Xilinx Vivado IP Packer |
* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available |
* Full-scale RISC-V microcontroller system (**SoC**): [**NEORV32 Processor**](#NEORV32-Processor-Features) |
* Optional embedded memories, timers, serial interfaces, external interfaces (Wishbone or [AXI4-Lite](#AXI4-Connectivity)) ... |
|
The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository. |
To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases). |
For more information take a look at the [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf). |
|
|
### Design Principles |
|
* From zero to `main()`: Completely open source and documented. |
86,7 → 66,7
* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz. |
|
|
## Status |
### Status |
|
The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute |
all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark). |
102,24 → 82,25
|
### To-Do / Wish List / [Help Wanted](#Contribute) |
|
* Add a cache for the external memory interface |
* Use LaTeX for data sheet |
* Further size and performance optimization |
* Synthesis results (+ wrappers?) for more platforms |
* Add a cache for the external memory interface |
* Synthesis results (+ wrappers?) for more/specific platforms |
* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org)) |
* Implement further CPU extensions: |
* Atomic operations (`A`) |
* Bitmanipulation operations (`B`), when they are "official" |
* Bitmanipulation operations (`B`) - when they are *official* |
* Floating-point instructions (`F`) |
* ... |
* ... |
|
|
|
## Features |
|
The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file: |
[ NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
### NEORV32 Processor (SoC) |
### NEORV32 Processor Features |
|
 |
|
127,7 → 108,7
is highly customizable via the processor's top generics. |
|
* Optional processor-internal data and instruction memories (**DMEM** / **IMEM**) |
* Optional internal **Bootloader** with UART console and automatic SPI flash boot option |
* Optional internal **Bootloader** with UART console and automatic application boot from SPI flash option |
* Optional machine system timer (**MTIME**), RISC-V-compliant |
* Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io |
* Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines |
141,7 → 122,7
* Optional custom functions units (**CFU0** and **CFU1**) for tightly-coupled custom co-processors |
* System configuration information memory to check hardware configuration by software (**SYSINFO**) |
|
### NEORV32 CPU |
### NEORV32 CPU Features |
|
 |
|
361,176 → 342,41
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration |
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic). |
|
When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles. |
When the `C` extension is enabled branches to an unaligned uncompressed instruction require additional instruction fetch cycles. |
|
|
|
## Top Entities |
|
The top entity of the **NEORV32 Processor** (SoC) is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) |
and the top entity of the **NEORV32 CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd). Both |
top entities are located in `rtl/core`. |
The top entity of the **NEORV32 Processor** (SoC) is [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd). |
|
All signals of the top entities are of type *std_ulogic* or *std_ulogic_vector*, respectively |
All signals of the top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively |
(except for the processor's TWI signals, which are of type *std_logic*). Leave all unused output ports unconnected (`open`) and tie all unused |
input ports to zero (`'0'` or `(others => '0')`, respectively). |
|
Alternative top entities, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project) or CPU/Processor |
wrappers with resolved port signal types (i.e. *std_logic*), can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates). |
|
Use the top's generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration. |
Use the top's generics to configure the system according to your needs. Each generic is initilized with the default configuration. |
Detailed information regarding the interface signals and configuration generics can be found in |
the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
the [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf). |
|
### NEORV32 CPU |
|
```vhdl |
entity neorv32_cpu is |
generic ( |
-- General -- |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Extension Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
-- Physical Memory Protection (PMP) -- |
PMP_USE : boolean := false; -- implement PMP? |
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8) |
PMP_GRANULARITY : natural := 14 -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
i_bus_we_o : out std_ulogic; -- write enable |
i_bus_re_o : out std_ulogic; -- read enable |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
d_bus_we_o : out std_ulogic; -- write enable |
d_bus_re_o : out std_ulogic; -- read enable |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0') |
); |
end neorv32_cpu; |
``` |
### Using the CPU in Stand-Alone Mode |
|
### NEORV32 Processor |
If you do not want to use the NEORV32 processor setup, you can also use the CPU in stand-alone mode and build your own system around it. |
The top entity of the stand-alone **NEORV32 CPU** is [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd). |
Note that the CPU uses a proprietary interface for accessing data and instruction memory. More information can be found in the |
[NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
```vhdl |
entity neorv32_top is |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
-- Extension Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
-- Physical Memory Protection (PMP) -- |
PMP_USE : boolean := false; -- implement PMP? |
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8) |
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64kB |
-- Internal Instruction memory -- |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Internal Data memory -- |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes |
-- External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)? |
IO_CFU0_USE : boolean := false; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_USE : boolean := false -- implement custom functions unit 1 (CFU1)? |
); |
port ( |
-- Global control -- |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
-- Wishbone bus interface (available if MEM_EXT_USE = true) -- |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
priv_o : out std_ulogic_vector(1 downto 0); -- current CPU privilege level |
fence_o : out std_ulogic; -- indicates an executed FENCE operation |
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation |
-- GPIO (available if IO_GPIO_USE = true) -- |
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output |
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input |
-- UART (available if IO_UART_USE = true) -- |
uart_txd_o : out std_ulogic; -- UART send data |
uart_rxd_i : in std_ulogic := '0'; -- UART receive data |
-- SPI (available if IO_SPI_USE = true) -- |
spi_sck_o : out std_ulogic; -- SPI serial clock |
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in |
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out |
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS |
-- TWI (available if IO_TWI_USE = true) -- |
twi_sda_io : inout std_logic; -- twi serial data line |
twi_scl_io : inout std_logic; -- twi serial clock line |
-- PWM (available if IO_PWM_USE = true) -- |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels |
-- Interrupts -- |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_USE = false |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
); |
end neorv32_top; |
``` |
:warning: It is recommended to use the processor setup even if you only want to use the CPU. Simply disable all the processor-internal modules via the generics |
and you will get a "CPU wrapper" that provides a minimal CPU environment and an external memory interface (like AXI4). This setup also allows to further use the default |
bootloader and application makefiles. From this base you can start building your own processor system. |
|
|
### Alternative Top Entities |
|
*Alternative top entities*, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project) or CPU/Processor |
wrappers with resolved port signal types (i.e. *std_logic*), can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates). |
|
|
### AXI4 Connectivity |
|
Via the [`rtl/top_templates/neorv32_top_axi4lite.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd) |
591,9 → 437,9
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl) |
folder to this project. Make sure to add these files to a **new design library** called `neorv32`. |
|
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you |
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's |
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity. |
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) or one of its |
[wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) in your own project. If you just want to try out the processor, |
you can use the simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity. |
|
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output signals are |
propagated as actual entity signals. Basically, it is a FPGA "hello world" example: |
688,10 → 534,9
## Contribute |
|
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free |
to [open a new issue](https://github.com/stnolting/neorv32/issues) or directly [drop me a line](mailto:stnolting@gmail.com). |
to [open a new issue](https://github.com/stnolting/neorv32/issues) or directly [drop me a line](mailto:stnolting@gmail.com). If you'd like to contribute: |
|
If you'd like to contribute: |
|
0. Check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md) |
1. [Fork](https://github.com/stnolting/neorv32/fork) this repository and clone the fork |
2. Create a feature branch in your fork: `git checkout -b awesome_new_feature_branch` |
3. Create a new remote for the upstream repo: `git remote add https://github.com/stnolting/neorv32` |
699,10 → 544,7
4. Push to the branch: `git push origin awesome_new_feature_branch` |
5. Create a new [pull request](https://github.com/stnolting/neorv32/pulls) |
|
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md). |
|
|
|
## Legal |
|
This project is released under the BSD 3-Clause license. No copyright infringement intended. |
743,7 → 585,7
|
#### Limitation of Liability for External Links |
|
Our website contains links to the websites of third parties („external links“). As the |
Our website contains links to the websites of third parties ("external links"). As the |
content of these websites is not under our control, we cannot assume any liability for |
such external content. In all cases, the provider of information of the linked websites |
is liable for the content and accuracy of the information provided. At the point in time |
783,4 → 625,4
|
This repository was created on June 23th, 2020. |
|
Made with :coffee: in Hannover, Germany. |
Made with :coffee: in Hannover, Germany :eu: |