URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk
- from Rev 36 to Rev 37
- ↔ Reverse comparison
Rev 36 → Rev 37
/.ci/hw_check.sh
10,11 → 10,5
# Run simulation |
sh $homedir/sim/ghdl/ghdl_sim.sh --stop-time=6ms |
|
# Check output |
echo "Checking NEORV32.UART_SIM_MODE text output. Should contain:"; cat $homedir/check_reference.out |
echo "" |
echo "Checking NEORV32.UART_SIM_MODE text output. NEORV32.UART_SIM_MODE text output is:" |
cat neorv32.uart.sim_mode.text.out |
|
# Check if reference can be found in output |
grep -qf $homedir/check_reference.out neorv32.uart.sim_mode.text.out && echo "Hardware test completed successfully!" |
/.ci/sw_check.sh
20,7 → 20,7
make -C $test_app_dir check |
|
# Generate executables for all example projects |
make -C $srcdir_examples clean_all exe |
make -C $srcdir_examples MARCH=-march=rv32imc clean_all exe |
|
# Compile and install bootloader |
make -C $srcdir_bootloader clean_all info bootloader |
/docs/figures/neorv32_logo_inverse_black_bg.png
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docs/figures/neorv32_logo_inverse_black_bg.png
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+application/octet-stream
\ No newline at end of property
Index: docs/figures/neorv32_logo_inverse_transparent_bg.png
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Index: docs/figures/neorv32_logo_inverse_transparent_bg.png
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--- docs/figures/neorv32_logo_inverse_transparent_bg.png (nonexistent)
+++ docs/figures/neorv32_logo_inverse_transparent_bg.png (revision 37)
docs/figures/neorv32_logo_inverse_transparent_bg.png
Property changes :
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Index: docs/figures/neorv32_logo_transparent_bg.png
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Index: docs/figures/neorv32_logo_transparent_bg.png
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--- docs/figures/neorv32_logo_transparent_bg.png (nonexistent)
+++ docs/figures/neorv32_logo_transparent_bg.png (revision 37)
docs/figures/neorv32_logo_transparent_bg.png
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+application/octet-stream
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Index: docs/figures/neorv32_logo_white_bg.png
===================================================================
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Index: docs/figures/neorv32_logo_white_bg.png
===================================================================
--- docs/figures/neorv32_logo_white_bg.png (nonexistent)
+++ docs/figures/neorv32_logo_white_bg.png (revision 37)
docs/figures/neorv32_logo_white_bg.png
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Index: docs/NEORV32.pdf
===================================================================
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Index: rtl/core/neorv32_bootloader_image.vhd
===================================================================
--- rtl/core/neorv32_bootloader_image.vhd (revision 36)
+++ rtl/core/neorv32_bootloader_image.vhd (revision 37)
@@ -6,7 +6,7 @@
package neorv32_bootloader_image is
- type bootloader_init_image_t is array (0 to 1018) of std_ulogic_vector(31 downto 0);
+ type bootloader_init_image_t is array (0 to 973) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
@@ -44,7 +44,7 @@
00000033 => x"00158593",
00000034 => x"ff5ff06f",
00000035 => x"00001597",
- 00000036 => x"f5c58593",
+ 00000036 => x"ea858593",
00000037 => x"80010617",
00000038 => x"f6c60613",
00000039 => x"80010697",
@@ -100,932 +100,887 @@
00000089 => x"00200513",
00000090 => x"0087f463",
00000091 => x"00400513",
- 00000092 => x"3b5000ef",
+ 00000092 => x"301000ef",
00000093 => x"00005537",
00000094 => x"00000613",
00000095 => x"00000593",
00000096 => x"b0050513",
- 00000097 => x"291000ef",
- 00000098 => x"249000ef",
+ 00000097 => x"1dd000ef",
+ 00000098 => x"195000ef",
00000099 => x"00245793",
00000100 => x"00a78533",
00000101 => x"00f537b3",
00000102 => x"00b785b3",
- 00000103 => x"261000ef",
+ 00000103 => x"1ad000ef",
00000104 => x"ffff07b7",
- 00000105 => x"49078793",
+ 00000105 => x"49478793",
00000106 => x"30579073",
00000107 => x"08000793",
00000108 => x"30479073",
00000109 => x"30046073",
00000110 => x"00100513",
- 00000111 => x"41d000ef",
+ 00000111 => x"369000ef",
00000112 => x"ffff1537",
00000113 => x"800007b7",
- 00000114 => x"f0450513",
+ 00000114 => x"e5050513",
00000115 => x"0007a023",
- 00000116 => x"2fd000ef",
- 00000117 => x"159000ef",
- 00000118 => x"ffff1537",
- 00000119 => x"f3c50513",
- 00000120 => x"2ed000ef",
- 00000121 => x"fe002503",
- 00000122 => x"238000ef",
- 00000123 => x"ffff1537",
- 00000124 => x"f4450513",
- 00000125 => x"2d9000ef",
- 00000126 => x"fe402503",
- 00000127 => x"224000ef",
- 00000128 => x"ffff1537",
- 00000129 => x"f5050513",
- 00000130 => x"2c5000ef",
- 00000131 => x"30102573",
- 00000132 => x"210000ef",
- 00000133 => x"ffff1537",
- 00000134 => x"f5850513",
- 00000135 => x"2b1000ef",
- 00000136 => x"fe802503",
- 00000137 => x"ffff14b7",
- 00000138 => x"00341413",
- 00000139 => x"1f4000ef",
- 00000140 => x"ffff1537",
- 00000141 => x"f6050513",
- 00000142 => x"295000ef",
- 00000143 => x"ff802503",
- 00000144 => x"1e0000ef",
- 00000145 => x"f6848513",
- 00000146 => x"285000ef",
- 00000147 => x"ff002503",
- 00000148 => x"1d0000ef",
- 00000149 => x"ffff1537",
- 00000150 => x"f7450513",
- 00000151 => x"271000ef",
- 00000152 => x"ffc02503",
- 00000153 => x"1bc000ef",
- 00000154 => x"f6848513",
- 00000155 => x"261000ef",
- 00000156 => x"ff402503",
- 00000157 => x"1ac000ef",
- 00000158 => x"ffff1537",
- 00000159 => x"f7c50513",
- 00000160 => x"24d000ef",
- 00000161 => x"14d000ef",
- 00000162 => x"00a404b3",
- 00000163 => x"0084b433",
- 00000164 => x"00b40433",
- 00000165 => x"fa402783",
- 00000166 => x"0207d263",
- 00000167 => x"ffff1537",
- 00000168 => x"fa450513",
- 00000169 => x"229000ef",
- 00000170 => x"219000ef",
- 00000171 => x"02300793",
- 00000172 => x"02f51263",
- 00000173 => x"00000513",
- 00000174 => x"0180006f",
- 00000175 => x"115000ef",
- 00000176 => x"fc85eae3",
- 00000177 => x"00b41463",
- 00000178 => x"fc9566e3",
- 00000179 => x"00100513",
- 00000180 => x"5b4000ef",
- 00000181 => x"0b4000ef",
- 00000182 => x"ffff1937",
- 00000183 => x"ffff19b7",
- 00000184 => x"02300a13",
- 00000185 => x"07200a93",
- 00000186 => x"06800b13",
- 00000187 => x"07500b93",
- 00000188 => x"ffff14b7",
- 00000189 => x"ffff1c37",
- 00000190 => x"fb090513",
- 00000191 => x"1d1000ef",
- 00000192 => x"1b1000ef",
- 00000193 => x"00050413",
- 00000194 => x"199000ef",
- 00000195 => x"ebc98513",
- 00000196 => x"1bd000ef",
- 00000197 => x"fb4400e3",
- 00000198 => x"01541863",
- 00000199 => x"ffff02b7",
- 00000200 => x"00028067",
- 00000201 => x"fd5ff06f",
- 00000202 => x"01641663",
- 00000203 => x"05c000ef",
- 00000204 => x"fc9ff06f",
- 00000205 => x"00000513",
- 00000206 => x"03740063",
- 00000207 => x"07300793",
- 00000208 => x"00f41663",
- 00000209 => x"66c000ef",
- 00000210 => x"fb1ff06f",
- 00000211 => x"06c00793",
- 00000212 => x"00f41863",
- 00000213 => x"00100513",
- 00000214 => x"3f0000ef",
- 00000215 => x"f9dff06f",
- 00000216 => x"06500793",
- 00000217 => x"00f41663",
- 00000218 => x"02c000ef",
- 00000219 => x"f8dff06f",
- 00000220 => x"03f00793",
- 00000221 => x"fb8c0513",
- 00000222 => x"00f40463",
- 00000223 => x"fcc48513",
- 00000224 => x"14d000ef",
- 00000225 => x"f75ff06f",
- 00000226 => x"ffff1537",
- 00000227 => x"de050513",
- 00000228 => x"13d0006f",
- 00000229 => x"800007b7",
- 00000230 => x"0007a783",
- 00000231 => x"00079863",
- 00000232 => x"ffff1537",
- 00000233 => x"e4450513",
- 00000234 => x"1250006f",
- 00000235 => x"ff010113",
- 00000236 => x"00112623",
- 00000237 => x"30047073",
- 00000238 => x"ffff1537",
- 00000239 => x"e6050513",
- 00000240 => x"10d000ef",
- 00000241 => x"fa002783",
- 00000242 => x"fe07cee3",
- 00000243 => x"b0001073",
- 00000244 => x"b8001073",
- 00000245 => x"b0201073",
- 00000246 => x"b8201073",
- 00000247 => x"ff002783",
- 00000248 => x"00078067",
- 00000249 => x"0000006f",
- 00000250 => x"ff010113",
- 00000251 => x"00812423",
- 00000252 => x"00050413",
- 00000253 => x"ffff1537",
- 00000254 => x"e7050513",
- 00000255 => x"00112623",
- 00000256 => x"0cd000ef",
- 00000257 => x"03040513",
- 00000258 => x"0ff57513",
- 00000259 => x"095000ef",
- 00000260 => x"30047073",
- 00000261 => x"00100513",
- 00000262 => x"1c1000ef",
- 00000263 => x"0000006f",
- 00000264 => x"fe010113",
- 00000265 => x"01212823",
- 00000266 => x"00050913",
- 00000267 => x"ffff1537",
- 00000268 => x"00912a23",
- 00000269 => x"e8850513",
- 00000270 => x"ffff14b7",
- 00000271 => x"00812c23",
- 00000272 => x"01312623",
- 00000273 => x"00112e23",
- 00000274 => x"01c00413",
- 00000275 => x"081000ef",
- 00000276 => x"fd848493",
- 00000277 => x"ffc00993",
- 00000278 => x"008957b3",
- 00000279 => x"00f7f793",
- 00000280 => x"00f487b3",
- 00000281 => x"0007c503",
- 00000282 => x"ffc40413",
- 00000283 => x"035000ef",
- 00000284 => x"ff3414e3",
- 00000285 => x"01c12083",
- 00000286 => x"01812403",
- 00000287 => x"01412483",
- 00000288 => x"01012903",
- 00000289 => x"00c12983",
- 00000290 => x"02010113",
- 00000291 => x"00008067",
- 00000292 => x"fb010113",
- 00000293 => x"04112623",
- 00000294 => x"04512423",
- 00000295 => x"04612223",
- 00000296 => x"04712023",
- 00000297 => x"02812e23",
- 00000298 => x"02a12c23",
- 00000299 => x"02b12a23",
- 00000300 => x"02c12823",
- 00000301 => x"02d12623",
- 00000302 => x"02e12423",
- 00000303 => x"02f12223",
- 00000304 => x"03012023",
- 00000305 => x"01112e23",
- 00000306 => x"01c12c23",
- 00000307 => x"01d12a23",
- 00000308 => x"01e12823",
- 00000309 => x"01f12623",
- 00000310 => x"34202473",
- 00000311 => x"800007b7",
- 00000312 => x"00778793",
- 00000313 => x"06f41a63",
- 00000314 => x"00000513",
- 00000315 => x"0d1000ef",
- 00000316 => x"6e0000ef",
- 00000317 => x"fe002783",
- 00000318 => x"0027d793",
- 00000319 => x"00a78533",
- 00000320 => x"00f537b3",
- 00000321 => x"00b785b3",
- 00000322 => x"6f4000ef",
- 00000323 => x"03c12403",
- 00000324 => x"04c12083",
- 00000325 => x"04812283",
- 00000326 => x"04412303",
- 00000327 => x"04012383",
- 00000328 => x"03812503",
- 00000329 => x"03412583",
- 00000330 => x"03012603",
- 00000331 => x"02c12683",
- 00000332 => x"02812703",
- 00000333 => x"02412783",
- 00000334 => x"02012803",
- 00000335 => x"01c12883",
- 00000336 => x"01812e03",
- 00000337 => x"01412e83",
- 00000338 => x"01012f03",
- 00000339 => x"00c12f83",
- 00000340 => x"05010113",
- 00000341 => x"30200073",
- 00000342 => x"00700793",
- 00000343 => x"00100513",
- 00000344 => x"02f40863",
- 00000345 => x"ffff1537",
- 00000346 => x"e7c50513",
- 00000347 => x"760000ef",
- 00000348 => x"00040513",
- 00000349 => x"eadff0ef",
- 00000350 => x"ffff1537",
- 00000351 => x"e8450513",
- 00000352 => x"74c000ef",
- 00000353 => x"34102573",
- 00000354 => x"e99ff0ef",
- 00000355 => x"00500513",
- 00000356 => x"e59ff0ef",
- 00000357 => x"ff010113",
- 00000358 => x"00000513",
- 00000359 => x"00112623",
- 00000360 => x"00812423",
- 00000361 => x"7c0000ef",
- 00000362 => x"00500513",
- 00000363 => x"7fc000ef",
- 00000364 => x"00000513",
- 00000365 => x"7f4000ef",
- 00000366 => x"00050413",
- 00000367 => x"00000513",
- 00000368 => x"7c4000ef",
- 00000369 => x"00c12083",
- 00000370 => x"0ff47513",
- 00000371 => x"00812403",
- 00000372 => x"01010113",
- 00000373 => x"00008067",
- 00000374 => x"ff010113",
- 00000375 => x"00000513",
+ 00000116 => x"249000ef",
+ 00000117 => x"f1302573",
+ 00000118 => x"24c000ef",
+ 00000119 => x"ffff1537",
+ 00000120 => x"e8850513",
+ 00000121 => x"235000ef",
+ 00000122 => x"fe002503",
+ 00000123 => x"238000ef",
+ 00000124 => x"ffff1537",
+ 00000125 => x"e9050513",
+ 00000126 => x"221000ef",
+ 00000127 => x"fe402503",
+ 00000128 => x"224000ef",
+ 00000129 => x"ffff1537",
+ 00000130 => x"e9c50513",
+ 00000131 => x"20d000ef",
+ 00000132 => x"30102573",
+ 00000133 => x"210000ef",
+ 00000134 => x"ffff1537",
+ 00000135 => x"ea450513",
+ 00000136 => x"1f9000ef",
+ 00000137 => x"fe802503",
+ 00000138 => x"ffff14b7",
+ 00000139 => x"00341413",
+ 00000140 => x"1f4000ef",
+ 00000141 => x"ffff1537",
+ 00000142 => x"eac50513",
+ 00000143 => x"1dd000ef",
+ 00000144 => x"ff802503",
+ 00000145 => x"1e0000ef",
+ 00000146 => x"eb448513",
+ 00000147 => x"1cd000ef",
+ 00000148 => x"ff002503",
+ 00000149 => x"1d0000ef",
+ 00000150 => x"ffff1537",
+ 00000151 => x"ec050513",
+ 00000152 => x"1b9000ef",
+ 00000153 => x"ffc02503",
+ 00000154 => x"1bc000ef",
+ 00000155 => x"eb448513",
+ 00000156 => x"1a9000ef",
+ 00000157 => x"ff402503",
+ 00000158 => x"1ac000ef",
+ 00000159 => x"ffff1537",
+ 00000160 => x"ec850513",
+ 00000161 => x"195000ef",
+ 00000162 => x"095000ef",
+ 00000163 => x"00a404b3",
+ 00000164 => x"0084b433",
+ 00000165 => x"00b40433",
+ 00000166 => x"fa402783",
+ 00000167 => x"0207d263",
+ 00000168 => x"ffff1537",
+ 00000169 => x"ef050513",
+ 00000170 => x"171000ef",
+ 00000171 => x"161000ef",
+ 00000172 => x"02300793",
+ 00000173 => x"02f51263",
+ 00000174 => x"00000513",
+ 00000175 => x"0180006f",
+ 00000176 => x"05d000ef",
+ 00000177 => x"fc85eae3",
+ 00000178 => x"00b41463",
+ 00000179 => x"fc9566e3",
+ 00000180 => x"00100513",
+ 00000181 => x"5b8000ef",
+ 00000182 => x"0b4000ef",
+ 00000183 => x"ffff1937",
+ 00000184 => x"ffff19b7",
+ 00000185 => x"02300a13",
+ 00000186 => x"07200a93",
+ 00000187 => x"06800b13",
+ 00000188 => x"07500b93",
+ 00000189 => x"ffff14b7",
+ 00000190 => x"ffff1c37",
+ 00000191 => x"efc90513",
+ 00000192 => x"119000ef",
+ 00000193 => x"0f9000ef",
+ 00000194 => x"00050413",
+ 00000195 => x"0e1000ef",
+ 00000196 => x"e0898513",
+ 00000197 => x"105000ef",
+ 00000198 => x"fb4400e3",
+ 00000199 => x"01541863",
+ 00000200 => x"ffff02b7",
+ 00000201 => x"00028067",
+ 00000202 => x"fd5ff06f",
+ 00000203 => x"01641663",
+ 00000204 => x"05c000ef",
+ 00000205 => x"fc9ff06f",
+ 00000206 => x"00000513",
+ 00000207 => x"03740063",
+ 00000208 => x"07300793",
+ 00000209 => x"00f41663",
+ 00000210 => x"658000ef",
+ 00000211 => x"fb1ff06f",
+ 00000212 => x"06c00793",
+ 00000213 => x"00f41863",
+ 00000214 => x"00100513",
+ 00000215 => x"3f4000ef",
+ 00000216 => x"f9dff06f",
+ 00000217 => x"06500793",
+ 00000218 => x"00f41663",
+ 00000219 => x"02c000ef",
+ 00000220 => x"f8dff06f",
+ 00000221 => x"03f00793",
+ 00000222 => x"f04c0513",
+ 00000223 => x"00f40463",
+ 00000224 => x"f1848513",
+ 00000225 => x"095000ef",
+ 00000226 => x"f75ff06f",
+ 00000227 => x"ffff1537",
+ 00000228 => x"d2c50513",
+ 00000229 => x"0850006f",
+ 00000230 => x"800007b7",
+ 00000231 => x"0007a783",
+ 00000232 => x"00079863",
+ 00000233 => x"ffff1537",
+ 00000234 => x"d9050513",
+ 00000235 => x"06d0006f",
+ 00000236 => x"ff010113",
+ 00000237 => x"00112623",
+ 00000238 => x"30047073",
+ 00000239 => x"ffff1537",
+ 00000240 => x"dac50513",
+ 00000241 => x"055000ef",
+ 00000242 => x"fa002783",
+ 00000243 => x"fe07cee3",
+ 00000244 => x"b0001073",
+ 00000245 => x"b8001073",
+ 00000246 => x"b0201073",
+ 00000247 => x"b8201073",
+ 00000248 => x"ff002783",
+ 00000249 => x"00078067",
+ 00000250 => x"0000006f",
+ 00000251 => x"ff010113",
+ 00000252 => x"00812423",
+ 00000253 => x"00050413",
+ 00000254 => x"ffff1537",
+ 00000255 => x"dbc50513",
+ 00000256 => x"00112623",
+ 00000257 => x"015000ef",
+ 00000258 => x"03040513",
+ 00000259 => x"0ff57513",
+ 00000260 => x"7dc000ef",
+ 00000261 => x"30047073",
+ 00000262 => x"00100513",
+ 00000263 => x"109000ef",
+ 00000264 => x"0000006f",
+ 00000265 => x"fe010113",
+ 00000266 => x"01212823",
+ 00000267 => x"00050913",
+ 00000268 => x"ffff1537",
+ 00000269 => x"00912a23",
+ 00000270 => x"dd450513",
+ 00000271 => x"ffff14b7",
+ 00000272 => x"00812c23",
+ 00000273 => x"01312623",
+ 00000274 => x"00112e23",
+ 00000275 => x"01c00413",
+ 00000276 => x"7c8000ef",
+ 00000277 => x"f2448493",
+ 00000278 => x"ffc00993",
+ 00000279 => x"008957b3",
+ 00000280 => x"00f7f793",
+ 00000281 => x"00f487b3",
+ 00000282 => x"0007c503",
+ 00000283 => x"ffc40413",
+ 00000284 => x"77c000ef",
+ 00000285 => x"ff3414e3",
+ 00000286 => x"01c12083",
+ 00000287 => x"01812403",
+ 00000288 => x"01412483",
+ 00000289 => x"01012903",
+ 00000290 => x"00c12983",
+ 00000291 => x"02010113",
+ 00000292 => x"00008067",
+ 00000293 => x"fb010113",
+ 00000294 => x"04112623",
+ 00000295 => x"04512423",
+ 00000296 => x"04612223",
+ 00000297 => x"04712023",
+ 00000298 => x"02812e23",
+ 00000299 => x"02a12c23",
+ 00000300 => x"02b12a23",
+ 00000301 => x"02c12823",
+ 00000302 => x"02d12623",
+ 00000303 => x"02e12423",
+ 00000304 => x"02f12223",
+ 00000305 => x"03012023",
+ 00000306 => x"01112e23",
+ 00000307 => x"01c12c23",
+ 00000308 => x"01d12a23",
+ 00000309 => x"01e12823",
+ 00000310 => x"01f12623",
+ 00000311 => x"34202473",
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+ 00000865 => x"45203a65",
+ 00000866 => x"75636578",
+ 00000867 => x"00006574",
+ 00000868 => x"65206f4e",
+ 00000869 => x"75636578",
+ 00000870 => x"6c626174",
+ 00000871 => x"76612065",
+ 00000872 => x"616c6961",
+ 00000873 => x"2e656c62",
+ 00000874 => x"00000000",
+ 00000875 => x"746f6f42",
+ 00000876 => x"2e676e69",
+ 00000877 => x"0a0a2e2e",
+ 00000878 => x"00000000",
+ 00000879 => x"52450a07",
+ 00000880 => x"5f524f52",
+ 00000881 => x"00000000",
+ 00000882 => x"58450a0a",
+ 00000883 => x"00282043",
+ 00000884 => x"20402029",
+ 00000885 => x"00007830",
+ 00000886 => x"69617741",
+ 00000887 => x"676e6974",
+ 00000888 => x"6f656e20",
+ 00000889 => x"32337672",
+ 00000890 => x"6578655f",
+ 00000891 => x"6e69622e",
+ 00000892 => x"202e2e2e",
+ 00000893 => x"00000000",
+ 00000894 => x"64616f4c",
+ 00000895 => x"2e676e69",
+ 00000896 => x"00202e2e",
+ 00000897 => x"00004b4f",
+ 00000898 => x"0000000a",
+ 00000899 => x"74697257",
+ 00000900 => x"78302065",
+ 00000901 => x"00000000",
+ 00000902 => x"74796220",
+ 00000903 => x"74207365",
+ 00000904 => x"5053206f",
+ 00000905 => x"6c662049",
+ 00000906 => x"20687361",
+ 00000907 => x"78302040",
+ 00000908 => x"00000000",
+ 00000909 => x"7928203f",
+ 00000910 => x"20296e2f",
+ 00000911 => x"00000000",
+ 00000912 => x"616c460a",
+ 00000913 => x"6e696873",
+ 00000914 => x"2e2e2e67",
+ 00000915 => x"00000020",
+ 00000916 => x"0a0a0a0a",
+ 00000917 => x"4e203c3c",
+ 00000918 => x"56524f45",
+ 00000919 => x"42203233",
+ 00000920 => x"6c746f6f",
+ 00000921 => x"6564616f",
+ 00000922 => x"3e3e2072",
+ 00000923 => x"4c420a0a",
+ 00000924 => x"203a5644",
+ 00000925 => x"20766f4e",
+ 00000926 => x"32203720",
+ 00000927 => x"0a303230",
+ 00000928 => x"3a565748",
+ 00000929 => x"00002020",
+ 00000930 => x"4b4c430a",
+ 00000931 => x"0020203a",
+ 00000932 => x"0a7a4820",
+ 00000933 => x"52455355",
+ 00000934 => x"0000203a",
+ 00000935 => x"53494d0a",
+ 00000936 => x"00203a41",
+ 00000937 => x"4f52500a",
+ 00000938 => x"00203a43",
+ 00000939 => x"454d490a",
+ 00000940 => x"00203a4d",
+ 00000941 => x"74796220",
+ 00000942 => x"40207365",
+ 00000943 => x"00000020",
+ 00000944 => x"454d440a",
+ 00000945 => x"00203a4d",
+ 00000946 => x"75410a0a",
+ 00000947 => x"6f626f74",
+ 00000948 => x"6920746f",
+ 00000949 => x"7338206e",
+ 00000950 => x"7250202e",
+ 00000951 => x"20737365",
+ 00000952 => x"2079656b",
+ 00000953 => x"61206f74",
+ 00000954 => x"74726f62",
+ 00000955 => x"00000a2e",
+ 00000956 => x"726f6241",
+ 00000957 => x"2e646574",
+ 00000958 => x"00000a0a",
+ 00000959 => x"444d430a",
+ 00000960 => x"00203e3a",
+ 00000961 => x"53207962",
+ 00000962 => x"68706574",
+ 00000963 => x"4e206e61",
+ 00000964 => x"69746c6f",
+ 00000965 => x"0000676e",
+ 00000966 => x"61766e49",
+ 00000967 => x"2064696c",
+ 00000968 => x"00444d43",
+ 00000969 => x"33323130",
+ 00000970 => x"37363534",
+ 00000971 => x"42413938",
+ 00000972 => x"46454443",
others => x"00000000"
);
/rtl/core/neorv32_cpu_control.vhd
156,18 → 156,12
end record; |
signal issue_engine : issue_engine_t; |
|
-- instruction buffer ("FIFO" with just one entry) -- |
type i_buf_t is record |
wdata : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction |
rdata : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction |
status : std_ulogic; |
clear : std_ulogic; |
we : std_ulogic; |
re : std_ulogic; |
free : std_ulogic; |
avail : std_ulogic; |
-- instruction issue interface -- |
type cmd_issue_t is record |
data : std_ulogic_vector(35 downto 0); -- 4-bit status + 32-bit instruction |
valid : std_ulogic; -- data word is valid when set |
end record; |
signal i_buf : i_buf_t; |
signal cmd_issue : cmd_issue_t; |
|
-- instruction execution engine -- |
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS); |
197,8 → 191,6
end record; |
signal execute_engine : execute_engine_t; |
|
signal next_pc_tmp : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- trap controller -- |
type trap_ctrl_t is record |
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0); |
369,7 → 361,7
elsif (ipb.we = '1') then |
ipb.w_pnt <= std_ulogic_vector(unsigned(ipb.w_pnt) + 1); |
end if; |
if (ipb.we = '1') then -- write port |
if (ipb.we = '1') then -- write data |
ipb.data(to_integer(unsigned(ipb.w_pnt(ipb.w_pnt'left-1 downto 0)))) <= ipb.wdata; |
end if; |
-- read port -- |
430,7 → 422,7
|
-- Issue Engine FSM Comb ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
issue_engine_fsm_comb: process(issue_engine, ipb, i_buf, execute_engine, ci_illegal, ci_instr32) |
issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32) |
begin |
-- arbiter defaults -- |
issue_engine.state_nxt <= issue_engine.state; |
440,10 → 432,10
-- instruction prefetch buffer interface defaults -- |
ipb.re <= '0'; |
|
-- instruction buffer interface defaults -- |
i_buf.we <= '0'; |
-- i_buf = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word> |
i_buf.wdata <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); |
-- instruction issue interface defaults -- |
-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word> |
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); |
cmd_issue.valid <= '0'; |
|
-- state machine -- |
case issue_engine.state is |
453,29 → 445,29
if (ipb.avail = '1') then -- instructions available? |
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word |
if (i_buf.free = '1') then |
i_buf.we <= '1'; |
if (execute_engine.state = DISPATCH) then |
cmd_issue.valid <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned" |
ipb.re <= '1'; |
i_buf.wdata <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); |
ipb.re <= '1'; |
cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0); |
else -- compressed |
ipb.re <= '1'; |
i_buf.wdata <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
ipb.re <= '1'; |
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
issue_engine.align_nxt <= '1'; |
end if; |
end if; |
|
else -- begin check in HIGH instruction half-word |
if (i_buf.free = '1') then |
i_buf.we <= '1'; |
if (execute_engine.state = DISPATCH) then |
cmd_issue.valid <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned" |
ipb.re <= '1'; |
i_buf.wdata <= '0' & issue_engine.buf(17 downto 16) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0)); |
ipb.re <= '1'; |
cmd_issue.data <= '0' & issue_engine.buf(17 downto 16) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0)); |
else -- compressed |
-- do not read from ipb here! |
i_buf.wdata <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32; |
issue_engine.align_nxt <= '0'; |
end if; |
end if; |
522,32 → 514,6
end generate; |
|
|
-- Instruction Buffer --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
instruction_buffer: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (i_buf.clear = '1') then |
i_buf.status <= '0'; |
elsif (i_buf.we = '1') then |
i_buf.status <= '1'; |
elsif (i_buf.re = '1') then |
i_buf.status <= '0'; |
end if; |
if (i_buf.we = '1') then |
i_buf.rdata <= i_buf.wdata; |
end if; |
end if; |
end process instruction_buffer; |
|
-- status -- |
i_buf.free <= not i_buf.status; |
i_buf.avail <= i_buf.status; |
|
-- clear i_buf when clearing ipb -- |
i_buf.clear <= ipb.clear; |
|
|
-- **************************************************************************************************************************** |
-- Instruction Execution |
-- **************************************************************************************************************************** |
556,9 → 522,11
-- Immediate Generator -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
imm_gen: process(clk_i) |
variable opcode_v : std_ulogic_vector(6 downto 0); |
begin |
if rising_edge(clk_i) then |
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is |
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; |
case opcode_v is -- save some bits here, LSBs are always 11 for rv32 |
when opcode_store_c => -- S-immediate |
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
644,18 → 612,20
if (execute_engine.state = EXECUTE) then |
execute_engine.i_reg_last <= execute_engine.i_reg; |
end if; |
-- next PC -- |
if (execute_engine.is_ci = '1') then -- compressed instruction? |
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 2); |
else |
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 4); |
end if; |
-- |
ctrl <= ctrl_nxt; |
end if; |
end process execute_engine_fsm_sync; |
|
-- next PC -- |
next_pc_tmp <= std_ulogic_vector(unsigned(execute_engine.pc) + 2) when (execute_engine.is_ci = '1') else std_ulogic_vector(unsigned(execute_engine.pc) + 4); |
execute_engine.next_pc <= next_pc_tmp(data_width_c-1 downto 1) & '0'; |
|
-- PC output -- |
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; |
next_pc_o <= next_pc_tmp(data_width_c-1 downto 1) & '0'; |
next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; |
|
|
-- CPU Control Bus Output ----------------------------------------------------------------- |
683,7 → 653,7
|
-- Execute Engine FSM Comb ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
execute_engine_fsm_comb: process(execute_engine, fetch_engine, i_buf, trap_ctrl, csr, ctrl, csr_acc_valid, |
execute_engine_fsm_comb: process(execute_engine, fetch_engine, cmd_issue, trap_ctrl, csr, ctrl, csr_acc_valid, |
alu_add_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i) |
variable alu_immediate_v : std_ulogic; |
variable rs1_is_r0_v : std_ulogic; |
701,23 → 671,22
execute_engine.if_rst_nxt <= execute_engine.if_rst; |
|
-- instruction dispatch -- |
fetch_engine.reset <= '0'; |
i_buf.re <= '0'; |
fetch_engine.reset <= '0'; |
|
-- trap environment control -- |
trap_ctrl.env_start_ack <= '0'; |
trap_ctrl.env_end <= '0'; |
trap_ctrl.env_start_ack <= '0'; |
trap_ctrl.env_end <= '0'; |
|
-- exception trigger -- |
trap_ctrl.instr_be <= '0'; |
trap_ctrl.instr_ma <= '0'; |
trap_ctrl.env_call <= '0'; |
trap_ctrl.break_point <= '0'; |
illegal_compressed <= '0'; |
trap_ctrl.instr_be <= '0'; |
trap_ctrl.instr_ma <= '0'; |
trap_ctrl.env_call <= '0'; |
trap_ctrl.break_point <= '0'; |
illegal_compressed <= '0'; |
|
-- CSR access -- |
csr.we_nxt <= '0'; |
csr.re_nxt <= '0'; |
csr.we_nxt <= '0'; |
csr.re_nxt <= '0'; |
|
-- control defaults -- |
ctrl_nxt <= (others => '0'); -- default: all off |
747,30 → 716,28
-- ------------------------------------------------------------ |
-- set reg_file's r0 to zero -- |
if (rf_r0_is_reg_c = true) then -- is r0 implemented as physical register, which has to be set to zero? |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output (hacky! results zero since there is no valid CSR_read request) |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output (hacky! results zero since there is no valid CSR_read) |
ctrl_nxt(ctrl_rf_r0_we_c) <= '1'; -- force RF write access and force rd=r0 |
end if; |
-- |
execute_engine.state_nxt <= DISPATCH; |
|
when DISPATCH => -- Get new command from instruction buffer (i_buf) |
when DISPATCH => -- Get new command from instruction issue engine |
-- ------------------------------------------------------------ |
if (i_buf.avail = '1') then -- instruction available? |
i_buf.re <= '1'; |
-- |
execute_engine.is_ci_nxt <= i_buf.rdata(32); -- flag to indicate this is a de-compressed instruction beeing executed |
execute_engine.i_reg_nxt <= i_buf.rdata(31 downto 0); |
trap_ctrl.instr_ma <= i_buf.rdata(33); -- misaligned instruction fetch address |
trap_ctrl.instr_be <= i_buf.rdata(34); -- bus access fault during instrucion fetch |
illegal_compressed <= i_buf.rdata(35); -- invalid decompressed instruction |
-- |
if (cmd_issue.valid = '1') then -- instruction available? |
-- IR update -- |
execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate this is a de-compressed instruction beeing executed |
execute_engine.i_reg_nxt <= cmd_issue.data(31 downto 0); |
trap_ctrl.instr_ma <= cmd_issue.data(33); -- misaligned instruction fetch address |
trap_ctrl.instr_be <= cmd_issue.data(34); -- bus access fault during instrucion fetch |
illegal_compressed <= cmd_issue.data(35); -- invalid decompressed instruction |
-- PC update -- |
execute_engine.if_rst_nxt <= '0'; |
if (execute_engine.if_rst = '0') then -- if there was NO non-linear PC modification |
execute_engine.pc_nxt <= execute_engine.next_pc; |
execute_engine.pc_nxt <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; |
end if; |
-- |
-- any reason to go FAST to trap state? -- |
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or (trap_ctrl.exc_fire = '1') or ((i_buf.rdata(33) or i_buf.rdata(34)) = '1') then |
-- any reason to go to trap state FAST? -- |
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or (trap_ctrl.exc_fire = '1') or ((cmd_issue.data(33) or cmd_issue.data(34)) = '1') then |
execute_engine.state_nxt <= TRAP; |
else |
execute_engine.state_nxt <= EXECUTE; |
885,7 → 852,7
-- for simplicity: internally, fence and fence.i perform the same operations (clear and reload instruction prefetch buffer) |
-- FENCE.I -- |
if (CPU_EXTENSION_RISCV_Zifencei = true) then |
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction |
execute_engine.pc_nxt <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- "refetch" next instruction |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
fetch_engine.reset <= '1'; |
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) then |
987,8 → 954,8
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD) |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD) |
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception |
execute_engine.state_nxt <= SYS_WAIT; |
if ((ma_load_i or be_load_i or ma_store_i or be_store_i) = '1') then -- abort if exception |
execute_engine.state_nxt <= DISPATCH; |
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (keep writing back all the time) |
1751,7 → 1718,7
csr.rdata(18) <= trap_ctrl.irq_buf(interrupt_firq_2_c); |
csr.rdata(19) <= trap_ctrl.irq_buf(interrupt_firq_3_c); |
|
-- physical memory protection -- |
-- physical memory protection - configuration -- |
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - physical memory protection configuration register 0 |
if (PMP_USE = true) then |
if (PMP_NUM_REGIONS >= 1) then |
1783,6 → 1750,7
end if; |
end if; |
|
-- physical memory protection - addresses -- |
when csr_pmpaddr0_c => -- R/W: pmpaddr0 - physical memory protection address register 0 |
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 1) then |
csr.rdata <= csr.pmpaddr(0); |
/rtl/core/neorv32_package.vhd
50,7 → 50,7
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040606"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040700"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
|
367,7 → 367,7
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13"; -- mimpid |
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; -- mhartid |
-- |
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0"; -- mzext (custom) |
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0"; -- mzext (neorv32-custom) |
|
-- Co-Processor Operations ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
/sw/bootloader/bootloader.c
165,13 → 165,13
void system_error(uint8_t err_code); |
void print_hex_word(uint32_t num); |
|
// SPI flash access |
// SPI flash driver functions |
uint8_t spi_flash_read_byte(uint32_t addr); |
void spi_flash_write_byte(uint32_t addr, uint8_t wdata); |
void spi_flash_write_word(uint32_t addr, uint32_t wdata); |
void spi_flash_erase_sector(uint32_t addr); |
uint8_t spi_flash_read_status(void); |
uint8_t spi_flash_read_1st_id(void); |
void spi_flash_write_wait(void); |
void spi_flash_write_enable(void); |
void spi_flash_write_addr(uint32_t addr); |
|
223,7 → 223,7
// ------------------------------------------------ |
neorv32_uart_print("\n\n\n\n<< NEORV32 Bootloader >>\n\n" |
"BLDV: "__DATE__"\nHWV: "); |
neorv32_rte_print_hw_version(); |
print_hex_word(neorv32_cpu_csr_read(CSR_MIMPID)); |
neorv32_uart_print("\nCLK: "); |
print_hex_word(SYSINFO_CLK); |
neorv32_uart_print(" Hz\nUSER: "); |
608,7 → 608,7
|
|
// ------------------------------------------------------------------------------------- |
// SPI flash functions |
// SPI flash driver functions |
// ------------------------------------------------------------------------------------- |
|
/**********************************************************************//** |
649,12 → 649,7
|
neorv32_spi_cs_dis(SPI_FLASH_CS); |
|
while (1) { |
uint8_t tmp = spi_flash_read_status(); |
if ((tmp & 0x01) == 0) { // write in progress flag cleared? |
break; |
} |
} |
spi_flash_write_wait(); // wait for write operation to finish |
} |
|
|
696,50 → 691,48
|
neorv32_spi_cs_dis(SPI_FLASH_CS); |
|
while (1) { |
uint8_t tmp = spi_flash_read_status(); |
if ((tmp & 0x01) == 0) { // write in progress flag cleared? |
break; |
} |
} |
spi_flash_write_wait(); // wait for write operation to finish |
} |
|
|
/**********************************************************************//** |
* Read status register. |
* Read first byte of ID (manufacturer ID), should be != 0x00. |
* |
* @return Status register. |
* @note The first bit of the manufacturer ID is used to detect if a Flash is connected at all. |
* |
* @return First byte of ID. |
**************************************************************************/ |
uint8_t spi_flash_read_status(void) { |
uint8_t spi_flash_read_1st_id(void) { |
|
neorv32_spi_cs_en(SPI_FLASH_CS); |
|
neorv32_spi_trans(SPI_FLASH_CMD_READ_STATUS); |
uint8_t status = (uint8_t)neorv32_spi_trans(0); |
neorv32_spi_trans(SPI_FLASH_CMD_READ_ID); |
uint8_t id = (uint8_t)neorv32_spi_trans(0); |
|
neorv32_spi_cs_dis(SPI_FLASH_CS); |
|
return status; |
return id; |
} |
|
|
/**********************************************************************//** |
* Read first byte of ID (manufacturer ID), should be != 0x00. |
* |
* @note The first bit of the manufacturer ID is used to detect if a Flash is connected at all. |
* |
* @return First byte of ID. |
* Wait for flash write operation to finisch. |
**************************************************************************/ |
uint8_t spi_flash_read_1st_id(void) { |
void spi_flash_write_wait(void) { |
|
neorv32_spi_cs_en(SPI_FLASH_CS); |
while(1) { |
|
neorv32_spi_trans(SPI_FLASH_CMD_READ_ID); |
uint8_t id = (uint8_t)neorv32_spi_trans(0); |
neorv32_spi_cs_en(SPI_FLASH_CS); |
|
neorv32_spi_cs_dis(SPI_FLASH_CS); |
neorv32_spi_trans(SPI_FLASH_CMD_READ_STATUS); |
uint8_t status = (uint8_t)neorv32_spi_trans(0); |
|
return id; |
neorv32_spi_cs_dis(SPI_FLASH_CS); |
|
if ((status & 0x01) == 0) { // write in progress flag cleared? |
break; |
} |
} |
} |
|
|
772,4 → 765,3
neorv32_spi_trans(address.uint8[1]); |
neorv32_spi_trans(address.uint8[0]); |
} |
|
/sw/example/blink_led/main.c
48,17 → 48,22
/**@{*/ |
/** UART BAUD rate */ |
#define BAUD_RATE 19200 |
/** Use the custom ASM version for blinking the LEDs if != 0 */ |
#define USE_ASM_VERSION 0 |
/** Use the custom ASM version for blinking the LEDs defined (= uncommented) */ |
//#define USE_ASM_VERSION |
/**@}*/ |
|
|
/**********************************************************************//** |
* ASM function to blink LEDs (if enabled) |
* ASM function to blink LEDs |
**************************************************************************/ |
extern void blink_led_asm(uint32_t gpio_out_addr); |
|
/**********************************************************************//** |
* C function to blink LEDs |
**************************************************************************/ |
void blink_led_c(void); |
|
|
/**********************************************************************//** |
* Main function; shows an incrementing 8-bit counter on GPIO.output(7:0). |
* |
85,9 → 90,26
neorv32_uart_print("Blinking LED demo program\n"); |
|
|
// use ASM version of LED blinking (file: blink_led_in_asm.S) |
#ifdef USE_ASM_VERSION |
|
blink_led_asm((uint32_t)(&GPIO_OUTPUT)); |
|
// use C version of LED blinking |
#if (USE_ASM_VERSION == 0) |
#else |
|
blink_led_c(); |
|
#endif |
return 0; |
} |
|
|
/**********************************************************************//** |
* C-version of blinky LED counter |
**************************************************************************/ |
void blink_led_c(void) { |
|
neorv32_gpio_port_set(0); // clear gpio output put |
|
int cnt = 0; |
96,12 → 118,4
neorv32_gpio_port_set(cnt++ & 0xFF); // increment counter and mask for lowest 8 bit |
neorv32_cpu_delay_ms(200); // wait 200ms using busy wait |
} |
|
// use ASM version of LED blinking (file: blink_led_in_asm.S) |
#else |
|
blink_led_asm((uint32_t)(&GPIO_OUTPUT)); |
|
#endif |
return 0; |
} |
/sw/example/cpu_test/main.c
107,11 → 107,13
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFUL; |
neorv32_mtime_set_timecmp(mtime_cmp_max); |
|
|
// intro |
neorv32_uart_printf("\n\n--- PROCESSOR/CPU TEST ---\n"); |
neorv32_uart_printf("build: "__DATE__" "__TIME__"\n"); |
neorv32_uart_printf("This test suite is intended to verify the default NEORV32 processor setup using the default testbench.\n\n"); |
// ----------------------------------------------- |
|
// logo |
neorv32_rte_print_logo(); |
|
// show project credits |
neorv32_rte_print_credits(); |
|
149,13 → 151,13
} |
|
// enable interrupt sources |
install_err = neorv32_cpu_irq_enable(CPU_MIE_MSIE); // activate software interrupt |
install_err += neorv32_cpu_irq_enable(CPU_MIE_MTIE); // activate timer interrupt |
install_err += neorv32_cpu_irq_enable(CPU_MIE_MEIE); // activate external interrupt |
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ0E);// activate fast interrupt channel 0 |
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E);// activate fast interrupt channel 1 |
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ2E);// activate fast interrupt channel 2 |
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ3E);// activate fast interrupt channel 3 |
install_err = neorv32_cpu_irq_enable(CPU_MIE_MSIE); // activate software interrupt |
install_err += neorv32_cpu_irq_enable(CPU_MIE_MTIE); // activate timer interrupt |
install_err += neorv32_cpu_irq_enable(CPU_MIE_MEIE); // activate external interrupt |
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ0E); // activate fast interrupt channel 0 |
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E); // activate fast interrupt channel 1 |
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ2E); // activate fast interrupt channel 2 |
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ3E); // activate fast interrupt channel 3 |
|
if (install_err) { |
neorv32_uart_printf("IRQ enable error (%i)!\n", install_err); |
162,8 → 164,11
return 0; |
} |
|
// intro2 |
neorv32_uart_printf("\n\nStarting tests...\n\n"); |
// test intro |
neorv32_uart_printf("\n--- PROCESSOR/CPU TEST ---\n"); |
neorv32_uart_printf("build: "__DATE__" "__TIME__"\n"); |
neorv32_uart_printf("This test suite is intended to verify the default NEORV32 processor setup using the default testbench.\n\n"); |
neorv32_uart_printf("Starting tests...\n\n"); |
|
// enable global interrupts |
neorv32_cpu_eint(); |
/sw/example/hello_world/main.c
0,0 → 1,79
// ################################################################################################# |
// # << NEORV32 - "Hello World" Demo Program >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
// # # |
// # Redistribution and use in source and binary forms, with or without modification, are # |
// # permitted provided that the following conditions are met: # |
// # # |
// # 1. Redistributions of source code must retain the above copyright notice, this list of # |
// # conditions and the following disclaimer. # |
// # # |
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
// # conditions and the following disclaimer in the documentation and/or other materials # |
// # provided with the distribution. # |
// # # |
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
// # endorse or promote products derived from this software without specific prior written # |
// # permission. # |
// # # |
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
// # OF THE POSSIBILITY OF SUCH DAMAGE. # |
// # ********************************************************************************************* # |
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
// ################################################################################################# |
|
|
/**********************************************************************//** |
* @file hello_world/main.c |
* @author Stephan Nolting |
* @brief Classic 'hello world' demo program. |
**************************************************************************/ |
|
#include <neorv32.h> |
|
|
/**********************************************************************//** |
* @name User configuration |
**************************************************************************/ |
/**@{*/ |
/** UART BAUD rate */ |
#define BAUD_RATE 19200 |
/**@}*/ |
|
|
|
/**********************************************************************//** |
* Main function; prints some fancy stuff via UART. |
* |
* @note This program requires the UART interface to be synthesized. |
* |
* @return Irrelevant. |
**************************************************************************/ |
int main() { |
|
// init UART at default baud rate, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0, 0); |
|
// capture all exceptions and give debug info via UART |
// this is not required, but keeps us safe |
neorv32_rte_setup(); |
|
// print project logo via UART |
neorv32_rte_print_logo(); |
|
// say hello |
neorv32_uart_print("Hello world! :)\n"); |
|
|
return 0; |
} |
/sw/example/hello_world/makefile
0,0 → 1,338
################################################################################################# |
# << NEORV32 - Application Makefile >> # |
# ********************************************************************************************* # |
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. # |
# ********************************************************************************************* # |
# BSD 3-Clause License # |
# # |
# Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
# # |
# Redistribution and use in source and binary forms, with or without modification, are # |
# permitted provided that the following conditions are met: # |
# # |
# 1. Redistributions of source code must retain the above copyright notice, this list of # |
# conditions and the following disclaimer. # |
# # |
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
# conditions and the following disclaimer in the documentation and/or other materials # |
# provided with the distribution. # |
# # |
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
# endorse or promote products derived from this software without specific prior written # |
# permission. # |
# # |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
# OF THE POSSIBILITY OF SUCH DAMAGE. # |
# ********************************************************************************************* # |
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
################################################################################################# |
|
|
# ***************************************************************************** |
# USER CONFIGURATION |
# ***************************************************************************** |
# User's application sources (*.c, *.cpp, *.s, *.S); add additional files here |
APP_SRC ?= $(wildcard ./*.c) $(wildcard ./*.s) $(wildcard ./*.cpp) $(wildcard ./*.S) |
|
# User's application include folders (don't forget the '-I' before each entry) |
APP_INC ?= -I . |
# User's application include folders - for assembly files only (don't forget the '-I' before each entry) |
ASM_INC ?= -I . |
|
# Optimization |
EFFORT ?= -Os |
|
# Compiler toolchain |
RISCV_TOOLCHAIN ?= riscv32-unknown-elf |
|
# CPU architecture and ABI |
MARCH ?= -march=rv32i |
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
|
# Relative or absolute path to the NEORV32 home folder |
NEORV32_HOME ?= ../../.. |
# ***************************************************************************** |
|
|
|
# ----------------------------------------------------------------------------- |
# NEORV32 framework |
# ----------------------------------------------------------------------------- |
# Path to NEORV32 linker script and startup file |
NEORV32_COM_PATH = $(NEORV32_HOME)/sw/common |
# Path to main NEORV32 library include files |
NEORV32_INC_PATH = $(NEORV32_HOME)/sw/lib/include |
# Path to main NEORV32 library source files |
NEORV32_SRC_PATH = $(NEORV32_HOME)/sw/lib/source |
# Path to NEORV32 executable generator |
NEORV32_EXG_PATH = $(NEORV32_HOME)/sw/image_gen |
# Path to NEORV32 core rtl folder |
NEORV32_RTL_PATH = $(NEORV32_HOME)/rtl/core |
# Marker file to check for NEORV32 home folder |
NEORV32_HOME_MARKER = $(NEORV32_INC_PATH)/neorv32.h |
|
# Core libraries (peripheral and CPU drivers) |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
# Application start-up code |
CORE_SRC += $(NEORV32_COM_PATH)/crt0.S |
|
# Linker script |
LD_SCRIPT = $(NEORV32_COM_PATH)/neorv32.ld |
|
# Main output files |
APP_EXE = neorv32_exe.bin |
APP_ASM = main.asm |
APP_IMG = neorv32_application_image.vhd |
BOOT_IMG = neorv32_bootloader_image.vhd |
|
|
# ----------------------------------------------------------------------------- |
# Sources and objects |
# ----------------------------------------------------------------------------- |
# Define all sources |
SRC = $(APP_SRC) |
SRC += $(CORE_SRC) |
|
# Define all object files |
OBJ = $(SRC:%=%.o) |
|
|
# ----------------------------------------------------------------------------- |
# Tools and flags |
# ----------------------------------------------------------------------------- |
# Compiler tools |
CC = $(RISCV_TOOLCHAIN)-gcc |
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump |
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy |
SIZE = $(RISCV_TOOLCHAIN)-size |
|
# Host native compiler |
CC_X86 = gcc -Wall -O -g |
|
# NEORV32 executable image generator |
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen |
|
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
# ----------------------------------------------------------------------------- |
# Application output definitions |
# ----------------------------------------------------------------------------- |
.PHONY: check info help elf_info clean clean_all bootloader |
.DEFAULT_GOAL := help |
|
# 'compile' is still here for compatibility |
exe: $(APP_ASM) $(APP_EXE) |
compile: $(APP_ASM) $(APP_EXE) |
install: $(APP_ASM) $(APP_IMG) |
all: $(APP_ASM) $(APP_EXE) $(APP_IMG) |
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
# Image generator targets |
# ----------------------------------------------------------------------------- |
# install/compile tools |
$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.cpp |
@echo Compiling $(IMAGE_GEN) |
@$(CC_X86) $< -o $(IMAGE_GEN) |
|
|
# ----------------------------------------------------------------------------- |
# General targets: Assemble, compile, link, dump |
# ----------------------------------------------------------------------------- |
# Compile app *.s sources (assembly) |
%.s.o: %.s |
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@ |
|
# Compile app *.S sources (assembly + C pre-processor) |
%.S.o: %.S |
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@ |
|
# Compile app *.c sources |
%.c.o: %.c |
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@ |
|
# Compile app *.cpp sources |
%.cpp.o: %.cpp |
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@ |
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
@$(OBJCOPY) -I elf32-little $< -j .text -O binary text.bin |
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.bin |
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.bin |
@cat text.bin rodata.bin data.bin > $@ |
@rm -f text.bin rodata.bin data.bin |
|
|
# ----------------------------------------------------------------------------- |
# Application targets: Generate binary executable, install (as VHDL file) |
# ----------------------------------------------------------------------------- |
# Generate NEORV32 executable image for upload via bootloader |
$(APP_EXE): main.bin $(IMAGE_GEN) |
@set -e |
@$(IMAGE_GEN) -app_bin $< $@ $(shell basename $(CURDIR)) |
@echo "Executable ($(APP_EXE)) size in bytes:" |
@wc -c < $(APP_EXE) |
|
# Generate NEORV32 executable VHDL boot image |
$(APP_IMG): main.bin $(IMAGE_GEN) |
@set -e |
@$(IMAGE_GEN) -app_img $< $@ $(shell basename $(CURDIR)) |
@echo "Installing application image to $(NEORV32_RTL_PATH)/$(APP_IMG)" |
@cp $(APP_IMG) $(NEORV32_RTL_PATH)/. |
|
|
# ----------------------------------------------------------------------------- |
# Bootloader targets |
# ----------------------------------------------------------------------------- |
# Create and install bootloader VHDL init image |
$(BOOT_IMG): main.bin $(IMAGE_GEN) |
@set -e |
@$(IMAGE_GEN) -bld_img $< $(BOOT_IMG) $(shell basename $(CURDIR)) |
@echo "Installing bootloader image to $(NEORV32_RTL_PATH)/$(BOOT_IMG)" |
@cp $(BOOT_IMG) $(NEORV32_RTL_PATH)/. |
|
# Just an alias that |
bootloader: $(BOOT_IMG) |
|
|
# ----------------------------------------------------------------------------- |
# Check toolchain |
# ----------------------------------------------------------------------------- |
check: $(IMAGE_GEN) |
@echo "---------------- Check: NEORV32_HOME folder ----------------" |
ifneq ($(shell [ -e $(NEORV32_HOME_MARKER) ] && echo 1 || echo 0 ), 1) |
$(error NEORV32_HOME folder not found!) |
endif |
@echo "NEORV32_HOME: $(NEORV32_HOME)" |
@echo "---------------- Check: $(CC) ----------------" |
@$(CC) -v |
@echo "---------------- Check: $(OBJDUMP) ----------------" |
@$(OBJDUMP) -V |
@echo "---------------- Check: $(OBJCOPY) ----------------" |
@$(OBJCOPY) -V |
@echo "---------------- Check: $(SIZE) ----------------" |
@$(SIZE) -V |
@echo "---------------- Check: NEORV32 image_gen ----------------" |
@$(IMAGE_GEN) -help |
@echo "---------------- Check: Native GCC ----------------" |
@$(CC_X86) -v |
@echo |
@echo "Toolchain check OK" |
|
|
# ----------------------------------------------------------------------------- |
# Upload executable via serial port to bootloader |
# ----------------------------------------------------------------------------- |
upload: $(APP_EXE) |
@sh $(NEORV32_EXG_PATH)/uart_upload.sh $(COM_PORT) $(APP_EXE) |
|
|
# ----------------------------------------------------------------------------- |
# Show configuration |
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "ASM include folder(s): $(ASM_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "---------------- Info: Objects ----------------" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
@echo "---------------- Info: Toolchain ----------------" |
@echo "Toolchain: $(RISCV_TOLLCHAIN)" |
@echo "CC: $(CC)" |
@echo "OBJDUMP: $(OBJDUMP)" |
@echo "OBJCOPY: $(OBJCOPY)" |
@echo "SIZE: $(SIZE)" |
@echo "---------------- Info: Compiler Libraries ----------------" |
@echo "LIBGCC:" |
@$(CC) -print-libgcc-file-name |
@echo "SEARCH-DIRS:" |
@$(CC) -print-search-dirs |
@echo "---------------- Info: Flags ----------------" |
@echo "USER_FLAGS: $(USER_FLAGS)" |
@echo "CC_OPTS: $(CC_OPTS)" |
@echo "---------------- Info: Host Native GCC Flags ----------------" |
@echo "CC_X86: $(CC_X86)" |
|
|
# ----------------------------------------------------------------------------- |
# Show final ELF details (just for debugging) |
# ----------------------------------------------------------------------------- |
elf_info: main.elf |
@$(OBJDUMP) -x main.elf |
|
|
# ----------------------------------------------------------------------------- |
# Help |
# ----------------------------------------------------------------------------- |
help: |
@echo "<<< NEORV32 Application Makefile >>>" |
@echo "Make sure to add the bin folder of RISC-V GCC to your PATH variable." |
@echo "Targets:" |
@echo " help - show this text" |
@echo " check - check toolchain" |
@echo " info - show makefile/toolchain configuration" |
@echo " exe - compile and generate <neorv32_exe.bin> executable for upload via bootloader" |
@echo " install - compile, generate and install VHDL IMEM boot image (for application)" |
@echo " all - compile and generate <neorv32_exe.bin> executable for upload via bootloader and generate and install VHDL IMEM boot image (for application)" |
@echo " clean - clean up project" |
@echo " clean_all - clean up project, core libraries and image generator" |
@echo " bootloader - compile, generate and install VHDL BOOTROM boot image (for bootloader only!)" |
@echo " upload - upload <neorv32_exe.bin> executable via serial port <COM_PORT> to bootloader" |
|
|
# ----------------------------------------------------------------------------- |
# Clean up |
# ----------------------------------------------------------------------------- |
clean: |
@rm -f *.elf *.o *.bin *.out *.asm *.vhd |
|
clean_all: clean |
@rm -f $(OBJ) $(IMAGE_GEN) |
/sw/lib/include/neorv32_rte.h
72,6 → 72,7
void neorv32_rte_print_hw_config(void); |
void neorv32_rte_print_hw_version(void); |
void neorv32_rte_print_credits(void); |
void neorv32_rte_print_logo(void); |
void neorv32_rte_print_license(void); |
|
#endif // neorv32_rte_h |
/sw/lib/source/neorv32_rte.c
506,14 → 506,35
**************************************************************************/ |
void neorv32_rte_print_credits(void) { |
|
neorv32_uart_print("\n\nThe NEORV32 Processor Project\n" |
"by Stephan Nolting\n" |
neorv32_uart_print("\nThe NEORV32 Processor Project, by Stephan Nolting\n" |
"https://github.com/stnolting/neorv32\n" |
"made in Hannover, Germany\n\n"); |
"made in Hannover, Germany EU\n\n"); |
} |
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Print project credits |
**************************************************************************/ |
void neorv32_rte_print_logo(void) { |
|
neorv32_uart_print( |
"\n" |
" ##\n" |
" ## ## ## ##\n" |
" ## ## ######### ######## ######## ## ## ######## ######## ## ###############\n" |
"#### ## ## ## ## ## ## ## ## ## ## ## ## ## #### ####\n" |
"## ## ## ## ## ## ## ## ## ## ## ## ## ## ##### ##\n" |
"## ## ## ######### ## ## ######### ## ## ##### ## ## #### ##### ####\n" |
"## ## ## ## ## ## ## ## ## ## ## ## ## ## ##### ##\n" |
"## #### ## ## ## ## ## ## ## ## ## ## ## #### ####\n" |
"## ## ######### ######## ## ## ## ######## ########## ## ###############\n" |
" ## ## ## ##\n" |
" ##\n" |
"\n"); |
} |
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Print project license |
**************************************************************************/ |
void neorv32_rte_print_license(void) { |
520,7 → 541,6
|
neorv32_uart_print( |
"\n" |
"\n" |
"BSD 3-Clause License\n" |
"\n" |
"Copyright (c) 2020, Stephan Nolting. All rights reserved.\n" |
549,9 → 569,7
"NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n" |
"OF THE POSSIBILITY OF SUCH DAMAGE.\n" |
"\n" |
"The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting\n" |
"\n" |
"\n" |
); |
} |
|
/CHANGELOG.md
14,6 → 14,8
|
| Date (*dd.mm.yyyy*) | Version | Comment | |
|:----------:|:-------:|:--------| |
| 11.11.2020 | 1.4.7.0 | Further optimized pipeline front-end: Jumps and branches are one cycle faster (+5% coremark performance); updated synthesis results; updated performance results; added `hello_world` example program | |
| 07.11.2020 | 1.4.6.7 | Updated bootloader (size optimization) and changed processor version output; added project logo; minor data sheet edits | |
| 03.11.2020 | 1.4.6.6 | Removed SPI module's *buggy* "LSB-first mode", SPI module now always sends data MSB-first; removed SPI.CTRL `SPI_CT_DIR` bit; modfied bit order in SPI CTRL register; updated SPI SW library | |
| 02.11.2020 | 1.4.6.5 | :warning: Fixed bug in CPU's illegal instruction detection logic; CPU rtl code optimizations - further reduced hardware footprint; rtl code clean-ups | |
| 01.11.2020 | 1.4.6.4 | :warning: Fixed bug in `[m]instret[h]` and `[m]cycle[h]` carry logic; CPU hardware optimizations (area reduction, shortend critical path) | |
/README.md
1,5 → 1,7
# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V) |
[](https://github.com/stnolting/neorv32) |
|
# The NEORV32 RISC-V Processor |
|
[](https://travis-ci.com/stnolting/neorv32) |
[](https://github.com/stnolting/neorv32/blob/master/LICENSE) |
[](https://github.com/stnolting/neorv32/releases) |
20,14 → 22,14
|
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based |
on the RISC-V-compliant NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC |
designs or as stand-alone custom microcontroller. Its top entity can be directly synthesized for *any* target technology without modifications. |
designs or as stand-alone custom microcontroller. |
|
|
### Key Features |
|
* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features) |
* Compliant to *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf) |
* Compliant to *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf) |
* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to |
* Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf) |
* Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf) |
* Optional CPU extensions |
* `C` - compressed instructions (16-bit) |
* `E` - embedded CPU (reduced register file) |
36,20 → 38,24
* `Zicsr` - control and status register access instructions (+ exception/irq system) |
* `Zifencei` - instruction stream synchronization |
* `PMP` - physical memory protection |
* Full-scale RISC-V microcontroller system (**SoC**) [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules |
* optional embedded memories (instruction/data/bootloader, RAM/ROM) |
* timers (watch dog, RISC-V-compliant machine timer) |
* serial interfaces (SPI, TWI, UART) |
* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity)) |
* [more ...](#NEORV32-Processor-Features) |
* Software framework |
* Core libraries for high-level usage of the provided functions and peripherals |
* Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
* core libraries for high-level usage of the provided functions and peripherals |
* application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile) |
* GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt)) |
* runtime environment |
* several example programs |
* [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html) |
* [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html) |
* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available |
* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf) |
* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc. |
* Fully synchronous design, no latches, no gated clocks |
* Small hardware footprint and high operating frequency |
* Full-scale RISC-V microcontroller system (**SoC**): [**NEORV32 Processor**](#NEORV32-Processor-Features) |
* Optional embedded memories, timers, serial interfaces, external interfaces (Wishbone or [AXI4-Lite](#AXI4-Connectivity)) ... |
|
The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository. |
To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases). |
83,6 → 89,7
### To-Do / Wish List / [Help Wanted](#Contribute) |
|
* Use LaTeX for data sheet |
* More support for FreeRTOS |
* Further size and performance optimization |
* Add a cache for the external memory interface |
* Synthesis results (+ wrappers?) for more/specific platforms |
105,22 → 112,22
 |
|
The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup |
is highly customizable via the processor's top generics. |
is highly customizable via the processor's top generics and already provides the following *optional* modules: |
|
* Optional processor-internal data and instruction memories (**DMEM** / **IMEM**) |
* Optional internal **Bootloader** with UART console and automatic application boot from SPI flash option |
* Optional machine system timer (**MTIME**), RISC-V-compliant |
* Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io |
* Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines |
* Optional two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard |
* Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt |
* Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode |
* Optional wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity)), compatibility verified with Xilinx Vivado Block Desginer |
* Optional watchdog timer (**WDT**) |
* Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**) |
* Optional GARO-based true random number generator (**TRNG**) |
* Optional custom functions units (**CFU0** and **CFU1**) for tightly-coupled custom co-processors |
* System configuration information memory to check hardware configuration by software (**SYSINFO**) |
* processor-internal data and instruction memories (**DMEM** / **IMEM**) |
* internal **Bootloader** with UART console and automatic application boot from SPI flash option |
* machine system timer (**MTIME**), RISC-V-compliant |
* watchdog timer (**WDT**) |
* universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io |
* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines |
* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard |
* general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt |
* 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode |
* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity)) |
* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**) |
* GARO-based true random number generator (**TRNG**) |
* custom functions units (**CFU0** and **CFU1**) for tightly-coupled custom co-processors |
* system configuration information memory to check hardware configuration by software (**SYSINFO**, mandatory - not *optional*) |
|
### NEORV32 CPU Features |
|
216,41 → 223,41
### NEORV32 CPU |
|
This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on |
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing |
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing |
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration |
of the CPU's generics is assumed (for example no PMP). No constraints were used at all. |
|
Results generated for hardware version `1.4.4.8`. |
Results generated for hardware version `1.4.7.0`. |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max | |
|:---------------------------------------|:----------:|:--------:|:-----------:|:----:|:--------:| |
| `rv32i` | 983 | 438 | 2048 | 0 | ~120 MHz | |
| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1877 | 802 | 2048 | 0 | ~112 MHz | |
| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2374 | 1048 | 2048 | 0 | ~110 MHz | |
| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2650 | 1064 | 2048 | 0 | ~110 MHz | |
| `rv32emc` + `u` + `Zicsr` + `Zifencei` | 2680 | 1061 | 1024 | 0 | ~110 MHz | |
| `rv32i` | 932 | 413 | 2048 | 0 | ~120 MHz | |
| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1800 | 815 | 2048 | 0 | ~118 MHz | |
| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2368 | 1058 | 2048 | 0 | ~117 MHz | |
| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2604 | 1073 | 2048 | 0 | ~113 MHz | |
| `rv32emc` + `u` + `Zicsr` + `Zifencei` | 2613 | 1073 | 1024 | 0 | ~113 MHz | |
|
|
### NEORV32 Processor-Internal Peripherals and Memories |
|
Results generated for hardware version `1.4.4.8`. |
Results generated for hardware version `1.4.7.0`. |
|
| Module | Description | LEs | FFs | Memory bits | DSPs | |
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:| |
| BOOT ROM | Bootloader ROM (default 4kB) | 4 | 1 | 32 768 | 0 | |
| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 | |
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 | |
| BUSSWITCH | Mux for CPU I & D interfaces | 63 | 8 | 0 | 0 | |
| CFU0 | Custom functions unit 0 | - | - | - | - | |
| CFU1 | Custom functions unit 1 | - | - | - | - | |
| DMEM | Processor-internal data memory (default 8kB) | 13 | 2 | 65 536 | 0 | |
| DMEM | Processor-internal data memory (default 8kB) | 12 | 2 | 65 536 | 0 | |
| GPIO | General purpose input/output ports | 66 | 65 | 0 | 0 | |
| IMEM | Processor-internal instruction memory (default 16kb) | 7 | 2 | 131 072 | 0 | |
| MTIME | Machine system timer | 268 | 166 | 0 | 0 | |
| MTIME | Machine system timer | 272 | 166 | 0 | 0 | |
| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 | |
| SPI | Serial peripheral interface | 184 | 125 | 0 | 0 | |
| SPI | Serial peripheral interface | 142 | 124 | 0 | 0 | |
| SYSINFO | System configuration information memory | 11 | 9 | 0 | 0 | |
| TRNG | True random number generator | 132 | 105 | 0 | 0 | |
| TWI | Two-wire interface | 74 | 44 | 0 | 0 | |
| UART | Universal asynchronous receiver/transmitter | 175 | 132 | 0 | 0 | |
| TWI | Two-wire interface | 77 | 44 | 0 | 0 | |
| UART | Universal asynchronous receiver/transmitter | 173 | 132 | 0 | 0 | |
| WDT | Watchdog timer | 58 | 45 | 0 | 0 | |
| WISHBONE | External memory interface | 106 | 104 | 0 | 0 | |
|
262,13 → 269,13
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals |
to FPGA pins - except for the Wishbone bus and the interrupt signals. |
|
Results generated for hardware version `1.4.4.8`. |
Results generated for hardware version `1.4.7.0`. |
|
| Vendor | FPGA | Board | Toolchain | Strategy | CPU Configuration | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency | |
|:--------|:----------------------------------|:-----------------|:---------------------------|:-------- |:-----------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|--------------:| |
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 4008 (18%) | 1849 (9%) | 0 (0%) | 231424 (38%) | - | - | 105 MHz | |
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | default | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4296 (81%) | 1611 (30%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.5 MHz | |
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2390 (11%) | 1888 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz | |
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | balanced | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 3892 (17%) | 1859 (8%) | 0 (0%) | 231424 (38%) | - | - | 113 MHz | |
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | default | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4331 (82%) | 1673 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.5 MHz | |
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2416 (12%) | 1900 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz | |
|
**_Notes_** |
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb). |
288,7 → 295,7
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark |
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC. |
|
Results generated for hardware version `1.4.5.4`. |
Results generated for hardware version `1.4.7.0`. |
|
~~~ |
**Configuration** |
301,11 → 308,11
|
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz | |
|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:| |
| `rv32i` | 26 940 bytes | `-O3` | 33.89 | **0.3389** | |
| `rv32im` | 25 772 bytes | `-O3` | 64.51 | **0.6451** | |
| `rv32imc` | 20 524 bytes | `-O3` | 64.51 | **0.6451** | |
| `rv32imc` + `FAST_MUL_EN` | 20 524 bytes | `-O3` | 80.00 | **0.8000** | |
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 20 524 bytes | `-O3` | 83.33 | **0.8333** | |
| `rv32i` | 27 424 bytes | `-O3` | 35.71 | **0.3571** | |
| `rv32im` | 26 232 bytes | `-O3` | 66.66 | **0.6666** | |
| `rv32imc` | 20 876 bytes | `-O3` | 66.66 | **0.6666** | |
| `rv32imc` + `FAST_MUL_EN` | 20 876 bytes | `-O3` | 83.33 | **0.8333** | |
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 20 876 bytes | `-O3` | 86.96 | **0.8696** | |
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration |
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic). |
328,15 → 335,15
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs) |
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`. |
|
Results generated for hardware version `1.4.5.4`. |
Results generated for hardware version `1.4.7.0`. |
|
| CPU | Required Clock Cycles | Executed Instructions | Average CPI | |
|:--------------------------------------------|----------------------:|----------------------:|:-----------:| |
| `rv32i` | 5 945 938 586 | 1 469 587 406 | **4.05** | |
| `rv32im` | 3 110 282 586 | 602 225 760 | **5.16** | |
| `rv32imc` | 3 172 969 968 | 615 388 890 | **5.16** | |
| `rv32imc` + `FAST_MUL_EN` | 2 590 417 968 | 615 388 890 | **4.21** | |
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 456 318 408 | 615 388 890 | **3.99** | |
| `rv32i` | 5 648 997 774 | 1 469 233 238 | **3.84** | |
| `rv32im` | 3 036 749 774 | 601 871 338 | **5.05** | |
| `rv32imc` | 3 036 959 882 | 615 034 616 | **4.94** | |
| `rv32imc` + `FAST_MUL_EN` | 2 454 407 882 | 615 034 588 | **3.99** | |
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 320 308 322 | 615 034 676 | **3.77** | |
|
|
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration |
500,8 → 507,8
``` |
<< NEORV32 Bootloader >> |
|
BLDV: Jul 6 2020 |
HWV: 1.0.1.0 |
BLDV: Nov 7 2020 |
HWV: 0x01040606 |
CLK: 0x0134FD90 Hz |
USER: 0x0001CE40 |
MISA: 0x42801104 |
550,7 → 557,7
This project is released under the BSD 3-Clause license. No copyright infringement intended. |
Other implied or used projects might have different licensing - see their documentation to get more information. |
|
#### Citation |
#### Citing |
|
If you are using the NEORV32 or some parts of the project in some kind of publication, please cite it as follows: |
|
623,6 → 630,6
|
-------- |
|
This repository was created on June 23th, 2020. |
This repository was created on June 23rd, 2020. |
|
Made with :coffee: in Hannover, Germany :eu: |