URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk
- from Rev 38 to Rev 39
- ↔ Reverse comparison
Rev 38 → Rev 39
/.ci/sw_check.sh
26,9 → 26,9
make -C $srcdir_bootloader clean_all info bootloader |
|
# Compile and install test application |
# Redirect UART TX to text.iosimulation_output via <UART_SIM_MODE> user flag |
echo "Compiling and installing test application" |
make -C $test_app_dir clean_all USER_FLAGS+=-DRUN_CPUTEST USER_FLAGS+=-DUART_SIM_MODE MARCH=-march=rv32imc info all |
# Redirect UART TX to text.io simulation output via <UART_SIM_MODE> user flag |
echo "Compiling and installing CPU (/Processor) test application" |
make -C $test_app_dir clean_all USER_FLAGS+=-DRUN_CPUTEST USER_FLAGS+=-DUART_SIM_MODE MARCH=-march=rv32imac info all |
|
# Verification reference string |
touch $homedir/check_reference.out |
/docs/figures/neorv32_cpu.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
docs/figures/neorv32_cpu.png
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: docs/NEORV32.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: rtl/core/neorv32_application_image.vhd
===================================================================
--- rtl/core/neorv32_application_image.vhd (revision 38)
+++ rtl/core/neorv32_application_image.vhd (revision 39)
@@ -1,5 +1,5 @@
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32
--- Auto-generated memory init file (for APPLICATION) from source file
+-- Auto-generated memory init file (for APPLICATION) from source file
library ieee;
use ieee.std_logic_1164.all;
@@ -6,7 +6,7 @@
package neorv32_application_image is
- type application_init_image_t is array (0 to 3656) of std_ulogic_vector(31 downto 0);
+ type application_init_image_t is array (0 to 783) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
@@ -35,3635 +35,762 @@
00000024 => x"00000e93",
00000025 => x"00000f13",
00000026 => x"00000f93",
- 00000027 => x"05136509",
- 00000028 => x"10738005",
- 00000029 => x"10733005",
- 00000030 => x"21173040",
- 00000031 => x"01138000",
- 00000032 => x"7113f821",
- 00000033 => x"0413ffc1",
- 00000034 => x"01970001",
- 00000035 => x"81938000",
- 00000036 => x"05977761",
- 00000037 => x"85930000",
- 00000038 => x"907306a5",
- 00000039 => x"05933055",
- 00000040 => x"a023f800",
- 00000041 => x"05910005",
- 00000042 => x"feb01de3",
- 00000043 => x"81818593",
- 00000044 => x"86418613",
- 00000045 => x"00c5d663",
- 00000046 => x"00058023",
- 00000047 => x"bfdd0585",
- 00000048 => x"00004597",
- 00000049 => x"84858593",
- 00000050 => x"80000617",
- 00000051 => x"f3860613",
- 00000052 => x"81818693",
- 00000053 => x"00d65963",
- 00000054 => x"00058703",
- 00000055 => x"00e60023",
- 00000056 => x"06050585",
- 00000057 => x"0513bfc5",
- 00000058 => x"05930000",
- 00000059 => x"00ef0000",
- 00000060 => x"707304a0",
- 00000061 => x"00733004",
- 00000062 => x"a0011050",
- 00000063 => x"c0221161",
- 00000064 => x"2473c226",
- 00000065 => x"43633420",
- 00000066 => x"24730204",
- 00000067 => x"14833410",
- 00000068 => x"888d0004",
- 00000069 => x"10730409",
- 00000070 => x"04133414",
- 00000071 => x"17630030",
- 00000072 => x"24730094",
- 00000073 => x"04093410",
- 00000074 => x"34141073",
- 00000075 => x"44124482",
- 00000076 => x"00730121",
- 00000077 => x"00003020",
- 00000078 => x"45017139",
- 00000079 => x"de064581",
- 00000080 => x"d64edc22",
- 00000081 => x"d84ada26",
- 00000082 => x"d256d452",
- 00000083 => x"ce5ed05a",
- 00000084 => x"10efcc62",
- 00000085 => x"450153f0",
- 00000086 => x"10ef4581",
- 00000087 => x"65155230",
- 00000088 => x"45814601",
- 00000089 => x"b0050513",
- 00000090 => x"2ad010ef",
- 00000091 => x"45814501",
- 00000092 => x"1a9010ef",
- 00000093 => x"557d55fd",
- 00000094 => x"1e5010ef",
- 00000095 => x"05136509",
- 00000096 => x"10ef0205",
- 00000097 => x"65093330",
- 00000098 => x"04050513",
- 00000099 => x"329010ef",
- 00000100 => x"05136509",
- 00000101 => x"69850605",
- 00000102 => x"31d010ef",
- 00000103 => x"141010ef",
- 00000104 => x"149010ef",
- 00000105 => x"400010ef",
- 00000106 => x"2c8010ef",
- 00000107 => x"04498593",
- 00000108 => x"10ef4501",
- 00000109 => x"842a3220",
- 00000110 => x"04498593",
- 00000111 => x"10ef4505",
- 00000112 => x"87aa3160",
- 00000113 => x"04498593",
- 00000114 => x"943e4509",
- 00000115 => x"308010ef",
- 00000116 => x"859387aa",
- 00000117 => x"450d0449",
- 00000118 => x"10ef943e",
- 00000119 => x"87aa2fa0",
- 00000120 => x"04498593",
- 00000121 => x"943e4511",
- 00000122 => x"2ec010ef",
- 00000123 => x"859387aa",
- 00000124 => x"45150449",
- 00000125 => x"10ef943e",
- 00000126 => x"87aa2de0",
- 00000127 => x"04498593",
- 00000128 => x"943e4519",
- 00000129 => x"2d0010ef",
- 00000130 => x"859387aa",
- 00000131 => x"451d0449",
- 00000132 => x"10ef943e",
- 00000133 => x"87aa2c20",
- 00000134 => x"04498593",
- 00000135 => x"943e4521",
- 00000136 => x"2b4010ef",
- 00000137 => x"859387aa",
- 00000138 => x"45290449",
- 00000139 => x"10ef943e",
- 00000140 => x"87aa2a60",
- 00000141 => x"04498593",
- 00000142 => x"943e4525",
- 00000143 => x"298010ef",
- 00000144 => x"859387aa",
- 00000145 => x"45290449",
- 00000146 => x"10ef943e",
- 00000147 => x"87aa28a0",
- 00000148 => x"04498593",
- 00000149 => x"943e4531",
- 00000150 => x"27c010ef",
- 00000151 => x"859387aa",
- 00000152 => x"45350449",
- 00000153 => x"10ef943e",
- 00000154 => x"87aa26e0",
- 00000155 => x"04498593",
- 00000156 => x"943e4539",
- 00000157 => x"260010ef",
- 00000158 => x"859387aa",
- 00000159 => x"453d0449",
- 00000160 => x"10ef943e",
- 00000161 => x"05b32520",
- 00000162 => x"996300a4",
- 00000163 => x"450d1005",
- 00000164 => x"3bd010ef",
- 00000165 => x"451d842a",
- 00000166 => x"3b5010ef",
- 00000167 => x"452d87aa",
- 00000168 => x"10ef943e",
- 00000169 => x"87aa3ab0",
- 00000170 => x"943e4541",
- 00000171 => x"3a1010ef",
- 00000172 => x"454587aa",
- 00000173 => x"10ef943e",
- 00000174 => x"87aa3970",
- 00000175 => x"943e4549",
- 00000176 => x"38d010ef",
- 00000177 => x"454d85aa",
- 00000178 => x"10ef942e",
- 00000179 => x"942a3830",
- 00000180 => x"6509e055",
- 00000181 => x"10050513",
- 00000182 => x"1dd010ef",
- 00000183 => x"30046073",
- 00000184 => x"34241073",
- 00000185 => x"82018913",
- 00000186 => x"00092583",
- 00000187 => x"05136509",
- 00000188 => x"10ef1185",
- 00000189 => x"2b831c30",
- 00000190 => x"6785fa00",
- 00000191 => x"00fbfbb3",
- 00000192 => x"0a0b9463",
- 00000193 => x"00092783",
- 00000194 => x"05136509",
- 00000195 => x"07851145",
- 00000196 => x"800004b7",
- 00000197 => x"20236a19",
- 00000198 => x"849300f9",
- 00000199 => x"10ef0004",
- 00000200 => x"44011970",
- 00000201 => x"0a134b01",
- 00000202 => x"6c09073a",
- 00000203 => x"a0296a85",
- 00000204 => x"0b630405",
- 00000205 => x"00010354",
- 00000206 => x"342b1073",
- 00000207 => x"01441793",
- 00000208 => x"0147e7b3",
- 00000209 => x"100fc09c",
- 00000210 => x"80e70000",
- 00000211 => x"27f30004",
- 00000212 => x"fff93420",
- 00000213 => x"051385a2",
- 00000214 => x"0405138c",
- 00000215 => x"159010ef",
- 00000216 => x"1be30b85",
- 00000217 => x"0001fd54",
- 00000218 => x"280b88e3",
- 00000219 => x"4e9000ef",
- 00000220 => x"0001a091",
- 00000221 => x"85a26509",
- 00000222 => x"0e850513",
- 00000223 => x"139010ef",
- 00000224 => x"546250f2",
- 00000225 => x"594254d2",
- 00000226 => x"5a2259b2",
- 00000227 => x"5b025a92",
- 00000228 => x"4c624bf2",
- 00000229 => x"61214501",
- 00000230 => x"00018082",
- 00000231 => x"05136509",
- 00000232 => x"10ef0cc5",
- 00000233 => x"bfe91130",
- 00000234 => x"05136509",
- 00000235 => x"10ef1445",
- 00000236 => x"00011070",
- 00000237 => x"90734781",
- 00000238 => x"25833427",
- 00000239 => x"65090009",
- 00000240 => x"16850513",
- 00000241 => x"0f1010ef",
- 00000242 => x"72c010ef",
- 00000243 => x"380502e3",
- 00000244 => x"00092703",
- 00000245 => x"012347b7",
- 00000246 => x"56778793",
- 00000247 => x"20230705",
- 00000248 => x"373700e9",
- 00000249 => x"20237654",
- 00000250 => x"0713fcf0",
- 00000251 => x"b6b72107",
- 00000252 => x"2223abcd",
- 00000253 => x"8693fce0",
- 00000254 => x"0637bcd6",
- 00000255 => x"2423ffab",
- 00000256 => x"0613fcd0",
- 00000257 => x"2623faa6",
- 00000258 => x"2583fcc0",
- 00000259 => x"9b63fc00",
- 00000260 => x"278300f5",
- 00000261 => x"9763fc40",
- 00000262 => x"278300e7",
- 00000263 => x"89e3fc80",
- 00000264 => x"00013cd7",
- 00000265 => x"455000ef",
- 00000266 => x"90734781",
- 00000267 => x"25833427",
- 00000268 => x"65090009",
- 00000269 => x"1a850513",
- 00000270 => x"07d010ef",
- 00000271 => x"6c4010ef",
- 00000272 => x"320508e3",
- 00000273 => x"00092703",
- 00000274 => x"223347b7",
- 00000275 => x"45578793",
- 00000276 => x"20230705",
- 00000277 => x"373700e9",
- 00000278 => x"28234478",
- 00000279 => x"0713fcf0",
- 00000280 => x"c6b79317",
- 00000281 => x"2a23ddaa",
- 00000282 => x"8693fce0",
- 00000283 => x"d637bff6",
- 00000284 => x"2c23a0b0",
- 00000285 => x"0613fcd0",
- 00000286 => x"2e230c06",
- 00000287 => x"2583fcc0",
- 00000288 => x"9b63fd00",
- 00000289 => x"278300f5",
- 00000290 => x"9763fd40",
- 00000291 => x"278300e7",
- 00000292 => x"8be3fd80",
- 00000293 => x"000136d7",
- 00000294 => x"3e1000ef",
- 00000295 => x"90734781",
- 00000296 => x"25833427",
- 00000297 => x"65090009",
- 00000298 => x"1e850513",
- 00000299 => x"009010ef",
- 00000300 => x"c00027f3",
- 00000301 => x"f0002023",
- 00000302 => x"c00025f3",
- 00000303 => x"00018d9d",
- 00000304 => x"342027f3",
- 00000305 => x"6509dff5",
- 00000306 => x"05138189",
- 00000307 => x"10ef2105",
- 00000308 => x"47817e60",
- 00000309 => x"34279073",
- 00000310 => x"00092583",
- 00000311 => x"06376509",
- 00000312 => x"0513f000",
- 00000313 => x"10ef21c5",
- 00000314 => x"27837ce0",
- 00000315 => x"6705fa00",
- 00000316 => x"87e38ff9",
- 00000317 => x"27832607",
- 00000318 => x"8b89fe80",
- 00000319 => x"100782e3",
- 00000320 => x"00092703",
- 00000321 => x"800007b7",
- 00000322 => x"00878793",
- 00000323 => x"43d44390",
- 00000324 => x"00170793",
- 00000325 => x"00f92023",
- 00000326 => x"f00007b7",
- 00000327 => x"c3d4c390",
- 00000328 => x"000780e7",
- 00000329 => x"342027f3",
- 00000330 => x"2773e791",
- 00000331 => x"47bd3400",
- 00000332 => x"2ef70ce3",
- 00000333 => x"345000ef",
- 00000334 => x"00092583",
- 00000335 => x"05136509",
- 00000336 => x"10ef29c5",
- 00000337 => x"27837720",
- 00000338 => x"07850009",
- 00000339 => x"00f92023",
- 00000340 => x"155010ef",
- 00000341 => x"84ae842a",
- 00000342 => x"5e0010ef",
- 00000343 => x"408507b3",
- 00000344 => x"00f53533",
- 00000345 => x"95e38d85",
- 00000346 => x"67050ca5",
- 00000347 => x"0ce7f2e3",
- 00000348 => x"2e5000ef",
- 00000349 => x"90734781",
- 00000350 => x"25833427",
- 00000351 => x"65090009",
- 00000352 => x"2c850513",
- 00000353 => x"730010ef",
- 00000354 => x"00092783",
- 00000355 => x"20230785",
- 00000356 => x"000f00f9",
- 00000357 => x"27f30ff0",
- 00000358 => x"87e33420",
- 00000359 => x"00ef0807",
- 00000360 => x"00012db0",
- 00000361 => x"10734401",
- 00000362 => x"25833424",
- 00000363 => x"65090009",
- 00000364 => x"2e850513",
- 00000365 => x"700010ef",
- 00000366 => x"0000100f",
- 00000367 => x"34202773",
- 00000368 => x"05e34789",
- 00000369 => x"27831ef7",
- 00000370 => x"07850009",
- 00000371 => x"00f92023",
- 00000372 => x"34241073",
- 00000373 => x"0000100f",
- 00000374 => x"342027f3",
- 00000375 => x"0c0792e3",
- 00000376 => x"275000ef",
- 00000377 => x"90734781",
- 00000378 => x"25833427",
- 00000379 => x"65090009",
- 00000380 => x"32450513",
- 00000381 => x"6c0010ef",
- 00000382 => x"00092783",
- 00000383 => x"20230785",
- 00000384 => x"27f300f9",
- 00000385 => x"2773fff0",
- 00000386 => x"47893420",
- 00000387 => x"0af702e3",
- 00000388 => x"269000ef",
- 00000389 => x"10734401",
- 00000390 => x"25833424",
- 00000391 => x"65090009",
- 00000392 => x"34c50513",
- 00000393 => x"690010ef",
- 00000394 => x"00092783",
- 00000395 => x"20230785",
- 00000396 => x"107300f9",
- 00000397 => x"2773c014",
- 00000398 => x"47893420",
- 00000399 => x"06f70ee3",
- 00000400 => x"239000ef",
- 00000401 => x"90734781",
- 00000402 => x"25833427",
- 00000403 => x"65090009",
- 00000404 => x"37c50513",
- 00000405 => x"660010ef",
- 00000406 => x"00092783",
- 00000407 => x"20230785",
- 00000408 => x"207300f9",
- 00000409 => x"27f3c010",
- 00000410 => x"9b633420",
- 00000411 => x"00ef7a07",
- 00000412 => x"00011e70",
- 00000413 => x"90734781",
- 00000414 => x"25833427",
- 00000415 => x"65090009",
- 00000416 => x"3b850513",
- 00000417 => x"630010ef",
- 00000418 => x"301027f3",
- 00000419 => x"9fe38b91",
- 00000420 => x"27830807",
- 00000421 => x"07850009",
- 00000422 => x"00f92023",
- 00000423 => x"97824789",
- 00000424 => x"342027f3",
- 00000425 => x"040796e3",
- 00000426 => x"05136509",
- 00000427 => x"10ef3f05",
- 00000428 => x"8a136060",
- 00000429 => x"278381c1",
- 00000430 => x"8493000a",
- 00000431 => x"07858181",
- 00000432 => x"00fa2023",
- 00000433 => x"90734781",
- 00000434 => x"25833427",
- 00000435 => x"65090009",
- 00000436 => x"43050513",
- 00000437 => x"5e0010ef",
- 00000438 => x"00092783",
- 00000439 => x"20230785",
- 00000440 => x"079300f9",
- 00000441 => x"9782f000",
- 00000442 => x"34202773",
- 00000443 => x"0d634785",
- 00000444 => x"00ef7ef7",
- 00000445 => x"00011870",
- 00000446 => x"90734781",
- 00000447 => x"25833427",
- 00000448 => x"65090009",
- 00000449 => x"46850513",
- 00000450 => x"5ac010ef",
- 00000451 => x"00092783",
- 00000452 => x"20230785",
- 00000453 => x"107300f9",
- 00000454 => x"2773fff0",
- 00000455 => x"47893420",
- 00000456 => x"00f71a63",
- 00000457 => x"34302773",
- 00000458 => x"fff017b7",
- 00000459 => x"07378793",
- 00000460 => x"08f706e3",
- 00000461 => x"145000ef",
- 00000462 => x"90734781",
- 00000463 => x"25833427",
- 00000464 => x"65090009",
- 00000465 => x"49c50513",
- 00000466 => x"56c010ef",
- 00000467 => x"301027f3",
- 00000468 => x"85638b91",
- 00000469 => x"27837c07",
- 00000470 => x"07850009",
- 00000471 => x"00f92023",
- 00000472 => x"81018793",
- 00000473 => x"000780e7",
- 00000474 => x"34202773",
- 00000475 => x"05e34789",
- 00000476 => x"00ef02f7",
- 00000477 => x"00011070",
- 00000478 => x"90734781",
- 00000479 => x"25833427",
- 00000480 => x"65090009",
- 00000481 => x"50850513",
- 00000482 => x"52c010ef",
- 00000483 => x"00092783",
- 00000484 => x"20230785",
- 00000485 => x"900200f9",
- 00000486 => x"34202773",
- 00000487 => x"0163478d",
- 00000488 => x"00ef74f7",
- 00000489 => x"00010d70",
- 00000490 => x"90734781",
- 00000491 => x"25833427",
- 00000492 => x"65090009",
- 00000493 => x"53850513",
- 00000494 => x"4fc010ef",
- 00000495 => x"00092783",
- 00000496 => x"20230785",
- 00000497 => x"200300f9",
- 00000498 => x"27730020",
- 00000499 => x"47913420",
- 00000500 => x"70f70463",
- 00000501 => x"0a5000ef",
- 00000502 => x"90734781",
- 00000503 => x"25833427",
- 00000504 => x"65090009",
- 00000505 => x"57050513",
- 00000506 => x"4cc010ef",
- 00000507 => x"00092783",
- 00000508 => x"20230785",
- 00000509 => x"278300f9",
- 00000510 => x"c63ef000",
- 00000511 => x"34202773",
- 00000512 => x"07634795",
- 00000513 => x"00ef6cf7",
- 00000514 => x"00010730",
- 00000515 => x"90734781",
- 00000516 => x"25833427",
- 00000517 => x"65090009",
- 00000518 => x"5a050513",
- 00000519 => x"498010ef",
- 00000520 => x"00092783",
- 00000521 => x"20230785",
- 00000522 => x"212300f9",
- 00000523 => x"27730000",
- 00000524 => x"47993420",
- 00000525 => x"68f70a63",
- 00000526 => x"041000ef",
- 00000527 => x"90734781",
- 00000528 => x"25833427",
- 00000529 => x"65090009",
- 00000530 => x"5d850513",
- 00000531 => x"468010ef",
- 00000532 => x"00092783",
- 00000533 => x"20230785",
- 00000534 => x"202300f9",
- 00000535 => x"2773f000",
- 00000536 => x"479d3420",
- 00000537 => x"64f70e63",
- 00000538 => x"011000ef",
- 00000539 => x"90734781",
- 00000540 => x"25833427",
- 00000541 => x"65090009",
- 00000542 => x"60850513",
- 00000543 => x"438010ef",
- 00000544 => x"00092783",
- 00000545 => x"20230785",
- 00000546 => x"007300f9",
- 00000547 => x"27730000",
- 00000548 => x"47ad3420",
- 00000549 => x"60f70a63",
- 00000550 => x"7e0000ef",
- 00000551 => x"90734781",
- 00000552 => x"25833427",
- 00000553 => x"65090009",
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+ 00000439 => x"00049e63",
+ 00000440 => x"00c12083",
+ 00000441 => x"00812403",
+ 00000442 => x"00412483",
+ 00000443 => x"00012903",
+ 00000444 => x"01010113",
+ 00000445 => x"00008067",
+ 00000446 => x"01249663",
+ 00000447 => x"00d00513",
+ 00000448 => x"fa9ff0ef",
+ 00000449 => x"00048513",
+ 00000450 => x"fa1ff0ef",
+ 00000451 => x"fc9ff06f",
+ 00000452 => x"ff010113",
+ 00000453 => x"c80026f3",
+ 00000454 => x"c0002773",
+ 00000455 => x"c80027f3",
+ 00000456 => x"fed79ae3",
+ 00000457 => x"00e12023",
+ 00000458 => x"00f12223",
+ 00000459 => x"00012503",
+ 00000460 => x"00412583",
+ 00000461 => x"01010113",
+ 00000462 => x"00008067",
+ 00000463 => x"fe010113",
+ 00000464 => x"00112e23",
+ 00000465 => x"00812c23",
+ 00000466 => x"00912a23",
+ 00000467 => x"00a12623",
+ 00000468 => x"fc1ff0ef",
+ 00000469 => x"00050493",
+ 00000470 => x"fe002503",
+ 00000471 => x"00058413",
+ 00000472 => x"3e800593",
+ 00000473 => x"0f8000ef",
+ 00000474 => x"00c12603",
+ 00000475 => x"00000693",
+ 00000476 => x"00000593",
+ 00000477 => x"050000ef",
+ 00000478 => x"009504b3",
+ 00000479 => x"00a4b533",
+ 00000480 => x"00858433",
+ 00000481 => x"00850433",
+ 00000482 => x"f89ff0ef",
+ 00000483 => x"fe85eee3",
+ 00000484 => x"00b41463",
+ 00000485 => x"fe956ae3",
+ 00000486 => x"01c12083",
+ 00000487 => x"01812403",
+ 00000488 => x"01412483",
+ 00000489 => x"02010113",
+ 00000490 => x"00008067",
+ 00000491 => x"fe802503",
+ 00000492 => x"01055513",
+ 00000493 => x"00157513",
+ 00000494 => x"00008067",
+ 00000495 => x"f8a02223",
+ 00000496 => x"00008067",
+ 00000497 => x"00050313",
+ 00000498 => x"ff010113",
+ 00000499 => x"00060513",
+ 00000500 => x"00068893",
+ 00000501 => x"00112623",
+ 00000502 => x"00030613",
+ 00000503 => x"00050693",
+ 00000504 => x"00000713",
+ 00000505 => x"00000793",
+ 00000506 => x"00000813",
+ 00000507 => x"0016fe13",
+ 00000508 => x"00171e93",
+ 00000509 => x"000e0c63",
+ 00000510 => x"01060e33",
+ 00000511 => x"010e3833",
+ 00000512 => x"00e787b3",
+ 00000513 => x"00f807b3",
+ 00000514 => x"000e0813",
+ 00000515 => x"01f65713",
+ 00000516 => x"0016d693",
+ 00000517 => x"00eee733",
+ 00000518 => x"00161613",
+ 00000519 => x"fc0698e3",
+ 00000520 => x"00058663",
+ 00000521 => x"0e4000ef",
+ 00000522 => x"00a787b3",
+ 00000523 => x"00088a63",
+ 00000524 => x"00030513",
+ 00000525 => x"00088593",
+ 00000526 => x"0d0000ef",
+ 00000527 => x"00f507b3",
+ 00000528 => x"00c12083",
+ 00000529 => x"00080513",
+ 00000530 => x"00078593",
+ 00000531 => x"01010113",
+ 00000532 => x"00008067",
+ 00000533 => x"06054063",
+ 00000534 => x"0605c663",
+ 00000535 => x"00058613",
+ 00000536 => x"00050593",
+ 00000537 => x"fff00513",
+ 00000538 => x"02060c63",
+ 00000539 => x"00100693",
+ 00000540 => x"00b67a63",
+ 00000541 => x"00c05863",
+ 00000542 => x"00161613",
+ 00000543 => x"00169693",
+ 00000544 => x"feb66ae3",
+ 00000545 => x"00000513",
+ 00000546 => x"00c5e663",
+ 00000547 => x"40c585b3",
+ 00000548 => x"00d56533",
+ 00000549 => x"0016d693",
+ 00000550 => x"00165613",
+ 00000551 => x"fe0696e3",
+ 00000552 => x"00008067",
+ 00000553 => x"00008293",
+ 00000554 => x"fb5ff0ef",
+ 00000555 => x"00058513",
+ 00000556 => x"00028067",
+ 00000557 => x"40a00533",
+ 00000558 => x"00b04863",
+ 00000559 => x"40b005b3",
+ 00000560 => x"f9dff06f",
+ 00000561 => x"40b005b3",
+ 00000562 => x"00008293",
+ 00000563 => x"f91ff0ef",
+ 00000564 => x"40a00533",
+ 00000565 => x"00028067",
+ 00000566 => x"00008293",
+ 00000567 => x"0005ca63",
+ 00000568 => x"00054c63",
+ 00000569 => x"f79ff0ef",
+ 00000570 => x"00058513",
+ 00000571 => x"00028067",
+ 00000572 => x"40b005b3",
+ 00000573 => x"fe0558e3",
+ 00000574 => x"40a00533",
+ 00000575 => x"f61ff0ef",
+ 00000576 => x"40b00533",
+ 00000577 => x"00028067",
+ 00000578 => x"00050613",
+ 00000579 => x"00000513",
+ 00000580 => x"0015f693",
+ 00000581 => x"00068463",
+ 00000582 => x"00c50533",
+ 00000583 => x"0015d593",
+ 00000584 => x"00161613",
+ 00000585 => x"fe0596e3",
+ 00000586 => x"00008067",
+ 00000587 => x"6f727245",
+ 00000588 => x"4e202172",
+ 00000589 => x"5047206f",
+ 00000590 => x"75204f49",
+ 00000591 => x"2074696e",
+ 00000592 => x"746e7973",
+ 00000593 => x"69736568",
+ 00000594 => x"2164657a",
+ 00000595 => x"0000000a",
+ 00000596 => x"6e696c42",
+ 00000597 => x"676e696b",
+ 00000598 => x"44454c20",
+ 00000599 => x"6d656420",
+ 00000600 => x"7270206f",
+ 00000601 => x"6172676f",
+ 00000602 => x"00000a6d",
+ 00000603 => x"0000030c",
+ 00000604 => x"00000318",
+ 00000605 => x"00000324",
+ 00000606 => x"00000330",
+ 00000607 => x"0000033c",
+ 00000608 => x"00000344",
+ 00000609 => x"0000034c",
+ 00000610 => x"00000354",
+ 00000611 => x"00000278",
+ 00000612 => x"00000278",
+ 00000613 => x"00000278",
+ 00000614 => x"0000035c",
+ 00000615 => x"00000364",
+ 00000616 => x"00000278",
+ 00000617 => x"00000278",
+ 00000618 => x"00000278",
+ 00000619 => x"0000036c",
+ 00000620 => x"00000278",
+ 00000621 => x"00000278",
+ 00000622 => x"00000278",
+ 00000623 => x"00000374",
+ 00000624 => x"00000278",
+ 00000625 => x"00000278",
+ 00000626 => x"00000278",
+ 00000627 => x"00000278",
+ 00000628 => x"0000037c",
+ 00000629 => x"00000384",
+ 00000630 => x"0000038c",
+ 00000631 => x"00000394",
+ 00000632 => x"00007830",
+ 00000633 => x"4554523c",
+ 00000634 => x"0000203e",
+ 00000635 => x"74736e49",
+ 00000636 => x"74637572",
+ 00000637 => x"206e6f69",
+ 00000638 => x"72646461",
+ 00000639 => x"20737365",
+ 00000640 => x"6173696d",
+ 00000641 => x"6e67696c",
+ 00000642 => x"00006465",
+ 00000643 => x"74736e49",
+ 00000644 => x"74637572",
+ 00000645 => x"206e6f69",
+ 00000646 => x"65636361",
+ 00000647 => x"66207373",
+ 00000648 => x"746c7561",
+ 00000649 => x"00000000",
+ 00000650 => x"656c6c49",
+ 00000651 => x"206c6167",
+ 00000652 => x"74736e69",
+ 00000653 => x"74637572",
+ 00000654 => x"006e6f69",
+ 00000655 => x"61657242",
+ 00000656 => x"696f706b",
+ 00000657 => x"0000746e",
+ 00000658 => x"64616f4c",
+ 00000659 => x"64646120",
+ 00000660 => x"73736572",
+ 00000661 => x"73696d20",
+ 00000662 => x"67696c61",
+ 00000663 => x"0064656e",
+ 00000664 => x"64616f4c",
+ 00000665 => x"63636120",
+ 00000666 => x"20737365",
+ 00000667 => x"6c756166",
+ 00000668 => x"00000074",
+ 00000669 => x"726f7453",
+ 00000670 => x"64612065",
+ 00000671 => x"73657264",
+ 00000672 => x"696d2073",
+ 00000673 => x"696c6173",
+ 00000674 => x"64656e67",
+ 00000675 => x"00000000",
+ 00000676 => x"726f7453",
+ 00000677 => x"63612065",
+ 00000678 => x"73736563",
+ 00000679 => x"75616620",
+ 00000680 => x"0000746c",
+ 00000681 => x"69766e45",
+ 00000682 => x"6d6e6f72",
+ 00000683 => x"20746e65",
+ 00000684 => x"6c6c6163",
+ 00000685 => x"00000000",
+ 00000686 => x"6863614d",
+ 00000687 => x"20656e69",
+ 00000688 => x"74666f73",
+ 00000689 => x"65726177",
+ 00000690 => x"746e6920",
+ 00000691 => x"75727265",
+ 00000692 => x"00007470",
+ 00000693 => x"6863614d",
+ 00000694 => x"20656e69",
+ 00000695 => x"656d6974",
+ 00000696 => x"6e692072",
+ 00000697 => x"72726574",
+ 00000698 => x"00747075",
+ 00000699 => x"6863614d",
+ 00000700 => x"20656e69",
+ 00000701 => x"65747865",
+ 00000702 => x"6c616e72",
+ 00000703 => x"746e6920",
+ 00000704 => x"75727265",
+ 00000705 => x"00007470",
+ 00000706 => x"74736146",
+ 00000707 => x"746e6920",
+ 00000708 => x"75727265",
+ 00000709 => x"30207470",
+ 00000710 => x"00000000",
+ 00000711 => x"74736146",
+ 00000712 => x"746e6920",
+ 00000713 => x"75727265",
+ 00000714 => x"31207470",
+ 00000715 => x"00000000",
+ 00000716 => x"74736146",
+ 00000717 => x"746e6920",
+ 00000718 => x"75727265",
+ 00000719 => x"32207470",
+ 00000720 => x"00000000",
+ 00000721 => x"74736146",
+ 00000722 => x"746e6920",
+ 00000723 => x"75727265",
+ 00000724 => x"33207470",
+ 00000725 => x"00000000",
+ 00000726 => x"6e6b6e55",
+ 00000727 => x"206e776f",
+ 00000728 => x"70617274",
+ 00000729 => x"75616320",
+ 00000730 => x"203a6573",
+ 00000731 => x"00000000",
+ 00000732 => x"50204020",
+ 00000733 => x"00003d43",
+ 00000734 => x"544d202c",
+ 00000735 => x"3d4c4156",
+ 00000736 => x"00000000",
+ 00000737 => x"0000053c",
+ 00000738 => x"00000448",
+ 00000739 => x"00000448",
+ 00000740 => x"00000448",
+ 00000741 => x"00000548",
+ 00000742 => x"00000448",
+ 00000743 => x"00000448",
+ 00000744 => x"00000448",
+ 00000745 => x"00000554",
+ 00000746 => x"00000448",
+ 00000747 => x"00000448",
+ 00000748 => x"00000448",
+ 00000749 => x"00000448",
+ 00000750 => x"00000560",
+ 00000751 => x"0000056c",
+ 00000752 => x"00000578",
+ 00000753 => x"00000584",
+ 00000754 => x"00000490",
+ 00000755 => x"000004dc",
+ 00000756 => x"000004e8",
+ 00000757 => x"000004f4",
+ 00000758 => x"00000500",
+ 00000759 => x"0000050c",
+ 00000760 => x"00000518",
+ 00000761 => x"00000524",
+ 00000762 => x"00000448",
+ 00000763 => x"00000448",
+ 00000764 => x"00000448",
+ 00000765 => x"00000530",
+ 00000766 => x"4554523c",
+ 00000767 => x"4157203e",
+ 00000768 => x"4e494e52",
+ 00000769 => x"43202147",
+ 00000770 => x"43205550",
+ 00000771 => x"73205253",
+ 00000772 => x"65747379",
+ 00000773 => x"6f6e206d",
+ 00000774 => x"76612074",
+ 00000775 => x"616c6961",
+ 00000776 => x"21656c62",
+ 00000777 => x"522f3c20",
+ 00000778 => x"003e4554",
+ 00000779 => x"33323130",
+ 00000780 => x"37363534",
+ 00000781 => x"42413938",
+ 00000782 => x"46454443",
others => x"00000000"
);
/rtl/core/neorv32_bootloader_image.vhd
6,7 → 6,7
|
package neorv32_bootloader_image is |
|
type bootloader_init_image_t is array (0 to 973) of std_ulogic_vector(31 downto 0); |
type bootloader_init_image_t is array (0 to 974) of std_ulogic_vector(31 downto 0); |
constant bootloader_init_image : bootloader_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
30,7 → 30,7
00000019 => x"80010197", |
00000020 => x"7b418193", |
00000021 => x"00000597", |
00000022 => x"08058593", |
00000022 => x"09458593", |
00000023 => x"30559073", |
00000024 => x"f8000593", |
00000025 => x"0005a023", |
44,7 → 44,7
00000033 => x"00158593", |
00000034 => x"ff5ff06f", |
00000035 => x"00001597", |
00000036 => x"ea858593", |
00000036 => x"eac58593", |
00000037 => x"80010617", |
00000038 => x"f6c60613", |
00000039 => x"80010697", |
57,930 → 57,931
00000046 => x"fedff06f", |
00000047 => x"00000513", |
00000048 => x"00000593", |
00000049 => x"05c000ef", |
00000050 => x"30047073", |
00000051 => x"10500073", |
00000052 => x"0000006f", |
00000053 => x"ff810113", |
00000054 => x"00812023", |
00000055 => x"00912223", |
00000056 => x"34202473", |
00000057 => x"02044663", |
00000058 => x"34102473", |
00000059 => x"00041483", |
00000060 => x"0034f493", |
00000061 => x"00240413", |
00000062 => x"34141073", |
00000063 => x"00300413", |
00000064 => x"00941863", |
00000065 => x"34102473", |
00000049 => x"b0001073", |
00000050 => x"b8001073", |
00000051 => x"b0201073", |
00000052 => x"b8201073", |
00000053 => x"060000ef", |
00000054 => x"30047073", |
00000055 => x"00000013", |
00000056 => x"10500073", |
00000057 => x"0000006f", |
00000058 => x"ff810113", |
00000059 => x"00812023", |
00000060 => x"00912223", |
00000061 => x"34202473", |
00000062 => x"02044663", |
00000063 => x"34102473", |
00000064 => x"00041483", |
00000065 => x"0034f493", |
00000066 => x"00240413", |
00000067 => x"34141073", |
00000068 => x"00012483", |
00000069 => x"00412403", |
00000070 => x"00810113", |
00000071 => x"30200073", |
00000072 => x"fd010113", |
00000073 => x"02812423", |
00000074 => x"fe002403", |
00000075 => x"026267b7", |
00000076 => x"02112623", |
00000077 => x"02912223", |
00000078 => x"03212023", |
00000079 => x"01312e23", |
00000080 => x"01412c23", |
00000081 => x"01512a23", |
00000082 => x"01612823", |
00000083 => x"01712623", |
00000084 => x"01812423", |
00000085 => x"9ff78793", |
00000086 => x"00000693", |
00000087 => x"00000613", |
00000088 => x"00000593", |
00000089 => x"00200513", |
00000090 => x"0087f463", |
00000091 => x"00400513", |
00000092 => x"301000ef", |
00000093 => x"00005537", |
00000094 => x"00000613", |
00000095 => x"00000593", |
00000096 => x"b0050513", |
00000097 => x"1dd000ef", |
00000098 => x"195000ef", |
00000099 => x"00245793", |
00000100 => x"00a78533", |
00000101 => x"00f537b3", |
00000102 => x"00b785b3", |
00000103 => x"1ad000ef", |
00000104 => x"ffff07b7", |
00000105 => x"49478793", |
00000106 => x"30579073", |
00000107 => x"08000793", |
00000108 => x"30479073", |
00000109 => x"30046073", |
00000110 => x"00100513", |
00000111 => x"369000ef", |
00000112 => x"ffff1537", |
00000113 => x"800007b7", |
00000114 => x"e5050513", |
00000115 => x"0007a023", |
00000116 => x"249000ef", |
00000117 => x"f1302573", |
00000118 => x"24c000ef", |
00000068 => x"00300413", |
00000069 => x"00941863", |
00000070 => x"34102473", |
00000071 => x"00240413", |
00000072 => x"34141073", |
00000073 => x"00012483", |
00000074 => x"00412403", |
00000075 => x"00810113", |
00000076 => x"30200073", |
00000077 => x"800007b7", |
00000078 => x"fd010113", |
00000079 => x"0007a023", |
00000080 => x"ffff07b7", |
00000081 => x"02112623", |
00000082 => x"02812423", |
00000083 => x"02912223", |
00000084 => x"03212023", |
00000085 => x"01312e23", |
00000086 => x"01412c23", |
00000087 => x"01512a23", |
00000088 => x"01612823", |
00000089 => x"01712623", |
00000090 => x"01812423", |
00000091 => x"49878793", |
00000092 => x"30579073", |
00000093 => x"fe002403", |
00000094 => x"026267b7", |
00000095 => x"9ff78793", |
00000096 => x"00000693", |
00000097 => x"00000613", |
00000098 => x"00000593", |
00000099 => x"00200513", |
00000100 => x"0087f463", |
00000101 => x"00400513", |
00000102 => x"2dd000ef", |
00000103 => x"00100513", |
00000104 => x"389000ef", |
00000105 => x"00005537", |
00000106 => x"00000613", |
00000107 => x"00000593", |
00000108 => x"b0050513", |
00000109 => x"1b1000ef", |
00000110 => x"169000ef", |
00000111 => x"00245793", |
00000112 => x"00a78533", |
00000113 => x"00f537b3", |
00000114 => x"00b785b3", |
00000115 => x"181000ef", |
00000116 => x"08000793", |
00000117 => x"30479073", |
00000118 => x"30046073", |
00000119 => x"ffff1537", |
00000120 => x"e8850513", |
00000121 => x"235000ef", |
00000122 => x"fe002503", |
00000123 => x"238000ef", |
00000120 => x"e5450513", |
00000121 => x"239000ef", |
00000122 => x"f1302573", |
00000123 => x"23c000ef", |
00000124 => x"ffff1537", |
00000125 => x"e9050513", |
00000126 => x"221000ef", |
00000127 => x"fe402503", |
00000128 => x"224000ef", |
00000125 => x"e8c50513", |
00000126 => x"225000ef", |
00000127 => x"fe002503", |
00000128 => x"228000ef", |
00000129 => x"ffff1537", |
00000130 => x"e9c50513", |
00000131 => x"20d000ef", |
00000132 => x"30102573", |
00000133 => x"210000ef", |
00000130 => x"e9450513", |
00000131 => x"211000ef", |
00000132 => x"fe402503", |
00000133 => x"214000ef", |
00000134 => x"ffff1537", |
00000135 => x"ea450513", |
00000136 => x"1f9000ef", |
00000137 => x"fe802503", |
00000138 => x"ffff14b7", |
00000139 => x"00341413", |
00000140 => x"1f4000ef", |
00000141 => x"ffff1537", |
00000142 => x"eac50513", |
00000143 => x"1dd000ef", |
00000144 => x"ff802503", |
00000145 => x"1e0000ef", |
00000146 => x"eb448513", |
00000147 => x"1cd000ef", |
00000148 => x"ff002503", |
00000149 => x"1d0000ef", |
00000150 => x"ffff1537", |
00000151 => x"ec050513", |
00000152 => x"1b9000ef", |
00000153 => x"ffc02503", |
00000154 => x"1bc000ef", |
00000155 => x"eb448513", |
00000156 => x"1a9000ef", |
00000157 => x"ff402503", |
00000158 => x"1ac000ef", |
00000159 => x"ffff1537", |
00000160 => x"ec850513", |
00000161 => x"195000ef", |
00000162 => x"095000ef", |
00000163 => x"00a404b3", |
00000164 => x"0084b433", |
00000165 => x"00b40433", |
00000166 => x"fa402783", |
00000167 => x"0207d263", |
00000168 => x"ffff1537", |
00000169 => x"ef050513", |
00000170 => x"171000ef", |
00000171 => x"161000ef", |
00000172 => x"02300793", |
00000173 => x"02f51263", |
00000174 => x"00000513", |
00000175 => x"0180006f", |
00000176 => x"05d000ef", |
00000177 => x"fc85eae3", |
00000178 => x"00b41463", |
00000179 => x"fc9566e3", |
00000180 => x"00100513", |
00000181 => x"5b8000ef", |
00000182 => x"0b4000ef", |
00000183 => x"ffff1937", |
00000184 => x"ffff19b7", |
00000185 => x"02300a13", |
00000186 => x"07200a93", |
00000187 => x"06800b13", |
00000188 => x"07500b93", |
00000189 => x"ffff14b7", |
00000190 => x"ffff1c37", |
00000191 => x"efc90513", |
00000192 => x"119000ef", |
00000193 => x"0f9000ef", |
00000194 => x"00050413", |
00000195 => x"0e1000ef", |
00000196 => x"e0898513", |
00000197 => x"105000ef", |
00000198 => x"fb4400e3", |
00000199 => x"01541863", |
00000200 => x"ffff02b7", |
00000201 => x"00028067", |
00000202 => x"fd5ff06f", |
00000203 => x"01641663", |
00000204 => x"05c000ef", |
00000205 => x"fc9ff06f", |
00000206 => x"00000513", |
00000207 => x"03740063", |
00000208 => x"07300793", |
00000209 => x"00f41663", |
00000210 => x"658000ef", |
00000211 => x"fb1ff06f", |
00000212 => x"06c00793", |
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00000653 => x"00050493", |
00000654 => x"1b8000ef", |
00000655 => x"07900793", |
00000656 => x"0af49e63", |
00000657 => x"b59ff0ef", |
00000658 => x"00051663", |
00000659 => x"00300513", |
00000660 => x"9a1ff0ef", |
00000661 => x"ffff1537", |
00000662 => x"e4450513", |
00000663 => x"01045493", |
00000664 => x"1bc000ef", |
00000665 => x"00148493", |
00000666 => x"00800937", |
00000667 => x"fff00993", |
00000668 => x"00010a37", |
00000669 => x"fff48493", |
00000670 => x"07349063", |
00000671 => x"4788d5b7", |
00000672 => x"afe58593", |
00000673 => x"00800537", |
00000674 => x"e81ff0ef", |
00000675 => x"00800537", |
00000676 => x"00040593", |
00000677 => x"00450513", |
00000678 => x"e71ff0ef", |
00000679 => x"ff002a03", |
00000680 => x"008009b7", |
00000681 => x"ffc47413", |
00000682 => x"00000493", |
00000683 => x"00000913", |
00000684 => x"00c98a93", |
00000685 => x"01548533", |
00000686 => x"009a07b3", |
00000687 => x"02849663", |
00000688 => x"00898513", |
00000689 => x"412005b3", |
00000690 => x"e41ff0ef", |
00000691 => x"ffff1537", |
00000692 => x"e0850513", |
00000693 => x"f05ff06f", |
00000694 => x"00090513", |
00000695 => x"e85ff0ef", |
00000696 => x"01490933", |
00000697 => x"f91ff06f", |
00000698 => x"0007a583", |
00000699 => x"00448493", |
00000700 => x"00b90933", |
00000701 => x"e15ff0ef", |
00000702 => x"fbdff06f", |
00000703 => x"01c12083", |
00000704 => x"01812403", |
00000705 => x"01412483", |
00000706 => x"01012903", |
00000707 => x"00c12983", |
00000708 => x"00812a03", |
00000709 => x"00412a83", |
00000710 => x"02010113", |
00000711 => x"00008067", |
00000712 => x"ff010113", |
00000713 => x"f9402783", |
00000714 => x"f9002703", |
00000715 => x"f9402683", |
00000716 => x"fed79ae3", |
00000717 => x"00e12023", |
00000718 => x"00f12223", |
00000719 => x"00012503", |
00000720 => x"00412583", |
00000721 => x"01010113", |
00000722 => x"00008067", |
00000723 => x"f9800693", |
00000724 => x"fff00613", |
00000725 => x"00c6a023", |
00000726 => x"00a6a023", |
00000727 => x"00b6a223", |
00000728 => x"00008067", |
00000729 => x"fa002023", |
00000730 => x"fe002683", |
00000731 => x"00151513", |
00000732 => x"00000713", |
00000733 => x"04a6f263", |
00000734 => x"000016b7", |
00000735 => x"00000793", |
00000736 => x"ffe68693", |
00000737 => x"04e6e463", |
00000738 => x"00167613", |
00000739 => x"0015f593", |
00000740 => x"01879793", |
00000741 => x"01e61613", |
00000742 => x"00c7e7b3", |
00000743 => x"01d59593", |
00000744 => x"00b7e7b3", |
00000745 => x"00e7e7b3", |
00000746 => x"10000737", |
00000747 => x"00e7e7b3", |
00000748 => x"faf02023", |
00000749 => x"00008067", |
00000750 => x"00170793", |
00000751 => x"01079713", |
00000752 => x"40a686b3", |
00000753 => x"01075713", |
00000754 => x"fadff06f", |
00000755 => x"ffe78513", |
00000756 => x"0fd57513", |
00000757 => x"00051a63", |
00000758 => x"00375713", |
00000759 => x"00178793", |
00000760 => x"0ff7f793", |
00000761 => x"fa1ff06f", |
00000762 => x"00175713", |
00000763 => x"ff1ff06f", |
00000764 => x"fa002783", |
00000765 => x"fe07cee3", |
00000766 => x"faa02223", |
00000767 => x"00008067", |
00000768 => x"fa402503", |
00000769 => x"fe055ee3", |
00000770 => x"0ff57513", |
00000771 => x"00008067", |
00000772 => x"fa402503", |
00000773 => x"0ff57513", |
00000774 => x"00008067", |
00000775 => x"ff010113", |
00000776 => x"00812423", |
00000777 => x"01212023", |
00000778 => x"00112623", |
00000779 => x"00912223", |
00000780 => x"00050413", |
00000781 => x"00a00913", |
00000782 => x"00044483", |
00000783 => x"00140413", |
00000784 => x"00049e63", |
00000785 => x"00c12083", |
00000786 => x"00812403", |
00000787 => x"00412483", |
00000788 => x"00012903", |
00000789 => x"01010113", |
00000790 => x"00008067", |
00000791 => x"01249663", |
00000792 => x"00d00513", |
00000793 => x"f8dff0ef", |
00000794 => x"00048513", |
00000795 => x"f85ff0ef", |
00000796 => x"fc9ff06f", |
00000797 => x"00757513", |
00000798 => x"0016f793", |
00000799 => x"00367613", |
00000800 => x"00a51513", |
00000801 => x"00f79793", |
00000802 => x"0015f593", |
00000803 => x"00f567b3", |
00000804 => x"00d61613", |
00000805 => x"00c7e7b3", |
00000806 => x"00959593", |
00000807 => x"fa800713", |
00000808 => x"00b7e7b3", |
00000809 => x"00072023", |
00000810 => x"1007e793", |
00000811 => x"00f72023", |
00000812 => x"00008067", |
00000813 => x"fa800713", |
00000814 => x"00072683", |
00000815 => x"00757793", |
00000816 => x"00100513", |
00000817 => x"00f51533", |
00000818 => x"00d56533", |
00000819 => x"00a72023", |
00000820 => x"00008067", |
00000821 => x"fa800713", |
00000822 => x"00072683", |
00000823 => x"00757513", |
00000824 => x"00100793", |
00000825 => x"00a797b3", |
00000826 => x"fff7c793", |
00000827 => x"00d7f7b3", |
00000828 => x"00f72023", |
00000829 => x"00008067", |
00000830 => x"faa02623", |
00000831 => x"fa802783", |
00000832 => x"fe07cee3", |
00000833 => x"fac02503", |
00000834 => x"00008067", |
00000835 => x"f8400713", |
00000836 => x"00072683", |
00000837 => x"00100793", |
00000838 => x"00a797b3", |
00000839 => x"00d7c7b3", |
00000840 => x"00f72023", |
00000841 => x"00008067", |
00000842 => x"f8a02223", |
00000843 => x"00008067", |
00000844 => x"69617641", |
00000845 => x"6c62616c", |
00000846 => x"4d432065", |
00000847 => x"0a3a7344", |
00000848 => x"203a6820", |
00000849 => x"706c6548", |
00000850 => x"3a72200a", |
00000851 => x"73655220", |
00000852 => x"74726174", |
00000853 => x"3a75200a", |
00000854 => x"6c705520", |
00000855 => x"0a64616f", |
00000856 => x"203a7320", |
00000857 => x"726f7453", |
00000858 => x"6f742065", |
00000859 => x"616c6620", |
00000860 => x"200a6873", |
00000861 => x"4c203a6c", |
00000862 => x"2064616f", |
00000863 => x"6d6f7266", |
00000864 => x"616c6620", |
00000865 => x"200a6873", |
00000866 => x"45203a65", |
00000867 => x"75636578", |
00000868 => x"00006574", |
00000869 => x"65206f4e", |
00000870 => x"75636578", |
00000871 => x"6c626174", |
00000872 => x"76612065", |
00000873 => x"616c6961", |
00000874 => x"2e656c62", |
00000875 => x"00000000", |
00000876 => x"746f6f42", |
00000877 => x"2e676e69", |
00000878 => x"0a0a2e2e", |
00000879 => x"00000000", |
00000880 => x"52450a07", |
00000881 => x"5f524f52", |
00000882 => x"00000000", |
00000883 => x"58450a0a", |
00000884 => x"00282043", |
00000885 => x"20402029", |
00000886 => x"00007830", |
00000887 => x"69617741", |
00000888 => x"676e6974", |
00000889 => x"6f656e20", |
00000890 => x"32337672", |
00000891 => x"6578655f", |
00000892 => x"6e69622e", |
00000893 => x"202e2e2e", |
00000894 => x"00000000", |
00000895 => x"64616f4c", |
00000896 => x"2e676e69", |
00000897 => x"00202e2e", |
00000898 => x"00004b4f", |
00000899 => x"0000000a", |
00000900 => x"74697257", |
00000901 => x"78302065", |
00000902 => x"00000000", |
00000903 => x"74796220", |
00000904 => x"74207365", |
00000905 => x"5053206f", |
00000906 => x"6c662049", |
00000907 => x"20687361", |
00000908 => x"78302040", |
00000909 => x"00000000", |
00000910 => x"7928203f", |
00000911 => x"20296e2f", |
00000912 => x"00000000", |
00000913 => x"616c460a", |
00000914 => x"6e696873", |
00000915 => x"2e2e2e67", |
00000916 => x"00000020", |
00000917 => x"0a0a0a0a", |
00000918 => x"4e203c3c", |
00000919 => x"56524f45", |
00000920 => x"42203233", |
00000921 => x"6c746f6f", |
00000922 => x"6564616f", |
00000923 => x"3e3e2072", |
00000924 => x"4c420a0a", |
00000925 => x"203a5644", |
00000926 => x"20636544", |
00000927 => x"32203320", |
00000928 => x"0a303230", |
00000929 => x"3a565748", |
00000930 => x"00002020", |
00000931 => x"4b4c430a", |
00000932 => x"0020203a", |
00000933 => x"0a7a4820", |
00000934 => x"52455355", |
00000935 => x"0000203a", |
00000936 => x"53494d0a", |
00000937 => x"00203a41", |
00000938 => x"4f52500a", |
00000939 => x"00203a43", |
00000940 => x"454d490a", |
00000941 => x"00203a4d", |
00000942 => x"74796220", |
00000943 => x"40207365", |
00000944 => x"00000020", |
00000945 => x"454d440a", |
00000946 => x"00203a4d", |
00000947 => x"75410a0a", |
00000948 => x"6f626f74", |
00000949 => x"6920746f", |
00000950 => x"7338206e", |
00000951 => x"7250202e", |
00000952 => x"20737365", |
00000953 => x"2079656b", |
00000954 => x"61206f74", |
00000955 => x"74726f62", |
00000956 => x"00000a2e", |
00000957 => x"726f6241", |
00000958 => x"2e646574", |
00000959 => x"00000a0a", |
00000960 => x"444d430a", |
00000961 => x"00203e3a", |
00000962 => x"53207962", |
00000963 => x"68706574", |
00000964 => x"4e206e61", |
00000965 => x"69746c6f", |
00000966 => x"0000676e", |
00000967 => x"61766e49", |
00000968 => x"2064696c", |
00000969 => x"00444d43", |
00000970 => x"33323130", |
00000971 => x"37363534", |
00000972 => x"42413938", |
00000973 => x"46454443", |
others => x"00000000" |
); |
|
/rtl/core/neorv32_busswitch.vhd
59,6 → 59,7
ca_bus_we_i : in std_ulogic; -- write enable |
ca_bus_re_i : in std_ulogic; -- read enable |
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction |
ca_bus_lock_i : in std_ulogic; -- locked/exclusive access |
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
ca_bus_err_o : out std_ulogic; -- bus transfer error |
-- controller interface b -- |
69,6 → 70,7
cb_bus_we_i : in std_ulogic; -- write enable |
cb_bus_re_i : in std_ulogic; -- read enable |
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction |
cb_bus_lock_i : in std_ulogic; -- locked/exclusive access |
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus -- |
80,6 → 82,7
p_bus_we_o : out std_ulogic; -- write enable |
p_bus_re_o : out std_ulogic; -- read enable |
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
p_bus_lock_o : out std_ulogic; -- locked/exclusive access |
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
p_bus_err_i : in std_ulogic -- bus transfer error |
); |
268,6 → 271,7
p_bus_cancel_o <= ca_bus_cancel_i when (arbiter.bus_sel = '0') else cb_bus_cancel_i; |
p_bus_we_o <= (p_bus_we or arbiter.we_trig); |
p_bus_re_o <= (p_bus_re or arbiter.re_trig); |
p_bus_lock_o <= ca_bus_lock_i or cb_bus_lock_i; |
|
ca_bus_rdata_o <= p_bus_rdata_i; |
cb_bus_rdata_o <= p_bus_rdata_i; |
/rtl/core/neorv32_cpu.vhd
58,6 → 58,7
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
88,6 → 89,7
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
i_bus_lock_o : out std_ulogic; -- locked/exclusive access |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
100,6 → 102,7
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
d_bus_lock_o : out std_ulogic; -- locked/exclusive access |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- interrupts (risc-v compliant) -- |
136,7 → 139,6
signal be_store : std_ulogic; -- bus error on store data access |
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch |
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction) |
signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next to-be-executed instruction) |
|
-- co-processor interface -- |
signal cp0_data, cp1_data, cp2_data, cp3_data : std_ulogic_vector(data_width_c-1 downto 0); |
163,6 → 165,8
assert not (((PMP_GRANULARITY < 1) or (PMP_GRANULARITY > 32)) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Invalid PMP granulartiy (0 < PMP_GRANULARITY < 33)." severity error; |
-- Instruction prefetch buffer size -- |
assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error; |
-- A extension - only lr.w and sc.w supported yet -- |
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports >lr.w< and >sc.w< instructions yet." severity warning; |
|
|
-- Control Unit --------------------------------------------------------------------------- |
173,6 → 177,7
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id |
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
202,7 → 207,6
imm_o => imm, -- immediate |
fetch_pc_o => fetch_pc, -- PC for instruction fetch |
curr_pc_o => curr_pc, -- current PC (corresponding to current instruction) |
next_pc_o => next_pc, -- next PC (corresponding to current instruction |
csr_rdata_o => csr_rdata, -- CSR read data |
-- interrupts (risc-v compliant) -- |
msw_irq_i => msw_irq_i, -- machine software interrupt |
240,7 → 244,6
mem_i => rdata, -- memory read data |
alu_i => alu_res, -- ALU result |
csr_i => csr_rdata, -- CSR read data |
pc_i => next_pc, -- next pc (for linking) |
-- data output -- |
rs1_o => rs1, -- operand 1 |
rs2_o => rs2 -- operand 2 |
317,12 → 320,21
end generate; |
|
|
-- Co-Processor 1: Not implemented (yet) -------------------------------------------------- |
-- Co-Processor 1: Atomic Memory Access (SC - store-conditional) -------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- control: ctrl cp1_start |
-- inputs: rs1 rs2 alu_cmp alu_opb |
cp1_data <= (others => '0'); |
cp1_valid <= '0'; |
atomic_op_cp: process(ctrl, cp1_start) |
begin |
-- "fake" co-processor for atomic operations |
-- used to get the result of a store-conditional operation into the data path |
if (CPU_EXTENSION_RISCV_A = true) and (cp1_start = '1') then |
cp1_data <= (others => '0'); |
cp1_data(0) <= not ctrl(ctrl_bus_lock_c); |
cp1_valid <= '1'; |
else |
cp1_data <= (others => '0'); |
cp1_valid <= '0'; |
end if; |
end process; |
|
|
-- Co-Processor 2: Not implemented (yet) -------------------------------------------------- |
364,7 → 376,7
ma_instr_o => ma_instr, -- misaligned instruction address |
be_instr_o => be_instr, -- bus error on instruction access |
-- cpu data access interface -- |
addr_i => alu_res, -- ALU result -> access address |
addr_i => alu_add, -- ALU.add result -> access address |
wdata_i => rs2, -- write data |
rdata_o => rdata, -- read data |
mar_o => mar, -- current memory address register |
388,6 → 400,7
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge |
i_bus_err_i => i_bus_err_i, -- bus transfer error |
i_bus_fence_o => i_bus_fence_o, -- fence operation |
i_bus_lock_o => i_bus_lock_o, -- locked/exclusive access |
-- data bus -- |
d_bus_addr_o => d_bus_addr_o, -- bus access address |
d_bus_rdata_i => d_bus_rdata_i, -- bus read data |
398,7 → 411,8
d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction |
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge |
d_bus_err_i => d_bus_err_i, -- bus transfer error |
d_bus_fence_o => d_bus_fence_o -- fence operation |
d_bus_fence_o => d_bus_fence_o, -- fence operation |
d_bus_lock_o => d_bus_lock_o -- locked/exclusive access |
); |
|
-- current privilege level -- |
/rtl/core/neorv32_cpu_alu.vhd
86,7 → 86,10
|
-- results -- |
signal addsub_res : std_ulogic_vector(data_width_c downto 0); |
-- |
signal cp_res : std_ulogic_vector(data_width_c-1 downto 0); |
signal arith_res : std_ulogic_vector(data_width_c-1 downto 0); |
signal logic_res : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- comparator -- |
signal cmp_opx : std_ulogic_vector(data_width_c downto 0); |
167,7 → 170,18
-- direct output of address result -- |
add_o <= addsub_res(data_width_c-1 downto 0); |
|
-- ALU arithmetic logic core -- |
arithmetic_core: process(ctrl_i, addsub_res) |
begin |
if (ctrl_i(ctrl_alu_arith_c) = alu_arith_cmd_addsub_c) then -- ADD/SUB |
arith_res <= addsub_res(data_width_c-1 downto 0); |
else -- SLT |
arith_res <= (others => '0'); |
arith_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow |
end if; |
end process arithmetic_core; |
|
|
-- Shifter Unit --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
shifter_unit: process(clk_i) |
276,7 → 290,7
end process shifter_unit; |
|
-- is shift operation? -- |
shifter.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0'; |
shifter.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_shift_c) else '0'; |
shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0'; |
|
-- shift operation running? -- |
294,10 → 308,10
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_M = true) then |
cp_ctrl.cmd_ff <= cp_ctrl.cmd; |
if (cp_ctrl.start = '1') then |
if ((cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i) = '1') then -- cp computation done? |
cp_ctrl.busy <= '0'; |
elsif (cp_ctrl.start = '1') then |
cp_ctrl.busy <= '1'; |
elsif ((cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i) = '1') then -- cp computation done? |
cp_ctrl.busy <= '0'; |
end if; |
else -- no co-processor(s) implemented |
cp_ctrl.cmd_ff <= '0'; |
307,34 → 321,51
end process cp_arbiter; |
|
-- is co-processor operation? -- |
cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_cp_c) else '0'; |
cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_copro_c) else '0'; |
cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0'; |
cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0'; -- CP0: MULDIV CP |
cp1_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0'; -- CP1: not implemented yet |
cp2_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0'; -- CP2: not implemented yet |
cp3_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0'; -- CP3: not implemented yet |
|
-- co-processor operation running? -- |
cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start; |
-- co-processor select -- |
cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0'; |
cp1_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0'; |
cp2_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0'; |
cp3_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0'; |
|
-- co-processor operation (still) running? -- |
cp_ctrl.halt <= (cp_ctrl.busy and (not (cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i))) or cp_ctrl.start; |
|
-- co-processor result -- |
cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0 |
cp_read_back: process(clk_i) |
begin |
if rising_edge(clk_i) then |
cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0 |
end if; |
end process cp_read_back; |
|
|
-- ALU Logic Core ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
alu_logic_core: process(ctrl_i, rs1_i, opb) |
begin |
case ctrl_i(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) is |
when alu_logic_cmd_movb_c => logic_res <= opb; -- (default) |
when alu_logic_cmd_xor_c => logic_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc) |
when alu_logic_cmd_or_c => logic_res <= rs1_i or opb; |
when alu_logic_cmd_and_c => logic_res <= rs1_i and opb; |
when others => logic_res <= opb; -- undefined |
end case; |
end process alu_logic_core; |
|
|
-- ALU Function Select -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
alu_function_mux: process(ctrl_i, rs1_i, opb, addsub_res, cp_res, shifter.sreg) |
alu_function_mux: process(ctrl_i, arith_res, logic_res, shifter.sreg, cp_res) |
begin |
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is |
when alu_cmd_xor_c => res_o <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc) |
when alu_cmd_or_c => res_o <= rs1_i or opb; |
when alu_cmd_and_c => res_o <= rs1_i and opb; |
when alu_cmd_movb_c => res_o <= opb; |
when alu_cmd_addsub_c => res_o <= addsub_res(data_width_c-1 downto 0); |
when alu_cmd_cp_c => res_o <= cp_res; |
when alu_cmd_shift_c => res_o <= shifter.sreg; |
when alu_cmd_slt_c => res_o <= (others => '0'); res_o(0) <= addsub_res(addsub_res'left); -- => carry/borrow |
when others => res_o <= opb; -- undefined |
case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is |
when alu_func_cmd_arith_c => res_o <= arith_res; -- (default) |
when alu_func_cmd_logic_c => res_o <= logic_res; |
when alu_func_cmd_shift_c => res_o <= shifter.sreg; |
when alu_func_cmd_copro_c => res_o <= cp_res; |
when others => res_o <= arith_res; -- undefined |
end case; |
end process alu_function_mux; |
|
/rtl/core/neorv32_cpu_bus.vhd
86,6 → 86,7
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- fence operation |
i_bus_lock_o : out std_ulogic; -- locked/exclusive access |
-- data bus -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
96,7 → 97,8
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic -- fence operation |
d_bus_fence_o : out std_ulogic; -- fence operation |
d_bus_lock_o : out std_ulogic -- locked/exclusive access |
); |
end neorv32_cpu_bus; |
|
165,7 → 167,7
mem_adr_reg: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then |
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then |
mar <= addr_i; |
end if; |
end if; |
199,7 → 201,7
mem_do_reg: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then |
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then |
mdo <= wdata_i; -- memory data out register (MDO) |
end if; |
end if; |
240,7 → 242,7
mem_out_buf: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then |
if (ctrl_i(ctrl_bus_mi_we_c) = '1') then |
mdi <= d_bus_rdata; -- memory data in register (MDI) |
end if; |
end if; |
272,22 → 274,59
end process read_align; |
|
|
-- Instruction Interface: Check for Misaligned Access ------------------------------------- |
-- Data Access Arbiter -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
misaligned_i_check: process(ctrl_i, fetch_pc_i) |
data_access_arbiter: process(rstn_i, clk_i) |
begin |
-- check instruction access -- |
i_misaligned <= '0'; -- default |
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses |
i_misaligned <= '0'; -- no alignment exceptions possible |
else -- 32-bit instruction accesses only |
if (fetch_pc_i(1) = '1') then -- PC(0) is always zero |
i_misaligned <= '1'; |
end if; |
if (rstn_i = '0') then |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
d_arbiter.err_align <= '0'; |
d_arbiter.err_bus <= '0'; |
d_arbiter.timeout <= (others => '0'); |
elsif rising_edge(clk_i) then |
-- data access request -- |
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle |
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c); |
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c); |
d_arbiter.err_align <= d_misaligned; |
d_arbiter.err_bus <= '0'; |
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c))); |
else -- in progress |
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1); |
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
end if; |
end if; |
end if; |
end process misaligned_i_check; |
end process data_access_arbiter; |
|
-- cancel bus access -- |
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c); |
|
-- wait for bus transaction to finish -- |
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i); |
|
-- output data access error to controller -- |
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align; |
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus; |
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align; |
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus; |
|
-- data bus (read/write)-- |
d_bus_addr_o <= mar; |
d_bus_wdata_o <= d_bus_wdata; |
d_bus_ben_o <= d_bus_ben; |
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault |
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault |
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c); |
d_bus_rdata <= d_bus_rdata_i; |
d_bus_lock_o <= ctrl_i(ctrl_bus_lock_c); |
|
|
-- Instruction Fetch Arbiter -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ifetch_arbiter: process(rstn_i, clk_i) |
335,60 → 374,14
i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault |
i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c); |
instr_o <= i_bus_rdata_i; |
i_bus_lock_o <= '0'; -- instruction fetch cannot be atomic |
|
|
-- Data Access Arbiter -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
data_access_arbiter: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
d_arbiter.err_align <= '0'; |
d_arbiter.err_bus <= '0'; |
d_arbiter.timeout <= (others => '0'); |
elsif rising_edge(clk_i) then |
-- data access request -- |
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle |
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c); |
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c); |
d_arbiter.err_align <= d_misaligned; |
d_arbiter.err_bus <= '0'; |
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c))); |
else -- in progress |
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1); |
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort |
d_arbiter.wr_req <= '0'; |
d_arbiter.rd_req <= '0'; |
end if; |
end if; |
end if; |
end process data_access_arbiter; |
-- check instruction access -- |
i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension |
'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only |
|
-- cancel bus access -- |
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c); |
|
-- wait for bus transaction to finish -- |
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i); |
|
-- output data access error to controller -- |
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align; |
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus; |
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align; |
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus; |
|
-- data bus (read/write)-- |
d_bus_addr_o <= mar; |
d_bus_wdata_o <= d_bus_wdata; |
d_bus_ben_o <= d_bus_ben; |
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault |
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault |
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c); |
d_bus_rdata <= d_bus_rdata_i; |
|
|
-- Physical Memory Protection (PMP) ------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- compute address masks -- |
401,7 → 394,7
if (i = PMP_GRANULARITY+1) then |
pmp.addr_mask(r)(i) <= '0'; |
else -- current bit = not AND(all previous bits) |
pmp.addr_mask(r)(i) <= not (and_all_f(pmp_addr_i(r)(i-1 downto PMP_GRANULARITY))); |
pmp.addr_mask(r)(i) <= not and_all_f(pmp_addr_i(r)(i-1 downto PMP_GRANULARITY)); |
end if; |
end loop; -- i |
end loop; -- r |
/rtl/core/neorv32_cpu_control.vhd
50,6 → 50,7
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
79,7 → 80,6
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction) |
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction) |
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic; -- machine software interrupt |
164,14 → 164,16
signal cmd_issue : cmd_issue_t; |
|
-- instruction execution engine -- |
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS); |
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, FENCE_OP, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS); |
type execute_engine_t is record |
state : execute_engine_state_t; |
state_prev : execute_engine_state_t; |
state_nxt : execute_engine_state_t; |
-- |
i_reg : std_ulogic_vector(31 downto 0); |
i_reg_nxt : std_ulogic_vector(31 downto 0); |
i_reg_last : std_ulogic_vector(31 downto 0); -- last executed instruction |
-- |
is_ci : std_ulogic; -- current instruction is de-compressed instruction |
is_ci_nxt : std_ulogic; |
is_jump : std_ulogic; -- current instruction is jump instruction |
178,16 → 180,18
is_jump_nxt : std_ulogic; |
is_cp_op : std_ulogic; -- current instruction is a co-processor operation |
is_cp_op_nxt : std_ulogic; |
-- |
branch_taken : std_ulogic; -- branch condition fullfilled |
pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction |
pc_nxt : std_ulogic_vector(data_width_c-1 downto 0); |
pc_mux_sel : std_ulogic_vector(1 downto 0); -- source select for PC update |
pc_we : std_ulogic; -- PC update enabled |
next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed |
last_pc : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction |
last_pc_nxt : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction |
-- |
sleep : std_ulogic; -- CPU in sleep mode |
sleep_nxt : std_ulogic; -- CPU in sleep mode |
sleep_nxt : std_ulogic; |
if_rst : std_ulogic; -- instruction fetch was reset |
if_rst_nxt : std_ulogic; -- instruction fetch was reset |
if_rst_nxt : std_ulogic; |
end record; |
signal execute_engine : execute_engine_t; |
|
214,6 → 218,16
break_point : std_ulogic; |
end record; |
signal trap_ctrl : trap_ctrl_t; |
|
-- atomic operations controller -- |
type atomic_ctrl_t is record |
env_start : std_ulogic; -- begin atomic operations |
env_end : std_ulogic; -- end atomic operations |
env_end_ff : std_ulogic; -- end atomic operations dealyed |
env_abort : std_ulogic; -- atomic operations abort (results in failure) |
lock : std_ulogic; -- lock status |
end record; |
signal atomic_ctrl : atomic_ctrl_t; |
|
-- CPU control signals -- |
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); |
331,10 → 345,9
when IFETCH_ISSUE => -- store instruction data to prefetch buffer |
-- ------------------------------------------------------------ |
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response |
fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer |
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4); |
ipb.we <= '1'; |
fetch_engine.state_nxt <= IFETCH_REQUEST; |
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4); |
ipb.we <= '1'; |
fetch_engine.state_nxt <= IFETCH_REQUEST; |
end if; |
|
when others => -- undefined |
446,7 → 459,7
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word |
if (execute_engine.state = DISPATCH) then |
cmd_issue.valid <= '1'; |
cmd_issue.valid <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned" |
ipb.re <= '1'; |
460,7 → 473,7
|
else -- begin check in HIGH instruction half-word |
if (execute_engine.state = DISPATCH) then |
cmd_issue.valid <= '1'; |
cmd_issue.valid <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned" |
ipb.re <= '1'; |
526,35 → 539,41
begin |
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; |
if rising_edge(clk_i) then |
case opcode_v is -- save some bits here, LSBs are always 11 for rv32 |
when opcode_store_c => -- S-immediate |
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08); |
imm_o(00) <= execute_engine.i_reg(07); |
when opcode_branch_c => -- B-immediate |
imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(11) <= execute_engine.i_reg(07); |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08); |
imm_o(00) <= '0'; |
when opcode_lui_c | opcode_auipc_c => -- U-immediate |
imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20); |
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12); |
imm_o(11 downto 00) <= (others => '0'); |
when opcode_jal_c => -- J-immediate |
imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12); |
imm_o(11) <= execute_engine.i_reg(20); |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21); |
imm_o(00) <= '0'; |
when others => -- I-immediate |
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21); |
imm_o(00) <= execute_engine.i_reg(20); |
end case; |
if (execute_engine.state = BRANCH) then -- next_PC as immediate fro jump-and-link operations (=return address) |
imm_o <= execute_engine.next_pc; |
else -- "nromal" immediate from instruction |
case opcode_v is -- save some bits here, LSBs are always 11 for rv32 |
when opcode_store_c => -- S-immediate |
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08); |
imm_o(00) <= execute_engine.i_reg(07); |
when opcode_branch_c => -- B-immediate |
imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(11) <= execute_engine.i_reg(07); |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08); |
imm_o(00) <= '0'; |
when opcode_lui_c | opcode_auipc_c => -- U-immediate |
imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20); |
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12); |
imm_o(11 downto 00) <= (others => '0'); |
when opcode_jal_c => -- J-immediate |
imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12); |
imm_o(11) <= execute_engine.i_reg(20); |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21); |
imm_o(00) <= '0'; |
when opcode_atomic_c => -- atomic memory access |
imm_o <= (others => '0'); -- effective address is reg + 0 |
when others => -- I-immediate |
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension |
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25); |
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21); |
imm_o(00) <= execute_engine.i_reg(20); |
end case; |
end if; |
end if; |
end process imm_gen; |
|
585,13 → 604,20
begin |
if (rstn_i = '0') then |
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0'; |
execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0'; |
execute_engine.state <= SYS_WAIT; |
execute_engine.sleep <= '0'; |
execute_engine.if_rst <= '1'; -- instruction fetch is reset after system reset |
elsif rising_edge(clk_i) then |
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0'; |
execute_engine.last_pc <= execute_engine.last_pc_nxt; |
-- PC update -- |
if (execute_engine.pc_we = '1') then |
case execute_engine.pc_mux_sel is |
when "00" => execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment |
when "01" => execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/branch |
when "10" => execute_engine.pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap |
when others => execute_engine.pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap return |
end case; |
end if; |
-- |
execute_engine.state <= execute_engine.state_nxt; |
execute_engine.sleep <= execute_engine.sleep_nxt; |
execute_engine.if_rst <= execute_engine.if_rst_nxt; |
608,29 → 634,29
execute_engine.is_ci <= execute_engine.is_ci_nxt; |
execute_engine.is_jump <= execute_engine.is_jump_nxt; |
execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt; |
-- |
if (execute_engine.state = EXECUTE) then |
execute_engine.i_reg_last <= execute_engine.i_reg; |
end if; |
-- next PC -- |
-- next PC (next linear instruction) -- |
if (execute_engine.is_ci = '1') then -- compressed instruction? |
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 2); |
else |
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 4); |
end if; |
-- |
-- PC & IR of last "executed" instruction -- |
if (execute_engine.state = EXECUTE) then |
execute_engine.last_pc <= execute_engine.pc; |
execute_engine.i_reg_last <= execute_engine.i_reg; |
end if; |
-- main control bus -- |
ctrl <= ctrl_nxt; |
end if; |
end process execute_engine_fsm_sync; |
|
-- PC output -- |
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; |
next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; |
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- PC for ALU ops |
|
|
-- CPU Control Bus Output ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, bus_fast_ir, execute_engine, csr.privilege) |
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, atomic_ctrl, bus_fast_ir, execute_engine, csr.privilege) |
begin |
-- signals from execute engine -- |
ctrl_o <= ctrl; |
648,6 → 674,8
-- instruction's function blocks (for co-processors) -- |
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c); |
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); |
-- locked bus operation (for atomica memory operations) -- |
ctrl_o(ctrl_bus_lock_c) <= atomic_ctrl.lock; -- (bus) lock status |
end process ctrl_output; |
|
|
654,10 → 682,12
-- Execute Engine FSM Comb ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
execute_engine_fsm_comb: process(execute_engine, fetch_engine, cmd_issue, trap_ctrl, csr, ctrl, csr_acc_valid, |
alu_add_i, alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i) |
alu_wait_i, bus_d_wait_i, ma_load_i, be_load_i, ma_store_i, be_store_i) |
variable alu_immediate_v : std_ulogic; |
variable rs1_is_r0_v : std_ulogic; |
variable opcode_v : std_ulogic_vector(6 downto 0); |
variable is_atomic_lr_v : std_ulogic; |
variable is_atomic_sc_v : std_ulogic; |
begin |
-- arbiter defaults -- |
execute_engine.state_nxt <= execute_engine.state; |
665,10 → 695,11
execute_engine.is_jump_nxt <= '0'; |
execute_engine.is_cp_op_nxt <= execute_engine.is_cp_op; |
execute_engine.is_ci_nxt <= execute_engine.is_ci; |
execute_engine.pc_nxt <= execute_engine.pc; |
execute_engine.last_pc_nxt <= execute_engine.last_pc; |
execute_engine.sleep_nxt <= execute_engine.sleep; |
execute_engine.if_rst_nxt <= execute_engine.if_rst; |
-- |
execute_engine.pc_mux_sel <= (others => '0'); |
execute_engine.pc_we <= '0'; |
|
-- instruction dispatch -- |
fetch_engine.reset <= '0'; |
688,7 → 719,12
csr.we_nxt <= '0'; |
csr.re_nxt <= '0'; |
|
-- control defaults -- |
-- atomic operations control -- |
atomic_ctrl.env_start <= '0'; |
atomic_ctrl.env_end <= '0'; |
atomic_ctrl.env_abort <= '0'; |
|
-- CONTROL DEFAULTS -- |
ctrl_nxt <= (others => '0'); -- default: all off |
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU) |
695,12 → 731,19
else -- branches |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU) |
end if; |
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU) |
-- memor access -- |
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU) |
ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size |
-- alu.shifter -- |
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right) |
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- default ALU operation: ADD(I) |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- only CP0 (=MULDIV) implemented yet |
ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size |
-- ALU control -- |
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I) |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- default ALU function select: arithmetic |
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- default ALU arithmetic operation: ADDSUB |
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- default ALU logic operation: MOVB |
-- co-processor id -- |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- default CP = MULDIV |
|
-- is immediate ALU operation? -- |
alu_immediate_v := not execute_engine.i_reg(instr_opcode_msb_c-1); |
708,7 → 751,16
-- is rs1 == r0? -- |
rs1_is_r0_v := not or_all_f(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c)); |
|
-- is atomic load-reservate/store-conditional? -- |
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode |
is_atomic_lr_v := not execute_engine.i_reg(instr_funct5_lsb_c); |
is_atomic_sc_v := execute_engine.i_reg(instr_funct5_lsb_c); |
else |
is_atomic_lr_v := '0'; |
is_atomic_sc_v := '0'; |
end if; |
|
|
-- state machine -- |
case execute_engine.state is |
|
722,8 → 774,10
-- |
execute_engine.state_nxt <= DISPATCH; |
|
|
when DISPATCH => -- Get new command from instruction issue engine |
-- ------------------------------------------------------------ |
execute_engine.pc_mux_sel <= "00"; -- linear next PC |
if (cmd_issue.valid = '1') then -- instruction available? |
-- IR update -- |
execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate this is a de-compressed instruction beeing executed |
734,7 → 788,7
-- PC update -- |
execute_engine.if_rst_nxt <= '0'; |
if (execute_engine.if_rst = '0') then -- if there was NO non-linear PC modification |
execute_engine.pc_nxt <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; |
execute_engine.pc_we <= '1'; |
end if; |
-- any reason to go to trap state FAST? -- |
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or (trap_ctrl.exc_fire = '1') or ((cmd_issue.data(33) or cmd_issue.data(34)) = '1') then |
744,49 → 798,38
end if; |
end if; |
|
|
when TRAP => -- Start trap environment (also used as cpu sleep state) |
-- ------------------------------------------------------------ |
execute_engine.pc_mux_sel <= "10"; -- csr.mtvec (trap) |
-- stay here for sleep |
if (trap_ctrl.env_start = '1') then -- trap triggered? |
fetch_engine.reset <= '1'; |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
trap_ctrl.env_start_ack <= '1'; |
execute_engine.pc_nxt <= csr.mtvec; |
execute_engine.pc_we <= '1'; |
execute_engine.sleep_nxt <= '0'; -- waky waky |
execute_engine.state_nxt <= SYS_WAIT; |
end if; |
|
|
when EXECUTE => -- Decode and execute instruction |
-- ------------------------------------------------------------ |
execute_engine.last_pc_nxt <= execute_engine.pc; -- store address of current instruction for commit |
-- |
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32 |
case opcode_v is |
|
when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA |
ctrl_nxt(ctrl_alu_opb_mux_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result |
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA |
ctrl_nxt(ctrl_alu_opb_mux_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations |
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result |
|
-- cp access? -- |
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and |
(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV? |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_cp_c; |
execute_engine.is_cp_op_nxt <= '1'; -- use CP |
-- ALU operation -- |
-- ALU arithmetic operation type and ADD/SUB -- |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) then |
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_slt_c; |
else |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU operation (re-coding) |
when funct3_sll_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c; -- SLL(I) |
when funct3_slt_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_slt_c; -- SLT(I) |
when funct3_sltu_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_slt_c; -- SLTU(I) |
when funct3_xor_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_xor_c; -- XOR(I) |
when funct3_sr_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c; -- SRL(I) / SRA(I) |
when funct3_or_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- OR(I) |
when funct3_and_c => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_and_c; -- AND(I) |
when others => ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- ADD(I) / SUB |
end case; |
execute_engine.is_cp_op_nxt <= '0'; -- no CP operation |
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; |
end if; |
|
-- ADD/SUB -- |
798,10 → 841,32
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I) |
end if; |
|
-- ALU logic operation -- |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.logic operation (re-coding) |
when funct3_xor_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_xor_c; -- XOR(I) |
when funct3_or_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_or_c; -- OR(I) |
when funct3_and_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_and_c; -- AND(I) |
when others => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- undefined |
end case; |
|
-- cp access? -- |
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV CP op? |
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c; |
-- ALU operation - function select -- |
else |
execute_engine.is_cp_op_nxt <= '0'; -- no CP operation |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.func operation (re-coding) |
when funct3_xor_c | funct3_or_c | funct3_and_c => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; |
when funct3_sll_c | funct3_sr_c => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_shift_c; |
when others => ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; |
end case; |
end if; |
|
-- multi cycle alu operation? -- |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation? |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation? |
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') and (CPU_EXTENSION_RISCV_M = true)) then -- MULDIV? |
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV CP op? |
execute_engine.state_nxt <= ALU_WAIT; |
else -- single cycle ALU operation |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
812,28 → 877,40
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- ALU.OPA = PC (for AUIPC only) |
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB |
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- actual ALU operation = ADD |
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB |
if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_movb_c; -- actual ALU operation = MOVB |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB |
else -- AUIPC |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- actual ALU operation = ADD |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- actual ALU operation = ADD |
end if; |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
execute_engine.state_nxt <= DISPATCH; |
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
execute_engine.state_nxt <= DISPATCH; |
|
when opcode_load_c | opcode_store_c => -- load/store |
when opcode_load_c | opcode_store_c | opcode_atomic_c => -- load/store / atomic memory access |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA |
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- actual ALU operation = ADD |
ctrl_nxt(ctrl_bus_mar_we_c) <= '1'; -- write to MAR |
ctrl_nxt(ctrl_bus_mdo_we_c) <= '1'; -- write to MDO (only relevant for stores) |
execute_engine.state_nxt <= LOADSTORE_0; |
ctrl_nxt(ctrl_bus_mo_we_c) <= '1'; -- write to MAR and MDO (MDO only relevant for store) |
-- |
if (CPU_EXTENSION_RISCV_A = false) or (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') then -- atomic (A) extension disabled or normal load/store |
execute_engine.state_nxt <= LOADSTORE_0; |
else -- atomic operation |
atomic_ctrl.env_start <= not execute_engine.i_reg(instr_funct5_lsb_c); -- LR: start LOCKED memory access environment |
if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_sc_c) or -- store-conditional |
(execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_lr_c) then -- load-reservate |
execute_engine.state_nxt <= LOADSTORE_0; |
else -- unimplemented (atomic) instruction |
execute_engine.state_nxt <= SYS_WAIT; |
end if; |
end if; |
|
when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link (with register) |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_addsub_c; -- actual ALU operation = ADD |
-- compute target address -- |
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- actual ALU operation = ADD |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- actual ALU operation = ADD |
if (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = opcode_jalr_c(3 downto 2)) then -- JALR |
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA (branch target address base) |
else -- JAL / branch |
840,62 → 917,53
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base) |
end if; |
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset) |
-- save return address -- |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "10"; -- RF input = next PC (save return address) |
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (for JAL/JALR) |
-- |
execute_engine.is_jump_nxt <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- is this is a jump operation? (for JAL/JALR) |
execute_engine.state_nxt <= BRANCH; |
|
when opcode_fence_c => -- fence operations |
-- ------------------------------------------------------------ |
execute_engine.state_nxt <= SYS_WAIT; |
-- for simplicity: internally, fence and fence.i perform the same operations (clear and reload instruction prefetch buffer) |
-- FENCE.I -- |
if (CPU_EXTENSION_RISCV_Zifencei = true) then |
execute_engine.pc_nxt <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- "refetch" next instruction |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
fetch_engine.reset <= '1'; |
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) then |
ctrl_nxt(ctrl_bus_fencei_c) <= '1'; |
end if; |
end if; |
-- FENCE -- |
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then |
ctrl_nxt(ctrl_bus_fence_c) <= '1'; |
end if; |
execute_engine.state_nxt <= FENCE_OP; |
|
when opcode_syscsr_c => -- system/csr access |
-- ------------------------------------------------------------ |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system |
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is |
when funct12_ecall_c => -- ECALL |
trap_ctrl.env_call <= '1'; |
when funct12_ebreak_c => -- EBREAK |
trap_ctrl.break_point <= '1'; |
when funct12_mret_c => -- MRET |
trap_ctrl.env_end <= '1'; |
execute_engine.pc_nxt <= csr.mepc; |
fetch_engine.reset <= '1'; |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
when funct12_wfi_c => -- WFI |
execute_engine.sleep_nxt <= '1'; -- good night |
when others => -- undefined |
NULL; |
end case; |
execute_engine.state_nxt <= SYS_WAIT; |
csr.re_nxt <= '1'; -- always read CSR (internally), only relevant for CSR-instructions |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment |
execute_engine.state_nxt <= SYS_ENV; |
else -- CSR access |
csr.re_nxt <= '1'; -- always read CSR (internally) |
execute_engine.state_nxt <= CSR_ACCESS; |
end if; |
|
when others => -- undefined |
-- ------------------------------------------------------------ |
execute_engine.state_nxt <= DISPATCH; |
execute_engine.state_nxt <= SYS_WAIT; |
|
end case; |
|
when CSR_ACCESS => -- write CSR data to RF, write ALU.res to CSR |
|
when SYS_ENV => -- system environment operation - execution |
-- ------------------------------------------------------------ |
execute_engine.pc_mux_sel <= "11"; -- csr.mepc (only for MRET) |
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is |
when funct12_ecall_c => -- ECALL |
trap_ctrl.env_call <= '1'; |
when funct12_ebreak_c => -- EBREAK |
trap_ctrl.break_point <= '1'; |
when funct12_mret_c => -- MRET |
trap_ctrl.env_end <= '1'; |
execute_engine.pc_we <= '1'; -- linear next PC |
fetch_engine.reset <= '1'; |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
when funct12_wfi_c => -- WFI |
execute_engine.sleep_nxt <= '1'; -- good night |
when others => -- undefined |
NULL; |
end case; |
execute_engine.state_nxt <= SYS_WAIT; |
|
|
when CSR_ACCESS => -- read & write status and control register (CSR) |
-- ------------------------------------------------------------ |
-- CSR write access -- |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is |
when funct3_csrrw_c | funct3_csrrwi_c => -- CSRRW(I) |
908,17 → 976,18
-- register file write back -- |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
execute_engine.state_nxt <= SYS_WAIT; -- have another cycle to let side-effects kick in (FIXME?) |
execute_engine.state_nxt <= DISPATCH; |
|
|
when ALU_WAIT => -- wait for multi-cycle ALU operation (shifter or CP) to finish |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back) |
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back) |
-- cp access or alu shift? -- |
if (execute_engine.is_cp_op = '1') then |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_cp_c; |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c; |
else |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c; |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_shift_c; |
end if; |
-- wait for result -- |
if (alu_wait_i = '0') then |
925,10 → 994,19
execute_engine.state_nxt <= DISPATCH; |
end if; |
|
|
when BRANCH => -- update PC for taken branches and jumps |
-- ------------------------------------------------------------ |
-- get and store return address (only relevant for jump-and-link operations) -- |
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (next_pc from immediate generator = return address) |
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB |
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result |
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.is_jump; -- valid RF write-back? (is jump-and-link?) |
-- destination address -- |
execute_engine.pc_mux_sel <= "01"; -- alu.add = branch/jump destination |
if (execute_engine.is_jump = '1') or (execute_engine.branch_taken = '1') then |
execute_engine.pc_nxt <= alu_add_i; -- branch/jump destination |
execute_engine.pc_we <= '1'; -- update PC |
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
execute_engine.state_nxt <= SYS_WAIT; |
936,33 → 1014,69
execute_engine.state_nxt <= DISPATCH; |
end if; |
|
|
when FENCE_OP => -- fence operations - execution |
-- ------------------------------------------------------------ |
execute_engine.state_nxt <= SYS_WAIT; |
execute_engine.pc_mux_sel <= "00"; -- linear next PC = "refetch" next instruction |
-- FENCE.I -- |
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) and (CPU_EXTENSION_RISCV_Zifencei = true) then |
execute_engine.pc_we <= '1'; |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
fetch_engine.reset <= '1'; |
ctrl_nxt(ctrl_bus_fencei_c) <= '1'; |
end if; |
-- FENCE -- |
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then |
ctrl_nxt(ctrl_bus_fence_c) <= '1'; |
end if; |
|
|
when LOADSTORE_0 => -- trigger memory request |
-- ------------------------------------------------------------ |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (is_atomic_lr_v = '1') then -- normal load or atomic load-reservate |
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request |
else -- STORE |
else -- store |
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- write request |
end if; |
execute_engine.state_nxt <= LOADSTORE_1; |
|
|
when LOADSTORE_1 => -- memory latency |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD) |
execute_engine.state_nxt <= LOADSTORE_2; |
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- write input data to MDI (only relevant for LOAD) |
execute_engine.state_nxt <= LOADSTORE_2; |
|
|
when LOADSTORE_2 => -- wait for bus transaction to finish |
-- ------------------------------------------------------------ |
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD) |
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD) |
if (CPU_EXTENSION_RISCV_A = true) then -- only relevant for atomic operations |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_atomic_c; -- SC: result comes from "atomic co-processor" |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c; |
end if; |
-- |
ctrl_nxt(ctrl_rf_in_mux_lsb_c) <= '0'; -- RF input = ALU.res or MEM |
if (is_atomic_sc_v = '1') then |
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU.res |
else |
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '1'; -- RF input = memory input (only relevant for LOAD) |
end if; |
-- |
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load operations) |
-- wait for memory response -- |
if ((ma_load_i or be_load_i or ma_store_i or be_store_i) = '1') then -- abort if exception |
execute_engine.state_nxt <= DISPATCH; |
atomic_ctrl.env_abort <= '1'; -- LOCKED (atomic) memory access environment failed (forces SC result to be non-zero => failure) |
ctrl_nxt(ctrl_rf_wb_en_c) <= is_atomic_sc_v; -- SC failes: allow write back of non-zero result |
execute_engine.state_nxt <= DISPATCH; |
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (keep writing back all the time) |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (is_atomic_lr_v = '1') or (is_atomic_sc_v = '1') then -- load / load-reservate / store conditional |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back |
end if; |
atomic_ctrl.env_end <= '1'; -- normal end of LOCKED (atomic) memory access environment |
execute_engine.state_nxt <= DISPATCH; |
end if; |
|
|
when others => -- undefined |
-- ------------------------------------------------------------ |
execute_engine.state_nxt <= SYS_WAIT; |
1003,7 → 1117,7
-- check CSR access -- |
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is |
when csr_mstatus_c => csr_acc_valid <= is_m_mode_v; -- M-mode only |
when csr_misa_c => csr_acc_valid <= is_m_mode_v;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only for the NEORV32 but we don't cause an exception here for compatibility |
when csr_misa_c => csr_acc_valid <= is_m_mode_v;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we don't cause an exception here for compatibility |
when csr_mie_c => csr_acc_valid <= is_m_mode_v; -- M-mode only |
when csr_mtvec_c => csr_acc_valid <= is_m_mode_v; -- M-mode only |
when csr_mscratch_c => csr_acc_valid <= is_m_mode_v; -- M-mode only |
1095,7 → 1209,7
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then |
illegal_register <= '1'; |
end if; |
|
|
when opcode_load_c => -- check LOAD funct3 |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or |
1110,7 → 1224,7
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then |
illegal_register <= '1'; |
end if; |
|
|
when opcode_store_c => -- check STORE funct3 |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or |
1217,6 → 1331,15
illegal_instruction <= '1'; |
end if; |
|
when opcode_atomic_c => -- atomic instructions -- |
if (CPU_EXTENSION_RISCV_A = true) and -- atomic memory operations (A extension) enabled |
((execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_lr_c) or -- LR |
(execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = funct5_a_sc_c)) then -- SC |
illegal_instruction <= '0'; |
else |
illegal_instruction <= '1'; |
end if; |
|
when others => -- undefined instruction -> illegal! |
illegal_instruction <= '1'; |
|
1271,11 → 1394,10
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not trap_ctrl.irq_ack(interrupt_firq_1_c)); |
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not trap_ctrl.irq_ack(interrupt_firq_2_c)); |
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not trap_ctrl.irq_ack(interrupt_firq_3_c)); |
|
-- trap control -- |
if (trap_ctrl.env_start = '0') then -- no started trap handler |
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected! |
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only -> continue execution even if permanent IRQ |
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only to continue execution even if permanent IRQ |
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr) |
trap_ctrl.exc_ack <= '1'; -- clear execption |
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask |
1393,6 → 1515,31
trap_ctrl.irq_ack_nxt <= (others => '0'); |
end if; |
end process trap_priority; |
|
|
-- Atomic Operation Controller ------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
atomics_controller: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
atomic_ctrl.lock <= '0'; |
atomic_ctrl.env_end_ff <= '0'; |
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_A = true) then |
if (atomic_ctrl.env_end_ff = '1') or -- normal termination |
(atomic_ctrl.env_abort = '1') or -- fast temrination (error) |
(trap_ctrl.env_start = '1') then -- triggered trap -> failure |
atomic_ctrl.lock <= '0'; |
elsif (atomic_ctrl.env_start = '1') then |
atomic_ctrl.lock <= '1'; |
end if; |
atomic_ctrl.env_end_ff <= atomic_ctrl.env_end; |
else |
atomic_ctrl.lock <= '0'; |
atomic_ctrl.env_end_ff <= '0'; |
end if; |
end if; |
end process atomics_controller; |
|
|
-- **************************************************************************************************************************** |
1677,12 → 1824,9
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low |
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high |
when csr_misa_c => -- R/-: misa - ISA and extensions |
csr.rdata(00) <= '0'; -- A CPU extension |
csr.rdata(01) <= '0'; -- B CPU extension |
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension |
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension |
csr.rdata(03) <= '0'; -- D CPU extension |
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension |
csr.rdata(05) <= '0'; -- F CPU extension |
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E) |
csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension |
csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension |
1851,7 → 1995,7
csr.rdata <= HW_THREAD_ID; |
|
-- custom machine read-only CSRs -- |
when csr_mzext_c => -- R/-: mzext |
when csr_mzext_c => -- R/-: mzext - available Z* extensions |
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension |
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension |
csr.rdata(2) <= bool_to_ulogic_f(PMP_USE); -- RISC-V physical memory protection |
/rtl/core/neorv32_cpu_cp_muldiv.vhd
73,6 → 73,7
signal state : state_t; |
signal cnt : std_ulogic_vector(4 downto 0); |
signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute |
signal cp_op_ff : std_ulogic_vector(2 downto 0); -- operation that was executed |
signal start : std_ulogic; |
signal operation : std_ulogic; |
signal opx, opy : std_ulogic_vector(data_width_c-1 downto 0); -- input operands |
80,6 → 81,7
signal opy_is_signed : std_ulogic; |
signal opy_is_zero : std_ulogic; |
signal div_res_corr : std_ulogic; |
signal valid : std_ulogic; |
|
-- divider core -- |
signal remainder : std_ulogic_vector(data_width_c-1 downto 0); |
111,13 → 113,15
opy <= (others => '0'); |
cnt <= (others => '0'); |
start <= '0'; |
valid_o <= '0'; |
valid <= '0'; |
div_res_corr <= '0'; |
opy_is_zero <= '0'; |
cp_op_ff <= (others => '0'); |
elsif rising_edge(clk_i) then |
-- defaults -- |
start <= '0'; |
valid_o <= '0'; |
start <= '0'; |
valid <= '0'; |
cp_op_ff <= cp_op; |
|
-- FSM -- |
case state is |
182,8 → 186,8
state <= COMPLETED; |
|
when COMPLETED => |
valid_o <= '1'; |
state <= IDLE; |
valid <= '1'; |
state <= IDLE; |
end case; |
end if; |
end process coprocessor_ctrl; |
286,11 → 290,11
|
-- Data Output ---------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
operation_result: process(clk_i) |
operation_result: process(valid, cp_op_ff, mul_product, div_res, quotient, opy_is_zero, rs1_i, remainder) |
begin |
if rising_edge(clk_i) then |
res_o <= (others => '0'); -- default |
case cp_op is |
if (valid = '1') then |
valid_o <= '1'; |
case cp_op_ff is |
when cp_op_mul_c => |
res_o <= mul_product(31 downto 00); |
when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c => |
303,13 → 307,14
if (opy_is_zero = '0') then |
res_o <= div_res; |
else |
res_o <= opx; |
res_o <= rs1_i; |
end if; |
when cp_op_remu_c => |
when others => -- cp_op_remu_c |
res_o <= remainder; |
when others => -- undefined |
res_o <= (others => '0'); |
end case; |
else |
valid_o <= '0'; |
res_o <= (others => '0'); |
end if; |
end process operation_result; |
|
/rtl/core/neorv32_cpu_regfile.vhd
2,10 → 2,9
-- # << NEORV32 - CPU Data Register File >> # |
-- # ********************************************************************************************* # |
-- # General purpose data register file. 32 entries for normal mode (I), 16 entries for embedded # |
-- # mode (E) when RISC-V "E" extension is enabled. Register zero (r0) is a normal physical # |
-- # registers, that has to be initialized to zero by the CPU control system. For normal # |
-- # operations r0 cannot be written. The register file uses synchronous reads. Hence it can be # |
-- # mapped to FPGA block RAM. # |
-- # mode (E) when RISC-V "E" extension is enabled. Register zero (r0) is a "normal" physical reg # |
-- # that has to be initialized to zero by the CPU control system. For normal operations r0 cannot # |
-- # be written. The register file uses synchronous reads so it can be mapped to FPGA block RAM. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
57,7 → 56,6
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data |
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current pc |
-- data output -- |
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1 |
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2 |
71,6 → 69,7
type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0); |
signal reg_file : reg_file_t; |
signal reg_file_emb : reg_file_emb_t; |
signal rf_mux_data : std_ulogic_vector(data_width_c-1 downto 0); |
signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data |
signal rd_is_r0 : std_ulogic; -- writing to r0? |
signal rf_we : std_ulogic; |
78,29 → 77,6
|
begin |
|
-- Input mux ------------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
input_mux: process(ctrl_i, mem_i, alu_i, pc_i, csr_i) |
begin |
case ctrl_i(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) is |
when "00" => rf_write_data <= alu_i; |
when "01" => rf_write_data <= mem_i; |
when "10" => rf_write_data <= pc_i; |
when others => rf_write_data <= csr_i; |
end case; |
end process input_mux; |
|
-- check if we are writing to x0 -- |
rd_is_r0 <= not or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else |
not or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)); |
|
-- valid RF write access -- |
rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c); |
|
-- destination address -- |
dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0? |
|
|
-- Register file read/write access -------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
rf_access: process(clk_i) |
109,7 → 85,7
if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries |
if (rf_we = '1') then |
reg_file(to_integer(unsigned(dst_addr(4 downto 0)))) <= rf_write_data; |
else -- read |
else |
rs1_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c)))); |
rs2_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c)))); |
end if; |
116,7 → 92,7
else -- embedded register file with 16 entries |
if (rf_we = '1') then |
reg_file_emb(to_integer(unsigned(dst_addr(3 downto 0)))) <= rf_write_data; |
else -- read |
else |
rs1_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c)))); |
rs2_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c)))); |
end if; |
124,5 → 100,20
end if; |
end process rf_access; |
|
-- data input mux -- |
rf_write_data <= alu_i when (ctrl_i(ctrl_rf_in_mux_msb_c) = '0') else rf_mux_data; |
rf_mux_data <= mem_i when (ctrl_i(ctrl_rf_in_mux_lsb_c) = '0') else csr_i; |
|
-- check if we are writing to x0 -- |
rd_is_r0 <= not or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else |
not or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)); |
|
-- valid RF write access -- |
rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c); |
|
-- destination address -- |
dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0? |
|
|
|
end neorv32_cpu_regfile_rtl; |
/rtl/core/neorv32_package.vhd
42,7 → 42,7
-- ------------------------------------------------------------------------------------------- |
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address |
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address |
constant bus_timeout_c : natural := 127; -- cycles after which an *unacknwoledged* bus access will timeout and trigger an access exception |
constant bus_timeout_c : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger an access exception |
constant wb_pipe_mode_c : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode |
constant ipb_entries_c : natural := 2; -- entries in instruction prefetch buffer, must be a power of 2, default=2 |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the CPU HW |
50,7 → 50,7
-- Architecture Constants ----------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040702"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040801"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
|
76,9 → 76,9
-- Processor-Internal Address Space Layout ------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
-- Internal Instruction Memory (IMEM) and Date Memory (DMEM) -- |
constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address |
constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address |
--> sizea are configured via top's generic |
constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address |
constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address |
--> memory sizes are configured via top's generics |
|
-- Internal Bootloader ROM -- |
constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed! |
161,8 → 161,8
-- Main Control Bus ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- register file -- |
constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (00=ALU, 01=MEM) |
constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (10=PC, 11=CSR) |
constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (10=MEM, 11=CSR) |
constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (0-=ALU) |
constant ctrl_rf_rs1_adr0_c : natural := 2; -- source register 1 address bit 0 |
constant ctrl_rf_rs1_adr1_c : natural := 3; -- source register 1 address bit 1 |
constant ctrl_rf_rs1_adr2_c : natural := 4; -- source register 1 address bit 2 |
181,53 → 181,55
constant ctrl_rf_wb_en_c : natural := 17; -- write back enable |
constant ctrl_rf_r0_we_c : natural := 18; -- force write access and force rd=r0 |
-- alu -- |
constant ctrl_alu_cmd0_c : natural := 19; -- ALU command bit 0 |
constant ctrl_alu_cmd1_c : natural := 20; -- ALU command bit 1 |
constant ctrl_alu_cmd2_c : natural := 21; -- ALU command bit 2 |
constant ctrl_alu_addsub_c : natural := 22; -- 0=ADD, 1=SUB |
constant ctrl_alu_opa_mux_c : natural := 23; -- operand A select (0=rs1, 1=PC) |
constant ctrl_alu_opb_mux_c : natural := 24; -- operand B select (0=rs2, 1=IMM) |
constant ctrl_alu_unsigned_c : natural := 25; -- is unsigned ALU operation |
constant ctrl_alu_shift_dir_c : natural := 26; -- shift direction (0=left, 1=right) |
constant ctrl_alu_shift_ar_c : natural := 27; -- is arithmetic shift |
constant ctrl_alu_arith_c : natural := 19; -- ALU arithmetic command |
constant ctrl_alu_logic0_c : natural := 20; -- ALU logic command bit 0 |
constant ctrl_alu_logic1_c : natural := 21; -- ALU logic command bit 1 |
constant ctrl_alu_func0_c : natural := 22; -- ALU function select command bit 0 |
constant ctrl_alu_func1_c : natural := 23; -- ALU function select command bit 1 |
constant ctrl_alu_addsub_c : natural := 24; -- 0=ADD, 1=SUB |
constant ctrl_alu_opa_mux_c : natural := 25; -- operand A select (0=rs1, 1=PC) |
constant ctrl_alu_opb_mux_c : natural := 26; -- operand B select (0=rs2, 1=IMM) |
constant ctrl_alu_unsigned_c : natural := 27; -- is unsigned ALU operation |
constant ctrl_alu_shift_dir_c : natural := 28; -- shift direction (0=left, 1=right) |
constant ctrl_alu_shift_ar_c : natural := 29; -- is arithmetic shift |
-- bus interface -- |
constant ctrl_bus_size_lsb_c : natural := 28; -- transfer size lsb (00=byte, 01=half-word) |
constant ctrl_bus_size_msb_c : natural := 29; -- transfer size msb (10=word, 11=?) |
constant ctrl_bus_rd_c : natural := 30; -- read data request |
constant ctrl_bus_wr_c : natural := 31; -- write data request |
constant ctrl_bus_if_c : natural := 32; -- instruction fetch request |
constant ctrl_bus_mar_we_c : natural := 33; -- memory address register write enable |
constant ctrl_bus_mdo_we_c : natural := 34; -- memory data out register write enable |
constant ctrl_bus_mdi_we_c : natural := 35; -- memory data in register write enable |
constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load |
constant ctrl_bus_ierr_ack_c : natural := 37; -- acknowledge instruction fetch bus exceptions |
constant ctrl_bus_derr_ack_c : natural := 38; -- acknowledge data access bus exceptions |
constant ctrl_bus_fence_c : natural := 39; -- executed fence operation |
constant ctrl_bus_fencei_c : natural := 40; -- executed fencei operation |
constant ctrl_bus_size_lsb_c : natural := 30; -- transfer size lsb (00=byte, 01=half-word) |
constant ctrl_bus_size_msb_c : natural := 31; -- transfer size msb (10=word, 11=?) |
constant ctrl_bus_rd_c : natural := 32; -- read data request |
constant ctrl_bus_wr_c : natural := 33; -- write data request |
constant ctrl_bus_if_c : natural := 34; -- instruction fetch request |
constant ctrl_bus_mo_we_c : natural := 35; -- memory address and data output register write enable |
constant ctrl_bus_mi_we_c : natural := 36; -- memory data input register write enable |
constant ctrl_bus_unsigned_c : natural := 37; -- is unsigned load |
constant ctrl_bus_ierr_ack_c : natural := 38; -- acknowledge instruction fetch bus exceptions |
constant ctrl_bus_derr_ack_c : natural := 39; -- acknowledge data access bus exceptions |
constant ctrl_bus_fence_c : natural := 40; -- executed fence operation |
constant ctrl_bus_fencei_c : natural := 41; -- executed fencei operation |
constant ctrl_bus_lock_c : natural := 42; -- locked/exclusive bus access |
-- co-processors -- |
constant ctrl_cp_id_lsb_c : natural := 41; -- cp select ID lsb |
constant ctrl_cp_id_msb_c : natural := 42; -- cp select ID msb |
constant ctrl_cp_id_lsb_c : natural := 43; -- cp select ID lsb |
constant ctrl_cp_id_msb_c : natural := 44; -- cp select ID msb |
-- current privilege level -- |
constant ctrl_priv_lvl_lsb_c : natural := 43; -- privilege level lsb |
constant ctrl_priv_lvl_msb_c : natural := 44; -- privilege level msb |
constant ctrl_priv_lvl_lsb_c : natural := 45; -- privilege level lsb |
constant ctrl_priv_lvl_msb_c : natural := 46; -- privilege level msb |
-- instruction's control blocks -- |
constant ctrl_ir_funct3_0_c : natural := 45; -- funct3 bit 0 |
constant ctrl_ir_funct3_1_c : natural := 46; -- funct3 bit 1 |
constant ctrl_ir_funct3_2_c : natural := 47; -- funct3 bit 2 |
constant ctrl_ir_funct12_0_c : natural := 48; -- funct12 bit 0 |
constant ctrl_ir_funct12_1_c : natural := 49; -- funct12 bit 1 |
constant ctrl_ir_funct12_2_c : natural := 50; -- funct12 bit 2 |
constant ctrl_ir_funct12_3_c : natural := 51; -- funct12 bit 3 |
constant ctrl_ir_funct12_4_c : natural := 52; -- funct12 bit 4 |
constant ctrl_ir_funct12_5_c : natural := 53; -- funct12 bit 5 |
constant ctrl_ir_funct12_6_c : natural := 54; -- funct12 bit 6 |
constant ctrl_ir_funct12_7_c : natural := 55; -- funct12 bit 7 |
constant ctrl_ir_funct12_8_c : natural := 56; -- funct12 bit 8 |
constant ctrl_ir_funct12_9_c : natural := 57; -- funct12 bit 9 |
constant ctrl_ir_funct12_10_c : natural := 58; -- funct12 bit 10 |
constant ctrl_ir_funct12_11_c : natural := 59; -- funct12 bit 11 |
constant ctrl_ir_funct3_0_c : natural := 47; -- funct3 bit 0 |
constant ctrl_ir_funct3_1_c : natural := 48; -- funct3 bit 1 |
constant ctrl_ir_funct3_2_c : natural := 49; -- funct3 bit 2 |
constant ctrl_ir_funct12_0_c : natural := 50; -- funct12 bit 0 |
constant ctrl_ir_funct12_1_c : natural := 51; -- funct12 bit 1 |
constant ctrl_ir_funct12_2_c : natural := 52; -- funct12 bit 2 |
constant ctrl_ir_funct12_3_c : natural := 53; -- funct12 bit 3 |
constant ctrl_ir_funct12_4_c : natural := 54; -- funct12 bit 4 |
constant ctrl_ir_funct12_5_c : natural := 55; -- funct12 bit 5 |
constant ctrl_ir_funct12_6_c : natural := 56; -- funct12 bit 6 |
constant ctrl_ir_funct12_7_c : natural := 57; -- funct12 bit 7 |
constant ctrl_ir_funct12_8_c : natural := 58; -- funct12 bit 8 |
constant ctrl_ir_funct12_9_c : natural := 59; -- funct12 bit 9 |
constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10 |
constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11 |
-- control bus size -- |
constant ctrl_width_c : natural := 60; -- control bus size |
constant ctrl_width_c : natural := 62; -- control bus size |
|
-- ALU Comparator Bus --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
256,6 → 258,8
constant instr_imm20_msb_c : natural := 31; -- immediate20 bit 21 |
constant instr_csr_id_lsb_c : natural := 20; -- csr select bit 0 |
constant instr_csr_id_msb_c : natural := 31; -- csr select bit 11 |
constant instr_funct5_lsb_c : natural := 27; -- funct5 select bit 0 |
constant instr_funct5_msb_c : natural := 31; -- funct5 select bit 4 |
|
-- RISC-V Opcodes ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
274,6 → 278,8
-- system/csr -- |
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i |
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3) |
-- atomic operations (A) -- |
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension) |
|
-- RISC-V Funct3 -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
315,7 → 321,7
constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP) |
constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync |
|
-- RISC-V Funct12 -------------------------------------------------------------------------- |
-- RISC-V Funct12 ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- system -- |
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL |
323,6 → 329,12
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET |
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI |
|
-- RISC-V Funct5 -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- atomic operations -- |
constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR |
constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC |
|
-- RISC-V CSR Addresses ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus |
372,10 → 384,10
-- Co-Processor Operations ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- cp ids -- |
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV |
constant cp_sel_bitmanip_c : std_ulogic_vector(1 downto 0) := "01"; -- BITMANIP |
--constant cp_sel_reserved_c : std_ulogic_vector(1 downto 0) := "10"; -- reserved |
--constant cp_sel_reserved_c : std_ulogic_vector(1 downto 0) := "11"; -- reserved |
constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV |
constant cp_sel_atomic_c : std_ulogic_vector(1 downto 0) := "01"; -- atomic operations success/failure evaluation |
--constant cp_sel_reserv_c : std_ulogic_vector(1 downto 0) := "10"; -- reserved |
--constant cp_sel_reserv_c : std_ulogic_vector(1 downto 0) := "11"; -- reserved |
-- muldiv cp -- |
constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul |
constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh |
388,36 → 400,41
|
-- ALU Function Codes --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant alu_cmd_addsub_c : std_ulogic_vector(2 downto 0) := "000"; -- r <= A +/- B |
constant alu_cmd_slt_c : std_ulogic_vector(2 downto 0) := "001"; -- r <= A < B |
constant alu_cmd_cp_c : std_ulogic_vector(2 downto 0) := "010"; -- r <= CP result (iterative) |
constant alu_cmd_shift_c : std_ulogic_vector(2 downto 0) := "011"; -- r <= A <</>> B (iterative) |
constant alu_cmd_movb_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= B |
constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A xor B |
constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A or B |
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and B |
-- arithmetic core -- |
constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B |
constant alu_arith_cmd_slt_c : std_ulogic := '1'; -- r.arith <= A < B |
-- logic core -- |
constant alu_logic_cmd_movb_c : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B |
constant alu_logic_cmd_xor_c : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B |
constant alu_logic_cmd_or_c : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B |
constant alu_logic_cmd_and_c : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B |
-- function select (actual alu result) -- |
constant alu_func_cmd_arith_c : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith |
constant alu_func_cmd_logic_c : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic |
constant alu_func_cmd_shift_c : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative) |
constant alu_func_cmd_copro_c : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative) |
|
-- Trap ID Codes -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- risc-v compliant -- |
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "000000"; -- 0.0: instruction misaligned |
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "000001"; -- 0.1: instruction access fault |
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "000010"; -- 0.2: illegal instruction |
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "000011"; -- 0.3: breakpoint |
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "000100"; -- 0.4: load address misaligned |
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "000101"; -- 0.5: load access fault |
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "000110"; -- 0.6: store address misaligned |
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "000111"; -- 0.7: store access fault |
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "001011"; -- 0.11: environment call from m-mode |
-- |
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "100011"; -- 1.3: machine software interrupt |
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "100111"; -- 1.7: machine timer interrupt |
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "101011"; -- 1.11: machine external interrupt |
-- custom -- |
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "110000"; -- 1.16: fast interrupt 0 |
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "110001"; -- 1.17: fast interrupt 1 |
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "110010"; -- 1.18: fast interrupt 2 |
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "110011"; -- 1.19: fast interrupt 3 |
-- RISC-V compliant exceptions -- |
constant trap_ima_c : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0: instruction misaligned |
constant trap_iba_c : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1: instruction access fault |
constant trap_iil_c : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2: illegal instruction |
constant trap_brk_c : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3: breakpoint |
constant trap_lma_c : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4: load address misaligned |
constant trap_lbe_c : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5: load access fault |
constant trap_sma_c : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6: store address misaligned |
constant trap_sbe_c : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7: store access fault |
constant trap_menv_c : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode |
-- RISC-V compliant interrupts -- |
constant trap_msi_c : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3: machine software interrupt |
constant trap_mti_c : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7: machine timer interrupt |
constant trap_mei_c : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt |
-- NEORV32-specific (custom) interrupts -- |
constant trap_firq0_c : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0 |
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1 |
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2 |
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3 |
|
-- CPU Control Exception System ----------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
449,7 → 466,7
constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode |
constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode |
|
-- Clock Generator ------------------------------------------------------------------------- |
-- Clock Generator ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
constant clk_div2_c : natural := 0; |
constant clk_div4_c : natural := 1; |
470,12 → 487,13
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? |
-- Extension Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
517,6 → 535,7
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_lock_o : out std_ulogic; -- locked/exclusive bus access |
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
553,6 → 572,7
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
583,6 → 603,7
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation |
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
i_bus_lock_o : out std_ulogic; -- locked/exclusive access |
-- data bus interface -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
595,6 → 616,7
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error |
d_bus_fence_o : out std_ulogic; -- executed FENCE operation |
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level |
d_bus_lock_o : out std_ulogic; -- locked/exclusive access |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- interrupts (risc-v compliant) -- |
614,6 → 636,7
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
643,7 → 666,6
imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch |
curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction) |
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction) |
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
-- interrupts (risc-v compliant) -- |
msw_irq_i : in std_ulogic; -- machine software interrupt |
681,7 → 703,6
mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data |
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current pc |
-- data output -- |
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1 |
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2 |
796,6 → 817,7
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
i_bus_err_i : in std_ulogic; -- bus transfer error |
i_bus_fence_o : out std_ulogic; -- fence operation |
i_bus_lock_o : out std_ulogic; -- locked/exclusive access |
-- data bus -- |
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
806,7 → 828,8
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
d_bus_err_i : in std_ulogic; -- bus transfer error |
d_bus_fence_o : out std_ulogic -- fence operation |
d_bus_fence_o : out std_ulogic; -- fence operation |
d_bus_lock_o : out std_ulogic -- locked/exclusive access |
); |
end component; |
|
829,6 → 852,7
ca_bus_we_i : in std_ulogic; -- write enable |
ca_bus_re_i : in std_ulogic; -- read enable |
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction |
ca_bus_lock_i : in std_ulogic; -- locked/exclusive access |
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
ca_bus_err_o : out std_ulogic; -- bus transfer error |
-- controller interface b -- |
839,6 → 863,7
cb_bus_we_i : in std_ulogic; -- write enable |
cb_bus_re_i : in std_ulogic; -- read enable |
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction |
cb_bus_lock_i : in std_ulogic; -- locked/exclusive access |
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge |
cb_bus_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus -- |
850,6 → 875,7
p_bus_we_o : out std_ulogic; -- write enable |
p_bus_re_o : out std_ulogic; -- read enable |
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
p_bus_lock_o : out std_ulogic; -- locked/exclusive access |
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
p_bus_err_i : in std_ulogic -- bus transfer error |
); |
1105,31 → 1131,33
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
-- host access -- |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
cancel_i : in std_ulogic; -- cancel current bus transaction |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
cancel_i : in std_ulogic; -- cancel current bus transaction |
lock_i : in std_ulogic; -- locked/exclusive bus access |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level |
-- wishbone interface -- |
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_ack_i : in std_ulogic; -- transfer acknowledge |
wb_err_i : in std_ulogic -- transfer error |
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_lock_o : out std_ulogic; -- locked/exclusive bus access |
wb_ack_i : in std_ulogic; -- transfer acknowledge |
wb_err_i : in std_ulogic -- transfer error |
); |
end component; |
|
/rtl/core/neorv32_top.vhd
53,15 → 53,16
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? |
-- Extension Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
-- Physical Memory Protection (PMP) -- |
PMP_USE : boolean := false; -- implement PMP? |
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8) |
100,6 → 101,7
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_lock_o : out std_ulogic; -- locked/exclusive bus access |
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge |
wb_err_i : in std_ulogic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
172,6 → 174,7
fence : std_ulogic; -- fence(i) instruction executed |
priv : std_ulogic_vector(1 downto 0); -- current privilege level |
src : std_ulogic; -- access source |
lock : std_ulogic; -- locked/exclusive (=atomic) access |
end record; |
signal cpu_i, cpu_d, p_bus : bus_interface_t; |
|
248,11 → 251,6
-- memory system - layout warning -- |
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning; |
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning; |
-- (external) memory latency notifier (warning) -- |
assert not (MEM_EXT_USE = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning; |
-- external memory iterface protocol notifier (warning) -- |
assert not ((MEM_EXT_USE = true) and (wb_pipe_mode_c = false)) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol." severity warning; |
assert not ((MEM_EXT_USE = true) and (wb_pipe_mode_c = true)) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using PIEPLINED Wishbone protocol." severity warning; |
|
|
-- Reset Generator ------------------------------------------------------------------------ |
321,6 → 319,7
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id |
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
351,6 → 350,7
i_bus_err_i => cpu_i.err, -- bus transfer error |
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation |
i_bus_priv_o => cpu_i.priv, -- privilege level |
i_bus_lock_o => cpu_i.lock, -- locked/exclusive access |
-- data bus interface -- |
d_bus_addr_o => cpu_d.addr, -- bus access address |
d_bus_rdata_i => cpu_d.rdata, -- bus read data |
363,6 → 363,7
d_bus_err_i => cpu_d.err, -- bus transfer error |
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation |
d_bus_priv_o => cpu_d.priv, -- privilege level |
d_bus_lock_o => cpu_d.lock, -- locked/exclusive access |
-- system time input from MTIME -- |
time_i => mtime_time, -- current system time |
-- interrupts (risc-v compliant) -- |
407,6 → 408,7
ca_bus_we_i => cpu_d.we, -- write enable |
ca_bus_re_i => cpu_d.re, -- read enable |
ca_bus_cancel_i => cpu_d.cancel, -- cancel current bus transaction |
ca_bus_lock_i => cpu_d.lock, -- locked/exclusive access |
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge |
ca_bus_err_o => cpu_d.err, -- bus transfer error |
-- controller interface b -- |
417,6 → 419,7
cb_bus_we_i => cpu_i.we, -- write enable |
cb_bus_re_i => cpu_i.re, -- read enable |
cb_bus_cancel_i => cpu_i.cancel, -- cancel current bus transaction |
cb_bus_lock_i => cpu_i.lock, -- locked/exclusive access |
cb_bus_ack_o => cpu_i.ack, -- bus transfer acknowledge |
cb_bus_err_o => cpu_i.err, -- bus transfer error |
-- peripheral bus -- |
428,6 → 431,7
p_bus_we_o => p_bus.we, -- write enable |
p_bus_re_o => p_bus.re, -- read enable |
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction |
p_bus_lock_o => p_bus.lock, -- locked/exclusive access |
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge |
p_bus_err_i => p_bus.err -- bus transfer error |
); |
546,31 → 550,33
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active |
-- host access -- |
src_i => p_bus.src, -- access type (0: data, 1:instruction) |
addr_i => p_bus.addr, -- address |
rden_i => p_bus.re, -- read enable |
wren_i => p_bus.we, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => wishbone_rdata, -- data out |
cancel_i => p_bus.cancel, -- cancel current transaction |
ack_o => wishbone_ack, -- transfer acknowledge |
err_o => wishbone_err, -- transfer error |
priv_i => p_bus.priv, -- current CPU privilege level |
src_i => p_bus.src, -- access type (0: data, 1:instruction) |
addr_i => p_bus.addr, -- address |
rden_i => p_bus.re, -- read enable |
wren_i => p_bus.we, -- write enable |
ben_i => p_bus.ben, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => wishbone_rdata, -- data out |
cancel_i => p_bus.cancel, -- cancel current transaction |
lock_i => p_bus.lock, -- locked/exclusive bus access |
ack_o => wishbone_ack, -- transfer acknowledge |
err_o => wishbone_err, -- transfer error |
priv_i => p_bus.priv, -- current CPU privilege level |
-- wishbone interface -- |
wb_tag_o => wb_tag_o, -- tag |
wb_adr_o => wb_adr_o, -- address |
wb_dat_i => wb_dat_i, -- read data |
wb_dat_o => wb_dat_o, -- write data |
wb_we_o => wb_we_o, -- read/write |
wb_sel_o => wb_sel_o, -- byte enable |
wb_stb_o => wb_stb_o, -- strobe |
wb_cyc_o => wb_cyc_o, -- valid cycle |
wb_ack_i => wb_ack_i, -- transfer acknowledge |
wb_err_i => wb_err_i -- transfer error |
wb_tag_o => wb_tag_o, -- tag |
wb_adr_o => wb_adr_o, -- address |
wb_dat_i => wb_dat_i, -- read data |
wb_dat_o => wb_dat_o, -- write data |
wb_we_o => wb_we_o, -- read/write |
wb_sel_o => wb_sel_o, -- byte enable |
wb_stb_o => wb_stb_o, -- strobe |
wb_cyc_o => wb_cyc_o, -- valid cycle |
wb_lock_o => wb_lock_o, -- locked/exclusive bus access |
wb_ack_i => wb_ack_i, -- transfer acknowledge |
wb_err_i => wb_err_i -- transfer error |
); |
end generate; |
|
580,13 → 586,14
wishbone_ack <= '0'; |
wishbone_err <= '0'; |
-- |
wb_adr_o <= (others => '0'); |
wb_dat_o <= (others => '0'); |
wb_we_o <= '0'; |
wb_sel_o <= (others => '0'); |
wb_stb_o <= '0'; |
wb_cyc_o <= '0'; |
wb_tag_o <= (others => '0'); |
wb_adr_o <= (others => '0'); |
wb_dat_o <= (others => '0'); |
wb_we_o <= '0'; |
wb_sel_o <= (others => '0'); |
wb_stb_o <= '0'; |
wb_cyc_o <= '0'; |
wb_lock_o <= '0'; |
wb_tag_o <= (others => '0'); |
end generate; |
|
|
/rtl/core/neorv32_wishbone.vhd
2,12 → 2,17
-- # << NEORV32 - External Bus Interface (WISHBONE) >> # |
-- # ********************************************************************************************* # |
-- # The interface provides registers for all outgoing signals. If the host cancels a running # |
-- # transfer, the Wishbone arbiter still waits some time for the bus system to ACK to transfer. # |
-- # transfer, the Wishbone arbiter still waits some time for the bus system to ACK the transfer # |
-- # before the arbiter forces termination. # |
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - # |
-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- # |
-- # loader or the internal instruction or data memories (if implemented), are delegated via this # |
-- # Wishbone gateway to the external bus interface. # |
-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address # |
-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). # |
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - # |
-- # All bus accesses from the CPU, which do not target the internal IO region / the internal # |
-- # bootlloader / the internal instruction or data memories (if implemented), are delegated via # |
-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response # |
-- # latency of up to neorv32_package.vhd:bus_timeout_c - 2 cycles. # |
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - # |
-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) # |
-- # and also pipelined transactions (WB_PIPELINED_MODE = true). # |
-- # ********************************************************************************************* # |
51,7 → 56,7
|
entity neorv32_wishbone is |
generic ( |
WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode |
WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode |
-- Internal instruction memory -- |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
61,31 → 66,33
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active |
-- host access -- |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
cancel_i : in std_ulogic; -- cancel current bus transaction |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level |
src_i : in std_ulogic; -- access type (0: data, 1:instruction) |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
cancel_i : in std_ulogic; -- cancel current bus transaction |
lock_i : in std_ulogic; -- locked/exclusive bus access |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level |
-- wishbone interface -- |
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_ack_i : in std_ulogic; -- transfer acknowledge |
wb_err_i : in std_ulogic -- transfer error |
wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address |
wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data |
wb_we_o : out std_ulogic; -- read/write |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_ulogic; -- strobe |
wb_cyc_o : out std_ulogic; -- valid cycle |
wb_lock_o : out std_ulogic; -- locked/exclusive bus access |
wb_ack_i : in std_ulogic; -- transfer acknowledge |
wb_err_i : in std_ulogic -- transfer error |
); |
end neorv32_wishbone; |
|
92,31 → 99,31
architecture neorv32_wishbone_rtl of neorv32_wishbone is |
|
-- constants -- |
constant wb_timeout_c : natural := bus_timeout_c/2; |
constant xbus_timeout_c : natural := bus_timeout_c/4; |
|
-- access control -- |
signal int_imem_acc, int_imem_acc_real : std_ulogic; |
signal int_dmem_acc, int_dmem_acc_real : std_ulogic; |
signal int_boot_acc : std_ulogic; |
signal wb_access : std_ulogic; |
signal int_imem_acc : std_ulogic; |
signal int_dmem_acc : std_ulogic; |
signal int_boot_acc : std_ulogic; |
signal xbus_access : std_ulogic; |
|
-- bus arbiter |
type ctrl_state_t is (IDLE, BUSY, CANCELED, RESYNC); |
type ctrl_t is record |
state : ctrl_state_t; |
state_prev : ctrl_state_t; |
we : std_ulogic; |
rd_req : std_ulogic; |
wr_req : std_ulogic; |
adr : std_ulogic_vector(31 downto 0); |
wdat : std_ulogic_vector(31 downto 0); |
rdat : std_ulogic_vector(31 downto 0); |
sel : std_ulogic_vector(3 downto 0); |
ack : std_ulogic; |
err : std_ulogic; |
timeout : std_ulogic_vector(index_size_f(wb_timeout_c)-1 downto 0); |
src : std_ulogic; |
priv : std_ulogic_vector(1 downto 0); |
state : ctrl_state_t; |
we : std_ulogic; |
rd_req : std_ulogic; |
wr_req : std_ulogic; |
adr : std_ulogic_vector(31 downto 0); |
wdat : std_ulogic_vector(31 downto 0); |
rdat : std_ulogic_vector(31 downto 0); |
sel : std_ulogic_vector(3 downto 0); |
ack : std_ulogic; |
err : std_ulogic; |
timeout : std_ulogic_vector(index_size_f(xbus_timeout_c)-1 downto 0); |
src : std_ulogic; |
lock : std_ulogic; |
priv : std_ulogic_vector(1 downto 0); |
end record; |
signal ctrl : ctrl_t; |
signal stb_int : std_ulogic; |
126,24 → 133,22
|
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
assert not (bus_timeout_c <= 15) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (bus_timeout_c) should be >16 for interfacing external modules." severity error; |
-- max bus timeout latency lower than recommended -- |
assert not (bus_timeout_c <= 32) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (neorv32_package.vhd:bus_timeout_c) should be >32 when using external bus interface." severity error; |
-- external memory iterface protocol + max timeout latency notifier (warning) -- |
assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning; |
assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using PIEPLINED Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning; |
|
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- access to internal IMEM or DMEM? -- |
int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) else '0'; |
int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) else '0'; |
int_imem_acc_real <= int_imem_acc when (MEM_INT_IMEM_USE = true) else '0'; |
int_dmem_acc_real <= int_dmem_acc when (MEM_INT_DMEM_USE = true) else '0'; |
|
-- access to internal BOOTROM or IO devices? -- |
int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space |
--int_boot_acc <= '1' when (addr_i(31 downto index_size_f(2*boot_rom_max_size_c)) = boot_rom_base_c(31 downto index_size_f(2*boot_rom_max_size_c))) else '0'; -- this also covers access to the IO space |
--int_io_acc <= '1' when (addr_i >= io_base_c) else '0'; |
|
-- access to processor-internal IMEM or DMEM? -- |
int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) and (MEM_INT_IMEM_USE = true) else '0'; |
int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_USE = true) else '0'; |
-- access to processor-internal BOOTROM or IO devices? -- |
int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky! |
-- actual external bus access? -- |
wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc); |
xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc); |
|
-- Bus Arbiter ----------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
150,27 → 155,26
bus_arbiter: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
ctrl.state <= IDLE; |
ctrl.state_prev <= IDLE; |
ctrl.we <= '0'; |
ctrl.rd_req <= '0'; |
ctrl.wr_req <= '0'; |
ctrl.adr <= (others => '0'); |
ctrl.wdat <= (others => '0'); |
ctrl.rdat <= (others => '0'); |
ctrl.sel <= (others => '0'); |
ctrl.timeout <= (others => '0'); |
ctrl.ack <= '0'; |
ctrl.err <= '0'; |
ctrl.src <= '0'; |
ctrl.priv <= "00"; |
ctrl.state <= IDLE; |
ctrl.we <= '0'; |
ctrl.rd_req <= '0'; |
ctrl.wr_req <= '0'; |
ctrl.adr <= (others => '0'); |
ctrl.wdat <= (others => '0'); |
ctrl.rdat <= (others => '0'); |
ctrl.sel <= (others => '0'); |
ctrl.timeout <= (others => '0'); |
ctrl.ack <= '0'; |
ctrl.err <= '0'; |
ctrl.src <= '0'; |
ctrl.lock <= '0'; |
ctrl.priv <= "00"; |
elsif rising_edge(clk_i) then |
-- defaults -- |
ctrl.state_prev <= ctrl.state; |
ctrl.rdat <= (others => '0'); |
ctrl.ack <= '0'; |
ctrl.err <= '0'; |
ctrl.timeout <= std_ulogic_vector(to_unsigned(wb_timeout_c, index_size_f(wb_timeout_c))); |
ctrl.rdat <= (others => '0'); |
ctrl.ack <= '0'; |
ctrl.err <= '0'; |
ctrl.timeout <= std_ulogic_vector(to_unsigned(xbus_timeout_c, index_size_f(xbus_timeout_c))); |
|
-- state machine -- |
case ctrl.state is |
185,9 → 189,10
ctrl.wdat <= data_i; |
ctrl.sel <= ben_i; |
ctrl.src <= src_i; |
ctrl.lock <= lock_i; |
ctrl.priv <= priv_i; |
-- valid read/write access -- |
if ((wb_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then |
-- valid new or buffered read/write request -- |
if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then |
ctrl.state <= BUSY; |
end if; |
|
230,24 → 235,25
end process bus_arbiter; |
|
-- host access -- |
data_o <= ctrl.rdat; |
ack_o <= ctrl.ack; |
err_o <= ctrl.err; |
data_o <= ctrl.rdat; |
ack_o <= ctrl.ack; |
err_o <= ctrl.err; |
|
-- wishbone interface -- |
wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode |
wb_tag_o(1) <= '0'; -- 0=secure, 1=non-secure |
wb_tag_o(2) <= ctrl.src; -- 0=data access, 1=instruction access |
wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure |
wb_tag_o(2) <= ctrl.src; -- 0 = data access, 1 = instruction access |
|
wb_adr_o <= ctrl.adr; |
wb_dat_o <= ctrl.wdat; |
wb_we_o <= ctrl.we; |
wb_sel_o <= ctrl.sel; |
wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int; |
wb_cyc_o <= cyc_int; |
wb_adr_o <= ctrl.adr; |
wb_dat_o <= ctrl.wdat; |
wb_we_o <= ctrl.we; |
wb_sel_o <= ctrl.sel; |
wb_lock_o <= ctrl.lock; |
wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int; |
wb_cyc_o <= cyc_int; |
|
stb_int <= '1' when ((ctrl.state = BUSY) and (ctrl.state_prev = IDLE)) else '0'; |
cyc_int <= '0' when ((ctrl.state = IDLE) or (ctrl.state = RESYNC)) else '1'; |
stb_int <= '1' when (ctrl.state = BUSY) else '0'; |
cyc_int <= '0' when (ctrl.state = IDLE) or (ctrl.state = RESYNC) else '1'; |
|
|
end neorv32_wishbone_rtl; |
/rtl/top_templates/neorv32_cpu_stdlogic.vhd
45,12 → 45,13
HW_THREAD_ID : std_logic_vector(31 downto 0):= (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_logic_vector(31 downto 0):= (others => '0'); -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? |
-- Extension Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
75,6 → 76,7
i_bus_err_i : in std_logic := '0'; -- bus transfer error |
i_bus_fence_o : out std_logic; -- executed FENCEI operation |
i_bus_priv_o : out std_logic_vector(1 downto 0); -- privilege level |
i_bus_lock_o : out std_logic; -- locked/exclusive access |
-- data bus interface -- |
d_bus_addr_o : out std_logic_vector(data_width_c-1 downto 0); -- bus access address |
d_bus_rdata_i : in std_logic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
87,6 → 89,7
d_bus_err_i : in std_logic := '0'; -- bus transfer error |
d_bus_fence_o : out std_logic; -- executed FENCE operation |
d_bus_priv_o : out std_logic_vector(1 downto 0); -- privilege level |
d_bus_lock_o : out std_logic; -- locked/exclusive access |
-- system time input from MTIME -- |
time_i : in std_logic_vector(63 downto 0) := (others => '0'); -- current system time |
-- interrupts (risc-v compliant) -- |
117,6 → 120,7
signal i_bus_err_i_int, d_bus_err_i_int : std_ulogic; |
signal i_bus_fence_o_int, d_bus_fence_o_int : std_ulogic; |
signal i_bus_priv_o_int, d_bus_priv_o_int : std_ulogic_vector(1 downto 0); |
signal i_bus_lock_o_int, d_bus_lock_o_int : std_ulogic; |
-- |
signal time_i_int : std_ulogic_vector(63 downto 0); |
-- |
134,6 → 138,7
HW_THREAD_ID => HW_THREAD_ID_INT, -- hardware thread id |
CPU_BOOT_ADDR => CPU_BOOT_ADDR_INT, -- cpu boot address |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
164,6 → 169,7
i_bus_err_i => i_bus_err_i_int, -- bus transfer error |
i_bus_fence_o => i_bus_fence_o_int, -- executed FENCEI operation |
i_bus_priv_o => i_bus_priv_o_int, -- privilege level |
i_bus_lock_o => i_bus_lock_o_int, -- locked/exclusive access |
-- data bus interface -- |
d_bus_addr_o => d_bus_addr_o_int, -- bus access address |
d_bus_rdata_i => d_bus_rdata_i_int, -- bus read data |
176,6 → 182,7
d_bus_err_i => d_bus_err_i_int, -- bus transfer error |
d_bus_fence_o => d_bus_fence_o_int, -- executed FENCEI operation |
d_bus_priv_o => d_bus_priv_o_int, -- privilege level |
d_bus_lock_o => d_bus_lock_o_int, -- locked/exclusive access |
-- system time input from MTIME -- |
time_i => time_i_int, -- current system time |
-- interrupts (risc-v compliant) -- |
201,6 → 208,7
i_bus_err_i_int <= std_ulogic(i_bus_err_i); |
i_bus_fence_o <= std_logic(i_bus_fence_o_int); |
i_bus_priv_o <= std_logic_vector(i_bus_priv_o_int); |
i_bus_lock_o <= std_logic(i_bus_lock_o_int); |
|
d_bus_addr_o <= std_logic_vector(d_bus_addr_o_int); |
d_bus_rdata_i_int <= std_ulogic_vector(d_bus_rdata_i); |
213,6 → 221,7
d_bus_err_i_int <= std_ulogic(d_bus_err_i); |
d_bus_fence_o <= std_logic(d_bus_fence_o_int); |
d_bus_priv_o <= std_logic_vector(d_bus_priv_o_int); |
d_bus_lock_o <= std_logic(d_bus_lock_o_int); |
|
time_i_int <= std_ulogic_vector(time_i); |
|
/rtl/top_templates/neorv32_test_setup.vhd
74,10 → 74,11
USER_CODE => x"00000000", -- custom user code |
HW_THREAD_ID => x"00000000", -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension? |
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => false, -- implement muld/div extension? |
CPU_EXTENSION_RISCV_U => false, -- implement user mode extension? |
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension? |
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.? |
-- Extension Options -- |
121,6 → 122,7
wb_sel_o => open, -- byte enable |
wb_stb_o => open, -- strobe |
wb_cyc_o => open, -- valid cycle |
wb_lock_o => open, -- locked/exclusive bus access |
wb_ack_i => '0', -- transfer acknowledge |
wb_err_i => '0', -- transfer error |
-- Advanced memory control signals -- |
/rtl/top_templates/neorv32_top_axi4lite.vhd
49,12 → 49,13
USER_CODE : std_logic_vector(31 downto 0) := x"00000000"; -- custom user code |
HW_THREAD_ID : std_logic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? |
-- Extension Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
190,7 → 191,8
|
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG ERROR: AXI4-Lite bridge requires STANDARD Wishbone mode (package.wb_pipe_mode_c = false)!" severity error; |
assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG ERROR: AXI4-Lite bridge requires STANDARD/CLASSIC Wishbone mode (package.wb_pipe_mode_c = false)." severity error; |
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 PROCESSOR CONFIG WARNING: AXI4-Lite provides NO support for atomic memory operations." severity warning; |
|
|
-- The Core Of The Problem ---------------------------------------------------------------- |
203,6 → 205,7
USER_CODE => USER_CODE_INT, -- custom user code |
HW_THREAD_ID => HW_THREAD_ID_INT, -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
250,6 → 253,7
wb_sel_o => wb_core.sel, -- byte enable |
wb_stb_o => wb_core.stb, -- strobe |
wb_cyc_o => wb_core.cyc, -- valid cycle |
wb_lock_o => open, -- locked/exclusive bus access |
wb_ack_i => wb_core.ack, -- transfer acknowledge |
wb_err_i => wb_core.err, -- transfer error |
-- Advanced memory control signals -- |
/rtl/top_templates/neorv32_top_stdlogic.vhd
47,12 → 47,13
USER_CODE : std_logic_vector(31 downto 0) := x"00000000"; -- custom user code |
HW_THREAD_ID : std_logic_vector(31 downto 0) := (others => '0'); -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.? |
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? |
-- Extension Options -- |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations |
94,6 → 95,7
wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable |
wb_stb_o : out std_logic; -- strobe |
wb_cyc_o : out std_logic; -- valid cycle |
wb_lock_o : out std_logic; -- locked/exclusive bus access |
wb_ack_i : in std_logic := '0'; -- transfer acknowledge |
wb_err_i : in std_logic := '0'; -- transfer error |
-- Advanced memory control signals (available if MEM_EXT_USE = true) -- |
139,6 → 141,7
signal wb_sel_o_int : std_ulogic_vector(03 downto 0); |
signal wb_stb_o_int : std_ulogic; |
signal wb_cyc_o_int : std_ulogic; |
signal wb_lock_o_int : std_ulogic; |
signal wb_ack_i_int : std_ulogic; |
signal wb_err_i_int : std_ulogic; |
-- |
174,6 → 177,7
USER_CODE => USER_CODE_INT, -- custom user code |
HW_THREAD_ID => HW_THREAD_ID_INT, -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension? |
221,6 → 225,7
wb_sel_o => wb_sel_o_int, -- byte enable |
wb_stb_o => wb_stb_o_int, -- strobe |
wb_cyc_o => wb_cyc_o_int, -- valid cycle |
wb_lock_o => wb_lock_o_int, -- locked/exclusive bus access |
wb_ack_i => wb_ack_i_int, -- transfer acknowledge |
wb_err_i => wb_err_i_int, -- transfer error |
-- Advanced memory control signals -- |
260,6 → 265,7
wb_sel_o <= std_logic_vector(wb_sel_o_int); |
wb_stb_o <= std_logic(wb_stb_o_int); |
wb_cyc_o <= std_logic(wb_cyc_o_int); |
wb_lock_o <= std_logic(wb_lock_o_int); |
wb_ack_i_int <= std_ulogic(wb_ack_i); |
wb_err_i_int <= std_ulogic(wb_err_i); |
|
/sim/vivado/neorv32_tb_behav.wcfg
12,15 → 12,15
</db_ref> |
</db_ref_list> |
<zoom_setting> |
<ZoomStartTime time="5295000fs"></ZoomStartTime> |
<ZoomEndTime time="5412501fs"></ZoomEndTime> |
<Cursor1Time time="5715000fs"></Cursor1Time> |
<ZoomStartTime time="1325333fs"></ZoomStartTime> |
<ZoomEndTime time="1342434fs"></ZoomEndTime> |
<Cursor1Time time="1349733fs"></Cursor1Time> |
</zoom_setting> |
<column_width_setting> |
<NameColumnWidth column_width="203"></NameColumnWidth> |
<ValueColumnWidth column_width="111"></ValueColumnWidth> |
<ValueColumnWidth column_width="103"></ValueColumnWidth> |
</column_width_setting> |
<WVObjectSize size="108" /> |
<WVObjectSize size="111" /> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.FETCH</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
60,7 → 60,6
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/fetch_engine" type="array"> |
<obj_property name="ElementShortName">fetch_engine</obj_property> |
<obj_property name="ObjectShortName">fetch_engine</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.IPB</obj_property> |
69,7 → 68,6
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ipb" type="array"> |
<obj_property name="ElementShortName">ipb</obj_property> |
<obj_property name="ObjectShortName">ipb</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.ISSUE</obj_property> |
78,7 → 76,6
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/issue_engine" type="array"> |
<obj_property name="ElementShortName">issue_engine</obj_property> |
<obj_property name="ObjectShortName">issue_engine</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ci_instr16" type="array"> |
<obj_property name="ElementShortName">ci_instr16[15:0]</obj_property> |
117,8 → 114,8
<obj_property name="ObjectShortName">be_store_i</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ctrl_o" type="array"> |
<obj_property name="ElementShortName">ctrl_o[59:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_o[59:0]</obj_property> |
<obj_property name="ElementShortName">ctrl_o[62:0]</obj_property> |
<obj_property name="ObjectShortName">ctrl_o[62:0]</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/ci_instr32" type="array"> |
<obj_property name="ElementShortName">ci_instr32[31:0]</obj_property> |
165,12 → 162,12
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg" type="array"> |
<obj_property name="ElementShortName">.i_reg[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg_nxt" type="array"> |
<obj_property name="ElementShortName">.i_reg_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.i_reg_nxt[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.i_reg_last" type="array"> |
<obj_property name="ElementShortName">.i_reg_last[31:0]</obj_property> |
207,12 → 204,12
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc" type="array"> |
<obj_property name="ElementShortName">.pc[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.pc_nxt" type="array"> |
<obj_property name="ElementShortName">.pc_nxt[31:0]</obj_property> |
<obj_property name="ObjectShortName">.pc_nxt[31:0]</obj_property> |
<obj_property name="CustomSignalColor">#FFFFFF</obj_property> |
<obj_property name="UseCustomSignalColor">true</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/execute_engine.next_pc" type="array"> |
<obj_property name="ElementShortName">.next_pc[31:0]</obj_property> |
244,6 → 241,15
</wvobject> |
</wvobject> |
<wvobject type="divider" fp_name="divider139"> |
<obj_property name="label">CPU: Control.ATOMICS</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/atomic_ctrl" type="array"> |
<obj_property name="ElementShortName">atomic_ctrl</obj_property> |
<obj_property name="ObjectShortName">atomic_ctrl</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider139"> |
<obj_property name="label">CPU: Control.TRAP</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
316,6 → 322,7
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_alu_inst/cp_ctrl" type="array"> |
<obj_property name="ElementShortName">cp_ctrl</obj_property> |
<obj_property name="ObjectShortName">cp_ctrl</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider367"> |
<obj_property name="label">CPU: BUS_UNIT</obj_property> |
546,7 → 553,6
<wvobject fp_name="/neorv32_tb/wb_cpu" type="array"> |
<obj_property name="ElementShortName">wb_cpu</obj_property> |
<obj_property name="ObjectShortName">wb_cpu</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/wb_mem_a" type="array"> |
<obj_property name="ElementShortName">wb_mem_a</obj_property> |
556,4 → 562,8
<obj_property name="ElementShortName">wb_mem_b</obj_property> |
<obj_property name="ObjectShortName">wb_mem_b</obj_property> |
</wvobject> |
<wvobject fp_name="/neorv32_tb/wb_mem_c" type="array"> |
<obj_property name="ElementShortName">wb_mem_c</obj_property> |
<obj_property name="ObjectShortName">wb_mem_c</obj_property> |
</wvobject> |
</wave_config> |
/sim/neorv32_tb.vhd
61,31 → 61,35
-- User Configuration --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- general -- |
constant boot_external_c : boolean := false; -- false: boot from proc-internal IMEM, true: boot from (initialized) simulated ext. mem A |
constant ext_imem_c : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A) |
constant ext_dmem_c : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B) |
constant imem_size_c : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A |
constant dmem_size_c : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B |
constant f_clock_c : natural := 100000000; -- main clock in Hz |
-- UART -- |
constant baud_rate_c : natural := 19200; -- standard UART baudrate |
constant baud_rate_c : natural := 19200; -- simulation UART output baudrate |
-- simulated external Wishbone memory A (can be used as external IMEM) -- |
constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (IMEM base) |
constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base) |
constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes |
constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay |
-- simulated external Wishbone memory B (can be used as external IO) -- |
constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area) |
constant ext_mem_b_size_c : natural := 64; -- wishbone memory size in bytes |
constant ext_mem_b_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay |
-- simulated external Wishbone memory B (can be used as external DMEM) -- |
constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base) |
constant ext_mem_b_size_c : natural := dmem_size_c; -- wishbone memory size in bytes |
constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay |
-- simulated external Wishbone memory C (can be used as external IO) -- |
constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area) |
constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes |
constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay |
-- ------------------------------------------------------------------------------------------- |
|
-- internals - hands off! -- |
constant boot_imem_c : boolean := not boot_external_c; |
constant int_imem_c : boolean := not ext_imem_c; |
constant int_dmem_c : boolean := not ext_dmem_c; |
constant baud_val_c : real := real(f_clock_c) / real(baud_rate_c); |
constant t_clock_c : time := (1 sec) / f_clock_c; |
|
-- text.io -- |
file file_uart_tx_out : text open write_mode is "neorv32.testbench_uart.out"; |
|
-- internal configuration -- |
constant baud_val_c : real := real(f_clock_c) / real(baud_rate_c); |
constant t_clock_c : time := (1 sec) / f_clock_c; |
|
-- generators -- |
signal clk_gen, rst_gen : std_ulogic := '0'; |
|
118,12 → 122,14
ack : std_ulogic; -- transfer acknowledge |
err : std_ulogic; -- transfer error |
tag : std_ulogic_vector(2 downto 0); -- tag |
lock : std_ulogic; -- locked/exclusive bus access |
end record; |
signal wb_cpu, wb_mem_a, wb_mem_b : wishbone_t; |
signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c : wishbone_t; |
|
-- Wishbone memories -- |
type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0); |
type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0); |
type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0); |
type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0); |
|
-- init function -- |
139,8 → 145,9
end function init_wbmem; |
|
-- external memory components -- |
signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external instruction boot memory |
signal ext_ram_b : ext_mem_b_ram_t; -- uninitialized, used to simulate external IO |
signal ext_ram_a : ext_mem_a_ram_t := init_wbmem(application_init_image); -- initialized, used to simulate external IMEM |
signal ext_ram_b : ext_mem_b_ram_t := (others => (others => '0')); -- zero, used to simulate external DMEM |
signal ext_ram_c : ext_mem_c_ram_t; -- uninitialized, used to simulate external IO |
|
type ext_mem_t is record |
rdata : ext_mem_read_latency_t; |
147,7 → 154,7
acc_en : std_ulogic; |
ack : std_ulogic_vector(ext_mem_a_latency_c-1 downto 0); |
end record; |
signal ext_mem_a, ext_mem_b : ext_mem_t; |
signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t; |
|
begin |
|
167,6 → 174,7
USER_CODE => x"12345678", -- custom user code |
HW_THREAD_ID => x"00000000", -- hardware thread id (hartid) |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension? |
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension? |
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension? |
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension? |
181,12 → 189,12
PMP_NUM_REGIONS => 4, -- number of regions (max 16) |
PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k |
-- Internal Instruction memory -- |
MEM_INT_IMEM_USE => boot_imem_c, -- implement processor-internal instruction memory |
MEM_INT_IMEM_USE => int_imem_c , -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM |
-- Internal Data memory -- |
MEM_INT_DMEM_USE => true, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes |
MEM_INT_DMEM_USE => int_dmem_c, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes |
-- External memory interface -- |
MEM_EXT_USE => true, -- implement external memory bus interface? |
-- Processor peripherals -- |
197,7 → 205,7
IO_TWI_USE => true, -- implement two-wire interface (TWI)? |
IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => true, -- implement watch dog timer (WDT)? |
IO_TRNG_USE => false, -- DEFAULT TRNG CONFIG CANNOT BE SIMULATED! |
IO_TRNG_USE => false, -- trng cannot be simulated |
IO_CFU0_USE => true, -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_USE => true -- implement custom functions unit 1 (CFU1)? |
) |
214,6 → 222,7
wb_sel_o => wb_cpu.sel, -- byte enable |
wb_stb_o => wb_cpu.stb, -- strobe |
wb_cyc_o => wb_cpu.cyc, -- valid cycle |
wb_lock_o => wb_cpu.lock, -- locked/exclusive bus access |
wb_ack_i => wb_cpu.ack, -- transfer acknowledge |
wb_err_i => wb_cpu.err, -- transfer error |
-- Advanced memory control signals -- |
302,29 → 311,41
-- ------------------------------------------------------------------------------------------- |
-- CPU broadcast signals -- |
wb_mem_a.addr <= wb_cpu.addr; |
wb_mem_a.wdata <= wb_cpu.wdata; |
wb_mem_a.we <= wb_cpu.we; |
wb_mem_a.sel <= wb_cpu.sel; |
wb_mem_a.tag <= wb_cpu.tag; |
wb_mem_a.cyc <= wb_cpu.cyc; |
wb_mem_a.lock <= wb_cpu.lock; |
|
wb_mem_b.addr <= wb_cpu.addr; |
wb_mem_a.wdata <= wb_cpu.wdata; |
wb_mem_b.wdata <= wb_cpu.wdata; |
wb_mem_a.we <= wb_cpu.we; |
wb_mem_b.we <= wb_cpu.we; |
wb_mem_a.sel <= wb_cpu.sel; |
wb_mem_b.sel <= wb_cpu.sel; |
wb_mem_a.tag <= wb_cpu.tag; |
wb_mem_b.tag <= wb_cpu.tag; |
wb_mem_a.cyc <= wb_cpu.cyc; |
wb_mem_b.cyc <= wb_cpu.cyc; |
|
wb_mem_b.lock <= wb_cpu.lock; |
|
wb_mem_c.addr <= wb_cpu.addr; |
wb_mem_c.wdata <= wb_cpu.wdata; |
wb_mem_c.we <= wb_cpu.we; |
wb_mem_c.sel <= wb_cpu.sel; |
wb_mem_c.tag <= wb_cpu.tag; |
wb_mem_c.cyc <= wb_cpu.cyc; |
wb_mem_c.lock <= wb_cpu.lock; |
|
-- CPU read-back signals (no mux here since peripherals have "output gates") -- |
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata; |
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack; |
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err; |
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata; |
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack; |
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err; |
|
-- peripheral select via STROBE signal -- |
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0'; |
wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0'; |
wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0'; |
|
|
-- Wishbone Memory A (simulated external memory) ------------------------------------------ |
-- Wishbone Memory A (simulated external IMEM) -------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ext_mem_a_access: process(clk_gen) |
begin |
364,7 → 385,7
end process ext_mem_a_access; |
|
|
-- Wishbone Memory B (simulated external memory) ------------------------------------------ |
-- Wishbone Memory B (simulated external DMEM) -------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ext_mem_b_access: process(clk_gen) |
begin |
404,4 → 425,46
end process ext_mem_b_access; |
|
|
-- Wishbone Memory C (simulated external IO) ---------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ext_mem_c_access: process(clk_gen) |
begin |
if rising_edge(clk_gen) then |
-- control -- |
ext_mem_c.ack(0) <= wb_mem_c.cyc and wb_mem_c.stb; -- wishbone acknowledge |
|
-- write access -- |
if ((wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.we) = '1') then -- valid write access |
for i in 0 to 3 loop |
if (wb_mem_c.sel(i) = '1') then |
ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_mem_c.wdata(7+i*8 downto 0+i*8); |
end if; |
end loop; -- i |
end if; |
|
-- read access -- |
ext_mem_c.rdata(0) <= ext_ram_c(to_integer(unsigned(wb_mem_c.addr(index_size_f(ext_mem_c_size_c/4)+1 downto 2)))); -- word aligned |
-- virtual read and ack latency -- |
if (ext_mem_c_latency_c > 1) then |
for i in 1 to ext_mem_c_latency_c-1 loop |
ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1); |
ext_mem_c.ack(i) <= ext_mem_c.ack(i-1) and wb_mem_c.cyc; |
end loop; |
end if; |
|
-- error to simulate interrupted LOCKED/EXCLUSIVE bus access -- |
wb_mem_c.err <= wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.lock and wb_mem_c.addr(2); -- locked access to odd word-addresses will fail |
|
-- bus output register -- |
if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') then |
wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1); |
wb_mem_c.ack <= '1'; |
else |
wb_mem_c.rdata <= (others => '0'); |
wb_mem_c.ack <= '0'; |
end if; |
end if; |
end process ext_mem_c_access; |
|
|
end neorv32_tb_rtl; |
/sw/bootloader/bootloader.c
69,6 → 69,8
#define AUTOBOOT_TIMEOUT 8 |
/** Set to 0 to disable bootloader status LED */ |
#define STATUS_LED_EN (1) |
/** SPI_DIRECT_BOOT_EN: Define/uncomment to enable SPI direct boot (disables the entire user console!) */ |
//#define SPI_DIRECT_BOOT_EN |
/** Bootloader status LED at GPIO output port */ |
#define STATUS_LED (0) |
/** SPI flash boot image base address (warning! address might wrap-around!) */ |
181,11 → 183,27
**************************************************************************/ |
int main(void) { |
|
#ifdef __riscv_compressed |
#warning In order to allow the bootloader to run on any CPU configuration it should be compiled using the base ISA (rv32i/e) only. |
#endif |
|
// global variable for executable size; 0 means there is no exe available |
exe_available = 0; |
|
// ------------------------------------------------ |
// Processor hardware initialization |
// Minimal CPU hardware initialization |
// - all IO devices are reset and disabled by the crt0 code |
// ------------------------------------------------ |
|
// confiure trap handler (bare-metal, no neorv32 rte available) |
neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&bootloader_trap_handler)); |
|
|
// ------------------------------------------------ |
// Minimal processor hardware initialization |
// - all IO devices are reset and disabled by the crt0 code |
// ------------------------------------------------ |
|
// get clock speed (in Hz) |
uint32_t clock_speed = SYSINFO_CLK; |
|
197,6 → 215,11
neorv32_spi_setup(CLK_PRSC_128, 0, 0, 0); |
} |
|
if (STATUS_LED_EN == 1) { |
// activate status LED, clear all others |
neorv32_gpio_port_set(1 << STATUS_LED); |
} |
|
// init UART (no interrupts) |
neorv32_uart_setup(BAUD_RATE, 0, 0); |
|
203,21 → 226,30
// Configure machine system timer interrupt for ~2Hz |
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (clock_speed/4)); |
|
// confiure trap handler (bare-metal, no neorv32 rte available) |
neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&bootloader_trap_handler)); |
|
neorv32_cpu_csr_write(CSR_MIE, 1 << CPU_MIE_MTIE); // activate MTIME IRQ source |
neorv32_cpu_eint(); // enable global interrupts |
|
if (STATUS_LED_EN == 1) { |
// activate status LED, clear all others |
neorv32_gpio_port_set(1 << STATUS_LED); |
} |
|
// global variable to executable size; 0 means there is no exe available |
exe_available = 0; |
// ------------------------------------------------ |
// Fast boot mode: Direct SPI boot |
// Bootloader will directly boot and execute image from SPI memory. |
// No user UART console is available in this mode! |
// ------------------------------------------------ |
#ifdef SPI_DIRECT_BOOT_EN |
#warning Compiling bootloader in 'SPI direct boot mode'. Bootloader will directly boot from SPI memory. No user UART console will be available. |
|
neorv32_uart_print("\nNEORV32 bootloader\nAccessing SPI flash at "); |
print_hex_word((uint32_t)SPI_FLASH_BOOT_ADR); |
neorv32_uart_print("\n"); |
|
get_exe(EXE_STREAM_FLASH); |
neorv32_uart_print("\n"); |
start_app(); |
|
return 0; |
#endif |
|
|
// ------------------------------------------------ |
// Show bootloader intro and system info |
// ------------------------------------------------ |
352,9 → 384,9
return; |
} |
|
// no need to shut down or reset the used peripherals |
// no need to shut down/reset the used peripherals |
// no need to disable interrupt sources |
// -> this will be done by application's crt0 |
// -> crt0 will do a clean CPU/processor reset/setup |
|
// deactivate global IRQs |
neorv32_cpu_dint(); |
364,12 → 396,6
// wait for UART to finish transmitting |
while ((UART_CT & (1<<UART_CT_TX_BUSY)) != 0); |
|
// reset performance counters (to benchmark actual application) |
asm volatile ("csrw mcycle, zero"); // also clears 'cycle' |
asm volatile ("csrw mcycleh, zero"); // also clears 'cycleh' |
asm volatile ("csrw minstret, zero"); // also clears 'instret' |
asm volatile ("csrw minstreth, zero"); // also clears 'instreth' |
|
// start app at instruction space base address |
register uint32_t app_base = SYSINFO_ISPACE_BASE; |
asm volatile ("jalr zero, %0" : : "r" (app_base)); |
668,7 → 694,7
|
data.uint32 = wdata; |
|
uint32_t i; |
int i; |
for (i=0; i<4; i++) { |
spi_flash_write_byte(addr + i, data.uint8[3-i]); |
} |
761,7 → 787,8
|
address.uint32 = addr; |
|
neorv32_spi_trans(address.uint8[2]); |
neorv32_spi_trans(address.uint8[1]); |
neorv32_spi_trans(address.uint8[0]); |
int i; |
for (i=2; i>=0; i--) { |
neorv32_spi_trans(address.uint8[i]); |
} |
} |
/sw/common/crt0.S
104,7 → 104,7
|
|
// ********************************************************* |
// Setup pointers using linker script symbol |
// Setup pointers using linker script symbols |
// ********************************************************* |
__crt0_pointer_init: |
.option push |
117,7 → 117,7
|
|
// ********************************************************* |
// Init trap handler base address |
// Initialize dummy trap handler base address |
// ********************************************************* |
__crt0_neorv32_trap_init: |
la x11, __crt0_dummy_trap_handler |
174,13 → 174,20
|
|
// ********************************************************* |
// Call main function (with argc = argv = 0) |
// Call main function |
// ********************************************************* |
__crt0_main_entry: |
|
// setup arguments for calling main |
addi x10, zero, 0 // argc = 0 |
addi x11, zero, 0 // argv = 0 |
|
// clear cycle and instruction counters |
csrw mcycle, zero |
csrw mcycleh, zero |
csrw minstret, zero |
csrw minstreth, zero |
|
jal ra, main |
|
|
189,8 → 196,10
// ********************************************************* |
__crt0_this_is_the_end: |
csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE) |
nop |
wfi |
j . // in case WFI is not available |
__crt0_this_is_the_end_my_friend: |
j __crt0_this_is_the_end_my_friend // in case WFI is not available |
|
|
// ********************************************************* |
/sw/example/cpu_test/main.c
79,6 → 79,17
|
|
/**********************************************************************//** |
* "Simulated external IO" - exclusive access will always succeed |
**************************************************************************/ |
# define ATOMIC_SUCCESS (*(IO_REG32 (EXT_MEM_BASE + 0))) |
|
/**********************************************************************//** |
* "Simulated external IO" - exclusive access will always fail |
**************************************************************************/ |
# define ATOMIC_FAILURE (*(IO_REG32 (EXT_MEM_BASE + 4))) |
|
|
/**********************************************************************//** |
* This program uses mostly synthetic case to trigger all implemented exceptions. |
* Each exception is captured and evaluated for correct detection. |
* |
1214,6 → 1225,72
|
|
// ---------------------------------------------------------- |
// Test atomic LR/SC operation - should succeed |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (succeeding access): ", cnt_test); |
|
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation |
|
// skip if A-mode is implemented |
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) { |
|
cnt_test++; |
|
ATOMIC_SUCCESS = 0x11223344; |
|
// atomic compare-and-swap |
if ((neorv32_cpu_atomic_cas((uint32_t)(&ATOMIC_SUCCESS), 0x11223344, 0xAABBCCDD) == 0) && |
(ATOMIC_SUCCESS == 0xAABBCCDD) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
} |
else { |
neorv32_uart_printf("skipped (A extension not implemented)\n"); |
} |
} |
else { |
neorv32_uart_printf("skipped (on real hardware)\n"); |
} |
|
|
// ---------------------------------------------------------- |
// Test atomic LR/SC operation - should fail |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (failing access): ", cnt_test); |
|
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation |
|
// skip if A-mode is implemented |
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) { |
|
cnt_test++; |
|
ATOMIC_FAILURE = 0x55667788; |
|
// atomic compare-and-swap |
if ((neorv32_cpu_atomic_cas((uint32_t)(&ATOMIC_FAILURE), 0x55667788, 0xEEFFDDBB) != 0) && (ATOMIC_FAILURE == 0x55667788)) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
} |
else { |
neorv32_uart_printf("skipped (A extension not implemented)\n"); |
} |
} |
else { |
neorv32_uart_printf("skipped (on real hardware)\n"); |
} |
|
|
|
// ---------------------------------------------------------- |
// Final test reports |
// ---------------------------------------------------------- |
neorv32_uart_printf("\nExecuted instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); |
/sw/example/demo_gpio_irq/main.c
0,0 → 1,155
// ################################################################################################# |
// # << NEORV32 - GPIO pin-change interrupt demo >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
// # # |
// # Redistribution and use in source and binary forms, with or without modification, are # |
// # permitted provided that the following conditions are met: # |
// # # |
// # 1. Redistributions of source code must retain the above copyright notice, this list of # |
// # conditions and the following disclaimer. # |
// # # |
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
// # conditions and the following disclaimer in the documentation and/or other materials # |
// # provided with the distribution. # |
// # # |
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
// # endorse or promote products derived from this software without specific prior written # |
// # permission. # |
// # # |
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
// # OF THE POSSIBILITY OF SUCH DAMAGE. # |
// # ********************************************************************************************* # |
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
// ################################################################################################# |
|
|
/**********************************************************************//** |
* @file demo_gpio_irq/main.c |
* @author Stephan Nolting |
* @brief Simple GPIO input pin-change interrupt example. |
**************************************************************************/ |
|
#include <neorv32.h> |
|
|
/**********************************************************************//** |
* @name User configuration |
**************************************************************************/ |
/**@{*/ |
/** UART BAUD rate */ |
#define BAUD_RATE 19200 |
/**@}*/ |
|
|
/**********************************************************************//** |
* GPIO pin-change interrupt handler (has to be a NORMAL function!) |
**************************************************************************/ |
void gpio_pin_change_irq_handler(void); |
|
|
/**********************************************************************//** |
* Simple demo program to show the GPIO pin-change interrupt feature. Whenever a gpio.input(7:0) pin changes |
* its state (low-to-high or high-to-low) a message is send via UART and a counter on gpio.out(7:0) is incremented. |
* |
* @note This program requires the GPIO controller to be synthesized (the UART is optional). |
* @note This program assumes high-active buttons connected to gpio.in(7:0). |
* @note This program assumes high-active LEDS connected to gpio.out(7:0). |
* |
* @return Irrelevant. |
**************************************************************************/ |
int main() { |
|
// setup run-time environment for interrupts and exceptions |
neorv32_rte_setup(); |
|
// init UART at default baud rate, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0, 0); |
|
|
// check if GPIO unit is implemented at all |
if (neorv32_gpio_available() == 0) { |
neorv32_uart_print("ERROR! GPIO unit not synthesized!\n"); |
return 0; |
} |
|
// say hello |
neorv32_uart_print("GPIO pin-change interrupt demo program.\n"); |
|
|
// clear all outputs |
neorv32_gpio_port_set(0); |
|
|
// wait for user to hit the start button |
neorv32_uart_print("Push button at GPIO.in(0) to start.\n"); |
|
while(1) { |
if (neorv32_gpio_pin_get(0)) { |
break; |
} |
} |
|
neorv32_uart_print("Started!\n"); |
|
|
// The pin-change interrupt of the GPIO module is connected to the |
// CPU's fast interrupt input channel 1 (= FIRQ1). |
|
// install interrupt handler for GPIO pin-change interrupt |
int install_err = 0; |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_1, gpio_pin_change_irq_handler); |
|
if (install_err) { |
neorv32_uart_printf("RTE install error!\n"); |
return 0; |
} |
|
// activate fast interrupt channel 1 (which is GPIO_PIN_CHANGE) |
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E); |
|
// activate GPIO pin-change irq only for input pins 0 to 7 |
neorv32_gpio_pin_change_config(0x000000ff); |
|
// enable global interrupts |
neorv32_cpu_eint(); |
|
|
neorv32_uart_printf("Press any button to trigger the GPIO pin-change interrupt.\n"); |
neorv32_uart_printf("This will trigger an UART message and increment a counter on GPIO.out(7:0).\n"); |
|
// go to endless sleep mode |
while(1) { |
neorv32_cpu_sleep(); |
} |
|
return 0; |
} |
|
|
/**********************************************************************//** |
* Interrupt handler for the GPIO pin-change interrupt. |
* @warning This has to be a normal function without any attributes when using the NEORV32 RTE (run-time environment)! |
**************************************************************************/ |
void gpio_pin_change_irq_handler(void) { |
|
// if ANY of the input pins, which have an enabled IRQ-mask via neorv32_gpio_pin_change_config(), toggles it's state |
// (low-to-high or high-to-low) this handler gets called |
|
uint32_t cnt = GPIO_OUTPUT; // get current state of GPIO.out port |
cnt++; // increment counter |
cnt = cnt & 0xff; // mask, only keep lowest 8 bits |
GPIO_OUTPUT = cnt; // set new state of GPIO.out port |
|
neorv32_uart_printf("GPIO pin-change IRQ triggered!\n"); |
} |
|
/sw/example/demo_gpio_irq/makefile
0,0 → 1,338
################################################################################################# |
# << NEORV32 - Application Makefile >> # |
# ********************************************************************************************* # |
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. # |
# ********************************************************************************************* # |
# BSD 3-Clause License # |
# # |
# Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
# # |
# Redistribution and use in source and binary forms, with or without modification, are # |
# permitted provided that the following conditions are met: # |
# # |
# 1. Redistributions of source code must retain the above copyright notice, this list of # |
# conditions and the following disclaimer. # |
# # |
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
# conditions and the following disclaimer in the documentation and/or other materials # |
# provided with the distribution. # |
# # |
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
# endorse or promote products derived from this software without specific prior written # |
# permission. # |
# # |
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
# OF THE POSSIBILITY OF SUCH DAMAGE. # |
# ********************************************************************************************* # |
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
################################################################################################# |
|
|
# ***************************************************************************** |
# USER CONFIGURATION |
# ***************************************************************************** |
# User's application sources (*.c, *.cpp, *.s, *.S); add additional files here |
APP_SRC ?= $(wildcard ./*.c) $(wildcard ./*.s) $(wildcard ./*.cpp) $(wildcard ./*.S) |
|
# User's application include folders (don't forget the '-I' before each entry) |
APP_INC ?= -I . |
# User's application include folders - for assembly files only (don't forget the '-I' before each entry) |
ASM_INC ?= -I . |
|
# Optimization |
EFFORT ?= -Os |
|
# Compiler toolchain |
RISCV_TOOLCHAIN ?= riscv32-unknown-elf |
|
# CPU architecture and ABI |
MARCH ?= -march=rv32i |
MABI ?= -mabi=ilp32 |
|
# User flags for additional configuration (will be added to compiler flags) |
USER_FLAGS ?= |
|
# Serial port for executable upload via bootloer |
COM_PORT ?= /dev/ttyUSB0 |
|
# Relative or absolute path to the NEORV32 home folder |
NEORV32_HOME ?= ../../.. |
# ***************************************************************************** |
|
|
|
# ----------------------------------------------------------------------------- |
# NEORV32 framework |
# ----------------------------------------------------------------------------- |
# Path to NEORV32 linker script and startup file |
NEORV32_COM_PATH = $(NEORV32_HOME)/sw/common |
# Path to main NEORV32 library include files |
NEORV32_INC_PATH = $(NEORV32_HOME)/sw/lib/include |
# Path to main NEORV32 library source files |
NEORV32_SRC_PATH = $(NEORV32_HOME)/sw/lib/source |
# Path to NEORV32 executable generator |
NEORV32_EXG_PATH = $(NEORV32_HOME)/sw/image_gen |
# Path to NEORV32 core rtl folder |
NEORV32_RTL_PATH = $(NEORV32_HOME)/rtl/core |
# Marker file to check for NEORV32 home folder |
NEORV32_HOME_MARKER = $(NEORV32_INC_PATH)/neorv32.h |
|
# Core libraries (peripheral and CPU drivers) |
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c) |
# Application start-up code |
CORE_SRC += $(NEORV32_COM_PATH)/crt0.S |
|
# Linker script |
LD_SCRIPT = $(NEORV32_COM_PATH)/neorv32.ld |
|
# Main output files |
APP_EXE = neorv32_exe.bin |
APP_ASM = main.asm |
APP_IMG = neorv32_application_image.vhd |
BOOT_IMG = neorv32_bootloader_image.vhd |
|
|
# ----------------------------------------------------------------------------- |
# Sources and objects |
# ----------------------------------------------------------------------------- |
# Define all sources |
SRC = $(APP_SRC) |
SRC += $(CORE_SRC) |
|
# Define all object files |
OBJ = $(SRC:%=%.o) |
|
|
# ----------------------------------------------------------------------------- |
# Tools and flags |
# ----------------------------------------------------------------------------- |
# Compiler tools |
CC = $(RISCV_TOOLCHAIN)-gcc |
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump |
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy |
SIZE = $(RISCV_TOOLCHAIN)-size |
|
# Host native compiler |
CC_X86 = gcc -Wall -O -g |
|
# NEORV32 executable image generator |
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen |
|
# Compiler & linker flags |
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles |
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc |
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled) |
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4 |
CC_OPTS += $(USER_FLAGS) |
|
|
# ----------------------------------------------------------------------------- |
# Application output definitions |
# ----------------------------------------------------------------------------- |
.PHONY: check info help elf_info clean clean_all bootloader |
.DEFAULT_GOAL := help |
|
# 'compile' is still here for compatibility |
exe: $(APP_ASM) $(APP_EXE) |
compile: $(APP_ASM) $(APP_EXE) |
install: $(APP_ASM) $(APP_IMG) |
all: $(APP_ASM) $(APP_EXE) $(APP_IMG) |
|
# Check if making bootloader |
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM) |
# Also define "make_bootloader" for crt0.S |
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader |
|
|
# ----------------------------------------------------------------------------- |
# Image generator targets |
# ----------------------------------------------------------------------------- |
# install/compile tools |
$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.cpp |
@echo Compiling $(IMAGE_GEN) |
@$(CC_X86) $< -o $(IMAGE_GEN) |
|
|
# ----------------------------------------------------------------------------- |
# General targets: Assemble, compile, link, dump |
# ----------------------------------------------------------------------------- |
# Compile app *.s sources (assembly) |
%.s.o: %.s |
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@ |
|
# Compile app *.S sources (assembly + C pre-processor) |
%.S.o: %.S |
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@ |
|
# Compile app *.c sources |
%.c.o: %.c |
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@ |
|
# Compile app *.cpp sources |
%.cpp.o: %.cpp |
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@ |
|
# Link object files and show memory utilization |
main.elf: $(OBJ) |
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ |
@echo "Memory utilization:" |
@$(SIZE) main.elf |
|
# Assembly listing file (for debugging) |
$(APP_ASM): main.elf |
@$(OBJDUMP) -d -S -z $< > $@ |
|
# Generate final executable from .text + .rodata + .data (in THIS order!) |
main.bin: main.elf $(APP_ASM) |
@$(OBJCOPY) -I elf32-little $< -j .text -O binary text.bin |
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.bin |
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.bin |
@cat text.bin rodata.bin data.bin > $@ |
@rm -f text.bin rodata.bin data.bin |
|
|
# ----------------------------------------------------------------------------- |
# Application targets: Generate binary executable, install (as VHDL file) |
# ----------------------------------------------------------------------------- |
# Generate NEORV32 executable image for upload via bootloader |
$(APP_EXE): main.bin $(IMAGE_GEN) |
@set -e |
@$(IMAGE_GEN) -app_bin $< $@ $(shell basename $(CURDIR)) |
@echo "Executable ($(APP_EXE)) size in bytes:" |
@wc -c < $(APP_EXE) |
|
# Generate NEORV32 executable VHDL boot image |
$(APP_IMG): main.bin $(IMAGE_GEN) |
@set -e |
@$(IMAGE_GEN) -app_img $< $@ $(shell basename $(CURDIR)) |
@echo "Installing application image to $(NEORV32_RTL_PATH)/$(APP_IMG)" |
@cp $(APP_IMG) $(NEORV32_RTL_PATH)/. |
|
|
# ----------------------------------------------------------------------------- |
# Bootloader targets |
# ----------------------------------------------------------------------------- |
# Create and install bootloader VHDL init image |
$(BOOT_IMG): main.bin $(IMAGE_GEN) |
@set -e |
@$(IMAGE_GEN) -bld_img $< $(BOOT_IMG) $(shell basename $(CURDIR)) |
@echo "Installing bootloader image to $(NEORV32_RTL_PATH)/$(BOOT_IMG)" |
@cp $(BOOT_IMG) $(NEORV32_RTL_PATH)/. |
|
# Just an alias that |
bootloader: $(BOOT_IMG) |
|
|
# ----------------------------------------------------------------------------- |
# Check toolchain |
# ----------------------------------------------------------------------------- |
check: $(IMAGE_GEN) |
@echo "---------------- Check: NEORV32_HOME folder ----------------" |
ifneq ($(shell [ -e $(NEORV32_HOME_MARKER) ] && echo 1 || echo 0 ), 1) |
$(error NEORV32_HOME folder not found!) |
endif |
@echo "NEORV32_HOME: $(NEORV32_HOME)" |
@echo "---------------- Check: $(CC) ----------------" |
@$(CC) -v |
@echo "---------------- Check: $(OBJDUMP) ----------------" |
@$(OBJDUMP) -V |
@echo "---------------- Check: $(OBJCOPY) ----------------" |
@$(OBJCOPY) -V |
@echo "---------------- Check: $(SIZE) ----------------" |
@$(SIZE) -V |
@echo "---------------- Check: NEORV32 image_gen ----------------" |
@$(IMAGE_GEN) -help |
@echo "---------------- Check: Native GCC ----------------" |
@$(CC_X86) -v |
@echo |
@echo "Toolchain check OK" |
|
|
# ----------------------------------------------------------------------------- |
# Upload executable via serial port to bootloader |
# ----------------------------------------------------------------------------- |
upload: $(APP_EXE) |
@sh $(NEORV32_EXG_PATH)/uart_upload.sh $(COM_PORT) $(APP_EXE) |
|
|
# ----------------------------------------------------------------------------- |
# Show configuration |
# ----------------------------------------------------------------------------- |
info: |
@echo "---------------- Info: Project ----------------" |
@echo "Project folder: $(shell basename $(CURDIR))" |
@echo "Source files: $(APP_SRC)" |
@echo "Include folder(s): $(APP_INC)" |
@echo "ASM include folder(s): $(ASM_INC)" |
@echo "---------------- Info: NEORV32 ----------------" |
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)" |
@echo "IMAGE_GEN: $(IMAGE_GEN)" |
@echo "Core source files:" |
@echo "$(CORE_SRC)" |
@echo "Core include folder:" |
@echo "$(NEORV32_INC_PATH)" |
@echo "---------------- Info: Objects ----------------" |
@echo "Project object files:" |
@echo "$(OBJ)" |
@echo "---------------- Info: RISC-V CPU ----------------" |
@echo "MARCH: $(MARCH)" |
@echo "MABI: $(MABI)" |
@echo "---------------- Info: Toolchain ----------------" |
@echo "Toolchain: $(RISCV_TOLLCHAIN)" |
@echo "CC: $(CC)" |
@echo "OBJDUMP: $(OBJDUMP)" |
@echo "OBJCOPY: $(OBJCOPY)" |
@echo "SIZE: $(SIZE)" |
@echo "---------------- Info: Compiler Libraries ----------------" |
@echo "LIBGCC:" |
@$(CC) -print-libgcc-file-name |
@echo "SEARCH-DIRS:" |
@$(CC) -print-search-dirs |
@echo "---------------- Info: Flags ----------------" |
@echo "USER_FLAGS: $(USER_FLAGS)" |
@echo "CC_OPTS: $(CC_OPTS)" |
@echo "---------------- Info: Host Native GCC Flags ----------------" |
@echo "CC_X86: $(CC_X86)" |
|
|
# ----------------------------------------------------------------------------- |
# Show final ELF details (just for debugging) |
# ----------------------------------------------------------------------------- |
elf_info: main.elf |
@$(OBJDUMP) -x main.elf |
|
|
# ----------------------------------------------------------------------------- |
# Help |
# ----------------------------------------------------------------------------- |
help: |
@echo "<<< NEORV32 Application Makefile >>>" |
@echo "Make sure to add the bin folder of RISC-V GCC to your PATH variable." |
@echo "Targets:" |
@echo " help - show this text" |
@echo " check - check toolchain" |
@echo " info - show makefile/toolchain configuration" |
@echo " exe - compile and generate <neorv32_exe.bin> executable for upload via bootloader" |
@echo " install - compile, generate and install VHDL IMEM boot image (for application)" |
@echo " all - compile and generate <neorv32_exe.bin> executable for upload via bootloader and generate and install VHDL IMEM boot image (for application)" |
@echo " clean - clean up project" |
@echo " clean_all - clean up project, core libraries and image generator" |
@echo " bootloader - compile, generate and install VHDL BOOTROM boot image (for bootloader only!)" |
@echo " upload - upload <neorv32_exe.bin> executable via serial port <COM_PORT> to bootloader" |
|
|
# ----------------------------------------------------------------------------- |
# Clean up |
# ----------------------------------------------------------------------------- |
clean: |
@rm -f *.elf *.o *.bin *.out *.asm *.vhd |
|
clean_all: clean |
@rm -f $(OBJ) $(IMAGE_GEN) |
/sw/lib/include/neorv32.h
143,8 → 143,11
* CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MISA_enum { |
CPU_MISA_A_EXT = 0, /**< CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)*/ |
CPU_MISA_B_EXT = 1, /**< CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)*/ |
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/ |
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */ |
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (4): E: Embedded CPU extension available (r/-) */ |
CPU_MISA_F_EXT = 4, /**< CPU misa CSR (5): F: Floating point (single-precision) extension available (r/-) */ |
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */ |
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/ |
CPU_MISA_U_EXT = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/ |
/sw/lib/include/neorv32_cpu.h
52,6 → 52,7
uint64_t neorv32_cpu_get_systime(void); |
void neorv32_cpu_delay_ms(uint32_t time_ms); |
void __attribute__((naked)) neorv32_cpu_goto_user_mode(void); |
int neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired); |
|
|
/**********************************************************************//** |
/sw/lib/source/neorv32_cpu.c
217,23 → 217,26
|
|
/**********************************************************************//** |
* Simple delay function (not very precise) using busy wait. |
* Simple delay function using busy wait. |
* |
* @warning This function requires the cycle CSR(s). Hence, the Zicsr extension is mandatory. |
* |
* @param[in] time_ms Time in ms to wait. |
**************************************************************************/ |
void neorv32_cpu_delay_ms(uint32_t time_ms) { |
|
uint32_t clock_speed = SYSINFO_CLK >> 10; // fake divide by 1000 |
clock_speed = clock_speed >> 5; // divide by loop execution time (~30 cycles) |
uint32_t cnt = clock_speed * time_ms; |
uint64_t time_resume = neorv32_cpu_get_cycle(); |
|
// one iteration = ~30 cycles |
while (cnt) { |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
cnt--; |
uint32_t clock = SYSINFO_CLK; // clock ticks per second |
clock = clock / 1000; // clock ticks per ms |
|
uint64_t wait_cycles = ((uint64_t)clock) * ((uint64_t)time_ms); |
time_resume += wait_cycles; |
|
while(1) { |
if (neorv32_cpu_get_cycle() >= time_resume) { |
break; |
} |
} |
} |
|
241,16 → 244,54
/**********************************************************************//** |
* Switch from privilege mode MACHINE to privilege mode USER. |
* |
* @note This function requires the U extension to be implemented. |
* @note Maybe you should do a fence.i after this. |
* @warning This function requires the U extension to be implemented. |
**************************************************************************/ |
void __attribute__((naked)) neorv32_cpu_goto_user_mode(void) { |
|
// make sure to use NO registers in here! -> naked |
|
asm volatile ("csrw mepc, ra \n\t" // move return address to mepc so we can return using "mret". also, we can use ra as general purpose register in here |
asm volatile ("csrw mepc, ra \n\t" // move return address to mepc so we can return using "mret". also, we can now use ra as general purpose register in here |
"li ra, %[input_imm] \n\t" // bit mask to clear the two MPP bits |
"csrrc zero, mstatus, ra \n\t" // clear MPP bits -> MPP=u-mode |
"mret \n\t" // return and switch to user mode |
: : [input_imm] "i" ((1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L))); |
} |
|
|
/**********************************************************************//** |
* Atomic compare-and-swap operation (for implemeneting semaphores and mutexes). |
* |
* @warning This function requires the A (atomic) CPU extension. |
* |
* @param[in] addr Address of memory location. |
* @param[in] expected Expected value (for comparison). |
* @param[in] desired Desired value (new value). |
* @return Returns 0 on success, 1 on failure. |
**************************************************************************/ |
int __attribute__ ((noinline)) neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired) { |
#ifdef __riscv_atomic |
|
register uint32_t addr_reg = addr; |
register uint32_t des_reg = desired; |
register uint32_t tmp_reg; |
|
// load original value + reservation (lock) |
asm volatile ("lr.w %[result], (%[input])" : [result] "=r" (tmp_reg) : [input] "r" (addr_reg)); |
|
if (tmp_reg != expected) { |
asm volatile ("lw x0, 0(%[input])" : : [input] "r" (addr_reg)); // clear reservation lock |
return 1; |
} |
|
// store-conditional |
asm volatile ("sc.w %[result], %[input_i], (%[input_j])" : [result] "=r" (tmp_reg) : [input_i] "r" (des_reg), [input_j] "r" (addr_reg)); |
|
if (tmp_reg) { |
return 1; |
} |
|
return 0; |
#else |
return 1; // A extension not implemented -Y always fail |
#endif |
} |
/sw/lib/source/neorv32_rte.c
397,38 → 397,38
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT)); |
|
// peripherals |
neorv32_uart_printf("\n-- Processor Peripherals --\n"); |
neorv32_uart_printf("\n-- Available Processor Peripherals --\n"); |
|
tmp = SYSINFO_FEATURES; |
|
neorv32_uart_printf("GPIO: "); |
neorv32_uart_printf("GPIO - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO)); |
|
neorv32_uart_printf("MTIME: "); |
neorv32_uart_printf("MTIME - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME)); |
|
neorv32_uart_printf("UART: "); |
neorv32_uart_printf("UART - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART)); |
|
neorv32_uart_printf("SPI: "); |
neorv32_uart_printf("SPI - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI)); |
|
neorv32_uart_printf("TWI: "); |
neorv32_uart_printf("TWI - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI)); |
|
neorv32_uart_printf("PWM: "); |
neorv32_uart_printf("PWM - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM)); |
|
neorv32_uart_printf("WDT: "); |
neorv32_uart_printf("WDT - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT)); |
|
neorv32_uart_printf("TRNG: "); |
neorv32_uart_printf("TRNG - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG)); |
|
neorv32_uart_printf("CFU0: "); |
neorv32_uart_printf("CFU0 - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFU0)); |
|
neorv32_uart_printf("CFU1: "); |
neorv32_uart_printf("CFU1 - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFU1)); |
} |
|
506,9 → 506,8
**************************************************************************/ |
void neorv32_rte_print_credits(void) { |
|
neorv32_uart_print("\nThe NEORV32 Processor Project, by Stephan Nolting\n" |
"https://github.com/stnolting/neorv32\n" |
"made in Hannover, Germany EU\n\n"); |
neorv32_uart_print("The NEORV32 Processor Project by Stephan Nolting\n" |
"https://github.com/stnolting/neorv32\n\n"); |
} |
|
|
/CHANGELOG.md
14,8 → 14,13
|
| Date (*dd.mm.yyyy*) | Version | Comment | |
|:----------:|:-------:|:--------| |
| 03.12.2020 | 1.4.8.1 | Optimized CPU program counter (PC) update logic and "next PC" computation (shortend critical path); updated bootloader (configuration option for direct-boot-from-SPI-flash only) and *customization* text in neorv32.pdf | |
| 01.12.2020 | [**:rocket:1.4.8.0**](https://github.com/stnolting/neorv32/releases/tag/v1.4.8.0) | :warning: fixed bug in CPU-internal co-processor interface; optimized multiplier unit (~1 faster); added CPU `A` (atomic) extension support (only `lr.w` and `sc.w` instructions yet); added `lock` signal to CPU and processor's external bus interface | |
| 28.11.2020 | 1.4.7.6 | Split ALU core operations: shortened critical path - replaced ALU output 8:1 mux by a 4:1 mux | |
| 26.11.2020 | 1.4.7.5 | Minor rtl clean-up; CSR access instructions are one cycle faster now (3 cycles now); system/environemnt instructions (`ecall` `ebreak` `mret` `wfi`) need one additional cycle (4 cycles now) | |
| 25.11.2020 | 1.4.7.4 | :warning: fixed bug in `FENCE.I` instruction that corrupted instruction fetch when executing code from processor-external memory; default testbench (`sim/neorv32_tb.vhd`) now features external IMEM, external DMEM and external IO connected via external bus interface; simulation now allows CPU to execute code using external memories only (no internal IMEM/DMEM); optimized CPU's instruction fetch interface (no more unnecessary transfer cancel requests) | |
| 20.11.2020 | 1.4.7.2 | :warning: fixed bug in CPU bus unit that caused a memory exception after reset in some cases; added second simulated external (Wishbone) memory to testbench (one memory for simulating an external IMEM, one memory for simulating external memory-mapped IO); external bus interface (`wishbone`) now makes sure that a canceled bus transfer is really understood by the accessed peripheral | |
| 20.11.2020 | 1.4.7.1 | Removed legacy (and unused) "update_enable signal" from IMEM | |
| 20.11.2020 | 1.4.7.1 | Removed deprecated "update_enable signal" from IMEM | |
| 11.11.2020 | [**:rocket:1.4.7.0**](https://github.com/stnolting/neorv32/releases/tag/v1.4.7.0) | Further optimized pipeline front-end: Jumps and branches are one cycle faster (+5% coremark performance); updated synthesis results; updated performance results; added `hello_world` example program | |
| 07.11.2020 | 1.4.6.7 | Updated bootloader (size optimization) and changed processor version output; added project logo; minor data sheet edits | |
| 03.11.2020 | 1.4.6.6 | Removed SPI module's *buggy* "LSB-first mode", SPI module now always sends data MSB-first; removed SPI.CTRL `SPI_CT_DIR` bit; modfied bit order in SPI CTRL register; updated SPI SW library | |
/README.md
30,7 → 30,8
* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to |
* Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf) |
* Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf) |
* Optional CPU extensions |
* Optional RISC-V CPU extensions |
* `A` - atomic memory access instructions |
* `C` - compressed instructions (16-bit) |
* `E` - embedded CPU (reduced register file) |
* `M` - integer multiplication and division hardware |
38,10 → 39,10
* `Zicsr` - control and status register access instructions (+ exception/irq system) |
* `Zifencei` - instruction stream synchronization |
* `PMP` - physical memory protection |
* Full-scale RISC-V microcontroller system (**SoC**) [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules |
* optional embedded memories (instruction/data/bootloader, RAM/ROM) |
* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules |
* optional embedded memories (instructions/data/bootloader, RAM/ROM) |
* timers (watch dog, RISC-V-compliant machine timer) |
* serial interfaces (SPI, TWI, UART) |
* serial interfaces (SPI, TWI, UART) and general purpose IO |
* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity)) |
* [more ...](#NEORV32-Processor-Features) |
* Software framework |
64,7 → 65,7
|
### Design Principles |
|
* From zero to `main()`: Completely open source and documented. |
* From zero to *hello_world*: Completely open source and documented. |
* Plain VHDL without technology-specific parts like attributes, macros or primitives. |
* Easy to use – working out of the box. |
* Clean synchronous design, no wacky combinatorial interfaces. |
86,22 → 87,22
| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | | |
|
|
### To-Do / Wish List / [Help Wanted](#Contribute) |
### To-Do / Wish List / Help Wanted |
|
* Use LaTeX for data sheet |
* Further size and performance optimization *(work in progress)* |
* A cache for the external memory/bus interface *(work in progress)* |
* Burst mode for the external memory/bus interface |
* RISC-V `B` extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) |
* Synthesis results (+ wrappers?) for more/specific platforms |
* More support for FreeRTOS |
* Further size and performance optimization |
* Synthesis results (+ wrappers?) for more/specific platforms |
* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org)) |
* Implement further RISC-V (or custom?) CPU extensions (like floating-point operations ('F')) |
* Implement further RISC-V (or custom?) CPU extensions (like floating-point extension `F`) |
* ... |
* [Ideas?](#Contribute) |
|
#### Work-in-progress |
|
* A cache for the external memory/bus interface (also providing burst mode?) |
* RISC-V `B` extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) |
|
|
## Features |
|
The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file: |
131,9 → 132,7
|
### NEORV32 CPU Features |
|
 |
|
The CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the |
The NEORV32 CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the |
[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the |
[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf). |
|
172,6 → 171,10
* By default, the multiplier and divider cores use an iterative bit-serial processing scheme |
* Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance |
|
**Atomic memory access** (`A` extension): |
* Supported instruction: `LR.W` `SC.W` |
* By default, the multiplier and divider cores use an iterative bit-serial processing scheme |
|
**Privileged architecture / CSR access** (`Zicsr` extension): |
* Privilege levels: `M-mode` (Machine mode) |
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI` |
207,6 → 210,7
|
* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception |
* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions |
* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations |
|
|
### NEORV32-Specific CPU Extensions |
227,39 → 231,41
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration |
of the CPU's generics is assumed (for example no PMP). No constraints were used at all. |
|
Results generated for hardware version `1.4.7.0`. |
Results generated for hardware version `1.4.8.0`. |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max | |
|:---------------------------------------|:----------:|:--------:|:-----------:|:----:|:--------:| |
| `rv32i` | 932 | 413 | 2048 | 0 | ~120 MHz | |
| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1800 | 815 | 2048 | 0 | ~118 MHz | |
| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2368 | 1058 | 2048 | 0 | ~117 MHz | |
| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2604 | 1073 | 2048 | 0 | ~113 MHz | |
| `rv32emc` + `u` + `Zicsr` + `Zifencei` | 2613 | 1073 | 1024 | 0 | ~113 MHz | |
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max | |
|:----------------------------------------|:----------:|:--------:|:-----------:|:----:|:--------:| |
| `rv32i` | 945 | 417 | 2048 | 0 | ~122 MHz | |
| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1944 | 901 | 2048 | 0 | ~119 MHz | |
| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2551 | 1147 | 2048 | 0 | ~117 MHz | |
| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2800 | 1162 | 2048 | 0 | ~113 MHz | |
| `rv32imac` + `u` + `Zicsr` + `Zifencei` | 1796 | 1165 | 2048 | 0 | ~113 MHz | |
|
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half. |
|
|
### NEORV32 Processor-Internal Peripherals and Memories |
|
Results generated for hardware version `1.4.7.0`. |
Results generated for hardware version `1.4.8.0`. |
|
| Module | Description | LEs | FFs | Memory bits | DSPs | |
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:| |
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 | |
| BUSSWITCH | Mux for CPU I & D interfaces | 63 | 8 | 0 | 0 | |
| BUSSWITCH | Mux for CPU I & D interfaces | 82 | 8 | 0 | 0 | |
| CFU0 | Custom functions unit 0 | - | - | - | - | |
| CFU1 | Custom functions unit 1 | - | - | - | - | |
| DMEM | Processor-internal data memory (default 8kB) | 12 | 2 | 65 536 | 0 | |
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 | |
| GPIO | General purpose input/output ports | 66 | 65 | 0 | 0 | |
| IMEM | Processor-internal instruction memory (default 16kb) | 7 | 2 | 131 072 | 0 | |
| MTIME | Machine system timer | 272 | 166 | 0 | 0 | |
| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 | |
| SPI | Serial peripheral interface | 142 | 124 | 0 | 0 | |
| SYSINFO | System configuration information memory | 11 | 9 | 0 | 0 | |
| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 | |
| MTIME | Machine system timer | 282 | 166 | 0 | 0 | |
| PWM | Pulse-width modulation controller | 71 | 69 | 0 | 0 | |
| SPI | Serial peripheral interface | 129 | 124 | 0 | 0 | |
| SYSINFO | System configuration information memory | 9 | 9 | 0 | 0 | |
| TRNG | True random number generator | 132 | 105 | 0 | 0 | |
| TWI | Two-wire interface | 77 | 44 | 0 | 0 | |
| UART | Universal asynchronous receiver/transmitter | 173 | 132 | 0 | 0 | |
| WDT | Watchdog timer | 58 | 45 | 0 | 0 | |
| WISHBONE | External memory interface | 106 | 104 | 0 | 0 | |
| UART | Universal asynchronous receiver/transmitter | 175 | 132 | 0 | 0 | |
| WDT | Watchdog timer | 59 | 45 | 0 | 0 | |
| WISHBONE | External memory interface | 129 | 104 | 0 | 0 | |
|
|
### NEORV32 Processor - Exemplary FPGA Setups |
546,7 → 552,7
0. Check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md) |
1. [Fork](https://github.com/stnolting/neorv32/fork) this repository and clone the fork |
2. Create a feature branch in your fork: `git checkout -b awesome_new_feature_branch` |
3. Create a new remote for the upstream repo: `git remote add https://github.com/stnolting/neorv32` |
3. Create a new remote for the upstream repo: `git remote add upstream https://github.com/stnolting/neorv32` |
3. Commit your modifications: `git commit -m "Awesome new feature!"` |
4. Push to the branch: `git push origin awesome_new_feature_branch` |
5. Create a new [pull request](https://github.com/stnolting/neorv32/pulls) |