Subversion Repositories neorv32

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docs/figures/neorv32_test_setup.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: docs/figures/oshw_logo.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: docs/NEORV32.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: docs/riscv-privileged.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: docs/riscv-spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/.ld_script/link.ld =================================================================== --- riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/.ld_script/link.ld (nonexistent) +++ riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/.ld_script/link.ld (revision 40) @@ -0,0 +1,28 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + + . = 0x00000000; + .text : { + *(.text.trap) + *(.text.init) + + . = ALIGN(0x1000); + *(.tohost) + + . = ALIGN(0x1000); + *(.text) + _etext = .; + + *(.data) + *(.data.string) + _edata = .; + + *(.bss) + _end = .; + + } + +} Index: riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zicsr/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zicsr/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zicsr/Makefile.include (revision 40) @@ -0,0 +1,39 @@ +ifndef NEORV32_HOME + $(error NEORV32_HOME is undefined) +endif + +LDSCRIPT = $(ROOTDIR)/riscv-target/neorv32/device/.ld_script/link.ld +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\ CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_HOME)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_HOME)/sw/example/blink_led install; \ + sh $(NEORV32_HOME)/sim/ghdl/ghdl_sim.sh --stop-time=100us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32i + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ + -I$(ROOTDIR)/riscv-test-env/ \ + -I$(ROOTDIR)/riscv-test-env/p/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(LDSCRIPT) $$< \ + -o $$@; Index: riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zifencei/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zifencei/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32Zifencei/Makefile.include (revision 40) @@ -0,0 +1,40 @@ +ifndef NEORV32_HOME + $(error NEORV32_HOME is undefined) +endif + +LDSCRIPT = $(ROOTDIR)/riscv-target/neorv32/device/.ld_script/link.ld +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\ CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\ CPU_EXTENSION_RISCV_Zifencei => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_HOME)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_HOME)/sw/example/blink_led install; \ + sh $(NEORV32_HOME)/sim/ghdl/ghdl_sim.sh --stop-time=100us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32i + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ + -I$(ROOTDIR)/riscv-test-env/ \ + -I$(ROOTDIR)/riscv-test-env/p/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(LDSCRIPT) $$< \ + -o $$@; Index: riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32i/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32i/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32i/Makefile.include (revision 40) @@ -0,0 +1,40 @@ +ifndef NEORV32_HOME + $(error NEORV32_HOME is undefined) +endif + +LDSCRIPT = $(ROOTDIR)/riscv-target/neorv32/device/.ld_script/link.ld +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + sed -i '/CPU_EXTENSION_RISCV_C/c\ CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\ CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_HOME)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_HOME)/sw/example/blink_led install; \ + sh $(NEORV32_HOME)/sim/ghdl/ghdl_sim.sh --stop-time=100us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32i + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ + -I$(ROOTDIR)/riscv-test-env/ \ + -I$(ROOTDIR)/riscv-test-env/p/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(LDSCRIPT) $$< \ + -o $$@; Index: riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32im/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32im/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32im/Makefile.include (revision 40) @@ -0,0 +1,40 @@ +ifndef NEORV32_HOME + $(error NEORV32_HOME is undefined) +endif + +LDSCRIPT = $(ROOTDIR)/riscv-target/neorv32/device/.ld_script/link.ld +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + sed -i '/CPU_EXTENSION_RISCV_M/c\ CPU_EXTENSION_RISCV_M => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\ CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_HOME)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_HOME)/sw/example/blink_led install; \ + sh $(NEORV32_HOME)/sim/ghdl/ghdl_sim.sh --stop-time=100us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32im + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ + -I$(ROOTDIR)/riscv-test-env/ \ + -I$(ROOTDIR)/riscv-test-env/p/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(LDSCRIPT) $$< \ + -o $$@; Index: riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32imc/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32imc/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/device/rv32imc/Makefile.include (revision 40) @@ -0,0 +1,41 @@ +ifndef NEORV32_HOME + $(error NEORV32_HOME is undefined) +endif + +LDSCRIPT = $(ROOTDIR)/riscv-target/neorv32/device/.ld_script/link.ld +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + sed -i '/CPU_EXTENSION_RISCV_C/c\ CPU_EXTENSION_RISCV_C => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_M/c\ CPU_EXTENSION_RISCV_M => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\ CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_HOME)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_HOME)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_HOME)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_HOME)/sw/example/blink_led install; \ + sh $(NEORV32_HOME)/sim/ghdl/ghdl_sim.sh --stop-time=100us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32imc + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ + -I$(ROOTDIR)/riscv-test-env/ \ + -I$(ROOTDIR)/riscv-test-env/p/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(LDSCRIPT) $$< \ + -o $$@; Index: riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/README.md =================================================================== --- riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/README.md (nonexistent) +++ riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/README.md (revision 40) @@ -0,0 +1,18 @@ +# Simulation + +The NEORV32 Processor is simulated using the its default testbench. + +Each architecture-specific makefile in the `device` folder uses an _uncool hack_: `sed` is used to +enable/disable the required `CPU_EXTENSION_RISCV_xxx` VHDL configuration generics in the testbench (`neorv32/sim/neorv32_tb.vhd`). + +For instance, the `rv32i` tests requires the `C`-extensions to be disabled - which is enabled by default in the testbench. + +GHDL is used for simulating the processor. + +The results are dumped via the SIM_MODE feature of the UART. The according code can be found in the `RV_COMPLIANCE_HALT` +macro in `compliance_test.h`. + +The `RVTEST_IO_INIT` macro in `compliance_io.h` is used to configure +the UART for SIM_MODE. + +The final data (plain 8-hex char data) is dumped to the `neorv32.uart.sim_mode.data.out` file. Index: riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/compliance_io.h =================================================================== --- riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/compliance_io.h (nonexistent) +++ riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/compliance_io.h (revision 40) @@ -0,0 +1,47 @@ +// RISC-V Compliance IO Test Header File + +/* + * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. + * + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +// Modified by Stephan Nolting for the NEORV32 Processor + +#ifndef _COMPLIANCE_IO_H +#define _COMPLIANCE_IO_H + +//----------------------------------------------------------------------- +// RV IO Macros +//----------------------------------------------------------------------- + +// enable UART (ctrl(28)) and enable UART_SIM_MODE (ctrl(12)) +#define RVTEST_IO_INIT \ + uart_init: \ + li a0, 0xFFFFFFA0; \ + sw zero, 0(a0); \ + li a1, 1 << 28; \ + li a2, 1 << 12; \ + or a1, a1, a2; \ + sw a1, 0(a0); \ + +#define RVTEST_IO_WRITE_STR(_R, _STR) +#define RVTEST_IO_CHECK() +#define RVTEST_IO_ASSERT_GPR_EQ(_G, _R, _I) +#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) +#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +#endif // _COMPLIANCE_IO_H Index: riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/compliance_test.h =================================================================== --- riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/compliance_test.h (nonexistent) +++ riscv-compliance/port-neorv32/framework_v1.0/riscv-target/neorv32/compliance_test.h (revision 40) @@ -0,0 +1,47 @@ +// RISC-V Compliance Test Header File +// Copyright (c) 2017, Codasip Ltd. All Rights Reserved. +// See LICENSE for license details. +// +// Description: Common header file for RV32I tests + +// Modified by Stephan Nolting for the NEORV32 Processor + +#ifndef _COMPLIANCE_TEST_H +#define _COMPLIANCE_TEST_H + +#include "riscv_test.h" + +//----------------------------------------------------------------------- +// RV Compliance Macros +//----------------------------------------------------------------------- + +// this will dump the results via the UART_SIM_MODE data file output +#define RV_COMPLIANCE_HALT \ + la a0, begin_signature; \ + la a1, end_signature; \ + li a2, 0xFFFFFFA4; \ + copy_loop: \ + beq a0, a1, copy_loop_end; \ + lw t0, 0(a0); \ + sw t0, 0(a2); \ + addi a0, a0, 4; \ + j copy_loop; \ + copy_loop_end: \ + RVTEST_PASS \ + +#define RV_COMPLIANCE_RV32M \ + RVTEST_RV32M \ + +#define RV_COMPLIANCE_CODE_BEGIN \ + RVTEST_CODE_BEGIN \ + +#define RV_COMPLIANCE_CODE_END \ + RVTEST_CODE_END \ + +#define RV_COMPLIANCE_DATA_BEGIN \ + RVTEST_DATA_BEGIN \ + +#define RV_COMPLIANCE_DATA_END \ + RVTEST_DATA_END \ + +#endif Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include (revision 40) @@ -0,0 +1,52 @@ +ifndef NEORV32_LOCAL_COPY + $(error NEORV32_LOCAL_COPY is undefined) +endif + +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + echo "copying/using SIM-only IMEM (ROM!)"; \ + rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + cp -f $(NEORV32_LOCAL_COPY)/sim/rtl_modules/neorv32_imem.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ + sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \ + sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=600us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32ic -mabi=ilp32 + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ + $$(RISCV_TARGET_FLAGS) \ + -I$(ROOTDIR)/riscv-test-suite/env/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_rom.ld \ + $$(<) -o $$@ Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/I/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/I/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/I/Makefile.include (revision 40) @@ -0,0 +1,52 @@ +ifndef NEORV32_LOCAL_COPY + $(error NEORV32_LOCAL_COPY is undefined) +endif + +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + echo "copying/using SIM-only IMEM (ROM!)"; \ + rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + cp -f $(NEORV32_LOCAL_COPY)/sim/rtl_modules/neorv32_imem.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ + sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \ + sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=800us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32i -mabi=ilp32 + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ + $$(RISCV_TARGET_FLAGS) \ + -I$(ROOTDIR)/riscv-test-suite/env/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_rom.ld \ + $$(<) -o $$@ Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/M/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/M/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/M/Makefile.include (revision 40) @@ -0,0 +1,52 @@ +ifndef NEORV32_LOCAL_COPY + $(error NEORV32_LOCAL_COPY is undefined) +endif + +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + echo "copying/using SIM-only IMEM (ROM!)"; \ + rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + cp -f $(NEORV32_LOCAL_COPY)/sim/rtl_modules/neorv32_imem.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ + sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \ + sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=800us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32im -mabi=ilp32 + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ + $$(RISCV_TARGET_FLAGS) \ + -I$(ROOTDIR)/riscv-test-suite/env/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_rom.ld \ + $$(<) -o $$@ Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/Zifencei/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/Zifencei/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/Zifencei/Makefile.include (revision 40) @@ -0,0 +1,51 @@ +ifndef NEORV32_LOCAL_COPY + $(error NEORV32_LOCAL_COPY is undefined) +endif + +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + echo "restoring/using original IMEM rtl file"; \ + rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + cp -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.ORIGINAL $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 32*1024, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ + sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=600us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32i -mabi=ilp32 + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ + $$(RISCV_TARGET_FLAGS) \ + -I$(ROOTDIR)/riscv-test-suite/env/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_ram.ld \ + $$(<) -o $$@ Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/privilege/Makefile.include =================================================================== --- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/privilege/Makefile.include (nonexistent) +++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/privilege/Makefile.include (revision 40) @@ -0,0 +1,52 @@ +ifndef NEORV32_LOCAL_COPY + $(error NEORV32_LOCAL_COPY is undefined) +endif + +TARGET_SIM ?= ghdl +TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS) + +ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),) + $(error Target simulator executable '$(TARGET_SIM)` not found) +endif + +RUN_TARGET=\ + cd $(work_dir_isa); \ + rm -f $(work_dir_isa)/*.out; \ + echo "copying/using SIM-only IMEM (ROM!)"; \ + rm -f $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + cp -f $(NEORV32_LOCAL_COPY)/sim/rtl_modules/neorv32_imem.vhd $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_imem.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_A/c\CPU_EXTENSION_RISCV_A => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_C/c\CPU_EXTENSION_RISCV_C => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_E/c\CPU_EXTENSION_RISCV_E => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_M/c\CPU_EXTENSION_RISCV_M => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_U/c\CPU_EXTENSION_RISCV_U => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zicsr/c\CPU_EXTENSION_RISCV_Zicsr => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/CPU_EXTENSION_RISCV_Zifencei/c\CPU_EXTENSION_RISCV_Zifencei => false, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/constant ext_imem_c/c\constant ext_imem_c : boolean := false; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/signal ext_ram_a : ext_mem_a_ram_t/c\signal ext_ram_a : ext_mem_a_ram_t; -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_USE/c\MEM_INT_IMEM_USE => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_SIZE/c\MEM_INT_IMEM_SIZE => 2*1024*1024, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + sed -i '/MEM_INT_IMEM_ROM/c\MEM_INT_IMEM_ROM => true, -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/sim/neorv32_tb.vhd; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.elf; \ + cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \ + make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ + sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \ + sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=600us >> /dev/null; \ + cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; + + +RISCV_PREFIX ?= riscv32-unknown-elf- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy +RISCV_READELF ?= $(RISCV_PREFIX)readelf +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -march=rv32i -mabi=ilp32 + +COMPILE_TARGET=\ + $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ + $$(RISCV_TARGET_FLAGS) \ + -I$(ROOTDIR)/riscv-test-suite/env/ \ + -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -T$(TARGETDIR)/$(RISCV_TARGET)/link.imem_rom.ld \ + $$(<) -o $$@ Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md =================================================================== --- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md (nonexistent) +++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md (revision 40) @@ -0,0 +1,22 @@ +# Running the RISC-V Compliance Framework in Simulation + + +The following tasks are executed by the device makefiles: + +* replace the original processor's IMEM rtl file by a simulation-optimized IMEM (ROM!) +* `sed` command is used to modify the default testbench (`neorv32/sim/neorv32_tb.vhd`): + * enable/disable the required `CPU_EXTENSION_RISCV_xxx` VHDL configuration generics in the testbench (`neorv32/sim/neorv32_tb.vhd`) + * configure the processor memory configuration (use internal IMEM, IMEM as ROM, IMEM size of 2MB) +* compile test code and install application image to processor's `rtl/core` folder + * compilation uses the `link.imem_rom.ld` linker script as default; code (the test code) is executed from IMEM (which is read-only); data including signatureis stored to DMEM (RAM) + * certain areas in the DMEM are initialized using port code in `model_test.h` (`RVTEST` = 0xbabecafe and `SIGNATURE` = 0xdeadbeef); can be disabled using `RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT` +* `sed` command is used to modify the default application image that is generated during compilation (`neorv32/rtl/core/neorv32_application_image.vhd`): + * the array size of the application image is set to 2MB +* the processor is simulated using the default testbench using GHDL +* the results are dumped via the SIM_MODE feature of the UART + * the according code can be found in the `RVMODEL_HALT` macro in `model_test.h` + * data output (the "signature") is zero-padded to be always a multiple of 16 bytes + +:warning: The `Zifencei` test requires the r/w/e capabilities of the original IMEM rtl file. +Hence, the original file is restored for this test. Also, this test uses `link.imem_ram.ld` as linker script since the +IMEM is used as RAM to allow self-modifying code. Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/link.imem_ram.ld =================================================================== --- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/link.imem_ram.ld (nonexistent) +++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/link.imem_ram.ld (revision 40) @@ -0,0 +1,22 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(rvtest_entry_point) + +SECTIONS +{ + . = 0x00000000; + .text : + { + *(.text.init) + . = ALIGN(0x1000); + *(.text) + . = ALIGN(0x1000); + *(.tohost) + *(.data) + *(.data.string) + *(.bss) + . = ALIGN(0x1000); + + _end = .; + } +} + Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/link.imem_rom.ld =================================================================== --- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/link.imem_rom.ld (nonexistent) +++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/link.imem_rom.ld (revision 40) @@ -0,0 +1,26 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(rvtest_entry_point) + +SECTIONS +{ + . = 0x00000000; + .text : + { + *(.text.init) + . = ALIGN(0x1000); + *(.text) + . = ALIGN(0x1000); + _end = .; + } + + . = 0x80000000; + .data : + { + . = ALIGN(0x1000); + *(.tohost) + *(.data) + *(.data.string) + *(.bss) + } +} + Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/model_test.h =================================================================== --- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/model_test.h (nonexistent) +++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/model_test.h (revision 40) @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: BSD-3-Clause + +// Modified by Stephan Nolting for the NEORV32 Processor + +#ifndef _COMPLIANCE_MODEL_H +#define _COMPLIANCE_MODEL_H + +#define RVMODEL_DATA_SECTION \ + .pushsection .tohost,"aw",@progbits; \ + .align 8; .global tohost; tohost: .dword 0; \ + .align 8; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 8; .global begin_regstate; begin_regstate: \ + .word 128; \ + .align 8; .global end_regstate; end_regstate: \ + .word 4; + +//RV_COMPLIANCE_HALT +// neorv32: this will dump the results via the UART_SIM_MODE data file output +// neorv32: due to the modifications on "end_signature" (not 4-aligned) we need to make sure we output a 4-aligned number of data here +// neorv32: -> for zero-padding of the rest of the SIGNATURE section +#define RVMODEL_HALT \ + signature_dump: \ + la a0, begin_signature; \ + la a1, end_signature; \ + li a2, 0xFFFFFFA4; \ + signature_dump_loop: \ + beq a0, a1, signature_dump_padding; \ + lw t0, 0(a0); \ + sw t0, 0(a2); \ + addi a0, a0, 4; \ + j signature_dump_loop; \ +nop; \ +nop; \ + signature_dump_padding: \ + andi a0, a1, 0x0000000C; \ + beq a0, zero, signature_dump_end; \ + li t0, 16; \ + sub a0, t0, a0; \ + signature_dump_padding_loop: \ + beq a0, zero, signature_dump_end; \ + sw zero, 0(a2); \ + addi a0, a0, -4; \ + j signature_dump_padding_loop; \ + signature_dump_end: \ + j signature_dump_end + +//TODO: declare the start of your signature region here. Nothing else to be used here. +// The .align 4 ensures that the signature ends at a 16-byte boundary +#define RVMODEL_DATA_BEGIN \ + .align 4; .global begin_signature; begin_signature: + +//TODO: declare the end of the signature region here. Add other target specific contents here. +//neorv32: DO NOT use align_4 here! end_signature is used to indicate the actual "number" of signature words +#define RVMODEL_DATA_END \ + .global end_signature; end_signature: \ + RVMODEL_DATA_SECTION + +//RVMODEL_BOOT +// neorv32: enable UART (ctrl(28)) and enable UART_SIM_MODE (ctrl(12)) +// neorv32: initialize the complete RVTEST_DATA section in data RAM (DMEM) with 0xBABECAFE +// neorv32: initialize the complete SIGNATURE section (that is a multiple of four 32-bit entries) in data RAM (DMEM) with 0xDEADBEEF +// neorv32: this code also provides a dummy trap handler that just moves on to the next instruction +// neorv32: -> this trap handler can be overriden by the compliance-suite by modifying mtval +// neorv32: -> the dummy trap handler is required to deal with the neorv32 X extension (-> all illegal/undefined instruction trigger an exception) +#ifdef NEORV32_NO_DATA_INIT +// ------------------------- WITHOUT DATA INIT ------------------------- +#define RVMODEL_BOOT \ + core_init: \ + la x1, core_dummy_trap_handler; \ + csrw mtvec, x1; \ + j uart_sim_mode_init; \ +nop; \ +nop; \ + .balign 4; \ + core_dummy_trap_handler: \ + csrw mscratch, sp; \ + la sp, end_signature; \ + addi sp, sp, 32; \ + sw x8, 0(sp); \ + sw x9, 4(sp); \ + csrr x8, mcause; \ + blt x8, zero, core_dummy_trap_handler_irq; \ + csrr x8, mepc; \ + core_dummy_trap_handler_exc_c_check: \ + lh x9, 0(x8); \ + andi x9, x9, 3; \ + addi x8, x8, +2; \ + csrw mepc, x8; \ + addi x8, zero, 3; \ + bne x8, x9, core_dummy_trap_handler_irq; \ + core_dummy_trap_handler_exc_uncrompressed: \ + csrr x8, mepc; \ + addi x8, x8, +2; \ + csrw mepc, x8; \ + core_dummy_trap_handler_irq: \ + lw x9, 0(sp); \ + lw x8, 4(sp); \ + csrr sp, mscratch; \ + mret; \ +nop; \ +nop; \ + uart_sim_mode_init: \ + li a0, 0xFFFFFFA0; \ + sw zero, 0(a0); \ + li a1, 1 << 28; \ + li a2, 1 << 12; \ + or a1, a1, a2; \ + sw a1, 0(a0); + +#else + +// ------------------------- WITH DATA INIT ------------------------- +#define RVMODEL_BOOT \ + core_init: \ + la x1, core_dummy_trap_handler; \ + csrw mtvec, x1; \ +nop; \ +nop; \ + init_rvtest_data: \ + la a0, rvtest_data_begin; \ + la a1, rvtest_data_end; \ + li a2, 0xBABECAFE; \ + init_rvtest_data_loop: \ + beq a0, a1, init_rvtest_data_loop_end; \ + sw a2, 0(a0); \ + addi a0, a0, 4; \ + j init_rvtest_data_loop; \ + init_rvtest_data_loop_end: \ +nop; \ +nop; \ + init_signature: \ + la a0, begin_signature; \ + la a1, end_signature; \ + li a2, 0xDEADBEEF; \ + init_signature_loop: \ + beq a0, a1, init_signature_loop_end; \ + sw a2, 0(a0); \ + addi a0, a0, 4; \ + j init_signature_loop; \ + init_signature_loop_end: \ + j uart_sim_mode_init; \ +nop; \ +nop; \ + .balign 4; \ + core_dummy_trap_handler: \ + csrw mscratch, sp; \ + la sp, end_signature; \ + addi sp, sp, 32; \ + sw x8, 0(sp); \ + sw x9, 4(sp); \ + csrr x8, mcause; \ + blt x8, zero, core_dummy_trap_handler_irq; \ + csrr x8, mepc; \ + core_dummy_trap_handler_exc_c_check: \ + lh x9, 0(x8); \ + andi x9, x9, 3; \ + addi x8, x8, +2; \ + csrw mepc, x8; \ + addi x8, zero, 3; \ + bne x8, x9, core_dummy_trap_handler_irq; \ + core_dummy_trap_handler_exc_uncrompressed: \ + csrr x8, mepc; \ + addi x8, x8, +2; \ + csrw mepc, x8; \ + core_dummy_trap_handler_irq: \ + lw x9, 0(sp); \ + lw x8, 4(sp); \ + csrr sp, mscratch; \ + mret; \ +nop; \ +nop; \ + uart_sim_mode_init: \ + li a0, 0xFFFFFFA0; \ + sw zero, 0(a0); \ + li a1, 1 << 28; \ + li a2, 1 << 12; \ + or a1, a1, a2; \ + sw a1, 0(a0); + +#endif + + +//RVTEST_IO_INIT +#define RVMODEL_IO_INIT +//RVTEST_IO_WRITE_STR +#define RVMODEL_IO_WRITE_STR(_R, _STR) +//RVTEST_IO_CHECK +#define RVMODEL_IO_CHECK() + +//RVTEST_IO_ASSERT_GPR_EQ +#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) +//RVTEST_IO_ASSERT_SFPR_EQ +#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) +//RVTEST_IO_ASSERT_DFPR_EQ +#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +// TODO: specify the routine for setting machine software interrupt +#define RVMODEL_SET_MSW_INT + +// TODO: specify the routine for clearing machine software interrupt +#define RVMODEL_CLEAR_MSW_INT + +// TODO: specify the routine for clearing machine timer interrupt +#define RVMODEL_CLEAR_MTIMER_INT + +// TODO: specify the routine for clearing machine external interrupt +#define RVMODEL_CLEAR_MEXT_INT + +#endif // _COMPLIANCE_MODEL_H Index: riscv-compliance/work/.gitignore =================================================================== --- riscv-compliance/work/.gitignore (nonexistent) +++ riscv-compliance/work/.gitignore (revision 40) @@ -0,0 +1,2 @@ +neorv32 +riscv-compliance \ No newline at end of file Index: riscv-compliance/README.md =================================================================== --- riscv-compliance/README.md (nonexistent) +++ riscv-compliance/README.md (revision 40) @@ -0,0 +1,50 @@ +# NEORV32 RISC-V-Compliance Test Framework + +**:sparkles: This setup uses the new [RISC-V Compliance Test Framework v2.1](https://github.com/riscv/riscv-compliance/releases/tag/v2.0) :sparkles:** + +## Overview + +This sub-project folder tests the [NEORV32 Processor Core](https://github.com/stnolting/neorv32) for **RISC-V compliance** by +using the [official RISC-V compliance test suite v2+](https://github.com/riscv/riscv-compliance). The core's HDL sources are *simulated* using +`GHDL` to provide a virtual execution platform for the test framework. + +The following tests are supported yet: + +* `rv32i_m/C` +* `rv32i_m/I` +* `rv32i_m/M` +* `rv32i_m/privilege` +* `rv32i_m/Zifencei` + + +## How To Run + +**Requirements:** +* `RISC-V GCC` toolchain (`riscv32-unknown-elf`) +* `GHDL` for simulating the processor + +To **execute all the supported tests** open a terminal an run (:warning: simulating everything takes quite some time): + + $ sh run_compliance_test.sh + + +## Details + +The [`run_compliance_test.sh`](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/run_compliance_test.sh) +bash script does the following: + +* Copy the `rtl`, `sim` and `sw` folders of the NEORV32 into `work/neorv32/` to keep the project's core files clean +* Clone (if not already there) the [riscv-compliance repository](https://github.com/riscv/riscv-compliance) into `work/` +* Install (copy) the custom `neorv32` test target from the ``port-neorv32/framework_v2.0/riscv-target` folder to the compliance test suite's target folder +* Replace the original IMEM VHDL source file of the processor (in `work/neorv32`) by the simulation-only file (`neorv32/sim/rtl_modules/neorv32_imem.vhd` to allow faster simulation) +* Run the actual compliance tests + +More datails regarding the actual simulation process can be found in the [target's +`README`](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md). +For more information regarding the NEORV32 Processor see the :page_facing_up: +[NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). + +:information_source: The port files for the *old framework (v1.0)* can be found in +[`port-neorv32/framework_v1.0`](https://github.com/stnolting/neorv32/tree/master/riscv-compliance/port-neorv32/framework_v1.0/riscv-target). + +:information_source: If the simulation of a test does not generate any signature outputs at all try increasing the simulation time in the NEORV32 port's device makefiles. Index: riscv-compliance/run_compliance_test.sh =================================================================== --- riscv-compliance/run_compliance_test.sh (nonexistent) +++ riscv-compliance/run_compliance_test.sh (revision 40) @@ -0,0 +1,87 @@ +#!/bin/bash + +# Abort if any command returns != 0 +set -e + +# Check GCC toolchain installation +echo "--------------------------------------------------------------------------" +echo "> Checking RISC-V GCC toolchain..." +echo "--------------------------------------------------------------------------" +riscv32-unknown-elf-gcc -v + +# Check GHDL installation +echo "--------------------------------------------------------------------------" +echo "> Checking GHDL simulator..." +echo "--------------------------------------------------------------------------" +ghdl -v + +# Clone RISC-V Compliance Test Suite GitHub repository if it not exists already +echo "--------------------------------------------------------------------------" +echo "> Checking 'RISC-V Compliance Test Suite' GitHub repository..." +echo "--------------------------------------------------------------------------" + +REPOSRC=https://github.com/riscv/riscv-compliance.git +LOCALREPO=work/riscv-compliance +LOCALREPO_VC_DIR=$LOCALREPO/.git + +if [ ! -d $LOCALREPO_VC_DIR ] +then + echo ">>> Cloning repository..." + git clone $REPOSRC $LOCALREPO +else + echo ">>> Repository already exists. Checking for updates..." + (cd work/riscv-compliance ; git status -uno) +fi + +# Copy NEORV32 files +echo "--------------------------------------------------------------------------" +echo "> Making local copy of NEORV32 'rtl', 'sim' & 'sw' folders..." +echo "--------------------------------------------------------------------------" +(cd work ; rm -rf neorv32 ; mkdir neorv32) +cp -r ../rtl/ work/neorv32/. +cp -r ../sim/ work/neorv32/. +cp -r ../sw/ work/neorv32/. + +# Copy neorv32 target folder into test suite +echo "--------------------------------------------------------------------------" +echo "> Copying neorv32 test-target into compliance framework..." +echo "--------------------------------------------------------------------------" +cp -rf port-neorv32/framework_v2.0/riscv-target/neorv32 work/riscv-compliance/riscv-target/. + +# Make a local copy of the original IMEM rtl file +echo "" +echo ">>> Making local backup if original IMEM rtl file (work/neorv32/rtl/core/neorv32_imem.vhd)..." +echo "" +cp work/neorv32/rtl/core/neorv32_imem.vhd work/neorv32/rtl/core/neorv32_imem.ORIGINAL + +# Component installation done +ls -al +echo "--------------------------------------------------------------------------" +echo "> Component installation done!" +echo "--------------------------------------------------------------------------" +echo "" + + +# Local NEORV32 copy - home folder +homedir="$( cd "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )" +homedir=$homedir + +# neorv32 home folder +NEORV32_LOCAL_HOME=$homedir/work/neorv32 + +echo "--------------------------------------------------------------------------" +echo "> Starting RISC-V compliance tests..." +echo "--------------------------------------------------------------------------" + +# Clean everything +make -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 clean + +# Run tests and check results +make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=I build run verify +make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=C build run verify +make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=M build run verify +make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=privilege build run verify +make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=Zifencei RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT build run verify + +echo "" +echo "Compliance tests completed" Index: rtl/core/neorv32_application_image.vhd =================================================================== --- rtl/core/neorv32_application_image.vhd (revision 39) +++ rtl/core/neorv32_application_image.vhd (revision 40) @@ -6,7 +6,7 @@ package neorv32_application_image is - type application_init_image_t is array (0 to 783) of std_ulogic_vector(31 downto 0); + type application_init_image_t is array (0 to 800) of std_ulogic_vector(31 downto 0); constant application_init_image : application_init_image_t := ( 00000000 => x"00000093", 00000001 => x"00000113", @@ -46,7 +46,7 @@ 00000035 => x"80000197", 00000036 => x"77418193", 00000037 => x"00000597", - 00000038 => x"09458593", + 00000038 => x"09c58593", 00000039 => x"30559073", 00000040 => x"f8000593", 00000041 => x"0005a023", @@ -54,13 +54,13 @@ 00000043 => x"feb01ce3", 00000044 => x"80000597", 00000045 => x"f5058593", - 00000046 => x"84018613", + 00000046 => x"84418613", 00000047 => x"00c5d863", 00000048 => x"00058023", 00000049 => x"00158593", 00000050 => x"ff5ff06f", 00000051 => x"00001597", - 00000052 => x"b7058593", + 00000052 => x"bb458593", 00000053 => x"80000617", 00000054 => x"f2c60613", 00000055 => x"80000697", @@ -77,65 +77,65 @@ 00000066 => x"b8001073", 00000067 => x"b0201073", 00000068 => x"b8201073", - 00000069 => x"060000ef", - 00000070 => x"30047073", - 00000071 => x"00000013", - 00000072 => x"10500073", - 00000073 => x"0000006f", - 00000074 => x"ff810113", - 00000075 => x"00812023", - 00000076 => x"00912223", - 00000077 => x"34202473", - 00000078 => x"02044663", - 00000079 => x"34102473", - 00000080 => x"00041483", - 00000081 => x"0034f493", - 00000082 => x"00240413", - 00000083 => x"34141073", - 00000084 => x"00300413", - 00000085 => x"00941863", - 00000086 => x"34102473", - 00000087 => x"00240413", - 00000088 => x"34141073", - 00000089 => x"00012483", - 00000090 => x"00412403", - 00000091 => x"00810113", - 00000092 => x"30200073", - 00000093 => x"00005537", - 00000094 => x"ff010113", - 00000095 => x"00000613", - 00000096 => x"00000593", - 00000097 => x"b0050513", - 00000098 => x"00112623", - 00000099 => x"490000ef", - 00000100 => x"61c000ef", - 00000101 => x"00050c63", - 00000102 => x"428000ef", - 00000103 => x"00001537", - 00000104 => x"95050513", - 00000105 => x"514000ef", - 00000106 => x"020000ef", - 00000107 => x"00001537", - 00000108 => x"92c50513", - 00000109 => x"504000ef", - 00000110 => x"00c12083", - 00000111 => x"00000513", - 00000112 => x"01010113", - 00000113 => x"00008067", - 00000114 => x"ff010113", - 00000115 => x"00000513", - 00000116 => x"00812423", - 00000117 => x"00112623", - 00000118 => x"00000413", - 00000119 => x"5e0000ef", - 00000120 => x"0ff47513", - 00000121 => x"5d8000ef", - 00000122 => x"0c800513", - 00000123 => x"550000ef", - 00000124 => x"00140413", - 00000125 => x"fedff06f", - 00000126 => x"00000000", - 00000127 => x"00000000", + 00000069 => x"80000637", + 00000070 => x"34261073", + 00000071 => x"060000ef", + 00000072 => x"30047073", + 00000073 => x"00000013", + 00000074 => x"10500073", + 00000075 => x"0000006f", + 00000076 => x"ff810113", + 00000077 => x"00812023", + 00000078 => x"00912223", + 00000079 => x"34202473", + 00000080 => x"02044663", + 00000081 => x"34102473", + 00000082 => x"00041483", + 00000083 => x"0034f493", + 00000084 => x"00240413", + 00000085 => x"34141073", + 00000086 => x"00300413", + 00000087 => x"00941863", + 00000088 => x"34102473", + 00000089 => x"00240413", + 00000090 => x"34141073", + 00000091 => x"00012483", + 00000092 => x"00412403", + 00000093 => x"00810113", + 00000094 => x"30200073", + 00000095 => x"00005537", + 00000096 => x"ff010113", + 00000097 => x"00000613", + 00000098 => x"00000593", + 00000099 => x"b0050513", + 00000100 => x"00112623", + 00000101 => x"4a0000ef", + 00000102 => x"62c000ef", + 00000103 => x"00050c63", + 00000104 => x"438000ef", + 00000105 => x"00001537", + 00000106 => x"96850513", + 00000107 => x"524000ef", + 00000108 => x"020000ef", + 00000109 => x"00001537", + 00000110 => x"94450513", + 00000111 => x"514000ef", + 00000112 => x"00c12083", + 00000113 => x"00000513", + 00000114 => x"01010113", + 00000115 => x"00008067", + 00000116 => x"ff010113", + 00000117 => x"00000513", + 00000118 => x"00812423", + 00000119 => x"00112623", + 00000120 => x"00000413", + 00000121 => x"5f0000ef", + 00000122 => x"0ff47513", + 00000123 => x"5e8000ef", + 00000124 => x"0c800513", + 00000125 => x"560000ef", + 00000126 => x"00140413", + 00000127 => x"fedff06f", 00000128 => x"fc010113", 00000129 => x"02112e23", 00000130 => x"02512c23", @@ -166,7 +166,7 @@ 00000155 => x"34161073", 00000156 => x"00b00713", 00000157 => x"04f77a63", - 00000158 => x"41000793", + 00000158 => x"41c00793", 00000159 => x"000780e7", 00000160 => x"03c12083", 00000161 => x"03812283", @@ -188,7 +188,7 @@ 00000177 => x"30200073", 00000178 => x"00001737", 00000179 => x"00279793", - 00000180 => x"96c70713", + 00000180 => x"98470713", 00000181 => x"00e787b3", 00000182 => x"0007a783", 00000183 => x"00078067", @@ -199,7 +199,7 @@ 00000188 => x"f8f764e3", 00000189 => x"00001737", 00000190 => x"00279793", - 00000191 => x"99c70713", + 00000191 => x"9b470713", 00000192 => x"00e787b3", 00000193 => x"0007a783", 00000194 => x"00078067", @@ -239,558 +239,575 @@ 00000228 => x"eedff06f", 00000229 => x"83c1a783", 00000230 => x"ee5ff06f", - 00000231 => x"00000000", - 00000232 => x"fe010113", - 00000233 => x"01212823", - 00000234 => x"00050913", - 00000235 => x"00001537", - 00000236 => x"00912a23", - 00000237 => x"9e050513", - 00000238 => x"000014b7", - 00000239 => x"00812c23", - 00000240 => x"01312623", - 00000241 => x"00112e23", - 00000242 => x"01c00413", - 00000243 => x"2ec000ef", - 00000244 => x"c2c48493", - 00000245 => x"ffc00993", - 00000246 => x"008957b3", - 00000247 => x"00f7f793", - 00000248 => x"00f487b3", - 00000249 => x"0007c503", - 00000250 => x"ffc40413", - 00000251 => x"2bc000ef", - 00000252 => x"ff3414e3", - 00000253 => x"01c12083", - 00000254 => x"01812403", - 00000255 => x"01412483", - 00000256 => x"01012903", - 00000257 => x"00c12983", - 00000258 => x"02010113", - 00000259 => x"00008067", - 00000260 => x"00001537", - 00000261 => x"ff010113", - 00000262 => x"9e450513", - 00000263 => x"00112623", - 00000264 => x"00812423", - 00000265 => x"294000ef", - 00000266 => x"34202473", - 00000267 => x"00b00793", - 00000268 => x"0487f463", - 00000269 => x"800007b7", - 00000270 => x"ffd7c793", - 00000271 => x"00f407b3", - 00000272 => x"01000713", - 00000273 => x"00f77e63", - 00000274 => x"00001537", - 00000275 => x"b5850513", - 00000276 => x"268000ef", - 00000277 => x"00040513", - 00000278 => x"f49ff0ef", - 00000279 => x"0400006f", - 00000280 => x"00001737", - 00000281 => x"00279793", - 00000282 => x"b8470713", - 00000283 => x"00e787b3", - 00000284 => x"0007a783", - 00000285 => x"00078067", - 00000286 => x"00001737", - 00000287 => x"00241793", - 00000288 => x"bc870713", - 00000289 => x"00e787b3", - 00000290 => x"0007a783", - 00000291 => x"00078067", - 00000292 => x"00001537", - 00000293 => x"9ec50513", - 00000294 => x"220000ef", + 00000231 => x"8401a783", + 00000232 => x"eddff06f", + 00000233 => x"00000000", + 00000234 => x"00000000", + 00000235 => x"fe010113", + 00000236 => x"01212823", + 00000237 => x"00050913", + 00000238 => x"00001537", + 00000239 => x"00912a23", + 00000240 => x"9f850513", + 00000241 => x"000014b7", + 00000242 => x"00812c23", + 00000243 => x"01312623", + 00000244 => x"00112e23", + 00000245 => x"01c00413", + 00000246 => x"2f8000ef", + 00000247 => x"c7048493", + 00000248 => x"ffc00993", + 00000249 => x"008957b3", + 00000250 => x"00f7f793", + 00000251 => x"00f487b3", + 00000252 => x"0007c503", + 00000253 => x"ffc40413", + 00000254 => x"2c8000ef", + 00000255 => x"ff3414e3", + 00000256 => x"01c12083", + 00000257 => x"01812403", + 00000258 => x"01412483", + 00000259 => x"01012903", + 00000260 => x"00c12983", + 00000261 => x"02010113", + 00000262 => x"00008067", + 00000263 => x"00001537", + 00000264 => x"ff010113", + 00000265 => x"9fc50513", + 00000266 => x"00112623", + 00000267 => x"00812423", + 00000268 => x"2a0000ef", + 00000269 => x"34202473", + 00000270 => x"00b00793", + 00000271 => x"0487f463", + 00000272 => x"800007b7", + 00000273 => x"ffd7c793", + 00000274 => x"00f407b3", + 00000275 => x"01000713", + 00000276 => x"00f77e63", + 00000277 => x"00001537", + 00000278 => x"b9c50513", + 00000279 => x"274000ef", + 00000280 => x"00040513", + 00000281 => x"f49ff0ef", + 00000282 => x"0400006f", + 00000283 => x"00001737", + 00000284 => x"00279793", + 00000285 => x"bc870713", + 00000286 => x"00e787b3", + 00000287 => x"0007a783", + 00000288 => x"00078067", + 00000289 => x"00001737", + 00000290 => x"00241793", + 00000291 => x"c0c70713", + 00000292 => x"00e787b3", + 00000293 => x"0007a783", + 00000294 => x"00078067", 00000295 => x"00001537", - 00000296 => x"b7050513", - 00000297 => x"214000ef", - 00000298 => x"34002573", - 00000299 => x"ef5ff0ef", - 00000300 => x"00001537", - 00000301 => x"b7850513", - 00000302 => x"200000ef", - 00000303 => x"34302573", - 00000304 => x"ee1ff0ef", - 00000305 => x"00812403", - 00000306 => x"00c12083", - 00000307 => x"00001537", - 00000308 => x"c2450513", - 00000309 => x"01010113", - 00000310 => x"1e00006f", - 00000311 => x"00001537", - 00000312 => x"a0c50513", - 00000313 => x"fb5ff06f", + 00000296 => x"a0450513", + 00000297 => x"22c000ef", + 00000298 => x"00001537", + 00000299 => x"bb450513", + 00000300 => x"220000ef", + 00000301 => x"34002573", + 00000302 => x"ef5ff0ef", + 00000303 => x"00001537", + 00000304 => x"bbc50513", + 00000305 => x"20c000ef", + 00000306 => x"34302573", + 00000307 => x"ee1ff0ef", + 00000308 => x"00812403", + 00000309 => x"00c12083", + 00000310 => x"00001537", + 00000311 => x"c6850513", + 00000312 => x"01010113", + 00000313 => x"1ec0006f", 00000314 => x"00001537", - 00000315 => x"a2850513", - 00000316 => x"fa9ff06f", + 00000315 => x"a2450513", + 00000316 => x"fb5ff06f", 00000317 => x"00001537", - 00000318 => x"a3c50513", - 00000319 => x"f9dff06f", + 00000318 => x"a4050513", + 00000319 => x"fa9ff06f", 00000320 => x"00001537", - 00000321 => x"a4850513", - 00000322 => x"f91ff06f", + 00000321 => x"a5450513", + 00000322 => x"f9dff06f", 00000323 => x"00001537", 00000324 => x"a6050513", - 00000325 => x"f85ff06f", + 00000325 => x"f91ff06f", 00000326 => x"00001537", - 00000327 => x"a7450513", - 00000328 => x"f79ff06f", + 00000327 => x"a7850513", + 00000328 => x"f85ff06f", 00000329 => x"00001537", - 00000330 => x"a9050513", - 00000331 => x"f6dff06f", + 00000330 => x"a8c50513", + 00000331 => x"f79ff06f", 00000332 => x"00001537", - 00000333 => x"aa450513", - 00000334 => x"f61ff06f", + 00000333 => x"aa850513", + 00000334 => x"f6dff06f", 00000335 => x"00001537", - 00000336 => x"ab850513", - 00000337 => x"f55ff06f", + 00000336 => x"abc50513", + 00000337 => x"f61ff06f", 00000338 => x"00001537", - 00000339 => x"ad450513", - 00000340 => x"f49ff06f", + 00000339 => x"adc50513", + 00000340 => x"f55ff06f", 00000341 => x"00001537", - 00000342 => x"aec50513", - 00000343 => x"f3dff06f", + 00000342 => x"afc50513", + 00000343 => x"f49ff06f", 00000344 => x"00001537", - 00000345 => x"b0850513", - 00000346 => x"f31ff06f", + 00000345 => x"b1850513", + 00000346 => x"f3dff06f", 00000347 => x"00001537", - 00000348 => x"b1c50513", - 00000349 => x"f25ff06f", + 00000348 => x"b3050513", + 00000349 => x"f31ff06f", 00000350 => x"00001537", - 00000351 => x"b3050513", - 00000352 => x"f19ff06f", + 00000351 => x"b4c50513", + 00000352 => x"f25ff06f", 00000353 => x"00001537", - 00000354 => x"b4450513", - 00000355 => x"f0dff06f", - 00000356 => x"00f00793", - 00000357 => x"02a7e263", - 00000358 => x"800007b7", - 00000359 => x"00078793", - 00000360 => x"00251513", - 00000361 => x"00a78533", - 00000362 => x"41000793", - 00000363 => x"00f52023", - 00000364 => x"00000513", - 00000365 => x"00008067", - 00000366 => x"00100513", - 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