URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
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- This comparison shows the changes necessary to convert path
/neorv32/trunk
- from Rev 40 to Rev 41
- ↔ Reverse comparison
Rev 40 → Rev 41
/docs/figures/neorv32_bus.png
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docs/figures/neorv32_bus.png
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Index: docs/figures/neorv32_processor.png
===================================================================
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Index: docs/NEORV32.pdf
===================================================================
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Index: riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include
===================================================================
--- riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include (revision 40)
+++ riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/C/Makefile.include (revision 41)
@@ -32,7 +32,7 @@
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \
sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \
- sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=600us >> /dev/null; \
+ sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \
cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output;
/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/I/Makefile.include
32,7 → 32,7
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \ |
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ |
sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \ |
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=800us >> /dev/null; \ |
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \ |
cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; |
|
|
/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/M/Makefile.include
32,7 → 32,7
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \ |
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ |
sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \ |
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=800us >> /dev/null; \ |
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \ |
cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; |
|
|
/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/Zifencei/Makefile.include
31,7 → 31,7
cp -f $< $(NEORV32_LOCAL_COPY)/sw/example/blink_led/main.elf; \ |
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \ |
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ |
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=600us >> /dev/null; \ |
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \ |
cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; |
|
|
/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/device/rv32i_m/privilege/Makefile.include
32,7 → 32,7
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led main.bin; \ |
make -C $(NEORV32_LOCAL_COPY)/sw/example/blink_led install; \ |
sed -i '/type application_init_image_t/c\type application_init_image_t is array (0 to ((2*1024*1024)/4)-1) of std_ulogic_vector(31 downto 0); -- MOD. BY RISCV-COMPL. TEST SCRIPT' $(NEORV32_LOCAL_COPY)/rtl/core/neorv32_application_image.vhd; \ |
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=600us >> /dev/null; \ |
sh $(NEORV32_LOCAL_COPY)/sim/ghdl/ghdl_sim.sh --stop-time=$(SIM_TIME) >> /dev/null; \ |
cp $(work_dir_isa)/neorv32.uart.sim_mode.data.out $(*).signature.output; |
|
|
/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md
17,6 → 17,13
* the according code can be found in the `RVMODEL_HALT` macro in `model_test.h` |
* data output (the "signature") is zero-padded to be always a multiple of 16 bytes |
|
|
**Notes** |
|
:warning: The `Zifencei` test requires the r/w/e capabilities of the original IMEM rtl file. |
Hence, the original file is restored for this test. Also, this test uses `link.imem_ram.ld` as linker script since the |
IMEM is used as RAM to allow self-modifying code. |
|
:information_source: The `RVMODEL_BOOT` macro in `model_test.h` provides a simple "dummy trap handler" that just advances to the next instruction. This trap handler is required |
for some `C` tests as the NEORV32 will raise an illegal instruction exception for **all** unimplemented instructions. The trap handler is overriden (by changing `mtval` CSR) if |
a test uses the defualt trap handler of the test framework. |
/riscv-compliance/README.md
47,4 → 47,5
:information_source: The port files for the *old framework (v1.0)* can be found in |
[`port-neorv32/framework_v1.0`](https://github.com/stnolting/neorv32/tree/master/riscv-compliance/port-neorv32/framework_v1.0/riscv-target). |
|
:information_source: If the simulation of a test does not generate any signature outputs at all try increasing the simulation time in the NEORV32 port's device makefiles. |
:information_source: If the simulation of a test does not generate any signature output at all or if the signature is truncated |
try increasing the simulation time by modiying the `SIM_TIME` variable when calling the test makefiles in 'run_compliance_test.sh'. |
/riscv-compliance/run_compliance_test.sh
77,11 → 77,11
make -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 clean |
|
# Run tests and check results |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=I build run verify |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=C build run verify |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=M build run verify |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=privilege build run verify |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=Zifencei RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT build run verify |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=600us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=I build run verify |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=400us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=C build run verify |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=800us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=M build run verify |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=200us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=privilege build run verify |
make --silent -C $homedir/work/riscv-compliance NEORV32_LOCAL_COPY=$NEORV32_LOCAL_HOME SIM_TIME=200us XLEN=32 RISCV_TARGET=neorv32 RISCV_DEVICE=Zifencei RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT build run verify |
|
echo "" |
echo "Compliance tests completed" |
/rtl/core/neorv32_application_image.vhd
6,7 → 6,7
|
package neorv32_application_image is |
|
type application_init_image_t is array (0 to 800) of std_ulogic_vector(31 downto 0); |
type application_init_image_t is array (0 to 804) of std_ulogic_vector(31 downto 0); |
constant application_init_image : application_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
46,7 → 46,7
00000035 => x"80000197", |
00000036 => x"77418193", |
00000037 => x"00000597", |
00000038 => x"09c58593", |
00000038 => x"0a458593", |
00000039 => x"30559073", |
00000040 => x"f8000593", |
00000041 => x"0005a023", |
60,7 → 60,7
00000049 => x"00158593", |
00000050 => x"ff5ff06f", |
00000051 => x"00001597", |
00000052 => x"bb458593", |
00000052 => x"bc458593", |
00000053 => x"80000617", |
00000054 => x"f2c60613", |
00000055 => x"80000697", |
77,737 → 77,741
00000066 => x"b8001073", |
00000067 => x"b0201073", |
00000068 => x"b8201073", |
00000069 => x"80000637", |
00000070 => x"34261073", |
00000071 => x"060000ef", |
00000072 => x"30047073", |
00000073 => x"00000013", |
00000074 => x"10500073", |
00000075 => x"0000006f", |
00000076 => x"ff810113", |
00000077 => x"00812023", |
00000078 => x"00912223", |
00000079 => x"34202473", |
00000080 => x"02044663", |
00000081 => x"34102473", |
00000082 => x"00041483", |
00000083 => x"0034f493", |
00000084 => x"00240413", |
00000085 => x"34141073", |
00000086 => x"00300413", |
00000087 => x"00941863", |
00000088 => x"34102473", |
00000089 => x"00240413", |
00000090 => x"34141073", |
00000091 => x"00012483", |
00000092 => x"00412403", |
00000093 => x"00810113", |
00000094 => x"30200073", |
00000095 => x"00005537", |
00000096 => x"ff010113", |
00000097 => x"00000613", |
00000098 => x"00000593", |
00000099 => x"b0050513", |
00000100 => x"00112623", |
00000101 => x"4a0000ef", |
00000102 => x"62c000ef", |
00000103 => x"00050c63", |
00000104 => x"438000ef", |
00000105 => x"00001537", |
00000106 => x"96850513", |
00000107 => x"524000ef", |
00000108 => x"020000ef", |
00000109 => x"00001537", |
00000110 => x"94450513", |
00000111 => x"514000ef", |
00000112 => x"00c12083", |
00000113 => x"00000513", |
00000114 => x"01010113", |
00000115 => x"00008067", |
00000116 => x"ff010113", |
00000117 => x"00000513", |
00000118 => x"00812423", |
00000119 => x"00112623", |
00000120 => x"00000413", |
00000121 => x"5f0000ef", |
00000122 => x"0ff47513", |
00000123 => x"5e8000ef", |
00000124 => x"0c800513", |
00000125 => x"560000ef", |
00000126 => x"00140413", |
00000127 => x"fedff06f", |
00000128 => x"fc010113", |
00000129 => x"02112e23", |
00000130 => x"02512c23", |
00000131 => x"02612a23", |
00000132 => x"02712823", |
00000133 => x"02a12623", |
00000134 => x"02b12423", |
00000135 => x"02c12223", |
00000136 => x"02d12023", |
00000137 => x"00e12e23", |
00000138 => x"00f12c23", |
00000139 => x"01012a23", |
00000140 => x"01112823", |
00000141 => x"01c12623", |
00000142 => x"01d12423", |
00000143 => x"01e12223", |
00000144 => x"01f12023", |
00000145 => x"34102773", |
00000146 => x"34071073", |
00000147 => x"342027f3", |
00000148 => x"0807c863", |
00000149 => x"00071683", |
00000150 => x"00300593", |
00000151 => x"0036f693", |
00000152 => x"00270613", |
00000153 => x"00b69463", |
00000154 => x"00470613", |
00000155 => x"34161073", |
00000156 => x"00b00713", |
00000157 => x"04f77a63", |
00000158 => x"41c00793", |
00000159 => x"000780e7", |
00000160 => x"03c12083", |
00000161 => x"03812283", |
00000162 => x"03412303", |
00000163 => x"03012383", |
00000164 => x"02c12503", |
00000165 => x"02812583", |
00000166 => x"02412603", |
00000167 => x"02012683", |
00000168 => x"01c12703", |
00000169 => x"01812783", |
00000170 => x"01412803", |
00000171 => x"01012883", |
00000172 => x"00c12e03", |
00000173 => x"00812e83", |
00000174 => x"00412f03", |
00000175 => x"00012f83", |
00000176 => x"04010113", |
00000177 => x"30200073", |
00000178 => x"00001737", |
00000179 => x"00279793", |
00000180 => x"98470713", |
00000181 => x"00e787b3", |
00000182 => x"0007a783", |
00000183 => x"00078067", |
00000184 => x"80000737", |
00000185 => x"ffd74713", |
00000186 => x"00e787b3", |
00000187 => x"01000713", |
00000188 => x"f8f764e3", |
00000189 => x"00001737", |
00000190 => x"00279793", |
00000191 => x"9b470713", |
00000192 => x"00e787b3", |
00000193 => x"0007a783", |
00000194 => x"00078067", |
00000195 => x"800007b7", |
00000196 => x"0007a783", |
00000197 => x"f69ff06f", |
00000198 => x"800007b7", |
00000199 => x"0047a783", |
00000200 => x"f5dff06f", |
00000201 => x"800007b7", |
00000202 => x"0087a783", |
00000203 => x"f51ff06f", |
00000204 => x"800007b7", |
00000205 => x"00c7a783", |
00000206 => x"f45ff06f", |
00000207 => x"8101a783", |
00000208 => x"f3dff06f", |
00000209 => x"8141a783", |
00000210 => x"f35ff06f", |
00000211 => x"8181a783", |
00000212 => x"f2dff06f", |
00000213 => x"81c1a783", |
00000214 => x"f25ff06f", |
00000215 => x"8201a783", |
00000216 => x"f1dff06f", |
00000217 => x"8241a783", |
00000218 => x"f15ff06f", |
00000219 => x"8281a783", |
00000220 => x"f0dff06f", |
00000221 => x"82c1a783", |
00000222 => x"f05ff06f", |
00000223 => x"8301a783", |
00000224 => x"efdff06f", |
00000225 => x"8341a783", |
00000226 => x"ef5ff06f", |
00000227 => x"8381a783", |
00000228 => x"eedff06f", |
00000229 => x"83c1a783", |
00000230 => x"ee5ff06f", |
00000231 => x"8401a783", |
00000232 => x"eddff06f", |
00000233 => x"00000000", |
00000234 => x"00000000", |
00000235 => x"fe010113", |
00000236 => x"01212823", |
00000237 => x"00050913", |
00000238 => x"00001537", |
00000239 => x"00912a23", |
00000240 => x"9f850513", |
00000241 => x"000014b7", |
00000242 => x"00812c23", |
00000243 => x"01312623", |
00000244 => x"00112e23", |
00000245 => x"01c00413", |
00000246 => x"2f8000ef", |
00000247 => x"c7048493", |
00000248 => x"ffc00993", |
00000249 => x"008957b3", |
00000250 => x"00f7f793", |
00000251 => x"00f487b3", |
00000252 => x"0007c503", |
00000253 => x"ffc40413", |
00000254 => x"2c8000ef", |
00000255 => x"ff3414e3", |
00000256 => x"01c12083", |
00000257 => x"01812403", |
00000258 => x"01412483", |
00000259 => x"01012903", |
00000260 => x"00c12983", |
00000261 => x"02010113", |
00000262 => x"00008067", |
00000263 => x"00001537", |
00000264 => x"ff010113", |
00000265 => x"9fc50513", |
00000266 => x"00112623", |
00000267 => x"00812423", |
00000268 => x"2a0000ef", |
00000269 => x"34202473", |
00000270 => x"00b00793", |
00000271 => x"0487f463", |
00000272 => x"800007b7", |
00000273 => x"ffd7c793", |
00000274 => x"00f407b3", |
00000275 => x"01000713", |
00000276 => x"00f77e63", |
00000277 => x"00001537", |
00000278 => x"b9c50513", |
00000279 => x"274000ef", |
00000280 => x"00040513", |
00000281 => x"f49ff0ef", |
00000282 => x"0400006f", |
00000283 => x"00001737", |
00000284 => x"00279793", |
00000285 => x"bc870713", |
00000286 => x"00e787b3", |
00000287 => x"0007a783", |
00000288 => x"00078067", |
00000289 => x"00001737", |
00000290 => x"00241793", |
00000291 => x"c0c70713", |
00000292 => x"00e787b3", |
00000293 => x"0007a783", |
00000294 => x"00078067", |
00000295 => x"00001537", |
00000296 => x"a0450513", |
00000297 => x"22c000ef", |
00000298 => x"00001537", |
00000299 => x"bb450513", |
00000300 => x"220000ef", |
00000301 => x"34002573", |
00000302 => x"ef5ff0ef", |
00000303 => x"00001537", |
00000304 => x"bbc50513", |
00000305 => x"20c000ef", |
00000306 => x"34302573", |
00000307 => x"ee1ff0ef", |
00000308 => x"00812403", |
00000309 => x"00c12083", |
00000310 => x"00001537", |
00000311 => x"c6850513", |
00000312 => x"01010113", |
00000313 => x"1ec0006f", |
00000069 => x"3063d073", |
00000070 => x"32001073", |
00000071 => x"80000637", |
00000072 => x"34261073", |
00000073 => x"060000ef", |
00000074 => x"30047073", |
00000075 => x"00000013", |
00000076 => x"10500073", |
00000077 => x"0000006f", |
00000078 => x"ff810113", |
00000079 => x"00812023", |
00000080 => x"00912223", |
00000081 => x"34202473", |
00000082 => x"02044663", |
00000083 => x"34102473", |
00000084 => x"00041483", |
00000085 => x"0034f493", |
00000086 => x"00240413", |
00000087 => x"34141073", |
00000088 => x"00300413", |
00000089 => x"00941863", |
00000090 => x"34102473", |
00000091 => x"00240413", |
00000092 => x"34141073", |
00000093 => x"00012483", |
00000094 => x"00412403", |
00000095 => x"00810113", |
00000096 => x"30200073", |
00000097 => x"00005537", |
00000098 => x"ff010113", |
00000099 => x"00000613", |
00000100 => x"00000593", |
00000101 => x"b0050513", |
00000102 => x"00112623", |
00000103 => x"4a8000ef", |
00000104 => x"598000ef", |
00000105 => x"00050c63", |
00000106 => x"440000ef", |
00000107 => x"00001537", |
00000108 => x"97850513", |
00000109 => x"52c000ef", |
00000110 => x"020000ef", |
00000111 => x"00001537", |
00000112 => x"95450513", |
00000113 => x"51c000ef", |
00000114 => x"00c12083", |
00000115 => x"00000513", |
00000116 => x"01010113", |
00000117 => x"00008067", |
00000118 => x"ff010113", |
00000119 => x"00000513", |
00000120 => x"00812423", |
00000121 => x"00112623", |
00000122 => x"00000413", |
00000123 => x"55c000ef", |
00000124 => x"0ff47513", |
00000125 => x"554000ef", |
00000126 => x"0c800513", |
00000127 => x"580000ef", |
00000128 => x"00140413", |
00000129 => x"fedff06f", |
00000130 => x"00000000", |
00000131 => x"00000000", |
00000132 => x"fc010113", |
00000133 => x"02112e23", |
00000134 => x"02512c23", |
00000135 => x"02612a23", |
00000136 => x"02712823", |
00000137 => x"02a12623", |
00000138 => x"02b12423", |
00000139 => x"02c12223", |
00000140 => x"02d12023", |
00000141 => x"00e12e23", |
00000142 => x"00f12c23", |
00000143 => x"01012a23", |
00000144 => x"01112823", |
00000145 => x"01c12623", |
00000146 => x"01d12423", |
00000147 => x"01e12223", |
00000148 => x"01f12023", |
00000149 => x"34102773", |
00000150 => x"34071073", |
00000151 => x"342027f3", |
00000152 => x"0807c863", |
00000153 => x"00071683", |
00000154 => x"00300593", |
00000155 => x"0036f693", |
00000156 => x"00270613", |
00000157 => x"00b69463", |
00000158 => x"00470613", |
00000159 => x"34161073", |
00000160 => x"00b00713", |
00000161 => x"04f77a63", |
00000162 => x"42c00793", |
00000163 => x"000780e7", |
00000164 => x"03c12083", |
00000165 => x"03812283", |
00000166 => x"03412303", |
00000167 => x"03012383", |
00000168 => x"02c12503", |
00000169 => x"02812583", |
00000170 => x"02412603", |
00000171 => x"02012683", |
00000172 => x"01c12703", |
00000173 => x"01812783", |
00000174 => x"01412803", |
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00000556 => x"fff00513", |
00000557 => x"02060c63", |
00000558 => x"00100693", |
00000559 => x"00b67a63", |
00000560 => x"00c05863", |
00000561 => x"00161613", |
00000562 => x"00169693", |
00000563 => x"feb66ae3", |
00000564 => x"00000513", |
00000565 => x"00c5e663", |
00000566 => x"40c585b3", |
00000567 => x"00d56533", |
00000568 => x"0016d693", |
00000569 => x"00165613", |
00000570 => x"fe0696e3", |
00000571 => x"00008067", |
00000572 => x"00008293", |
00000573 => x"0005ca63", |
00000574 => x"00054c63", |
00000575 => x"f79ff0ef", |
00000576 => x"00058513", |
00000577 => x"00028067", |
00000573 => x"fb5ff0ef", |
00000574 => x"00058513", |
00000575 => x"00028067", |
00000576 => x"40a00533", |
00000577 => x"00b04863", |
00000578 => x"40b005b3", |
00000579 => x"fe0558e3", |
00000580 => x"40a00533", |
00000581 => x"f61ff0ef", |
00000582 => x"40b00533", |
00000583 => x"00028067", |
00000584 => x"00050613", |
00000585 => x"00000513", |
00000586 => x"0015f693", |
00000587 => x"00068463", |
00000588 => x"00c50533", |
00000589 => x"0015d593", |
00000590 => x"00161613", |
00000591 => x"fe0596e3", |
00000592 => x"00008067", |
00000593 => x"6f727245", |
00000594 => x"4e202172", |
00000595 => x"5047206f", |
00000596 => x"75204f49", |
00000597 => x"2074696e", |
00000598 => x"746e7973", |
00000599 => x"69736568", |
00000600 => x"2164657a", |
00000601 => x"0000000a", |
00000602 => x"6e696c42", |
00000603 => x"676e696b", |
00000604 => x"44454c20", |
00000605 => x"6d656420", |
00000606 => x"7270206f", |
00000607 => x"6172676f", |
00000608 => x"00000a6d", |
00000609 => x"0000030c", |
00000610 => x"00000318", |
00000611 => x"00000324", |
00000612 => x"00000330", |
00000613 => x"0000033c", |
00000614 => x"00000344", |
00000615 => x"0000034c", |
00000616 => x"00000354", |
00000617 => x"0000035c", |
00000618 => x"00000278", |
00000619 => x"00000278", |
00000579 => x"f9dff06f", |
00000580 => x"40b005b3", |
00000581 => x"00008293", |
00000582 => x"f91ff0ef", |
00000583 => x"40a00533", |
00000584 => x"00028067", |
00000585 => x"00008293", |
00000586 => x"0005ca63", |
00000587 => x"00054c63", |
00000588 => x"f79ff0ef", |
00000589 => x"00058513", |
00000590 => x"00028067", |
00000591 => x"40b005b3", |
00000592 => x"fe0558e3", |
00000593 => x"40a00533", |
00000594 => x"f61ff0ef", |
00000595 => x"40b00533", |
00000596 => x"00028067", |
00000597 => x"6f727245", |
00000598 => x"4e202172", |
00000599 => x"5047206f", |
00000600 => x"75204f49", |
00000601 => x"2074696e", |
00000602 => x"746e7973", |
00000603 => x"69736568", |
00000604 => x"2164657a", |
00000605 => x"0000000a", |
00000606 => x"6e696c42", |
00000607 => x"676e696b", |
00000608 => x"44454c20", |
00000609 => x"6d656420", |
00000610 => x"7270206f", |
00000611 => x"6172676f", |
00000612 => x"00000a6d", |
00000613 => x"0000031c", |
00000614 => x"00000328", |
00000615 => x"00000334", |
00000616 => x"00000340", |
00000617 => x"0000034c", |
00000618 => x"00000354", |
00000619 => x"0000035c", |
00000620 => x"00000364", |
00000621 => x"0000036c", |
00000622 => x"00000278", |
00000623 => x"00000278", |
00000624 => x"00000278", |
00000625 => x"00000374", |
00000626 => x"00000278", |
00000627 => x"00000278", |
00000628 => x"00000278", |
00000629 => x"0000037c", |
00000630 => x"00000278", |
00000631 => x"00000278", |
00000632 => x"00000278", |
00000633 => x"00000278", |
00000634 => x"00000384", |
00000635 => x"0000038c", |
00000636 => x"00000394", |
00000637 => x"0000039c", |
00000638 => x"00007830", |
00000639 => x"4554523c", |
00000640 => x"0000203e", |
00000641 => x"74736e49", |
00000642 => x"74637572", |
00000643 => x"206e6f69", |
00000644 => x"72646461", |
00000645 => x"20737365", |
00000646 => x"6173696d", |
00000647 => x"6e67696c", |
00000648 => x"00006465", |
00000649 => x"74736e49", |
00000650 => x"74637572", |
00000651 => x"206e6f69", |
00000652 => x"65636361", |
00000653 => x"66207373", |
00000654 => x"746c7561", |
00000655 => x"00000000", |
00000656 => x"656c6c49", |
00000657 => x"206c6167", |
00000658 => x"74736e69", |
00000659 => x"74637572", |
00000660 => x"006e6f69", |
00000661 => x"61657242", |
00000662 => x"696f706b", |
00000663 => x"0000746e", |
00000664 => x"64616f4c", |
00000665 => x"64646120", |
00000666 => x"73736572", |
00000667 => x"73696d20", |
00000668 => x"67696c61", |
00000669 => x"0064656e", |
00000670 => x"64616f4c", |
00000671 => x"63636120", |
00000672 => x"20737365", |
00000673 => x"6c756166", |
00000674 => x"00000074", |
00000675 => x"726f7453", |
00000676 => x"64612065", |
00000677 => x"73657264", |
00000678 => x"696d2073", |
00000679 => x"696c6173", |
00000680 => x"64656e67", |
00000681 => x"00000000", |
00000682 => x"726f7453", |
00000683 => x"63612065", |
00000684 => x"73736563", |
00000685 => x"75616620", |
00000686 => x"0000746c", |
00000687 => x"69766e45", |
00000688 => x"6d6e6f72", |
00000689 => x"20746e65", |
00000690 => x"6c6c6163", |
00000691 => x"6f726620", |
00000692 => x"2d55206d", |
00000693 => x"65646f6d", |
00000694 => x"00000000", |
00000695 => x"69766e45", |
00000696 => x"6d6e6f72", |
00000697 => x"20746e65", |
00000698 => x"6c6c6163", |
00000699 => x"6f726620", |
00000700 => x"2d4d206d", |
00000701 => x"65646f6d", |
00000702 => x"00000000", |
00000703 => x"6863614d", |
00000704 => x"20656e69", |
00000705 => x"74666f73", |
00000706 => x"65726177", |
00000707 => x"746e6920", |
00000708 => x"75727265", |
00000709 => x"00007470", |
00000710 => x"6863614d", |
00000711 => x"20656e69", |
00000712 => x"656d6974", |
00000713 => x"6e692072", |
00000714 => x"72726574", |
00000715 => x"00747075", |
00000716 => x"6863614d", |
00000717 => x"20656e69", |
00000718 => x"65747865", |
00000719 => x"6c616e72", |
00000720 => x"746e6920", |
00000721 => x"75727265", |
00000722 => x"00007470", |
00000723 => x"74736146", |
00000622 => x"00000288", |
00000623 => x"00000288", |
00000624 => x"00000374", |
00000625 => x"0000037c", |
00000626 => x"00000288", |
00000627 => x"00000288", |
00000628 => x"00000288", |
00000629 => x"00000384", |
00000630 => x"00000288", |
00000631 => x"00000288", |
00000632 => x"00000288", |
00000633 => x"0000038c", |
00000634 => x"00000288", |
00000635 => x"00000288", |
00000636 => x"00000288", |
00000637 => x"00000288", |
00000638 => x"00000394", |
00000639 => x"0000039c", |
00000640 => x"000003a4", |
00000641 => x"000003ac", |
00000642 => x"00007830", |
00000643 => x"4554523c", |
00000644 => x"0000203e", |
00000645 => x"74736e49", |
00000646 => x"74637572", |
00000647 => x"206e6f69", |
00000648 => x"72646461", |
00000649 => x"20737365", |
00000650 => x"6173696d", |
00000651 => x"6e67696c", |
00000652 => x"00006465", |
00000653 => x"74736e49", |
00000654 => x"74637572", |
00000655 => x"206e6f69", |
00000656 => x"65636361", |
00000657 => x"66207373", |
00000658 => x"746c7561", |
00000659 => x"00000000", |
00000660 => x"656c6c49", |
00000661 => x"206c6167", |
00000662 => x"74736e69", |
00000663 => x"74637572", |
00000664 => x"006e6f69", |
00000665 => x"61657242", |
00000666 => x"696f706b", |
00000667 => x"0000746e", |
00000668 => x"64616f4c", |
00000669 => x"64646120", |
00000670 => x"73736572", |
00000671 => x"73696d20", |
00000672 => x"67696c61", |
00000673 => x"0064656e", |
00000674 => x"64616f4c", |
00000675 => x"63636120", |
00000676 => x"20737365", |
00000677 => x"6c756166", |
00000678 => x"00000074", |
00000679 => x"726f7453", |
00000680 => x"64612065", |
00000681 => x"73657264", |
00000682 => x"696d2073", |
00000683 => x"696c6173", |
00000684 => x"64656e67", |
00000685 => x"00000000", |
00000686 => x"726f7453", |
00000687 => x"63612065", |
00000688 => x"73736563", |
00000689 => x"75616620", |
00000690 => x"0000746c", |
00000691 => x"69766e45", |
00000692 => x"6d6e6f72", |
00000693 => x"20746e65", |
00000694 => x"6c6c6163", |
00000695 => x"6f726620", |
00000696 => x"2d55206d", |
00000697 => x"65646f6d", |
00000698 => x"00000000", |
00000699 => x"69766e45", |
00000700 => x"6d6e6f72", |
00000701 => x"20746e65", |
00000702 => x"6c6c6163", |
00000703 => x"6f726620", |
00000704 => x"2d4d206d", |
00000705 => x"65646f6d", |
00000706 => x"00000000", |
00000707 => x"6863614d", |
00000708 => x"20656e69", |
00000709 => x"74666f73", |
00000710 => x"65726177", |
00000711 => x"746e6920", |
00000712 => x"75727265", |
00000713 => x"00007470", |
00000714 => x"6863614d", |
00000715 => x"20656e69", |
00000716 => x"656d6974", |
00000717 => x"6e692072", |
00000718 => x"72726574", |
00000719 => x"00747075", |
00000720 => x"6863614d", |
00000721 => x"20656e69", |
00000722 => x"65747865", |
00000723 => x"6c616e72", |
00000724 => x"746e6920", |
00000725 => x"75727265", |
00000726 => x"30207470", |
00000727 => x"00000000", |
00000728 => x"74736146", |
00000729 => x"746e6920", |
00000730 => x"75727265", |
00000731 => x"31207470", |
00000732 => x"00000000", |
00000733 => x"74736146", |
00000734 => x"746e6920", |
00000735 => x"75727265", |
00000736 => x"32207470", |
00000737 => x"00000000", |
00000738 => x"74736146", |
00000739 => x"746e6920", |
00000740 => x"75727265", |
00000741 => x"33207470", |
00000742 => x"00000000", |
00000743 => x"6e6b6e55", |
00000744 => x"206e776f", |
00000745 => x"70617274", |
00000746 => x"75616320", |
00000747 => x"203a6573", |
00000748 => x"00000000", |
00000749 => x"50204020", |
00000750 => x"00003d43", |
00000751 => x"544d202c", |
00000752 => x"3d4c4156", |
00000753 => x"00000000", |
00000754 => x"00000554", |
00000755 => x"00000454", |
00000756 => x"00000454", |
00000757 => x"00000454", |
00000758 => x"00000560", |
00000759 => x"00000454", |
00000760 => x"00000454", |
00000761 => x"00000454", |
00000762 => x"0000056c", |
00000763 => x"00000454", |
00000764 => x"00000454", |
00000765 => x"00000454", |
00000766 => x"00000454", |
00000767 => x"00000578", |
00000768 => x"00000584", |
00000769 => x"00000590", |
00000770 => x"0000059c", |
00000771 => x"0000049c", |
00000772 => x"000004e8", |
00000773 => x"000004f4", |
00000774 => x"00000500", |
00000775 => x"0000050c", |
00000776 => x"00000518", |
00000777 => x"00000524", |
00000778 => x"00000530", |
00000779 => x"0000053c", |
00000780 => x"00000454", |
00000781 => x"00000454", |
00000782 => x"00000548", |
00000783 => x"4554523c", |
00000784 => x"4157203e", |
00000785 => x"4e494e52", |
00000786 => x"43202147", |
00000787 => x"43205550", |
00000788 => x"73205253", |
00000789 => x"65747379", |
00000790 => x"6f6e206d", |
00000791 => x"76612074", |
00000792 => x"616c6961", |
00000793 => x"21656c62", |
00000794 => x"522f3c20", |
00000795 => x"003e4554", |
00000796 => x"33323130", |
00000797 => x"37363534", |
00000798 => x"42413938", |
00000799 => x"46454443", |
00000726 => x"00007470", |
00000727 => x"74736146", |
00000728 => x"746e6920", |
00000729 => x"75727265", |
00000730 => x"30207470", |
00000731 => x"00000000", |
00000732 => x"74736146", |
00000733 => x"746e6920", |
00000734 => x"75727265", |
00000735 => x"31207470", |
00000736 => x"00000000", |
00000737 => x"74736146", |
00000738 => x"746e6920", |
00000739 => x"75727265", |
00000740 => x"32207470", |
00000741 => x"00000000", |
00000742 => x"74736146", |
00000743 => x"746e6920", |
00000744 => x"75727265", |
00000745 => x"33207470", |
00000746 => x"00000000", |
00000747 => x"6e6b6e55", |
00000748 => x"206e776f", |
00000749 => x"70617274", |
00000750 => x"75616320", |
00000751 => x"203a6573", |
00000752 => x"00000000", |
00000753 => x"50204020", |
00000754 => x"00003d43", |
00000755 => x"544d202c", |
00000756 => x"3d4c4156", |
00000757 => x"00000000", |
00000758 => x"00000564", |
00000759 => x"00000464", |
00000760 => x"00000464", |
00000761 => x"00000464", |
00000762 => x"00000570", |
00000763 => x"00000464", |
00000764 => x"00000464", |
00000765 => x"00000464", |
00000766 => x"0000057c", |
00000767 => x"00000464", |
00000768 => x"00000464", |
00000769 => x"00000464", |
00000770 => x"00000464", |
00000771 => x"00000588", |
00000772 => x"00000594", |
00000773 => x"000005a0", |
00000774 => x"000005ac", |
00000775 => x"000004ac", |
00000776 => x"000004f8", |
00000777 => x"00000504", |
00000778 => x"00000510", |
00000779 => x"0000051c", |
00000780 => x"00000528", |
00000781 => x"00000534", |
00000782 => x"00000540", |
00000783 => x"0000054c", |
00000784 => x"00000464", |
00000785 => x"00000464", |
00000786 => x"00000558", |
00000787 => x"4554523c", |
00000788 => x"4157203e", |
00000789 => x"4e494e52", |
00000790 => x"43202147", |
00000791 => x"43205550", |
00000792 => x"73205253", |
00000793 => x"65747379", |
00000794 => x"6f6e206d", |
00000795 => x"76612074", |
00000796 => x"616c6961", |
00000797 => x"21656c62", |
00000798 => x"522f3c20", |
00000799 => x"003e4554", |
00000800 => x"33323130", |
00000801 => x"37363534", |
00000802 => x"42413938", |
00000803 => x"46454443", |
others => x"00000000" |
); |
|
/rtl/core/neorv32_bootloader_image.vhd
6,7 → 6,7
|
package neorv32_bootloader_image is |
|
type bootloader_init_image_t is array (0 to 982) of std_ulogic_vector(31 downto 0); |
type bootloader_init_image_t is array (0 to 984) of std_ulogic_vector(31 downto 0); |
constant bootloader_init_image : bootloader_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
30,7 → 30,7
00000019 => x"80010197", |
00000020 => x"7b418193", |
00000021 => x"00000597", |
00000022 => x"09c58593", |
00000022 => x"0a458593", |
00000023 => x"30559073", |
00000024 => x"f8000593", |
00000025 => x"0005a023", |
44,7 → 44,7
00000033 => x"00158593", |
00000034 => x"ff5ff06f", |
00000035 => x"00001597", |
00000036 => x"ecc58593", |
00000036 => x"ed458593", |
00000037 => x"80010617", |
00000038 => x"f6c60613", |
00000039 => x"80010697", |
61,935 → 61,937
00000050 => x"b8001073", |
00000051 => x"b0201073", |
00000052 => x"b8201073", |
00000053 => x"80000637", |
00000054 => x"34261073", |
00000055 => x"060000ef", |
00000056 => x"30047073", |
00000057 => x"00000013", |
00000058 => x"10500073", |
00000059 => x"0000006f", |
00000060 => x"ff810113", |
00000061 => x"00812023", |
00000062 => x"00912223", |
00000063 => x"34202473", |
00000064 => x"02044663", |
00000065 => x"34102473", |
00000066 => x"00041483", |
00000067 => x"0034f493", |
00000068 => x"00240413", |
00000069 => x"34141073", |
00000070 => x"00300413", |
00000071 => x"00941863", |
00000072 => x"34102473", |
00000073 => x"00240413", |
00000074 => x"34141073", |
00000075 => x"00012483", |
00000076 => x"00412403", |
00000077 => x"00810113", |
00000078 => x"30200073", |
00000079 => x"800007b7", |
00000080 => x"fd010113", |
00000081 => x"0007a023", |
00000082 => x"ffff07b7", |
00000083 => x"02112623", |
00000084 => x"02812423", |
00000085 => x"02912223", |
00000086 => x"03212023", |
00000087 => x"01312e23", |
00000088 => x"01412c23", |
00000089 => x"01512a23", |
00000090 => x"01612823", |
00000091 => x"01712623", |
00000092 => x"01812423", |
00000093 => x"4b878793", |
00000094 => x"30579073", |
00000095 => x"fe002403", |
00000096 => x"026267b7", |
00000097 => x"9ff78793", |
00000098 => x"00000693", |
00000099 => x"00000613", |
00000100 => x"00000593", |
00000101 => x"00200513", |
00000102 => x"0087f463", |
00000103 => x"00400513", |
00000104 => x"2f5000ef", |
00000105 => x"00100513", |
00000106 => x"3a1000ef", |
00000107 => x"00005537", |
00000108 => x"00000613", |
00000109 => x"00000593", |
00000110 => x"b0050513", |
00000111 => x"1c9000ef", |
00000112 => x"181000ef", |
00000113 => x"00245793", |
00000114 => x"00a78533", |
00000115 => x"00f537b3", |
00000116 => x"00b785b3", |
00000117 => x"199000ef", |
00000118 => x"08000793", |
00000119 => x"30479073", |
00000120 => x"30046073", |
00000121 => x"00000013", |
00000122 => x"00000013", |
00000123 => x"ffff1537", |
00000124 => x"e7450513", |
00000125 => x"249000ef", |
00000126 => x"f1302573", |
00000127 => x"24c000ef", |
00000128 => x"ffff1537", |
00000129 => x"eac50513", |
00000130 => x"235000ef", |
00000131 => x"fe002503", |
00000132 => x"238000ef", |
00000133 => x"ffff1537", |
00000134 => x"eb450513", |
00000135 => x"221000ef", |
00000136 => x"fe402503", |
00000137 => x"224000ef", |
00000138 => x"ffff1537", |
00000139 => x"ec050513", |
00000140 => x"20d000ef", |
00000141 => x"30102573", |
00000142 => x"210000ef", |
00000143 => x"ffff1537", |
00000144 => x"ec850513", |
00000145 => x"1f9000ef", |
00000146 => x"fe802503", |
00000147 => x"ffff14b7", |
00000148 => x"00341413", |
00000149 => x"1f4000ef", |
00000150 => x"ffff1537", |
00000151 => x"ed050513", |
00000152 => x"1dd000ef", |
00000153 => x"ff802503", |
00000154 => x"1e0000ef", |
00000155 => x"ed848513", |
00000156 => x"1cd000ef", |
00000157 => x"ff002503", |
00000158 => x"1d0000ef", |
00000159 => x"ffff1537", |
00000160 => x"ee450513", |
00000161 => x"1b9000ef", |
00000162 => x"ffc02503", |
00000163 => x"1bc000ef", |
00000164 => x"ed848513", |
00000165 => x"1a9000ef", |
00000166 => x"ff402503", |
00000167 => x"1ac000ef", |
00000168 => x"ffff1537", |
00000169 => x"eec50513", |
00000170 => x"195000ef", |
00000171 => x"095000ef", |
00000172 => x"00a404b3", |
00000173 => x"0084b433", |
00000174 => x"00b40433", |
00000175 => x"fa402783", |
00000176 => x"0207d263", |
00000177 => x"ffff1537", |
00000178 => x"f1450513", |
00000179 => x"171000ef", |
00000180 => x"161000ef", |
00000181 => x"02300793", |
00000182 => x"02f51263", |
00000183 => x"00000513", |
00000184 => x"0180006f", |
00000185 => x"05d000ef", |
00000186 => x"fc85eae3", |
00000187 => x"00b41463", |
00000188 => x"fc9566e3", |
00000189 => x"00100513", |
00000190 => x"5b8000ef", |
00000191 => x"0b4000ef", |
00000192 => x"ffff1937", |
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others => x"00000000" |
); |
|
/rtl/core/neorv32_cache.vhd
0,0 → 1,538
-- ################################################################################################# |
-- # << NEORV32 - Processor-Internal Instruction Cache >> # |
-- # ********************************************************************************************* # |
-- # Direct-mapped instruction cache. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
|
entity neorv32_cache is |
generic ( |
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE : natural := 16 -- block size in bytes (min 4), has to be a power of 2 |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clear_i : in std_ulogic; -- cache clear |
-- host controller interface -- |
host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
host_we_i : in std_ulogic; -- write enable |
host_re_i : in std_ulogic; -- read enable |
host_cancel_i : in std_ulogic; -- cancel current bus transaction |
host_lock_i : in std_ulogic; -- locked/exclusive access |
host_ack_o : out std_ulogic; -- bus transfer acknowledge |
host_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_lock_o : out std_ulogic; -- locked/exclusive access |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
); |
end neorv32_cache; |
|
architecture neorv32_cache_rtl of neorv32_cache is |
|
-- cache layout -- |
constant cache_offset_size_c : natural := index_size_f(CACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words |
constant cache_index_size_c : natural := index_size_f(CACHE_NUM_BLOCKS); |
constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset |
|
-- cache memory -- |
component neorv32_cache_memory |
generic ( |
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE : natural := 16 -- block size in bytes (min 4), has to be a power of 2 |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
invalidate_i : in std_ulogic; -- invalidate whole cache |
-- host cache access (read-only) -- |
host_addr_i : in std_ulogic_vector(31 downto 0); -- access address |
host_rdata_o : out std_ulogic_vector(31 downto 0); -- read data |
-- access status (1 cycle delay to access) -- |
hit_o : out std_ulogic; -- hit access |
-- ctrl cache access (write-only) -- |
ctrl_en_i : in std_ulogic; -- control interface enable |
ctrl_addr_i : in std_ulogic_vector(31 downto 0); -- access address |
ctrl_we_i : in std_ulogic; -- write enable (full-word) |
ctrl_wdata_i : in std_ulogic_vector(31 downto 0); -- write data |
ctrl_tag_we_i : in std_ulogic; -- write tag to selected block |
ctrl_valid_i : in std_ulogic; -- make selected block valid |
ctrl_invalid_i : in std_ulogic -- make selected block invalid |
); |
end component; |
|
-- cache interface -- |
type cache_if_t is record |
clear : std_ulogic; -- cache clear |
-- |
host_addr : std_ulogic_vector(31 downto 0); -- cpu access address |
host_rdata : std_ulogic_vector(31 downto 0); -- cpu read data |
-- |
hit : std_ulogic; -- hit access |
-- |
ctrl_en : std_ulogic; -- control access enable |
ctrl_addr : std_ulogic_vector(31 downto 0); -- control access address |
ctrl_we : std_ulogic; -- control write enable |
ctrl_wdata : std_ulogic_vector(31 downto 0); -- control write data |
ctrl_tag_we : std_ulogic; -- control tag write enabled |
ctrl_valid_we : std_ulogic; -- control valid flag set |
ctrl_invalid_we : std_ulogic; -- control valid flag clear |
end record; |
signal cache : cache_if_t; |
|
-- control engine -- |
type ctrl_engine_state_t is (S_IDLE, S_CACHE_CLEAR, S_CACHE_CHECK, S_CACHE_MISS, S_BUS_DOWNLOAD_REQ, S_BUS_DOWNLOAD_GET, |
S_CACHE_RESYNC_0, S_CACHE_RESYNC_1, S_BUS_ERROR, S_ERROR, S_HOST_CANCEL); |
type ctrl_t is record |
state : ctrl_engine_state_t; -- current state |
state_nxt : ctrl_engine_state_t; -- next state |
addr_reg : std_ulogic_vector(31 downto 0); -- address register for block download |
addr_reg_nxt : std_ulogic_vector(31 downto 0); |
-- |
re_buf : std_ulogic; -- read request buffer |
re_buf_nxt : std_ulogic; |
cancel_buf : std_ulogic; -- cancel request buffer |
cancel_buf_nxt : std_ulogic; |
end record; |
signal ctrl : ctrl_t; |
|
begin |
|
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- configuration -- |
assert not (is_power_of_two_f(CACHE_NUM_BLOCKS) = false) report "NEORV32 PROCESSOR CONFIG ERROR! Cache number of blocks <NUM_BLOCKS> has to be a power of 2." severity error; |
assert not (is_power_of_two_f(CACHE_BLOCK_SIZE) = false) report "NEORV32 PROCESSOR CONFIG ERROR! Cache block size <BLOCK_SIZE> has to be a power of 2." severity error; |
assert not (CACHE_NUM_BLOCKS < 1) report "NEORV32 PROCESSOR CONFIG ERROR! Cache number of blocks <NUM_BLOCKS> has to be >= 1." severity error; |
assert not (CACHE_BLOCK_SIZE < 4) report "NEORV32 PROCESSOR CONFIG ERROR! Cache block size <BLOCK_SIZE> has to be >= 4." severity error; |
|
|
-- Control Engine FSM Sync ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- registers that REQUIRE a specific reset state -- |
ctrl_engine_fsm_sync_rst: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
ctrl.state <= S_IDLE; |
ctrl.re_buf <= '0'; |
ctrl.cancel_buf <= '0'; |
elsif rising_edge(clk_i) then |
ctrl.state <= ctrl.state_nxt; |
ctrl.re_buf <= ctrl.re_buf_nxt; |
ctrl.cancel_buf <= ctrl.cancel_buf_nxt; |
end if; |
end process ctrl_engine_fsm_sync_rst; |
|
-- registers that do not require a specific reset state -- |
ctrl_engine_fsm_sync: process(clk_i) |
begin |
if rising_edge(clk_i) then |
ctrl.addr_reg <= ctrl.addr_reg_nxt; |
end if; |
end process ctrl_engine_fsm_sync; |
|
|
-- Control Engine FSM Comb ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ctrl_engine_fsm_comb: process(ctrl, cache, clear_i, host_addr_i, host_lock_i, host_re_i, host_cancel_i, bus_rdata_i, bus_ack_i, bus_err_i) |
begin |
-- control defaults -- |
ctrl.state_nxt <= ctrl.state; |
ctrl.addr_reg_nxt <= ctrl.addr_reg; |
ctrl.re_buf_nxt <= (ctrl.re_buf or host_re_i) and (not host_cancel_i); |
ctrl.cancel_buf_nxt <= ctrl.cancel_buf or host_cancel_i; |
|
-- cache defaults -- |
cache.clear <= '0'; |
cache.host_addr <= host_addr_i; |
cache.ctrl_en <= '0'; |
cache.ctrl_addr <= ctrl.addr_reg; |
cache.ctrl_we <= '0'; |
cache.ctrl_wdata <= bus_rdata_i; |
cache.ctrl_tag_we <= '0'; |
cache.ctrl_valid_we <= '0'; |
cache.ctrl_invalid_we <= '0'; |
|
-- host interface defaults -- |
host_ack_o <= '0'; |
host_err_o <= '0'; |
host_rdata_o <= cache.host_rdata; |
|
-- peripheral bus interface defaults -- |
bus_addr_o <= ctrl.addr_reg; |
bus_wdata_o <= (others => '0'); -- cache is read-only |
bus_ben_o <= (others => '0'); -- cache is read-only |
bus_we_o <= '0'; -- cache is read-only |
bus_re_o <= '0'; |
bus_cancel_o <= '0'; |
bus_lock_o <= host_lock_i; |
|
-- fsm -- |
case ctrl.state is |
|
when S_IDLE => -- wait for host access request or cache control operation |
-- ------------------------------------------------------------ |
if (clear_i = '1') then -- cache control operation? |
ctrl.state_nxt <= S_CACHE_CLEAR; |
elsif (host_re_i = '1') or (ctrl.re_buf = '1') then -- cache access |
ctrl.re_buf_nxt <= '0'; |
ctrl.cancel_buf_nxt <= '0'; |
ctrl.state_nxt <= S_CACHE_CHECK; |
end if; |
|
when S_CACHE_CLEAR => -- invalidate all cache entries |
-- ------------------------------------------------------------ |
cache.clear <= '1'; |
ctrl.state_nxt <= S_IDLE; |
|
when S_CACHE_CHECK => -- finalize host access if cache hit |
-- ------------------------------------------------------------ |
if (cache.hit = '1') then -- cache HIT |
host_ack_o <= not ctrl.cancel_buf; -- ACK if request has not been canceled |
ctrl.state_nxt <= S_IDLE; |
else -- cache MISS |
ctrl.state_nxt <= S_CACHE_MISS; |
end if; |
|
when S_CACHE_MISS => -- |
-- ------------------------------------------------------------ |
-- compute block base address -- |
ctrl.addr_reg_nxt <= host_addr_i; |
ctrl.addr_reg_nxt((2+cache_offset_size_c)-1 downto 2) <= (others => '0'); -- block-aligned |
ctrl.addr_reg_nxt(1 downto 0) <= "00"; -- word-aligned |
-- |
if (host_cancel_i = '1') or (ctrl.cancel_buf = '1') then -- 'early' CPU cancel (abort before bus transaction has even started) |
ctrl.state_nxt <= S_IDLE; |
else |
ctrl.state_nxt <= S_BUS_DOWNLOAD_REQ; |
end if; |
|
when S_BUS_DOWNLOAD_REQ => -- download new cache block: request new word |
-- ------------------------------------------------------------ |
bus_re_o <= '1'; -- request new read transfer |
ctrl.state_nxt <= S_BUS_DOWNLOAD_GET; |
|
when S_BUS_DOWNLOAD_GET => -- download new cache block: wait for bus response |
-- ------------------------------------------------------------ |
cache.ctrl_en <= '1'; -- we are in cache control mode |
-- |
if (bus_err_i = '1') then -- bus error |
ctrl.state_nxt <= S_BUS_ERROR; |
elsif (ctrl.cancel_buf = '1') then -- 'late' CPU cancel (timeout?) |
ctrl.state_nxt <= S_HOST_CANCEL; |
elsif (bus_ack_i = '1') then -- ACK = write to cache and get next word |
cache.ctrl_we <= '1'; -- write to cache |
if (and_all_f(ctrl.addr_reg((2+cache_offset_size_c)-1 downto 2)) = '1') then -- block complete? |
cache.ctrl_tag_we <= '1'; -- current block is valid now |
cache.ctrl_valid_we <= '1'; -- write tag of current address |
ctrl.state_nxt <= S_CACHE_RESYNC_0; |
else -- get next word |
ctrl.addr_reg_nxt <= std_ulogic_vector(unsigned(ctrl.addr_reg) + 4); |
ctrl.state_nxt <= S_BUS_DOWNLOAD_REQ; |
end if; |
end if; |
|
when S_CACHE_RESYNC_0 => -- re-sync host/cache access: cache read-latency |
-- ------------------------------------------------------------ |
ctrl.state_nxt <= S_CACHE_RESYNC_1; |
|
when S_CACHE_RESYNC_1 => -- re-sync host/cache access: finalize CPU request |
-- ------------------------------------------------------------ |
host_ack_o <= not ctrl.cancel_buf; -- ACK if request has not been canceled |
ctrl.state_nxt <= S_IDLE; |
|
when S_BUS_ERROR => -- bus error during download |
-- ------------------------------------------------------------ |
host_err_o <= '1'; |
ctrl.state_nxt <= S_ERROR; |
|
when S_ERROR => -- wait for CPU to cancel faulting transfer |
-- ------------------------------------------------------------ |
if (host_cancel_i = '1') then |
bus_cancel_o <= '1'; |
ctrl.state_nxt <= S_IDLE; |
end if; |
|
when S_HOST_CANCEL => -- host cancels transfer |
-- ------------------------------------------------------------ |
cache.ctrl_en <= '1'; -- we are in cache control mode |
cache.ctrl_invalid_we <= '1'; -- invalidate current cache block |
bus_cancel_o <= '1'; |
ctrl.state_nxt <= S_IDLE; |
|
when others => -- undefined |
-- ------------------------------------------------------------ |
ctrl.state_nxt <= S_IDLE; |
|
end case; |
end process ctrl_engine_fsm_comb; |
|
|
-- Cache Memory --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cache_memory_inst: neorv32_cache_memory |
generic map ( |
CACHE_NUM_BLOCKS => CACHE_NUM_BLOCKS, -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE => CACHE_BLOCK_SIZE -- block size in bytes (min 4), has to be a power of 2 |
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => rstn_i, -- global reset, low-active, async |
invalidate_i => cache.clear, -- invalidate whole cache |
-- host cache access (read-only) -- |
host_addr_i => cache.host_addr, -- access address |
host_rdata_o => cache.host_rdata, -- read data |
-- access status (1 cycle delay to access) -- |
hit_o => cache.hit, -- hit access |
-- ctrl cache access (write-only) -- |
ctrl_en_i => cache.ctrl_en, -- control interface enable |
ctrl_addr_i => cache.ctrl_addr, -- access address |
ctrl_we_i => cache.ctrl_we, -- write enable (full-word) |
ctrl_wdata_i => cache.ctrl_wdata, -- write data |
ctrl_tag_we_i => cache.ctrl_tag_we, -- write tag to selected block |
ctrl_valid_i => cache.ctrl_valid_we, -- make selected block valid |
ctrl_invalid_i => cache.ctrl_invalid_we -- make selected block invalid |
); |
|
end neorv32_cache_rtl; |
|
|
-- ########################################################################################################################################### |
-- ########################################################################################################################################### |
|
|
-- ################################################################################################# |
-- # << NEORV32 - Cache Memory >> # |
-- # ********************************************************************************************* # |
-- # Direct mapped (fixed). Read-only for host, write-only for control. All output signals have # |
-- # one cycle latency. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
|
entity neorv32_cache_memory is |
generic ( |
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE : natural := 16 -- block size in bytes (min 4), has to be a power of 2 |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
invalidate_i : in std_ulogic; -- invalidate whole cache |
-- host cache access (read-only) -- |
host_addr_i : in std_ulogic_vector(31 downto 0); -- access address |
host_rdata_o : out std_ulogic_vector(31 downto 0); -- read data |
-- access status (1 cycle delay to access) -- |
hit_o : out std_ulogic; -- hit access |
-- ctrl cache access (write-only) -- |
ctrl_en_i : in std_ulogic; -- control interface enable |
ctrl_addr_i : in std_ulogic_vector(31 downto 0); -- access address |
ctrl_we_i : in std_ulogic; -- write enable (full-word) |
ctrl_wdata_i : in std_ulogic_vector(31 downto 0); -- write data |
ctrl_tag_we_i : in std_ulogic; -- write tag to selected block |
ctrl_valid_i : in std_ulogic; -- make selected block valid |
ctrl_invalid_i : in std_ulogic -- make selected block invalid |
); |
end neorv32_cache_memory; |
|
architecture neorv32_cache_memory_rtl of neorv32_cache_memory is |
|
-- cache layout -- |
constant cache_offset_size_c : natural := index_size_f(CACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words |
constant cache_index_size_c : natural := index_size_f(CACHE_NUM_BLOCKS); |
constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset |
constant cache_entries_c : natural := CACHE_NUM_BLOCKS * (CACHE_BLOCK_SIZE/4); -- number of 32-bit entries |
|
-- status flag memory -- |
signal valid_flag : std_ulogic_vector(CACHE_NUM_BLOCKS-1 downto 0); |
signal valid : std_ulogic; -- flag read data |
|
-- tag memory -- |
type tag_mem_t is array (0 to CACHE_NUM_BLOCKS-1) of std_ulogic_vector(cache_tag_size_c-1 downto 0); |
signal tag_mem : tag_mem_t; |
signal tag : std_ulogic_vector(cache_tag_size_c-1 downto 0); |
|
-- access status -- |
signal hit : std_ulogic; |
|
-- access address decomposition -- |
type acc_addr_t is record |
tag : std_ulogic_vector(cache_tag_size_c-1 downto 0); |
index : std_ulogic_vector(cache_index_size_c-1 downto 0); |
offset : std_ulogic_vector(cache_offset_size_c-1 downto 0); |
end record; |
signal host_acc_addr, ctrl_acc_addr : acc_addr_t; |
|
-- cache data memory -- |
type cache_mem_t is array (0 to cache_entries_c-1) of std_ulogic_vector(31 downto 0); |
signal cache_data_memory : cache_mem_t; |
|
-- cache data memory access -- |
signal cache_index : std_ulogic_vector(cache_index_size_c-1 downto 0); |
signal cache_offset : std_ulogic_vector(cache_offset_size_c-1 downto 0); |
signal cache_addr : std_ulogic_vector((cache_index_size_c+cache_offset_size_c)-1 downto 0); -- = index & offset |
signal cache_we : std_ulogic; -- write enable (full-word) |
|
begin |
|
-- Access Address Decomposition ----------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
host_acc_addr.tag <= host_addr_i(31 downto 31-(cache_tag_size_c-1)); |
host_acc_addr.index <= host_addr_i(31-cache_tag_size_c downto 2+cache_offset_size_c); |
host_acc_addr.offset <= host_addr_i(2+(cache_offset_size_c-1) downto 2); -- discard byte offset |
|
ctrl_acc_addr.tag <= ctrl_addr_i(31 downto 31-(cache_tag_size_c-1)); |
ctrl_acc_addr.index <= ctrl_addr_i(31-cache_tag_size_c downto 2+cache_offset_size_c); |
ctrl_acc_addr.offset <= ctrl_addr_i(2+(cache_offset_size_c-1) downto 2); -- discard byte offset |
|
|
-- Status flag memory --------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
status_memory: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
valid_flag <= (others => '0'); |
elsif rising_edge(clk_i) then |
-- write access -- |
if (invalidate_i = '1') then -- invalidate whole cache |
valid_flag <= (others => '0'); |
elsif (ctrl_en_i = '1') then |
if (ctrl_invalid_i = '1') then -- make current block invalid |
valid_flag(to_integer(unsigned(cache_index))) <= '0'; |
elsif (ctrl_valid_i = '1') then -- make current block valid |
valid_flag(to_integer(unsigned(cache_index))) <= '1'; |
end if; |
end if; |
-- read access (sync) -- |
valid <= valid_flag(to_integer(unsigned(cache_index))); |
end if; |
end process status_memory; |
|
|
-- Tag memory ----------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
tag_memory: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (ctrl_en_i = '1') and (ctrl_tag_we_i = '1') then -- write access |
tag_mem(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag; |
else -- read access |
tag <= tag_mem(to_integer(unsigned(cache_index))); |
end if; |
end if; |
end process tag_memory; |
|
-- compare tag entry with adress tag -- |
hit <= '1' when (host_acc_addr.tag = tag) and (valid = '1') else '0'; |
hit_o <= hit; |
|
|
-- Cache Data Memory ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
cache_mem_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (cache_we = '1') then -- write access from control (full-word) |
cache_data_memory(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i; |
else -- read access from host (full-word) |
host_rdata_o <= cache_data_memory(to_integer(unsigned(cache_addr))); |
end if; |
end if; |
end process cache_mem_access; |
|
-- cache block ram access address -- |
cache_addr <= cache_index & cache_offset; |
|
-- cache access select -- |
cache_index <= host_acc_addr.index when (ctrl_en_i = '0') else ctrl_acc_addr.index; |
cache_offset <= host_acc_addr.offset when (ctrl_en_i = '0') else ctrl_acc_addr.offset; |
cache_we <= '0' when (ctrl_en_i = '0') else ctrl_we_i; |
|
|
end neorv32_cache_memory_rtl; |
/rtl/core/neorv32_cpu.vhd
57,6 → 57,7
-- General -- |
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address |
BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
152,14 → 153,15
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- CSR system -- |
assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning; |
assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/privileged features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning; |
-- U-extension requires Zicsr extension -- |
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr extension." severity error; |
-- PMP requires Zicsr extension -- |
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr extension." severity error; |
-- RISC-V standard performance counters - |
assert not ((CPU_EXTENSION_RISCV_Zicsr = true) and (zicnt_en_c = false)) report "NEORV32 CPU CONFIG WARNING! Standard RISC-V peformance counters ([m]cycle[h], [m]instret[h]) will not be implemented (not RISC-V-compliant!)." severity warning; |
|
-- Bus timeout -- |
assert not (BUS_TIMEOUT < 2) report "NEORV32 CPU CONFIG ERROR! Invalid bus access timeout value <BUS_TIMEOUT>. Has to be >= 2." severity error; |
|
-- Instruction prefetch buffer size -- |
assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error; |
-- A extension - only lr.w and sc.w supported yet -- |
174,6 → 176,7
-- PMP notifier -- |
assert not (PMP_USE = true) report "NEORV32 CPU CONFIG NOTE: Implementing physical memory protection (PMP) with " & integer'image(pmp_num_regions_c) & " regions and " & integer'image(pmp_min_granularity_c) & " bytes minimal region size (granulartiy)." severity note; |
|
|
-- Control Unit --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cpu_control_inst: neorv32_cpu_control |
367,7 → 370,9
generic map ( |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
-- Physical memory protection (PMP) -- |
PMP_USE => PMP_USE -- implement physical memory protection? |
PMP_USE => PMP_USE, -- implement physical memory protection? |
-- Bus Timeout -- |
BUS_TIMEOUT => BUS_TIMEOUT -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception |
) |
port map ( |
-- global control -- |
/rtl/core/neorv32_cpu_bus.vhd
43,9 → 43,11
|
entity neorv32_cpu_bus is |
generic ( |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
-- Physical memory protection (PMP) -- |
PMP_USE : boolean := false -- implement physical memory protection? |
PMP_USE : boolean := false; -- implement physical memory protection? |
-- Bus Timeout -- |
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception |
); |
port ( |
-- global control -- |
136,7 → 138,7
wr_req : std_ulogic; -- write access in progress |
err_align : std_ulogic; -- alignment error |
err_bus : std_ulogic; -- bus access error |
timeout : std_ulogic_vector(index_size_f(bus_timeout_c)-1 downto 0); |
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0); |
end record; |
signal i_arbiter, d_arbiter : bus_arbiter_t; |
|
291,7 → 293,7
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c); |
d_arbiter.err_align <= d_misaligned; |
d_arbiter.err_bus <= '0'; |
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c))); |
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT))); |
else -- in progress |
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1); |
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c)); |
343,7 → 345,7
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c); |
i_arbiter.err_align <= i_misaligned; |
i_arbiter.err_bus <= '0'; |
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c))); |
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT))); |
else -- in progress |
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1); |
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c)); |
/rtl/core/neorv32_cpu_control.vhd
234,40 → 234,48
type pmp_ctrl_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0); |
type pmp_addr_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(data_width_c-1 downto 0); |
type csr_t is record |
we : std_ulogic; -- csr write enable |
we_nxt : std_ulogic; |
re : std_ulogic; -- csr read enable |
re_nxt : std_ulogic; |
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data |
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data |
addr : std_ulogic_vector(11 downto 0); -- csr address |
we : std_ulogic; -- csr write enable |
we_nxt : std_ulogic; |
re : std_ulogic; -- csr read enable |
re_nxt : std_ulogic; |
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data |
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data |
-- |
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W) |
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W) |
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode |
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W) |
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W) |
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode |
-- |
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W) |
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W) |
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W) |
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W) |
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W) |
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W) |
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W) |
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W) |
-- |
mip_status : std_ulogic_vector(interrupt_width_c-1 downto 0); -- current buffered IRQs |
mip_clear : std_ulogic_vector(interrupt_width_c-1 downto 0); -- set bits clear the according buffered IRQ |
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode |
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode |
mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode |
-- |
privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode |
priv_m_mode : std_ulogic; -- CPU in M-mode |
priv_u_mode : std_ulogic; -- CPU in u-mode |
mcountinhibit_cy : std_ulogic; -- mcounterinhibit.cy: enable auto-increment |
mcountinhibit_ir : std_ulogic; -- mcounterinhibit.ir: enable auto-increment |
-- |
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W) |
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W) |
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00 |
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W) |
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W) |
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit |
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit |
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W) |
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W) |
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers |
pmpaddr : pmp_addr_t; -- physical memory protection - address registers |
mip_status : std_ulogic_vector(interrupt_width_c-1 downto 0); -- current buffered IRQs |
mip_clear : std_ulogic_vector(interrupt_width_c-1 downto 0); -- set bits clear the according buffered IRQ |
-- |
privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode |
priv_m_mode : std_ulogic; -- CPU in M-mode |
priv_u_mode : std_ulogic; -- CPU in u-mode |
-- |
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W) |
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W) |
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00 |
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W) |
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W) |
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit |
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit |
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W) |
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W) |
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers |
pmpaddr : pmp_addr_t; -- physical memory protection - address registers |
end record; |
signal csr : csr_t; |
|
344,6 → 352,7
|
when IFETCH_ISSUE => -- store instruction data to prefetch buffer |
-- ------------------------------------------------------------ |
fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors |
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response |
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4); |
ipb.we <= '1'; |
458,7 → 467,7
if (ipb.avail = '1') then -- instructions available? |
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word |
if (execute_engine.state = DISPATCH) then |
if (execute_engine.state = DISPATCH) then -- ready to issue new command? |
cmd_issue.valid <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned" |
472,7 → 481,7
end if; |
|
else -- begin check in HIGH instruction half-word |
if (execute_engine.state = DISPATCH) then |
if (execute_engine.state = DISPATCH) then -- ready to issue new command? |
cmd_issue.valid <= '1'; |
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction |
if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned" |
502,7 → 511,7
end case; |
end process issue_engine_fsm_comb; |
|
-- 16-bit instruction: half-word select -- |
-- 16-bit instructions: half-word select -- |
ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0); |
|
|
612,9 → 621,9
if (execute_engine.pc_we = '1') then |
case execute_engine.pc_mux_sel is |
when "00" => execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment |
when "01" => execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/branch |
when "01" => execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/taken_branch |
when "10" => execute_engine.pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter |
when others => execute_engine.pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap return |
when others => execute_engine.pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap exit |
end case; |
end if; |
-- |
650,6 → 659,9
end if; |
end process execute_engine_fsm_sync; |
|
-- CSR access address -- |
csr.addr <= execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c); |
|
-- PC output -- |
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- PC for ALU ops |
|
843,7 → 855,7
when others => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_and_c; -- AND(I) |
end case; |
|
-- cp access? -- |
-- co-processor (cp) access? -- |
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- just in case a mul/div operation |
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV CP op? |
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation |
1102,52 → 1114,56
end if; |
|
-- check CSR access -- |
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is |
when csr_mstatus_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mstatush_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_misa_c => csr_acc_valid <= csr.priv_m_mode;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we don't cause an exception here for compatibility |
when csr_mie_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mtvec_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mscratch_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mepc_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mcause_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mtval_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mip_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
case csr.addr is |
-- standard read/write CSRs -- |
when csr_mstatus_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mstatush_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_misa_c => csr_acc_valid <= csr.priv_m_mode;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility |
when csr_mie_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mtvec_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mscratch_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mepc_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mcause_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mcounteren_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mtval_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_mip_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
-- |
when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only |
-- |
when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 2)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 3)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 4)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 6)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 7)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 8)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 2)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 3)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 4)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 6)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 7)) and csr.priv_m_mode; -- M-mode only |
when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 8)) and csr.priv_m_mode; -- M-mode only |
-- |
when csr_mcycle_c => csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(zicnt_en_c); -- M-mode only and "Zicnt" = true |
when csr_minstret_c => csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(zicnt_en_c); -- M-mode only and "Zicnt" = true |
when csr_mcountinhibit_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
-- |
when csr_mcycleh_c => csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(zicnt_en_c); -- M-mode only and "Zicnt" = true |
when csr_minstreth_c => csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(zicnt_en_c); -- M-mode only and "Zicnt" = true |
when csr_mcycle_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_minstret_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
-- |
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v) and bool_to_ulogic_f(zicnt_en_c); -- all modes, read-only and "Zicnt" = true |
when csr_time_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only |
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v) and bool_to_ulogic_f(zicnt_en_c); -- all modes, read-only and "Zicnt" = true |
when csr_mcycleh_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
when csr_minstreth_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only |
-- standard read-only CSRs -- |
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only |
when csr_time_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only |
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only |
-- |
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v) and bool_to_ulogic_f(zicnt_en_c); -- all modes, read-only and "Zicnt" = true |
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only |
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v) and bool_to_ulogic_f(zicnt_en_c); -- all modes, read-only and "Zicnt" = true |
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only |
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only |
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only |
-- |
when csr_mvendorid_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only |
when csr_marchid_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only |
when csr_mimpid_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only |
when csr_mhartid_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only |
when csr_mvendorid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only |
when csr_marchid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only |
when csr_mimpid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only |
when csr_mhartid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only |
-- custom read-only CSRs -- |
when csr_mzext_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only |
-- |
when csr_mzext_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only |
-- |
when others => csr_acc_valid <= '0'; -- undefined, invalid access |
when others => csr_acc_valid <= '0'; -- invalid access |
end case; |
end process invalid_csr_access_check; |
|
1587,17 → 1603,23
csr.mcause(csr.mcause'left) <= trap_reset_c(trap_reset_c'left); |
csr.mcause(trap_reset_c'left-1 downto 0) <= trap_reset_c(trap_reset_c'left-1 downto 0); |
-- |
csr.mtval <= (others => '0'); |
csr.mip_clear <= (others => '0'); |
csr.pmpcfg <= (others => (others => '0')); |
csr.pmpaddr <= (others => (others => '1')); |
csr.mtval <= (others => '0'); |
csr.mip_clear <= (others => '0'); |
csr.pmpcfg <= (others => (others => '0')); |
csr.pmpaddr <= (others => (others => '1')); |
-- |
csr.mcycle <= (others => '0'); |
csr.minstret <= (others => '0'); |
csr.mcycleh <= (others => '0'); |
csr.minstreth <= (others => '0'); |
mcycle_msb <= '0'; |
minstret_msb <= '0'; |
csr.mcounteren_cy <= '0'; |
csr.mcounteren_tm <= '0'; |
csr.mcounteren_ir <= '0'; |
csr.mcountinhibit_cy <= '0'; |
csr.mcountinhibit_ir <= '0'; |
-- |
csr.mcycle <= (others => '0'); |
csr.minstret <= (others => '0'); |
csr.mcycleh <= (others => '0'); |
csr.minstreth <= (others => '0'); |
mcycle_msb <= '0'; |
minstret_msb <= '0'; |
elsif rising_edge(clk_i) then |
-- write access? -- |
csr.we <= csr.we_nxt; |
1610,7 → 1632,7
-- CSR access by application software |
-- -------------------------------------------------------------------------------- |
if (csr.we = '1') then -- manual update |
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is |
case csr.addr is |
|
-- machine trap setup -- |
-- -------------------------------------------------------------------- |
1623,7 → 1645,7
else -- only machine mode is available |
csr.mstatus_mpp <= priv_mode_m_c; |
end if; |
when csr_mie_c => -- R/W: mie - machine interrupt-enable register |
when csr_mie_c => -- R/W: mie - machine interrupt enable register |
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable |
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable |
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable |
1634,6 → 1656,10
csr.mie_firqe(3) <= csr.wdata(19); -- fast interrupt channel 3 |
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
when csr_mcounteren_c => -- R/W: machine counter enable register |
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h] |
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h] |
csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h] |
|
-- machine trap handling -- |
-- -------------------------------------------------------------------- |
1652,10 → 1678,10
csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07); |
csr.mip_clear(interrupt_mext_irq_c) <= not csr.wdata(11); |
-- |
csr.mip_clear(interrupt_firq_0_c) <= not csr.wdata(16); |
csr.mip_clear(interrupt_firq_1_c) <= not csr.wdata(17); |
csr.mip_clear(interrupt_firq_2_c) <= not csr.wdata(18); |
csr.mip_clear(interrupt_firq_3_c) <= not csr.wdata(19); |
csr.mip_clear(interrupt_firq_0_c) <= not csr.wdata(16); |
csr.mip_clear(interrupt_firq_1_c) <= not csr.wdata(17); |
csr.mip_clear(interrupt_firq_2_c) <= not csr.wdata(18); |
csr.mip_clear(interrupt_firq_3_c) <= not csr.wdata(19); |
|
-- physical memory protection - configuration -- |
-- -------------------------------------------------------------------- |
1700,7 → 1726,7
csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c => -- R/W: pmpaddr0..7 - PMP address register 0..7 |
if (PMP_USE = true) then |
for i in 0 to pmp_num_regions_c-1 loop |
if (execute_engine.i_reg(23 downto 20) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access |
if (csr.addr(2 downto 0) = std_ulogic_vector(to_unsigned(i, 3))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access |
csr.pmpaddr(i) <= csr.wdata; |
csr.pmpaddr(i)(index_size_f(pmp_min_granularity_c)-4 downto 0) <= (others => '1'); |
end if; |
1707,6 → 1733,12
end loop; -- i (CSRs) |
end if; |
|
-- machine counter setup -- |
-- -------------------------------------------------------------------- |
when csr_mcountinhibit_c => -- R/W: mcountinhibit - machine counter-inhibit register |
csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter |
csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter |
|
-- undefined -- |
-- -------------------------------------------------------------------- |
when others => |
1773,47 → 1805,38
end if; -- hardware csr access |
|
-- -------------------------------------------------------------------------------- |
-- Counter CSRs (each counter is split in 2 32-bit counters) |
-- Counter CSRs (each counter is split in two 32-bit counters) |
-- -------------------------------------------------------------------------------- |
if (zicnt_en_c = true) then -- implement standard RISC-V performance counters? |
-- [m]cycle -- |
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycle_c) then -- write access |
csr.mcycle <= '0' & csr.wdata; |
mcycle_msb <= '0'; |
elsif (execute_engine.sleep = '0') then -- automatic update (if CPU is not in sleep mode) |
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1); |
mcycle_msb <= csr.mcycle(csr.mcycle'left); |
end if; |
-- [m]cycle -- |
if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access |
csr.mcycle <= '0' & csr.wdata; |
mcycle_msb <= '0'; |
elsif (csr.mcountinhibit_cy = '0') and (execute_engine.sleep = '0') then -- non-inhibited automatic update (if CPU is not in sleep mode) |
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1); |
mcycle_msb <= csr.mcycle(csr.mcycle'left); |
end if; |
|
-- [m]cycleh -- |
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycleh_c) then -- write access |
csr.mcycleh <= csr.wdata(csr.mcycleh'left downto 0); |
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update |
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1); |
end if; |
-- [m]cycleh -- |
if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access |
csr.mcycleh <= csr.wdata; |
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update (continued) |
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1); |
end if; |
|
-- [m]instret -- |
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstret_c) then -- write access |
csr.minstret <= '0' & csr.wdata; |
minstret_msb <= '0'; |
elsif (execute_engine.state = EXECUTE) then -- automatic update (if CPU actually executes an instruction) |
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1); |
minstret_msb <= csr.minstret(csr.minstret'left); |
end if; |
-- [m]instret -- |
if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access |
csr.minstret <= '0' & csr.wdata; |
minstret_msb <= '0'; |
elsif (csr.mcountinhibit_ir = '0') and (execute_engine.state = EXECUTE) then -- non-inhibited automatic update (if CPU actually executes an instruction) |
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1); |
minstret_msb <= csr.minstret(csr.minstret'left); |
end if; |
|
-- [m]instreth -- |
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstreth_c) then -- write access |
csr.minstreth <= csr.wdata(csr.minstreth'left downto 0); |
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update |
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1); |
end if; |
else -- performance counters NOT implemented (not RISC-V-compliant!) |
csr.mcycle <= (others => '0'); |
csr.minstret <= (others => '0'); |
csr.mcycleh <= (others => '0'); |
csr.minstreth <= (others => '0'); |
mcycle_msb <= '0'; |
minstret_msb <= '0'; |
-- [m]instreth -- |
if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access |
csr.minstreth <= csr.wdata; |
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update (continued) |
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1); |
end if; |
|
end if; |
1847,16 → 1870,17
csr.re <= csr.re_nxt; -- read access? |
csr.rdata <= (others => '0'); -- default output |
if (CPU_EXTENSION_RISCV_Zicsr = true) and (csr.re = '1') then |
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is |
case csr.addr is |
|
-- machine trap setup -- |
when csr_mstatus_c => -- R/W: mstatus - machine status register |
csr.rdata(03) <= csr.mstatus_mie; -- MIE |
csr.rdata(03) <= csr.mstatus_mie; -- MIE |
csr.rdata(06) <= '1' and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- UBE: CPU/Processor is BIG-ENDIAN (in user-mode) |
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE |
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low |
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high |
when csr_mstatush_c => -- R/-: mstatush - machine status register - high part |
csr.rdata(05) <= '1'; -- MBE: CPU/Processor is BIG-ENDIAN |
csr.rdata(05) <= '1'; -- MBE: CPU/Processor is BIG-ENDIAN (in machine-mode) |
when csr_misa_c => -- R/-: misa - ISA and extensions |
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension |
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension |
1878,6 → 1902,10
csr.rdata(19) <= csr.mie_firqe(3); -- fast interrupt channel 3 |
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
when csr_mcounteren_c => -- R/W: machine counter enable register |
csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h] |
csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h] |
csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h] |
|
-- machine trap handling -- |
when csr_mscratch_c => -- R/W: mscratch - machine scratch register |
1988,6 → 2016,12
end if; |
end if; |
|
-- machine counter setup -- |
-- -------------------------------------------------------------------- |
when csr_mcountinhibit_c => -- R/W: mcountinhibit - machine counter-inhibit register |
csr.rdata(0) <= csr.mcountinhibit_cy; -- enable auto-increment of [m]cycle[h] counter |
csr.rdata(2) <= csr.mcountinhibit_ir; -- enable auto-increment of [m]instret[h] counter |
|
-- counters and timers -- |
when csr_cycle_c | csr_mcycle_c => -- R/(W): [m]cycle: Cycle counter LOW |
csr.rdata <= csr.mcycle(31 downto 0); |
2017,7 → 2051,6
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension |
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension |
csr.rdata(2) <= bool_to_ulogic_f(PMP_USE); -- RISC-V physical memory protection |
csr.rdata(3) <= bool_to_ulogic_f(zicnt_en_c); -- RISC-V performance counters ([m]cycle[h] & [m]instret[h]) implemented |
|
-- undefined/unavailable -- |
when others => |
/rtl/core/neorv32_cpu_decompressor.vhd
1,5 → 1,5
-- ################################################################################################# |
-- # << NEORV32 - CPU Compressed Instructions (C-extension) Decoder >> # |
-- # << NEORV32 - CPU Compressed Instructions (RISC-V C-extension) Decoder >> # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
238,16 → 238,16
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer |
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00010"; -- stack pointer |
ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend |
ci_instr32_o(instr_imm12_lsb_c + 00) <= '0'; |
ci_instr32_o(instr_imm12_lsb_c + 01) <= '0'; |
ci_instr32_o(instr_imm12_lsb_c + 02) <= '0'; |
ci_instr32_o(instr_imm12_lsb_c + 03) <= '0'; |
ci_instr32_o(instr_imm12_lsb_c + 04) <= ci_instr16_i(6); |
ci_instr32_o(instr_imm12_lsb_c + 05) <= ci_instr16_i(2); |
ci_instr32_o(instr_imm12_lsb_c + 06) <= ci_instr16_i(5); |
ci_instr32_o(instr_imm12_lsb_c + 07) <= ci_instr16_i(3); |
ci_instr32_o(instr_imm12_lsb_c + 08) <= ci_instr16_i(4); |
ci_instr32_o(instr_imm12_lsb_c + 09) <= ci_instr16_i(12); |
ci_instr32_o(instr_imm12_lsb_c + 0) <= '0'; |
ci_instr32_o(instr_imm12_lsb_c + 1) <= '0'; |
ci_instr32_o(instr_imm12_lsb_c + 2) <= '0'; |
ci_instr32_o(instr_imm12_lsb_c + 3) <= '0'; |
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6); |
ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(2); |
ci_instr32_o(instr_imm12_lsb_c + 6) <= ci_instr16_i(5); |
ci_instr32_o(instr_imm12_lsb_c + 7) <= ci_instr16_i(3); |
ci_instr32_o(instr_imm12_lsb_c + 8) <= ci_instr16_i(4); |
ci_instr32_o(instr_imm12_lsb_c + 9) <= ci_instr16_i(12); |
|
else -- C.LUI |
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_lui_c; |
/rtl/core/neorv32_package.vhd
45,13 → 45,12
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address |
|
-- (external) bus interface -- |
constant bus_timeout_c : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus access exception (min 3) |
constant bus_timeout_c : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2) |
constant wb_pipe_mode_c : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode |
constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian |
|
-- CPU core -- |
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, must be a power of 2, default=2 |
constant zicnt_en_c : boolean := true; -- enable RISC-V performance counters ([m]cycle[h], [m]instret[h]), default=true |
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2 |
|
-- physical memory protection (PMP) -- |
constant pmp_num_regions_c : natural := 2; -- number of regions (1..8) |
60,7 → 59,7
-- Architecture Constants (do not modify!)= ----------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040900"; -- no touchy! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040904"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the HW |
350,50 → 349,54
|
-- RISC-V CSR Addresses ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus |
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; -- misa |
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; -- mie |
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305"; -- mtvec |
constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := x"310"; -- mstatush |
-- read/write CSRs -- |
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus |
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; -- misa |
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; -- mie |
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305"; -- mtvec |
constant csr_mcounteren_c : std_ulogic_vector(11 downto 0) := x"306"; -- mcounteren |
constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := x"310"; -- mstatush |
-- |
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340"; -- mscratch |
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341"; -- mepc |
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342"; -- mcause |
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343"; -- mtval |
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344"; -- mip |
constant csr_mcountinhibit_c : std_ulogic_vector(11 downto 0) := x"320"; -- mcountinhibit |
-- |
constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := x"3a0"; -- pmpcfg0 |
constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := x"3a1"; -- pmpcfg1 |
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340"; -- mscratch |
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341"; -- mepc |
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342"; -- mcause |
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343"; -- mtval |
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344"; -- mip |
-- |
constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := x"3b0"; -- pmpaddr0 |
constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := x"3b1"; -- pmpaddr1 |
constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := x"3b2"; -- pmpaddr2 |
constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := x"3b3"; -- pmpaddr3 |
constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := x"3b4"; -- pmpaddr4 |
constant csr_pmpaddr5_c : std_ulogic_vector(11 downto 0) := x"3b5"; -- pmpaddr5 |
constant csr_pmpaddr6_c : std_ulogic_vector(11 downto 0) := x"3b6"; -- pmpaddr6 |
constant csr_pmpaddr7_c : std_ulogic_vector(11 downto 0) := x"3b7"; -- pmpaddr7 |
constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := x"3a0"; -- pmpcfg0 |
constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := x"3a1"; -- pmpcfg1 |
-- |
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00"; -- mcycle |
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02"; -- minstret |
constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := x"3b0"; -- pmpaddr0 |
constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := x"3b1"; -- pmpaddr1 |
constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := x"3b2"; -- pmpaddr2 |
constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := x"3b3"; -- pmpaddr3 |
constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := x"3b4"; -- pmpaddr4 |
constant csr_pmpaddr5_c : std_ulogic_vector(11 downto 0) := x"3b5"; -- pmpaddr5 |
constant csr_pmpaddr6_c : std_ulogic_vector(11 downto 0) := x"3b6"; -- pmpaddr6 |
constant csr_pmpaddr7_c : std_ulogic_vector(11 downto 0) := x"3b7"; -- pmpaddr7 |
-- |
constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := x"b80"; -- mcycleh |
constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := x"b82"; -- minstreth |
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00"; -- mcycle |
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02"; -- minstret |
-- |
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00"; -- cycle |
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01"; -- time |
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02"; -- instret |
constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := x"b80"; -- mcycleh |
constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := x"b82"; -- minstreth |
-- read-only CSRs -- |
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00"; -- cycle |
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01"; -- time |
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02"; -- instret |
-- |
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80"; -- cycleh |
constant csr_timeh_c : std_ulogic_vector(11 downto 0) := x"c81"; -- timeh |
constant csr_instreth_c : std_ulogic_vector(11 downto 0) := x"c82"; -- instreth |
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80"; -- cycleh |
constant csr_timeh_c : std_ulogic_vector(11 downto 0) := x"c81"; -- timeh |
constant csr_instreth_c : std_ulogic_vector(11 downto 0) := x"c82"; -- instreth |
-- |
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11"; -- mvendorid |
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12"; -- marchid |
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13"; -- mimpid |
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; -- mhartid |
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11"; -- mvendorid |
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12"; -- marchid |
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13"; -- mimpid |
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; -- mhartid |
-- |
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0"; -- mzext (neorv32-custom) |
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0"; -- mzext (neorv32-custom) |
|
-- Co-Processor Operations ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
523,6 → 526,10
-- Internal Data memory -- |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE : boolean := false; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
-- External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
588,6 → 595,7
-- General -- |
HW_THREAD_ID : std_ulogic_vector(31 downto 0) := (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := (others => '0'); -- cpu boot address |
BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
789,7 → 797,9
generic ( |
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension? |
-- Physical memory protection (PMP) -- |
PMP_USE : boolean := false -- implement physical memory protection? |
PMP_USE : boolean := false; -- implement physical memory protection? |
-- Bus Timeout -- |
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception |
); |
port ( |
-- global control -- |
844,6 → 854,43
); |
end component; |
|
-- Component: CPU Cache ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cache |
generic ( |
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE : natural := 16 -- block size in bytes (min 4), has to be a power of 2 |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic; -- global clock, rising edge |
rstn_i : in std_ulogic; -- global reset, low-active, async |
clear_i : in std_ulogic; -- cache clear |
-- host controller interface -- |
host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable |
host_we_i : in std_ulogic; -- write enable |
host_re_i : in std_ulogic; -- read enable |
host_cancel_i : in std_ulogic; -- cancel current bus transaction |
host_lock_i : in std_ulogic; -- locked/exclusive access |
host_ack_o : out std_ulogic; -- bus transfer acknowledge |
host_err_o : out std_ulogic; -- bus transfer error |
-- peripheral bus interface -- |
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data |
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data |
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable |
bus_we_o : out std_ulogic; -- write enable |
bus_re_o : out std_ulogic; -- read enable |
bus_cancel_o : out std_ulogic; -- cancel current bus transaction |
bus_lock_o : out std_ulogic; -- locked/exclusive access |
bus_ack_i : in std_ulogic; -- bus transfer acknowledge |
bus_err_i : in std_ulogic -- bus transfer error |
); |
end component; |
|
-- Component: CPU Bus Switch -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_busswitch |
1219,29 → 1266,34
component neorv32_sysinfo |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
-- Internal Instruction memory -- |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Internal Data memory -- |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE : boolean := true; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity (min 1), has to be a power 2 |
-- External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_CFU0_USE : boolean := true; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_USE : boolean := true -- implement custom functions unit 1 (CFU1)? |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_CFU0_USE : boolean := true; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_USE : boolean := true -- implement custom functions unit 1 (CFU1)? |
); |
port ( |
-- host access -- |
1257,7 → 1309,7
|
package body neorv32_package is |
|
-- Function: Minimal required bit width --------------------------------------------------- |
-- Function: Minimal required number of bits to represent input number -------------------- |
-- ------------------------------------------------------------------------------------------- |
function index_size_f(input : natural) return natural is |
begin |
/rtl/core/neorv32_sysinfo.vhd
45,29 → 45,34
entity neorv32_sysinfo is |
generic ( |
-- General -- |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader? |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code |
-- Internal Instruction memory -- |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM |
-- Internal Data memory -- |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE : boolean := true; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity (min 1), has to be a power 2 |
-- External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_CFU0_USE : boolean := true; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_USE : boolean := true -- implement custom functions unit 1 (CFU1)? |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)? |
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)? |
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)? |
IO_CFU0_USE : boolean := true; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_USE : boolean := true -- implement custom functions unit 1 (CFU1)? |
); |
port ( |
-- host access -- |
122,8 → 127,9
sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM); -- processor-internal instruction memory implemented as ROM? |
sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE); -- processor-internal data memory implemented? |
sysinfo_mem(2)(05) <= bool_to_ulogic_f(xbus_big_endian_c); -- is external memory bus interface using BIG-endian byte-order? |
sysinfo_mem(2)(06) <= bool_to_ulogic_f(ICACHE_USE); -- processor-internal instruction cache implemented? |
-- |
sysinfo_mem(2)(15 downto 06) <= (others => '0'); -- reserved |
sysinfo_mem(2)(15 downto 07) <= (others => '0'); -- reserved |
-- IO -- |
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_USE); -- general purpose input/output port unit (GPIO) implemented? |
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- machine system timer (MTIME) implemented? |
138,8 → 144,16
-- |
sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved |
|
-- SYSINFO(3): reserved -- |
sysinfo_mem(3) <= (others => '0'); -- reserved |
-- SYSINFO(3): Cache configuration -- |
sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_USE = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes) |
sysinfo_mem(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when (ICACHE_USE = true) else (others => '0'); -- i-cache: log2(number_of_block) |
sysinfo_mem(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_USE = true) else (others => '0'); -- i-cache: log2(associativity) |
sysinfo_mem(3)(15 downto 12) <= (others => '0'); -- replacement strategy (irrelevant since i-cache is read-only) |
-- |
sysinfo_mem(3)(19 downto 16) <= (others => '0'); -- reserved (for d-cache.block_size) |
sysinfo_mem(3)(23 downto 20) <= (others => '0'); -- reserved (for d-cache.num_blocks) |
sysinfo_mem(3)(27 downto 24) <= (others => '0'); -- reserved (for d-cache.associativity) |
sysinfo_mem(3)(31 downto 28) <= (others => '0'); -- reserved (for d-cache.replacement_Strategy) |
|
-- SYSINFO(4): Base address of instruction memory space -- |
sysinfo_mem(4) <= ispace_base_c; -- defined in neorv32_package.vhd file |
/rtl/core/neorv32_top.vhd
72,6 → 72,10
-- Internal Data memory -- |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE : boolean := false; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
-- External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
135,6 → 139,10
-- CPU boot address -- |
constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := cond_sel_stdulogicvector_f(BOOTLOADER_USE, boot_rom_base_c, ispace_base_c); |
|
-- Bus timeout -- |
constant bus_timeout_temp_c : natural := 2**index_size_f(bus_timeout_c); -- round to next power-of-two |
constant bus_timeout_proc_c : natural := cond_sel_natural_f(ICACHE_USE, ((ICACHE_BLOCK_SIZE/4)*bus_timeout_temp_c)-1, bus_timeout_c); |
|
-- alignment check for internal memories -- |
constant imem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_IMEM_SIZE)-1 downto 0) := (others => '0'); |
constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0'); |
176,7 → 184,7
src : std_ulogic; -- access source (1=instruction fetch, 0=data access) |
lock : std_ulogic; -- locked/exclusive (=atomic) access |
end record; |
signal cpu_i, cpu_d, p_bus : bus_interface_t; |
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t; |
|
-- io space access -- |
signal io_acc : std_ulogic; |
251,6 → 259,10
-- memory system - layout warning -- |
assert not (ispace_base_c /= x"00000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framework." severity warning; |
assert not (dspace_base_c /= x"80000000") report "NEORV32 PROCESSOR CONFIG WARNING! Non-default base address for data address space. Make sure this is sync with the software framework." severity warning; |
-- memory system - the i-cache is intended to accelerate instruction fetch via the external memory interface only -- |
assert not ((ICACHE_USE = true) and (MEM_EXT_USE = false)) report "NEORV32 PROCESSOR CONFIG NOTE. Implementing i-cache without having the external memory interface implemented. The i-cache is intended to accelerate instruction fetch via the external memory interface." severity note; |
-- memory system - cached instruction fetch latency check -- |
assert not (ICACHE_USE = true) report "NEORV32 PROCESSOR CONFIG WARNING! Implementing i-cache. Increasing bus access timeout from " & integer'image(bus_timeout_c) & " cycles to " & integer'image(bus_timeout_proc_c) & " cycles." severity warning; |
|
|
-- Reset Generator ------------------------------------------------------------------------ |
316,8 → 328,9
neorv32_cpu_inst: neorv32_cpu |
generic map ( |
-- General -- |
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id |
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address |
HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id |
CPU_BOOT_ADDR => cpu_boot_addr_c, -- cpu boot address |
BUS_TIMEOUT => bus_timeout_proc_c, -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
327,10 → 340,10
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? |
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? |
-- Extension Options -- |
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations |
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations |
-- Physical Memory Protection (PMP) -- |
PMP_USE => PMP_USE -- implement PMP? |
PMP_USE => PMP_USE -- implement PMP? |
) |
port map ( |
-- global control -- |
387,6 → 400,60
fast_irq(3) <= spi_irq or twi_irq; -- lowest priority, can be triggered by SPI or TWI |
|
|
-- CPU Instruction Cache ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
neorv32_icache_inst_true: |
if (ICACHE_USE = true) generate |
neorv32_icache_inst: neorv32_cache |
generic map ( |
CACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 2), has to be a power of 2 |
CACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE -- block size in bytes (min 4), has to be a power of 2 |
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
clear_i => cpu_i.fence, -- cache clear |
-- host controller interface -- |
host_addr_i => cpu_i.addr, -- bus access address |
host_rdata_o => cpu_i.rdata, -- bus read data |
host_wdata_i => cpu_i.wdata, -- bus write data |
host_ben_i => cpu_i.ben, -- byte enable |
host_we_i => cpu_i.we, -- write enable |
host_re_i => cpu_i.re, -- read enable |
host_cancel_i => cpu_i.cancel, -- cancel current bus transaction |
host_lock_i => cpu_i.lock, -- locked/exclusive access |
host_ack_o => cpu_i.ack, -- bus transfer acknowledge |
host_err_o => cpu_i.err, -- bus transfer error |
-- peripheral bus interface -- |
bus_addr_o => i_cache.addr, -- bus access address |
bus_rdata_i => i_cache.rdata, -- bus read data |
bus_wdata_o => i_cache.wdata, -- bus write data |
bus_ben_o => i_cache.ben, -- byte enable |
bus_we_o => i_cache.we, -- write enable |
bus_re_o => i_cache.re, -- read enable |
bus_cancel_o => i_cache.cancel, -- cancel current bus transaction |
bus_lock_o => i_cache.lock, -- locked/exclusive access |
bus_ack_i => i_cache.ack, -- bus transfer acknowledge |
bus_err_i => i_cache.err -- bus transfer error |
); |
end generate; |
|
neorv32_icache_inst_false: |
if (ICACHE_USE = false) generate |
i_cache.addr <= cpu_i.addr; |
cpu_i.rdata <= i_cache.rdata; |
i_cache.wdata <= cpu_i.wdata; |
i_cache.ben <= cpu_i.ben; |
i_cache.we <= cpu_i.we; |
i_cache.re <= cpu_i.re; |
i_cache.cancel <= cpu_i.cancel; |
i_cache.lock <= cpu_i.lock; |
cpu_i.ack <= i_cache.ack; |
cpu_i.err <= i_cache.err; |
end generate; |
|
|
-- CPU Crossbar Switch -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_busswitch_inst: neorv32_busswitch |
396,42 → 463,42
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
-- controller interface a -- |
ca_bus_addr_i => cpu_d.addr, -- bus access address |
ca_bus_rdata_o => cpu_d.rdata, -- bus read data |
ca_bus_wdata_i => cpu_d.wdata, -- bus write data |
ca_bus_ben_i => cpu_d.ben, -- byte enable |
ca_bus_we_i => cpu_d.we, -- write enable |
ca_bus_re_i => cpu_d.re, -- read enable |
ca_bus_cancel_i => cpu_d.cancel, -- cancel current bus transaction |
ca_bus_lock_i => cpu_d.lock, -- locked/exclusive access |
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge |
ca_bus_err_o => cpu_d.err, -- bus transfer error |
ca_bus_addr_i => cpu_d.addr, -- bus access address |
ca_bus_rdata_o => cpu_d.rdata, -- bus read data |
ca_bus_wdata_i => cpu_d.wdata, -- bus write data |
ca_bus_ben_i => cpu_d.ben, -- byte enable |
ca_bus_we_i => cpu_d.we, -- write enable |
ca_bus_re_i => cpu_d.re, -- read enable |
ca_bus_cancel_i => cpu_d.cancel, -- cancel current bus transaction |
ca_bus_lock_i => cpu_d.lock, -- locked/exclusive access |
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge |
ca_bus_err_o => cpu_d.err, -- bus transfer error |
-- controller interface b -- |
cb_bus_addr_i => cpu_i.addr, -- bus access address |
cb_bus_rdata_o => cpu_i.rdata, -- bus read data |
cb_bus_wdata_i => cpu_i.wdata, -- bus write data |
cb_bus_ben_i => cpu_i.ben, -- byte enable |
cb_bus_we_i => cpu_i.we, -- write enable |
cb_bus_re_i => cpu_i.re, -- read enable |
cb_bus_cancel_i => cpu_i.cancel, -- cancel current bus transaction |
cb_bus_lock_i => cpu_i.lock, -- locked/exclusive access |
cb_bus_ack_o => cpu_i.ack, -- bus transfer acknowledge |
cb_bus_err_o => cpu_i.err, -- bus transfer error |
cb_bus_addr_i => i_cache.addr, -- bus access address |
cb_bus_rdata_o => i_cache.rdata, -- bus read data |
cb_bus_wdata_i => i_cache.wdata, -- bus write data |
cb_bus_ben_i => i_cache.ben, -- byte enable |
cb_bus_we_i => i_cache.we, -- write enable |
cb_bus_re_i => i_cache.re, -- read enable |
cb_bus_cancel_i => i_cache.cancel, -- cancel current bus transaction |
cb_bus_lock_i => i_cache.lock, -- locked/exclusive access |
cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge |
cb_bus_err_o => i_cache.err, -- bus transfer error |
-- peripheral bus -- |
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions) |
p_bus_addr_o => p_bus.addr, -- bus access address |
p_bus_rdata_i => p_bus.rdata, -- bus read data |
p_bus_wdata_o => p_bus.wdata, -- bus write data |
p_bus_ben_o => p_bus.ben, -- byte enable |
p_bus_we_o => p_bus.we, -- write enable |
p_bus_re_o => p_bus.re, -- read enable |
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction |
p_bus_lock_o => p_bus.lock, -- locked/exclusive access |
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge |
p_bus_err_i => p_bus.err -- bus transfer error |
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions) |
p_bus_addr_o => p_bus.addr, -- bus access address |
p_bus_rdata_i => p_bus.rdata, -- bus read data |
p_bus_wdata_o => p_bus.wdata, -- bus write data |
p_bus_ben_o => p_bus.ben, -- byte enable |
p_bus_we_o => p_bus.we, -- write enable |
p_bus_re_o => p_bus.re, -- read enable |
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction |
p_bus_lock_o => p_bus.lock, -- locked/exclusive access |
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge |
p_bus_err_i => p_bus.err -- bus transfer error |
); |
|
-- processor bus: CPU data input -- |
931,29 → 998,34
neorv32_sysinfo_inst: neorv32_sysinfo |
generic map ( |
-- General -- |
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz |
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader? |
USER_CODE => USER_CODE, -- custom user code |
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz |
BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader? |
USER_CODE => USER_CODE, -- custom user code |
-- internal Instruction memory -- |
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM |
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
MEM_INT_IMEM_ROM => MEM_INT_IMEM_ROM, -- implement processor-internal instruction memory as ROM |
-- Internal Data memory -- |
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes |
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE => ICACHE_USE, -- implement instruction cache |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 |
ICACHE_ASSOCIATIVITY => 1, -- i-cache: associativity (min 1), has to be a power 2 |
-- External memory interface -- |
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface? |
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface? |
-- Processor peripherals -- |
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)? |
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)? |
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)? |
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)? |
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)? |
IO_CFU0_USE => IO_CFU0_USE, -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_USE => IO_CFU1_USE -- implement custom functions unit 1 (CFU1)? |
IO_GPIO_USE => IO_GPIO_USE, -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE => IO_MTIME_USE, -- implement machine system timer (MTIME)? |
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)? |
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)? |
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)? |
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)? |
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)? |
IO_CFU0_USE => IO_CFU0_USE, -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_USE => IO_CFU1_USE -- implement custom functions unit 1 (CFU1)? |
) |
port map ( |
-- host access -- |
/rtl/core/neorv32_wishbone.vhd
1,18 → 1,18
-- ################################################################################################# |
-- # << NEORV32 - External Bus Interface (WISHBONE) >> # |
-- # ********************************************************************************************* # |
-- # The interface provides registers for all outgoing signals. If the host cancels a running # |
-- # transfer, the Wishbone arbiter still waits some time for the bus system to ACK the transfer # |
-- # before the arbiter forces termination. # |
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - # |
-- # The interface provides registers for all outgoing and for all incoming signals. If the host # |
-- # cancels an activetransfer, the Wishbone arbiter still waits some time for the bus system to # |
-- # ACK/ERR the transfer before the arbiter forces termination. # |
-- # # |
-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address # |
-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). # |
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - # |
-- # # |
-- # All bus accesses from the CPU, which do not target the internal IO region / the internal # |
-- # bootlloader / the internal instruction or data memories (if implemented), are delegated via # |
-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response # |
-- # latency of up to neorv32_package.vhd:bus_timeout_c - 2 cycles. # |
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - # |
-- # latency of up to BUS_TIMEOUT - 2 cycles. # |
-- # # |
-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) # |
-- # and also pipelined transactions (WB_PIPELINED_MODE = true). # |
-- # ********************************************************************************************* # |
62,7 → 62,9
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes |
-- Internal data memory -- |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes |
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes |
-- Bus Timeout -- |
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception |
); |
port ( |
-- global control -- |
99,7 → 101,7
architecture neorv32_wishbone_rtl of neorv32_wishbone is |
|
-- constants -- |
constant xbus_timeout_c : natural := bus_timeout_c/4; |
constant xbus_timeout_c : natural := BUS_TIMEOUT/4; |
|
-- access control -- |
signal int_imem_acc : std_ulogic; |
134,10 → 136,10
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- max bus timeout latency lower than recommended -- |
assert not (bus_timeout_c <= 32) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (neorv32_package.vhd:bus_timeout_c) should be >32 when using external bus interface." severity error; |
assert not (BUS_TIMEOUT <= 32) report "NEORV32 PROCESSOR CONFIG WARNING: Bus timeout should be >32 when using external bus interface." severity warning; |
-- external memory iterface protocol + max timeout latency notifier (warning) -- |
assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity note; |
assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG WARNING! Implementing external memory interface using PIEPLINED Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning; |
assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol." severity note; |
assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE! Implementing external memory interface using PIEPLINED Wishbone protocol." severity note; |
-- endianness -- |
assert not (xbus_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Using LITTLE-ENDIAN byte order for external memory interface." severity note; |
assert not (xbus_big_endian_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: Using BIG-ENDIAN byte order for external memory interface." severity note; |
/rtl/top_templates/neorv32_cpu_stdlogic.vhd
44,6 → 44,7
-- General -- |
HW_THREAD_ID : std_logic_vector(31 downto 0):= (others => '0'); -- hardware thread id |
CPU_BOOT_ADDR : std_logic_vector(31 downto 0):= (others => '0'); -- cpu boot address |
BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension? |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? |
135,6 → 136,7
-- General -- |
HW_THREAD_ID => HW_THREAD_ID_INT, -- hardware thread id |
CPU_BOOT_ADDR => CPU_BOOT_ADDR_INT, -- cpu boot address |
BUS_TIMEOUT => BUS_TIMEOUT, -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception |
-- RISC-V CPU Extensions -- |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension? |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? |
/rtl/top_templates/neorv32_test_setup.vhd
93,6 → 93,10
-- Internal Data memory -- |
MEM_INT_DMEM_USE => true, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE => false, -- implement instruction cache |
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2 |
-- External memory interface -- |
MEM_EXT_USE => false, -- implement external memory bus interface? |
-- Processor peripherals -- |
/rtl/top_templates/neorv32_top_axi4lite.vhd
68,6 → 68,10
-- Internal Data memory -- |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE : boolean := false; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
-- Processor peripherals -- |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)? |
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)? |
222,6 → 226,10
-- Internal Data memory -- |
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE => ICACHE_USE, -- implement instruction cache |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 |
-- External memory interface -- |
MEM_EXT_USE => true, -- implement external memory bus interface? |
-- Processor peripherals -- |
/rtl/top_templates/neorv32_top_stdlogic.vhd
66,6 → 66,10
-- Internal Data memory -- |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE : boolean := false; -- implement instruction cache |
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 |
-- External memory interface -- |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface? |
-- Processor peripherals -- |
198,6 → 202,10
-- Internal Data memory -- |
MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE => ICACHE_USE, -- implement instruction cache |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 |
-- External memory interface -- |
MEM_EXT_USE => MEM_EXT_USE, -- implement external memory bus interface? |
-- Processor peripherals -- |
/sim/ghdl/ghdl_sim.sh
41,6 → 41,7
# |
ghdl -a --work=neorv32 $srcdir_core/neorv32_boot_rom.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_busswitch.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cache.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfu0.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfu1.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu.vhd |
/sim/vivado/neorv32_tb_behav.wcfg
12,15 → 12,15
</db_ref> |
</db_ref_list> |
<zoom_setting> |
<ZoomStartTime time="0fs"></ZoomStartTime> |
<ZoomEndTime time="1111160fs"></ZoomEndTime> |
<Cursor1Time time="15000fs"></Cursor1Time> |
<ZoomStartTime time="396191834fs"></ZoomStartTime> |
<ZoomEndTime time="396390835fs"></ZoomEndTime> |
<Cursor1Time time="396225000fs"></Cursor1Time> |
</zoom_setting> |
<column_width_setting> |
<NameColumnWidth column_width="203"></NameColumnWidth> |
<ValueColumnWidth column_width="95"></ValueColumnWidth> |
<ValueColumnWidth column_width="124"></ValueColumnWidth> |
</column_width_setting> |
<WVObjectSize size="121" /> |
<WVObjectSize size="122" /> |
<wvobject type="divider" fp_name="divider273"> |
<obj_property name="label">CPU: Control.FETCH</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
153,7 → 153,6
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/atomic_ctrl" type="array"> |
<obj_property name="ElementShortName">atomic_ctrl</obj_property> |
<obj_property name="ObjectShortName">atomic_ctrl</obj_property> |
<obj_property name="isExpanded"></obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider139"> |
<obj_property name="label">CPU: Control.TRAP</obj_property> |
376,6 → 375,10
<obj_property name="ObjectShortName">st_pmp_fault</obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider298"> |
<obj_property name="label">I-CACHE</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
<wvobject type="divider" fp_name="divider298"> |
<obj_property name="label">CPU: MULDIV CP</obj_property> |
<obj_property name="DisplayName">label</obj_property> |
</wvobject> |
/sim/neorv32_tb.vhd
55,6 → 55,7
-- general -- |
constant ext_imem_c : boolean := false; -- false: use and boot from proc-internal IMEM, true: use and boot from external (initialized) simulated IMEM (ext. mem A) |
constant ext_dmem_c : boolean := false; -- false: use proc-internal DMEM, true: use external simulated DMEM (ext. mem B) |
constant icache_use_c : boolean := false; -- set true to use processor-internal instruction cache |
constant imem_size_c : natural := 16*1024; -- size in bytes of processor-internal IMEM / external mem A |
constant dmem_size_c : natural := 8*1024; -- size in bytes of processor-internal DMEM / external mem B |
constant f_clock_c : natural := 100000000; -- main clock in Hz |
195,6 → 196,10
-- Internal Data memory -- |
MEM_INT_DMEM_USE => int_dmem_c, -- implement processor-internal data memory |
MEM_INT_DMEM_SIZE => dmem_size_c, -- size of processor-internal data memory in bytes |
-- Internal Cache memory -- |
ICACHE_USE => icache_use_c, -- implement instruction cache |
ICACHE_NUM_BLOCKS => 8, -- i-cache: number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2 |
-- External memory interface -- |
MEM_EXT_USE => true, -- implement external memory bus interface? |
-- Processor peripherals -- |
/sw/common/crt0.S
187,6 → 187,10
csrw mcycleh, zero |
csrw minstret, zero |
csrw minstreth, zero |
// enable read-access from user-mode for cycle[h], time[h] and instret[h] |
csrwi 0x306, 7 // mcounteren |
// enable auto-increment of all counters |
csrw 0x320, x0 // mcountinhibit |
|
// restore mcause reset value (so that 'main' knows we are coming from reset) |
li x12, 0x80000000 |
/sw/example/cpu_test/main.c
72,6 → 72,8
int cnt_ok = 0; |
/// Global counter for total number of tests |
int cnt_test = 0; |
/// Global timestamp for traps (stores mcycle.low on trap enter) |
uint32_t trap_timestamp32 = 0; |
|
|
/**********************************************************************//** |
160,6 → 162,10
neorv32_cpu_set_minstret(0); |
neorv32_cpu_set_mcycle(0); |
|
// enable performance counter auto increment |
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); |
neorv32_cpu_csr_write(CSR_MCOUNTEREN, 7); // allow access from user-mode code |
|
neorv32_mtime_set_time(0); |
// set CMP of machine system timer MTIME to max to prevent an IRQ |
uint64_t mtime_cmp_max = 0xFFFFFFFFFFFFFFFFUL; |
181,7 → 187,9
// show full HW config report |
neorv32_rte_print_hw_config(); |
|
|
// configure RTE |
// ----------------------------------------------- |
neorv32_uart_printf("\n\nInitializing NEORV32 run-time environment (RTE)... "); |
|
neorv32_rte_setup(); // this will install a full-detailed debug handler for all traps |
295,29 → 303,22
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Testing [m]instret[h] counters: ", cnt_test); |
|
// check if counters are implemented |
if (neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_ZICNT)) { |
cnt_test++; |
cnt_test++; |
|
// get current cycle counter |
volatile uint64_t cycle_csr_test = neorv32_cpu_get_cycle(); |
// get current cycle counter |
tmp_a = neorv32_cpu_get_cycle(); |
|
// wait some time to have a nice increment |
asm volatile ("nop"); |
asm volatile ("nop"); |
asm volatile ("nop"); |
// wait some time to have a nice increment |
asm volatile ("nop"); |
asm volatile ("nop"); |
|
// make sure cycle counter has incremented and there was no exception during access |
if ((neorv32_cpu_get_cycle() > cycle_csr_test) && |
(neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
// make sure cycle counter has incremented and there was no exception during access |
if ((neorv32_cpu_get_cycle() > tmp_a) && |
(neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
test_ok(); |
} |
else { |
neorv32_uart_printf("skipped (not implemented)\n"); |
test_fail(); |
} |
|
|
327,34 → 328,104
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Testing [m]cycle[h] counters: ", cnt_test); |
|
// check if counters are implemented |
if (neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_ZICNT)) { |
cnt_test++; |
cnt_test++; |
|
// get current instruction counter |
volatile uint64_t instret_csr_test = neorv32_cpu_get_instret(); |
// get current instruction counter |
tmp_a = neorv32_cpu_get_instret(); |
|
// wait some time to have a nice increment |
asm volatile ("nop"); |
asm volatile ("nop"); |
asm volatile ("nop"); |
// wait some time to have a nice increment |
asm volatile ("nop"); |
asm volatile ("nop"); |
|
// make sure instruction counter has incremented and there was no exception during access |
if ((neorv32_cpu_get_instret() > instret_csr_test) && |
(neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
// make sure instruction counter has incremented and there was no exception during access |
if ((neorv32_cpu_get_instret() > tmp_a) && |
(neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
|
// ---------------------------------------------------------- |
// Test mcountinhibt: inhibit auto-inc of [m]cycle |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Testing mcountINHIBT.cy CSR: ", cnt_test); |
|
cnt_test++; |
|
// inhibit [m]cycle CSR |
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT); |
tmp_a |= (1<<CPU_MCOUNTINHIBIT_CY); // inhibit cycle counter auto-increment |
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a); |
|
// get current cycle counter |
tmp_a = neorv32_cpu_csr_read(CSR_CYCLE); |
|
// wait some time to have a nice "increment" (there should be NO increment at all!) |
asm volatile ("nop"); |
asm volatile ("nop"); |
|
tmp_b = neorv32_cpu_csr_read(CSR_CYCLE); |
|
// make sure instruction counter has NOT incremented and there was no exception during access |
if ((tmp_a == tmp_b) && (neorv32_cpu_csr_read(CSR_MCAUSE) == 0)) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
|
// re-enable [m]cycle CSR |
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT); |
tmp_a &= ~(1<<CPU_MCOUNTINHIBIT_CY); // clear inhibit of cycle counter auto-increment |
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a); |
|
|
// ---------------------------------------------------------- |
// Test mcounteren: do not allow cycle[h] access from user-mode |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Testing mcounterEN.cy CSR: ", cnt_test); |
|
cnt_test++; |
|
// do not allow user-level code to access cycle[h] CSRs |
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN); |
tmp_a &= ~(1<<CPU_MCOUNTEREN_CY); // clear access right |
neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a); |
|
// switch to user mode (hart will be back in MACHINE mode when trap handler returns) |
neorv32_cpu_goto_user_mode(); |
{ |
// access to cycle CSR is no longer allowed |
tmp_a = neorv32_cpu_csr_read(CSR_CYCLE); |
} |
|
// make sure there was an illegal instruction trap |
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) { |
if (tmp_a == 0) { // make sure user-level code CANNOT read locked CSR content! |
test_ok(); |
} |
else { |
neorv32_uart_printf("SECURITY VIOLATION! "); |
test_fail(); |
} |
} |
else { |
neorv32_uart_printf("skipped (not implemented)\n"); |
test_fail(); |
} |
|
|
// re-allow user-level code to access cycle[h] CSRs |
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN); |
tmp_a |= (1<<CPU_MCOUNTEREN_CY); // re-allow access right |
neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a); |
|
|
// ---------------------------------------------------------- |
// Bus timeout latency estimation (very unprecise!) |
// Bus timeout latency estimation |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Estimating bus time-out latency: ", cnt_test); |
364,13 → 435,11
neorv32_cpu_csr_write(CSR_MCYCLE, 0); |
|
// this store access will timeout |
MMR_UNREACHABLE = 0; |
MMR_UNREACHABLE = 0; // trap handler will stor mcycle.low to "trap_timestamp32" |
|
tmp_a = neorv32_cpu_csr_read(CSR_MCYCLE); |
|
// make sure there was a time-out |
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) { |
neorv32_uart_printf("~%u cycles ", tmp_a/4); // divide by average CPI |
neorv32_uart_printf("~%u cycles ", trap_timestamp32-178); // remove trap handler overhead - empiric value ;) |
test_ok(); |
} |
else { |
560,7 → 629,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
// no more mtime interrupts |
neorv32_mtime_set_timecmp(-1); |
599,7 → 667,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
// no more mtime interrupts |
neorv32_mtime_set_timecmp(-1); |
854,7 → 921,6
// switch to user mode (hart will be back in MACHINE mode when trap handler returns) |
neorv32_cpu_goto_user_mode(); |
{ |
// access to misa not allowed for user-level programs |
asm volatile("ECALL"); |
} |
|
886,10 → 952,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MTI) { |
test_ok(); |
921,10 → 983,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MSI) { |
test_ok(); |
953,10 → 1011,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_MEI) { |
test_ok(); |
987,10 → 1041,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_0) { |
test_ok(); |
1030,10 → 1080,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_1) { |
test_ok(); |
1087,10 → 1133,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
// wait for UART to finish transmitting |
while(neorv32_uart_tx_busy()); |
1130,10 → 1172,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) { |
test_ok(); |
1170,10 → 1208,6
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
asm volatile("nop"); |
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_3) { |
test_ok(); |
1438,9 → 1472,10
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (succeeding access): ", cnt_test); |
|
#ifdef __riscv_atomic |
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation |
|
// skip if A-mode is implemented |
// skip if A-mode is not implemented |
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) { |
|
cnt_test++; |
1463,6 → 1498,9
else { |
neorv32_uart_printf("skipped (on real hardware)\n"); |
} |
#else |
neorv32_uart_printf("skipped (not implemented)\n"); |
#endif |
|
|
// ---------------------------------------------------------- |
1471,9 → 1509,10
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Atomic access (LR+SC) test (failing access): ", cnt_test); |
|
#ifdef __riscv_atomic |
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation |
|
// skip if A-mode is implemented |
// skip if A-mode is not implemented |
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) { |
|
cnt_test++; |
1495,9 → 1534,44
else { |
neorv32_uart_printf("skipped (on real hardware)\n"); |
} |
#else |
neorv32_uart_printf("skipped (not implemented)\n"); |
#endif |
|
|
// ---------------------------------------------------------- |
// Test AMO atomic operation - should raise illegal instruction exception |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Atomic AMOSWAP test (should raise illegal CMD exception): ", cnt_test); |
|
#ifdef __riscv_atomic |
// skip if A-mode is not implemented |
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) { |
|
cnt_test++; |
|
// AMO operations are not implemented! |
// this should cause an illegal instruction exception |
asm volatile ("amoswap.w x0, x0, (x0)"); |
|
// atomic compare-and-swap |
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
} |
else { |
neorv32_uart_printf("skipped (not implemented)\n"); |
} |
#else |
neorv32_uart_printf("skipped (not implemented)\n"); |
#endif |
|
|
// ---------------------------------------------------------- |
// Final test reports |
// ---------------------------------------------------------- |
neorv32_uart_printf("\nExecuted instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); |
1522,6 → 1596,9
**************************************************************************/ |
void global_trap_handler(void) { |
|
// store time stamp |
trap_timestamp32 = neorv32_cpu_csr_read(CSR_MCYCLE); |
|
// hack: always come back in MACHINE MODE |
register uint32_t mask = (1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L); |
asm volatile ("csrrs zero, mstatus, %[input_j]" : : [input_j] "r" (mask)); |
/sw/lib/include/neorv32.h
53,50 → 53,53
* Available CPU Control and Status Registers (CSRs) |
**************************************************************************/ |
enum NEORV32_CPU_CSRS_enum { |
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */ |
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */ |
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */ |
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */ |
CSR_MSTATUSH = 0x310, /**< 0x310 - mstatush (r/-): Machine status register - high word */ |
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */ |
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */ |
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */ |
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */ |
CSR_MCOUNTEREN = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */ |
CSR_MSTATUSH = 0x310, /**< 0x310 - mstatush (r/-): Machine status register - high word */ |
|
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */ |
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */ |
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */ |
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */ |
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */ |
CSR_MCOUNTINHIBIT = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */ |
|
CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */ |
CSR_PMPCFG1 = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */ |
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */ |
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */ |
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */ |
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */ |
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */ |
|
CSR_PMPADDR0 = 0x3b0, /**< 0x3b0 - pmpaddr0 (r/w): Physical memory protection address register 0 */ |
CSR_PMPADDR1 = 0x3b1, /**< 0x3b1 - pmpaddr1 (r/w): Physical memory protection address register 1 */ |
CSR_PMPADDR2 = 0x3b2, /**< 0x3b2 - pmpaddr2 (r/w): Physical memory protection address register 2 */ |
CSR_PMPADDR3 = 0x3b3, /**< 0x3b3 - pmpaddr3 (r/w): Physical memory protection address register 3 */ |
CSR_PMPADDR4 = 0x3b4, /**< 0x3b4 - pmpaddr4 (r/w): Physical memory protection address register 4 */ |
CSR_PMPADDR5 = 0x3b5, /**< 0x3b5 - pmpaddr5 (r/w): Physical memory protection address register 5 */ |
CSR_PMPADDR6 = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */ |
CSR_PMPADDR7 = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */ |
CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */ |
CSR_PMPCFG1 = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */ |
|
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */ |
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */ |
CSR_PMPADDR0 = 0x3b0, /**< 0x3b0 - pmpaddr0 (r/w): Physical memory protection address register 0 */ |
CSR_PMPADDR1 = 0x3b1, /**< 0x3b1 - pmpaddr1 (r/w): Physical memory protection address register 1 */ |
CSR_PMPADDR2 = 0x3b2, /**< 0x3b2 - pmpaddr2 (r/w): Physical memory protection address register 2 */ |
CSR_PMPADDR3 = 0x3b3, /**< 0x3b3 - pmpaddr3 (r/w): Physical memory protection address register 3 */ |
CSR_PMPADDR4 = 0x3b4, /**< 0x3b4 - pmpaddr4 (r/w): Physical memory protection address register 4 */ |
CSR_PMPADDR5 = 0x3b5, /**< 0x3b5 - pmpaddr5 (r/w): Physical memory protection address register 5 */ |
CSR_PMPADDR6 = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */ |
CSR_PMPADDR7 = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */ |
|
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */ |
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */ |
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */ |
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */ |
|
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */ |
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */ |
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */ |
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */ |
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */ |
|
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */ |
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */ |
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */ |
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */ |
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */ |
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */ |
|
CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */ |
CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */ |
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */ |
CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */ |
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */ |
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */ |
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */ |
|
CSR_MZEXT = 0xfc0 /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */ |
CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */ |
CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */ |
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */ |
CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */ |
|
CSR_MZEXT = 0xfc0 /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */ |
}; |
|
|
105,6 → 108,7
**************************************************************************/ |
enum NEORV32_CPU_MSTATUS_enum { |
CPU_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */ |
CPU_MSTATUS_UBE = 6, /**< CPU mstatus CSR (6): UBE - User-mode endianness (little-endian=0, big-endian=1) (r/-) */ |
CPU_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */ |
CPU_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */ |
CPU_MSTATUS_MPP_H = 12 /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */ |
112,14 → 116,33
|
|
/**********************************************************************//** |
* CPU <b>mstatush</b> CSR (r/-): Machine status - high word(RISC-V spec.) |
* CPU <b>mstatush</b> CSR (r/-): Machine status - high word (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MSTATUSH_enum { |
CPU_MSTATUSH_MBE = 5 /**< CPU mstatush CSR (5): MBE - Machine endianness (little-endian=0, big-endian=1) (r/w) */ |
CPU_MSTATUSH_MBE = 5 /**< CPU mstatush CSR (5): MBE - Machine-mode endianness (little-endian=0, big-endian=1) (r/-) */ |
}; |
|
|
/**********************************************************************//** |
* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MCOUNTEREN_enum { |
CPU_MCOUNTEREN_CY = 0, /**< CPU mcounteren CSR (0): CY - Allow access to cycle[h] CSRs from U-mode when set (r/w) */ |
CPU_MCOUNTEREN_TM = 1, /**< CPU mcounteren CSR (1): TM - Allow access to time[h] CSRs from U-mode when set (r/w) */ |
CPU_MCOUNTEREN_IR = 2 /**< CPU mcounteren CSR (2): IR - Allow access to instret[h] CSRs from U-mode when set (r/w) */ |
}; |
|
|
/**********************************************************************//** |
* CPU <b>mcountinhibit</b> CSR (r/w): Machine counter-inhibit (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MCOUNTINHIBIT_enum { |
CPU_MCOUNTINHIBIT_CY = 0, /**< CPU mcountinhibit CSR (0): CY - Enable auto-increment of [m]cycle[h] CSR when set (r/w) */ |
CPU_MCOUNTINHIBIT_IR = 2 /**< CPU mcountinhibit CSR (2): IR - Enable auto-increment of [m]instret[h] CSR when set (r/w) */ |
}; |
|
|
/**********************************************************************//** |
* CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.) |
**************************************************************************/ |
enum NEORV32_CPU_MIE_enum { |
172,8 → 195,7
enum NEORV32_CPU_MZEXT_enum { |
CPU_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */ |
CPU_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */ |
CPU_MZEXT_PMP = 2, /**< CPU mzext CSR (2): PMP extension available when set (r/-) */ |
CPU_MZEXT_ZICNT = 3 /**< CPU mzext CSR (3): Standard RISC-V performance counters ([m]cycle[h] & [m]instret[h]) available when set (r/-) */ |
CPU_MZEXT_PMP = 2 /**< CPU mzext CSR (2): PMP extension available when set (r/-) */ |
}; |
|
|
521,8 → 543,8
#define SYSINFO_USER_CODE (*(IO_ROM32 0xFFFFFFE4UL)) |
/** SYSINFO(2): Clock speed */ |
#define SYSINFO_FEATURES (*(IO_ROM32 0xFFFFFFE8UL)) |
/** SYSINFO(3): reserved */ |
#define SYSINFO_reserved (*(IO_ROM32 0xFFFFFFECUL)) |
/** SYSINFO(3): Cache configuration */ |
#define SYSINFO_CACHE (*(IO_ROM32 0xFFFFFFECUL)) |
/** SYSINFO(4): Instruction memory address space base */ |
#define SYSINFO_ISPACE_BASE (*(IO_ROM32 0xFFFFFFF0UL)) |
/** SYSINFO(5): Data memory address space base */ |
533,7 → 555,6
#define SYSINFO_DMEM_SIZE (*(IO_ROM32 0xFFFFFFFCUL)) |
/**@}*/ |
|
|
/**********************************************************************//** |
* SYSINFO_FEATURES (r/-): Implemented processor devices/features |
**************************************************************************/ |
544,6 → 565,7
SYSINFO_FEATURES_MEM_INT_IMEM_ROM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal instruction memory implemented as ROM when 1 (via MEM_INT_IMEM_ROM generic) */ |
SYSINFO_FEATURES_MEM_INT_DMEM = 4, /**< SYSINFO_FEATURES (4) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_USE generic) */ |
SYSINFO_FEATURES_MEM_EXT_ENDIAN = 5, /**< SYSINFO_FEATURES (5) (r/-): External bus interface uses BIG-endian byte-order when 1 (via package.xbus_big_endian_c constant) */ |
SYSINFO_FEATURES_ICACHE = 6, /**< SYSINFO_FEATURES (6) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_USE generic) */ |
|
SYSINFO_FEATURES_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_USE generic) */ |
SYSINFO_FEATURES_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_USE generic) */ |
557,7 → 579,27
SYSINFO_FEATURES_IO_CFU1 = 25 /**< SYSINFO_FEATURES (25) (r/-): Custom functions unit 1 implemented when 1 (via IO_CFU1_USE generic) */ |
}; |
|
/**********************************************************************//** |
* SYSINFO_CACHE (r/-): Cache configuration |
**************************************************************************/ |
enum NEORV32_SYSINFO_CACHE_enum { |
SYSINFO_CACHE_IC_BLOCK_SIZE_0 = 0, /**< SYSINFO_CACHE (0) (r/-): i-cache: log2(Block size in bytes), bit 0 (via ICACHE_BLOCK_SIZE generic) */ |
SYSINFO_CACHE_IC_BLOCK_SIZE_1 = 1, /**< SYSINFO_CACHE (1) (r/-): i-cache: log2(Block size in bytes), bit 1 (via ICACHE_BLOCK_SIZE generic) */ |
SYSINFO_CACHE_IC_BLOCK_SIZE_2 = 2, /**< SYSINFO_CACHE (2) (r/-): i-cache: log2(Block size in bytes), bit 2 (via ICACHE_BLOCK_SIZE generic) */ |
SYSINFO_CACHE_IC_BLOCK_SIZE_3 = 3, /**< SYSINFO_CACHE (3) (r/-): i-cache: log2(Block size in bytes), bit 3 (via ICACHE_BLOCK_SIZE generic) */ |
|
SYSINFO_CACHE_IC_NUM_BLOCKS_0 = 4, /**< SYSINFO_CACHE (4) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 0 (via ICACHE_NUM_BLOCKS generic) */ |
SYSINFO_CACHE_IC_NUM_BLOCKS_1 = 5, /**< SYSINFO_CACHE (5) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 1 (via ICACHE_NUM_BLOCKS generic) */ |
SYSINFO_CACHE_IC_NUM_BLOCKS_2 = 6, /**< SYSINFO_CACHE (6) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 2 (via ICACHE_NUM_BLOCKS generic) */ |
SYSINFO_CACHE_IC_NUM_BLOCKS_3 = 7, /**< SYSINFO_CACHE (7) (r/-): i-cache: log2(Number of cache blocks/pages/lines), bit 3 (via ICACHE_NUM_BLOCKS generic) */ |
|
SYSINFO_CACHE_IC_ASSOCIATIVITY_0 = 8, /**< SYSINFO_CACHE (10) (r/-): i-cache: log2(associativity), bit 0 (always 0 -> direct mapped) */ |
SYSINFO_CACHE_IC_ASSOCIATIVITY_1 = 9, /**< SYSINFO_CACHE (11) (r/-): i-cache: log2(associativity), bit 1 (always 0 -> direct mapped) */ |
SYSINFO_CACHE_IC_ASSOCIATIVITY_2 = 10, /**< SYSINFO_CACHE (12) (r/-): i-cache: log2(associativity), bit 2 (always 0 -> direct mapped) */ |
SYSINFO_CACHE_IC_ASSOCIATIVITY_3 = 11, /**< SYSINFO_CACHE (13) (r/-): i-cache: log2(associativity), bit 3 (always 0 -> direct mapped) */ |
}; |
|
|
// ---------------------------------------------------------------------------- |
// Include all IO driver headers |
// ---------------------------------------------------------------------------- |
/sw/lib/source/neorv32_rte.c
277,13 → 277,13
neorv32_uart_printf("unknown"); |
} |
if (tmp == 1) { |
neorv32_uart_printf("RV32"); |
neorv32_uart_printf("rv32"); |
} |
if (tmp == 2) { |
neorv32_uart_printf("RV64"); |
neorv32_uart_printf("rv64"); |
} |
if (tmp == 3) { |
neorv32_uart_printf("RV128"); |
neorv32_uart_printf("rv128"); |
} |
|
// CPU extensions |
317,9 → 317,6
if (tmp & (1<<CPU_MZEXT_PMP)) { |
neorv32_uart_printf("PMP "); |
} |
if (tmp & (1<<CPU_MZEXT_ZICNT)) { |
neorv32_uart_printf("Zicnt "); |
} |
|
|
// check physical memory protection |
386,7 → 383,43
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM)); |
neorv32_uart_printf("DMEM size: %u bytes\n", SYSINFO_DMEM_SIZE); |
|
neorv32_uart_printf("Bootloader: "); |
neorv32_uart_printf("\nInternal i-cache: "); |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE)); |
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE)) { |
neorv32_uart_printf("- "); |
|
uint32_t ic_block_size = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_BLOCK_SIZE_0) & 0x0F; |
if (ic_block_size) { |
ic_block_size = 1 << ic_block_size; |
} |
else { |
ic_block_size = 0; |
} |
|
uint32_t ic_num_blocks = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_NUM_BLOCKS_0) & 0x0F; |
if (ic_num_blocks) { |
ic_num_blocks = 1 << ic_num_blocks; |
} |
else { |
ic_num_blocks = 0; |
} |
|
uint32_t ic_associativity = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_ASSOCIATIVITY_0) & 0x0F; |
ic_associativity = 1 << ic_associativity; |
|
neorv32_uart_printf("%u bytes (%u set(s), %u block(s) per set, %u bytes per block), ", ic_associativity*ic_num_blocks*ic_block_size, ic_associativity, ic_num_blocks, ic_block_size); |
if (ic_associativity == 0) { |
neorv32_uart_printf("direct-mapped\n"); |
} |
else if (ic_associativity == ic_num_blocks) { |
neorv32_uart_printf("%u-way set-associative\n", ic_associativity); |
} |
else { |
neorv32_uart_printf("fully-associative\n"); |
} |
} |
|
neorv32_uart_printf("\nBootloader: "); |
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER)); |
|
neorv32_uart_printf("\nExternal memory bus interface: "); |
475,7 → 508,7
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Function to show the processor version in human-readable format. |
* NEORV32 runtime environment: Print the processor version in human-readable format. |
**************************************************************************/ |
void neorv32_rte_print_hw_version(void) { |
|
515,7 → 548,7
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Print project credits |
* NEORV32 runtime environment: Print project logo |
**************************************************************************/ |
void neorv32_rte_print_logo(void) { |
|
/CHANGELOG.md
1,12 → 1,15
## Project Change Log |
|
The most recent **NEORV32** project version can be found on top of this list. |
"Officially released" versions are linked and highlighted (:rocket:). |
"Officially released" versions are linked and highlighted :rocket:. |
The latest release is [](https://github.com/stnolting/neorv32/releases). |
A list of all releases can be found [here](https://github.com/stnolting/neorv32/releases). The most recent version of the *NEORV32 data sheet* |
can be found [here](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf). |
|
The processor can determine its version from the `mimpid` CSR (at CSR address 0xf13). A 2x4-bit decimal-coded representation is used. Leading |
:information_source: To see a list of all commits |
between release run `git log v1.4.7.0..v1.4.8.0` (example to to see commits between v1.4.7.0 and v1.4.8.0). |
|
The processor can determine its version from the `mimpid` CSR (at CSR address 0xf13). A 8x4-bit BCD representation is used. Leading |
zeros are optional. Example: `CSR(mimpid) = 0x01040312 => 01.04.03.12 = Version 01.04.03.12 = v1.4.3.12` |
|
For the HDL sources the version number is globally defined by the `hw_version_c` constant in the main VHDL package file |
14,7 → 17,11
|
| Date (*dd.mm.yyyy*) | Version | Comment | |
|:----------:|:-------:|:--------| |
| 19.12.2020 | 1.4.9.0 | Testbench: added memory-mapped triggers to trigger core's "machine software & external interrupts"; `sw/example/cpu_test`: removed CFU tests, added `MEI` and `MSI` tests; added **RISC-V-Compliance Test Framework** to repository (`riscv-compliance/`), core passes all `rv32` tests (riscv-compliance v2.1) | |
| 26.12.2020 | 1.4.9.4 | removed `zicnt_en` option (was used to discard the standard RISC-V counters and timers from implementation); added missing `mcounteren` CSR (to allow read-access from user-level code to `cycle[h]` / `time[h]` / `[m]instret[h]` CSRs); available bits: 0: `CY`, 1: `TM`, 2: `IR`; added missing `mcountinhibit` CSR (to disable auto-increment of `[m]cycle[h]` / `[m]instret[h]` CSRs); available bits: 0: `CY`, 2: `IR` | |
| 25.12.2020 | 1.4.9.3 | Added missing `UBE` flag to `mstatus` CSR, indicates Endianness for load/stores in user mode (always set indicating BIG-endian mode), is a copy of `mstatush.mbe` | |
| 23.12.2020 | 1.4.9.2 | :sparkles: added processor-internal instruction cache `rtl/core/neorv32_cache.vhd` (direct mapped); new configuration generics: `ICACHE_USE` (implement cache), `ICACHE_BLOCK_SIZE` (cache block/page/line size), `ICACHE_NUM_BLOCKS` (number of cache blocks); added `SYSINFO_CACHE` register to SYSINFO to check cache configuration by software | |
| 20.12.2020 | 1.4.9.1 | :bug: fixed bug in CPU's instruction fetch engine (alignment_errros/bus_errors were not acknowledged correctly); added `BUS_TIMEOUT` generic to CPU (defines the amount of cycles after which an *unacknowledged* bus access will get terminated and raises a bus access fault exception) | |
| 19.12.2020 | [**:rocket:1.4.9.0**](https://github.com/stnolting/neorv32/releases/tag/v1.4.9.0) | Testbench: added memory-mapped triggers to trigger core's "machine software & external interrupts"; `sw/example/cpu_test`: removed CFU tests, added `MEI` and `MSI` tests; added **RISC-V-Compliance Test Framework** to repository (`riscv-compliance/`), core passes all `rv32` tests (riscv-compliance v2.1) | |
| 18.12.2020 | 1.4.8.13 | Added additional simulation files: simulation-optimized IMEM-ROM (so far, this is only relevant for the *new* NEORV32 RISC-V Compliance test framework v2.0); **:sparkles: Processor now passes all `rv32` tests of the new [RISC-V Compliance Test Framework v2.0](https://github.com/riscv/riscv-compliance/releases/tag/v2.0) :sparkles:** | |
| 16.12.2020 | 1.4.8.12 | :warning: fixed (another) bug in `mtval` CSR generation (wrong value for "breakpoint" trap); updated `mtval` value table in data sheet; fixed bug in load/store operation (intoroduced in version 1.4.8.10) | |
| 16.12.2020 | 1.4.8.11 | :warning: fixed bug in `mtval` CSR generation (wrong values for some traps); fixed bug in `mip` CSR (writing zero to implemented bits now actually clears pending interrupts); fixed bug in IRQ priority encoding (machine software interrupt `MSI` comes before machine timer interrupt `MTI`) | |
/README.md
44,7 → 44,7
* `Zifencei` - instruction stream synchronization |
* `PMP` - physical memory protection |
* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules |
* optional embedded memories (instructions/data/bootloader, RAM/ROM) |
* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches |
* timers (watch dog, RISC-V-compliant machine timer) |
* serial interfaces (SPI, TWI, UART) and general purpose IO |
* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity)) |
93,7 → 93,8
|
* Use LaTeX for data sheet |
* Further size and performance optimization *(work in progress)* |
* A cache for the external memory/bus interface *(work in progress)* |
* Add associativity configuration for instruction cache |
* Add a data cache |
* Burst mode for the external memory/bus interface |
* RISC-V `B` extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) *(shelved)* |
* Synthesis results (+ wrappers?) for more/specific platforms |
120,8 → 121,8
The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup |
is highly customizable via the processor's top generics and already provides the following *optional* modules: |
|
* processor-internal data and instruction memories (**DMEM** / **IMEM**) |
* internal **Bootloader** with UART console and automatic application boot from SPI flash option |
* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**) |
* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option |
* machine system timer (**MTIME**), RISC-V-compliant |
* watchdog timer (**WDT**) |
* universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io |
188,7 → 189,7
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI` |
* System instructions: `MRET` `WFI` |
* Pseudo-instructions are not listed |
* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth` |
* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth` `mcounteren` `mcountinhibit` |
* Machine CSRs: `mstatus` `mstatush` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom) |
* Supported exceptions and interrupts: |
* Misaligned instruction address |
210,7 → 211,7
* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode) |
|
**Privileged architecture / instruction stream synchronization** (`Zifencei` extension): |
* System instructions: `FENCE.I` |
* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache) |
|
**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension): |
* Additional machine CSRs: `pmpcfg0` `pmpcfg1` `pmpaddr0` `pmpaddr1` `pmpaddr2` `pmpaddr3` `pmpaddr4` `pmpaddr5` `pmpaddr6` `pmpaddr7` |
245,7 → 246,7
of the CPU's generics is assumed (for example no PMP). No constraints were used at all. The `u` and `Zifencei` extensions have |
a negligible impact on the hardware requirements. |
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md). |
Results generated for hardware version [`1.4.9.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md). |
|
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max | |
|:----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:| |
260,12 → 261,13
|
### NEORV32 Processor-Internal Peripherals and Memories |
|
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md). |
Results generated for hardware version [`1.4.9.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md). |
|
| Module | Description | LEs | FFs | Memory bits | DSPs | |
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:| |
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 | |
| BUSSWITCH | Mux for CPU I & D interfaces | 65 | 8 | 0 | 0 | |
| iCACHE | Proc.-int. nstruction cache (default 1x4x54 bytes) | 234 | 156 | 8 192 | 0 | |
| CFU0 | Custom functions unit 0 | - | - | - | - | |
| CFU1 | Custom functions unit 1 | - | - | - | - | |
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 | |
319,7 → 321,7
|
~~~ |
**Configuration** |
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock |
Hardware: 32kB IMEM, 16kB DMEM, no caches, 100MHz clock |
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK |
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain) |
Compiler flags: default, see makefile |