OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk
    from Rev 41 to Rev 42
    ↔ Reverse comparison
  •

Rev 41 → Rev 42

/docs/figures/neorv32_processor.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/docs/NEORV32.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/riscv-compliance/port-neorv32/framework_v2.0/riscv-target/neorv32/README.md
8,7 → 8,7
* enable/disable the required `CPU_EXTENSION_RISCV_xxx` VHDL configuration generics in the testbench (`neorv32/sim/neorv32_tb.vhd`)
* configure the processor memory configuration (use internal IMEM, IMEM as ROM, IMEM size of 2MB)
* compile test code and install application image to processor's `rtl/core` folder
* compilation uses the `link.imem_rom.ld` linker script as default; code (the test code) is executed from IMEM (which is read-only); data including signatureis stored to DMEM (RAM)
* compilation uses the `link.imem_rom.ld` linker script as default; code (the test code) is executed from IMEM (which is read-only); data including signature is stored to DMEM (RAM)
* certain areas in the DMEM are initialized using port code in `model_test.h` (`RVTEST` = 0xbabecafe and `SIGNATURE` = 0xdeadbeef); can be disabled using `RISCV_TARGET_FLAGS=-DNEORV32_NO_DATA_INIT`
* `sed` command is used to modify the default application image that is generated during compilation (`neorv32/rtl/core/neorv32_application_image.vhd`):
* the array size of the application image is set to 2MB
/riscv-compliance/README.md
36,7 → 36,8
* Copy the `rtl`, `sim` and `sw` folders of the NEORV32 into `work/neorv32/` to keep the project's core files clean
* Clone (if not already there) the [riscv-compliance repository](https://github.com/riscv/riscv-compliance) into `work/`
* Install (copy) the custom `neorv32` test target from the ``port-neorv32/framework_v2.0/riscv-target` folder to the compliance test suite's target folder
* Replace the original IMEM VHDL source file of the processor (in `work/neorv32`) by the simulation-only file (`neorv32/sim/rtl_modules/neorv32_imem.vhd` to allow faster simulation)
* Replace the original DMEM VHDL source file of the processor (in `work/neorv32/rtl/core/neorv32_dmem.vhd`) by the simulation-optimized file (`neorv32/sim/rtl_modules/neorv32_dmem.vhd` to allow faster simulation)
* Make a copy of the original IMEM VHDL source file of the processor (in `work/neorv32/rtl/core/neorv32_imem.vhd`) by the simulation-optimized file (`work/neorv32/rtl/core/neorv32_imem.ORIGINAL`); the original IMEM will be overriden by the device makefiles with a simulation-optimized one (`neorv32/sim/rtl_modules/neorv32_imem.vhd`); the original IMEM is required for certain tests that use self-modifying code
* Run the actual compliance tests
 
More datails regarding the actual simulation process can be found in the [target's
/riscv-compliance/run_compliance_test.sh
48,9 → 48,16
echo "--------------------------------------------------------------------------"
cp -rf port-neorv32/framework_v2.0/riscv-target/neorv32 work/riscv-compliance/riscv-target/.
 
# Use simulation-optimized DMEM
echo ""
echo ">>> Replacing default DMEM *vhd file with simulation-optimized one..."
echo ""
rm -rf work/neorv32/rtl/core/neorv32_dmem.vhd
cp work/neorv32/sim/rtl_modules/neorv32_dmem.vhd work/neorv32/rtl/core/.
 
# Make a local copy of the original IMEM rtl file
echo ""
echo ">>> Making local backup if original IMEM rtl file (work/neorv32/rtl/core/neorv32_imem.vhd)..."
echo ">>> Making local backup if original IMEM rtl file (work/neorv32/rtl/core/neorv32_imem.ORIGINAL)..."
echo ""
cp work/neorv32/rtl/core/neorv32_imem.vhd work/neorv32/rtl/core/neorv32_imem.ORIGINAL
 
/rtl/core/neorv32_application_image.vhd
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 804) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 807) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
60,7 → 60,7
00000049 => x"00158593",
00000050 => x"ff5ff06f",
00000051 => x"00001597",
00000052 => x"bc458593",
00000052 => x"bd058593",
00000053 => x"80000617",
00000054 => x"f2c60613",
00000055 => x"80000697",
107,38 → 107,38
00000096 => x"30200073",
00000097 => x"00005537",
00000098 => x"ff010113",
00000099 => x"00000613",
00000100 => x"00000593",
00000101 => x"b0050513",
00000102 => x"00112623",
00000103 => x"4a8000ef",
00000104 => x"598000ef",
00000105 => x"00050c63",
00000106 => x"440000ef",
00000107 => x"00001537",
00000108 => x"97850513",
00000109 => x"52c000ef",
00000110 => x"020000ef",
00000111 => x"00001537",
00000112 => x"95450513",
00000113 => x"51c000ef",
00000114 => x"00c12083",
00000115 => x"00000513",
00000116 => x"01010113",
00000117 => x"00008067",
00000118 => x"ff010113",
00000119 => x"00000513",
00000120 => x"00812423",
00000121 => x"00112623",
00000122 => x"00000413",
00000123 => x"55c000ef",
00000124 => x"0ff47513",
00000125 => x"554000ef",
00000126 => x"0c800513",
00000127 => x"580000ef",
00000128 => x"00140413",
00000129 => x"fedff06f",
00000130 => x"00000000",
00000099 => x"00000693",
00000100 => x"00000613",
00000101 => x"00000593",
00000102 => x"b0050513",
00000103 => x"00112623",
00000104 => x"4a4000ef",
00000105 => x"5a0000ef",
00000106 => x"00050c63",
00000107 => x"43c000ef",
00000108 => x"00001537",
00000109 => x"98450513",
00000110 => x"534000ef",
00000111 => x"020000ef",
00000112 => x"00001537",
00000113 => x"96050513",
00000114 => x"524000ef",
00000115 => x"00c12083",
00000116 => x"00000513",
00000117 => x"01010113",
00000118 => x"00008067",
00000119 => x"ff010113",
00000120 => x"00000513",
00000121 => x"00812423",
00000122 => x"00112623",
00000123 => x"00000413",
00000124 => x"564000ef",
00000125 => x"0ff47513",
00000126 => x"55c000ef",
00000127 => x"0c800513",
00000128 => x"588000ef",
00000129 => x"00140413",
00000130 => x"fedff06f",
00000131 => x"00000000",
00000132 => x"fc010113",
00000133 => x"02112e23",
192,7 → 192,7
00000181 => x"30200073",
00000182 => x"00001737",
00000183 => x"00279793",
00000184 => x"99470713",
00000184 => x"9a070713",
00000185 => x"00e787b3",
00000186 => x"0007a783",
00000187 => x"00078067",
203,7 → 203,7
00000192 => x"f8f764e3",
00000193 => x"00001737",
00000194 => x"00279793",
00000195 => x"9c470713",
00000195 => x"9d070713",
00000196 => x"00e787b3",
00000197 => x"0007a783",
00000198 => x"00078067",
252,14 → 252,14
00000241 => x"00050913",
00000242 => x"00001537",
00000243 => x"00912a23",
00000244 => x"a0850513",
00000244 => x"a1450513",
00000245 => x"000014b7",
00000246 => x"00812c23",
00000247 => x"01312623",
00000248 => x"00112e23",
00000249 => x"01c00413",
00000250 => x"2f8000ef",
00000251 => x"c8048493",
00000250 => x"304000ef",
00000251 => x"c8c48493",
00000252 => x"ffc00993",
00000253 => x"008957b3",
00000254 => x"00f7f793",
266,7 → 266,7
00000255 => x"00f487b3",
00000256 => x"0007c503",
00000257 => x"ffc40413",
00000258 => x"2c8000ef",
00000258 => x"2d4000ef",
00000259 => x"ff3414e3",
00000260 => x"01c12083",
00000261 => x"01812403",
277,10 → 277,10
00000266 => x"00008067",
00000267 => x"00001537",
00000268 => x"ff010113",
00000269 => x"a0c50513",
00000269 => x"a1850513",
00000270 => x"00112623",
00000271 => x"00812423",
00000272 => x"2a0000ef",
00000272 => x"2ac000ef",
00000273 => x"34202473",
00000274 => x"00b00793",
00000275 => x"0487f463",
290,89 → 290,89
00000279 => x"01000713",
00000280 => x"00f77e63",
00000281 => x"00001537",
00000282 => x"bac50513",
00000283 => x"274000ef",
00000282 => x"bb850513",
00000283 => x"280000ef",
00000284 => x"00040513",
00000285 => x"f49ff0ef",
00000286 => x"0400006f",
00000287 => x"00001737",
00000288 => x"00279793",
00000289 => x"bd870713",
00000289 => x"be470713",
00000290 => x"00e787b3",
00000291 => x"0007a783",
00000292 => x"00078067",
00000293 => x"00001737",
00000294 => x"00241793",
00000295 => x"c1c70713",
00000295 => x"c2870713",
00000296 => x"00e787b3",
00000297 => x"0007a783",
00000298 => x"00078067",
00000299 => x"00001537",
00000300 => x"a1450513",
00000301 => x"22c000ef",
00000300 => x"a2050513",
00000301 => x"238000ef",
00000302 => x"00001537",
00000303 => x"bc450513",
00000304 => x"220000ef",
00000303 => x"bd050513",
00000304 => x"22c000ef",
00000305 => x"34002573",
00000306 => x"ef5ff0ef",
00000307 => x"00001537",
00000308 => x"bcc50513",
00000309 => x"20c000ef",
00000308 => x"bd850513",
00000309 => x"218000ef",
00000310 => x"34302573",
00000311 => x"ee1ff0ef",
00000312 => x"00812403",
00000313 => x"00c12083",
00000314 => x"00001537",
00000315 => x"c7850513",
00000315 => x"c8450513",
00000316 => x"01010113",
00000317 => x"1ec0006f",
00000317 => x"1f80006f",
00000318 => x"00001537",
00000319 => x"a3450513",
00000319 => x"a4050513",
00000320 => x"fb5ff06f",
00000321 => x"00001537",
00000322 => x"a5050513",
00000322 => x"a5c50513",
00000323 => x"fa9ff06f",
00000324 => x"00001537",
00000325 => x"a6450513",
00000325 => x"a7050513",
00000326 => x"f9dff06f",
00000327 => x"00001537",
00000328 => x"a7050513",
00000328 => x"a7c50513",
00000329 => x"f91ff06f",
00000330 => x"00001537",
00000331 => x"a8850513",
00000331 => x"a9450513",
00000332 => x"f85ff06f",
00000333 => x"00001537",
00000334 => x"a9c50513",
00000334 => x"aa850513",
00000335 => x"f79ff06f",
00000336 => x"00001537",
00000337 => x"ab850513",
00000337 => x"ac450513",
00000338 => x"f6dff06f",
00000339 => x"00001537",
00000340 => x"acc50513",
00000340 => x"ad850513",
00000341 => x"f61ff06f",
00000342 => x"00001537",
00000343 => x"aec50513",
00000343 => x"af850513",
00000344 => x"f55ff06f",
00000345 => x"00001537",
00000346 => x"b0c50513",
00000346 => x"b1850513",
00000347 => x"f49ff06f",
00000348 => x"00001537",
00000349 => x"b2850513",
00000349 => x"b3450513",
00000350 => x"f3dff06f",
00000351 => x"00001537",
00000352 => x"b4050513",
00000352 => x"b4c50513",
00000353 => x"f31ff06f",
00000354 => x"00001537",
00000355 => x"b5c50513",
00000355 => x"b6850513",
00000356 => x"f25ff06f",
00000357 => x"00001537",
00000358 => x"b7050513",
00000358 => x"b7c50513",
00000359 => x"f19ff06f",
00000360 => x"00001537",
00000361 => x"b8450513",
00000361 => x"b9050513",
00000362 => x"f0dff06f",
00000363 => x"00001537",
00000364 => x"b9850513",
00000364 => x"ba450513",
00000365 => x"f01ff06f",
00000366 => x"01000793",
00000367 => x"02a7e263",
393,8 → 393,8
00000382 => x"301027f3",
00000383 => x"00079863",
00000384 => x"00001537",
00000385 => x"c4c50513",
00000386 => x"0d8000ef",
00000385 => x"c5850513",
00000386 => x"0e4000ef",
00000387 => x"21000793",
00000388 => x"30579073",
00000389 => x"00000413",
410,408 → 410,411
00000399 => x"01010113",
00000400 => x"00008067",
00000401 => x"fa002023",
00000402 => x"fe002683",
00000402 => x"fe002803",
00000403 => x"00151513",
00000404 => x"00000713",
00000405 => x"04a6f263",
00000406 => x"000016b7",
00000405 => x"04a87863",
00000406 => x"00001537",
00000407 => x"00000793",
00000408 => x"ffe68693",
00000409 => x"04e6e463",
00000410 => x"00167613",
00000411 => x"0015f593",
00000408 => x"ffe50513",
00000409 => x"04e56a63",
00000410 => x"0016f693",
00000411 => x"00167613",
00000412 => x"01879793",
00000413 => x"01e61613",
00000414 => x"00c7e7b3",
00000415 => x"01d59593",
00000416 => x"00b7e7b3",
00000417 => x"00e7e7b3",
00000418 => x"10000737",
00000419 => x"00e7e7b3",
00000420 => x"faf02023",
00000421 => x"00008067",
00000422 => x"00170793",
00000423 => x"01079713",
00000424 => x"40a686b3",
00000425 => x"01075713",
00000426 => x"fadff06f",
00000427 => x"ffe78513",
00000428 => x"0fd57513",
00000429 => x"00051a63",
00000430 => x"00375713",
00000431 => x"00178793",
00000432 => x"0ff7f793",
00000433 => x"fa1ff06f",
00000434 => x"00175713",
00000435 => x"ff1ff06f",
00000436 => x"fa002783",
00000437 => x"fe07cee3",
00000438 => x"faa02223",
00000439 => x"00008067",
00000440 => x"ff010113",
00000441 => x"00812423",
00000442 => x"01212023",
00000443 => x"00112623",
00000444 => x"00912223",
00000445 => x"00050413",
00000446 => x"00a00913",
00000447 => x"00044483",
00000448 => x"00140413",
00000449 => x"00049e63",
00000450 => x"00c12083",
00000451 => x"00812403",
00000452 => x"00412483",
00000453 => x"00012903",
00000454 => x"01010113",
00000455 => x"00008067",
00000456 => x"01249663",
00000457 => x"00d00513",
00000458 => x"fa9ff0ef",
00000459 => x"00048513",
00000460 => x"fa1ff0ef",
00000461 => x"fc9ff06f",
00000462 => x"fe802503",
00000463 => x"01055513",
00000464 => x"00157513",
00000465 => x"00008067",
00000466 => x"f8a02223",
00000467 => x"00008067",
00000468 => x"ff010113",
00000469 => x"c80026f3",
00000470 => x"c0002773",
00000471 => x"c80027f3",
00000472 => x"fed79ae3",
00000473 => x"00e12023",
00000474 => x"00f12223",
00000475 => x"00012503",
00000476 => x"00412583",
00000477 => x"01010113",
00000478 => x"00008067",
00000479 => x"fe010113",
00000480 => x"00112e23",
00000481 => x"00812c23",
00000482 => x"00912a23",
00000483 => x"00a12623",
00000484 => x"fc1ff0ef",
00000485 => x"00050493",
00000486 => x"fe002503",
00000487 => x"00058413",
00000488 => x"3e800593",
00000489 => x"104000ef",
00000490 => x"00c12603",
00000491 => x"00000693",
00000492 => x"00000593",
00000493 => x"05c000ef",
00000494 => x"009504b3",
00000495 => x"00a4b533",
00000496 => x"00858433",
00000497 => x"00850433",
00000498 => x"f89ff0ef",
00000499 => x"fe85eee3",
00000500 => x"00b41463",
00000501 => x"fe956ae3",
00000502 => x"01c12083",
00000503 => x"01812403",
00000504 => x"01412483",
00000505 => x"02010113",
00000506 => x"00008067",
00000507 => x"00050613",
00000508 => x"00000513",
00000509 => x"0015f693",
00000510 => x"00068463",
00000511 => x"00c50533",
00000512 => x"0015d593",
00000513 => x"00161613",
00000514 => x"fe0596e3",
00000515 => x"00008067",
00000516 => x"00050313",
00000517 => x"ff010113",
00000518 => x"00060513",
00000519 => x"00068893",
00000520 => x"00112623",
00000521 => x"00030613",
00000522 => x"00050693",
00000523 => x"00000713",
00000524 => x"00000793",
00000525 => x"00000813",
00000526 => x"0016fe13",
00000527 => x"00171e93",
00000528 => x"000e0c63",
00000529 => x"01060e33",
00000530 => x"010e3833",
00000531 => x"00e787b3",
00000532 => x"00f807b3",
00000533 => x"000e0813",
00000534 => x"01f65713",
00000535 => x"0016d693",
00000536 => x"00eee733",
00000537 => x"00161613",
00000538 => x"fc0698e3",
00000539 => x"00058663",
00000540 => x"f7dff0ef",
00000541 => x"00a787b3",
00000542 => x"00088a63",
00000543 => x"00030513",
00000544 => x"00088593",
00000545 => x"f69ff0ef",
00000546 => x"00f507b3",
00000547 => x"00c12083",
00000548 => x"00080513",
00000549 => x"00078593",
00000550 => x"01010113",
00000551 => x"00008067",
00000552 => x"06054063",
00000553 => x"0605c663",
00000554 => x"00058613",
00000555 => x"00050593",
00000556 => x"fff00513",
00000557 => x"02060c63",
00000558 => x"00100693",
00000559 => x"00b67a63",
00000560 => x"00c05863",
00000561 => x"00161613",
00000562 => x"00169693",
00000563 => x"feb66ae3",
00000564 => x"00000513",
00000565 => x"00c5e663",
00000566 => x"40c585b3",
00000567 => x"00d56533",
00000568 => x"0016d693",
00000569 => x"00165613",
00000570 => x"fe0696e3",
00000571 => x"00008067",
00000572 => x"00008293",
00000573 => x"fb5ff0ef",
00000574 => x"00058513",
00000575 => x"00028067",
00000576 => x"40a00533",
00000577 => x"00b04863",
00000578 => x"40b005b3",
00000579 => x"f9dff06f",
00000580 => x"40b005b3",
00000581 => x"00008293",
00000582 => x"f91ff0ef",
00000583 => x"40a00533",
00000584 => x"00028067",
00000585 => x"00008293",
00000586 => x"0005ca63",
00000587 => x"00054c63",
00000588 => x"f79ff0ef",
00000589 => x"00058513",
00000590 => x"00028067",
00000591 => x"40b005b3",
00000592 => x"fe0558e3",
00000593 => x"40a00533",
00000594 => x"f61ff0ef",
00000595 => x"40b00533",
00000596 => x"00028067",
00000597 => x"6f727245",
00000598 => x"4e202172",
00000599 => x"5047206f",
00000600 => x"75204f49",
00000601 => x"2074696e",
00000602 => x"746e7973",
00000603 => x"69736568",
00000604 => x"2164657a",
00000605 => x"0000000a",
00000606 => x"6e696c42",
00000607 => x"676e696b",
00000608 => x"44454c20",
00000609 => x"6d656420",
00000610 => x"7270206f",
00000611 => x"6172676f",
00000612 => x"00000a6d",
00000613 => x"0000031c",
00000614 => x"00000328",
00000615 => x"00000334",
00000616 => x"00000340",
00000617 => x"0000034c",
00000618 => x"00000354",
00000619 => x"0000035c",
00000620 => x"00000364",
00000621 => x"0000036c",
00000622 => x"00000288",
00000623 => x"00000288",
00000624 => x"00000374",
00000625 => x"0000037c",
00000413 => x"01e69693",
00000414 => x"0035f593",
00000415 => x"00d7e7b3",
00000416 => x"01d61613",
00000417 => x"00c7e7b3",
00000418 => x"01659593",
00000419 => x"00b7e7b3",
00000420 => x"00e7e7b3",
00000421 => x"10000737",
00000422 => x"00e7e7b3",
00000423 => x"faf02023",
00000424 => x"00008067",
00000425 => x"00170793",
00000426 => x"01079713",
00000427 => x"40a80833",
00000428 => x"01075713",
00000429 => x"fa1ff06f",
00000430 => x"ffe78813",
00000431 => x"0fd87813",
00000432 => x"00081a63",
00000433 => x"00375713",
00000434 => x"00178793",
00000435 => x"0ff7f793",
00000436 => x"f95ff06f",
00000437 => x"00175713",
00000438 => x"ff1ff06f",
00000439 => x"fa002783",
00000440 => x"fe07cee3",
00000441 => x"faa02223",
00000442 => x"00008067",
00000443 => x"ff010113",
00000444 => x"00812423",
00000445 => x"01212023",
00000446 => x"00112623",
00000447 => x"00912223",
00000448 => x"00050413",
00000449 => x"00a00913",
00000450 => x"00044483",
00000451 => x"00140413",
00000452 => x"00049e63",
00000453 => x"00c12083",
00000454 => x"00812403",
00000455 => x"00412483",
00000456 => x"00012903",
00000457 => x"01010113",
00000458 => x"00008067",
00000459 => x"01249663",
00000460 => x"00d00513",
00000461 => x"fa9ff0ef",
00000462 => x"00048513",
00000463 => x"fa1ff0ef",
00000464 => x"fc9ff06f",
00000465 => x"fe802503",
00000466 => x"01055513",
00000467 => x"00157513",
00000468 => x"00008067",
00000469 => x"f8a02223",
00000470 => x"00008067",
00000471 => x"ff010113",
00000472 => x"c80026f3",
00000473 => x"c0002773",
00000474 => x"c80027f3",
00000475 => x"fed79ae3",
00000476 => x"00e12023",
00000477 => x"00f12223",
00000478 => x"00012503",
00000479 => x"00412583",
00000480 => x"01010113",
00000481 => x"00008067",
00000482 => x"fe010113",
00000483 => x"00112e23",
00000484 => x"00812c23",
00000485 => x"00912a23",
00000486 => x"00a12623",
00000487 => x"fc1ff0ef",
00000488 => x"00050493",
00000489 => x"fe002503",
00000490 => x"00058413",
00000491 => x"3e800593",
00000492 => x"104000ef",
00000493 => x"00c12603",
00000494 => x"00000693",
00000495 => x"00000593",
00000496 => x"05c000ef",
00000497 => x"009504b3",
00000498 => x"00a4b533",
00000499 => x"00858433",
00000500 => x"00850433",
00000501 => x"f89ff0ef",
00000502 => x"fe85eee3",
00000503 => x"00b41463",
00000504 => x"fe956ae3",
00000505 => x"01c12083",
00000506 => x"01812403",
00000507 => x"01412483",
00000508 => x"02010113",
00000509 => x"00008067",
00000510 => x"00050613",
00000511 => x"00000513",
00000512 => x"0015f693",
00000513 => x"00068463",
00000514 => x"00c50533",
00000515 => x"0015d593",
00000516 => x"00161613",
00000517 => x"fe0596e3",
00000518 => x"00008067",
00000519 => x"00050313",
00000520 => x"ff010113",
00000521 => x"00060513",
00000522 => x"00068893",
00000523 => x"00112623",
00000524 => x"00030613",
00000525 => x"00050693",
00000526 => x"00000713",
00000527 => x"00000793",
00000528 => x"00000813",
00000529 => x"0016fe13",
00000530 => x"00171e93",
00000531 => x"000e0c63",
00000532 => x"01060e33",
00000533 => x"010e3833",
00000534 => x"00e787b3",
00000535 => x"00f807b3",
00000536 => x"000e0813",
00000537 => x"01f65713",
00000538 => x"0016d693",
00000539 => x"00eee733",
00000540 => x"00161613",
00000541 => x"fc0698e3",
00000542 => x"00058663",
00000543 => x"f7dff0ef",
00000544 => x"00a787b3",
00000545 => x"00088a63",
00000546 => x"00030513",
00000547 => x"00088593",
00000548 => x"f69ff0ef",
00000549 => x"00f507b3",
00000550 => x"00c12083",
00000551 => x"00080513",
00000552 => x"00078593",
00000553 => x"01010113",
00000554 => x"00008067",
00000555 => x"06054063",
00000556 => x"0605c663",
00000557 => x"00058613",
00000558 => x"00050593",
00000559 => x"fff00513",
00000560 => x"02060c63",
00000561 => x"00100693",
00000562 => x"00b67a63",
00000563 => x"00c05863",
00000564 => x"00161613",
00000565 => x"00169693",
00000566 => x"feb66ae3",
00000567 => x"00000513",
00000568 => x"00c5e663",
00000569 => x"40c585b3",
00000570 => x"00d56533",
00000571 => x"0016d693",
00000572 => x"00165613",
00000573 => x"fe0696e3",
00000574 => x"00008067",
00000575 => x"00008293",
00000576 => x"fb5ff0ef",
00000577 => x"00058513",
00000578 => x"00028067",
00000579 => x"40a00533",
00000580 => x"00b04863",
00000581 => x"40b005b3",
00000582 => x"f9dff06f",
00000583 => x"40b005b3",
00000584 => x"00008293",
00000585 => x"f91ff0ef",
00000586 => x"40a00533",
00000587 => x"00028067",
00000588 => x"00008293",
00000589 => x"0005ca63",
00000590 => x"00054c63",
00000591 => x"f79ff0ef",
00000592 => x"00058513",
00000593 => x"00028067",
00000594 => x"40b005b3",
00000595 => x"fe0558e3",
00000596 => x"40a00533",
00000597 => x"f61ff0ef",
00000598 => x"40b00533",
00000599 => x"00028067",
00000600 => x"6f727245",
00000601 => x"4e202172",
00000602 => x"5047206f",
00000603 => x"75204f49",
00000604 => x"2074696e",
00000605 => x"746e7973",
00000606 => x"69736568",
00000607 => x"2164657a",
00000608 => x"0000000a",
00000609 => x"6e696c42",
00000610 => x"676e696b",
00000611 => x"44454c20",
00000612 => x"6d656420",
00000613 => x"7270206f",
00000614 => x"6172676f",
00000615 => x"00000a6d",
00000616 => x"0000031c",
00000617 => x"00000328",
00000618 => x"00000334",
00000619 => x"00000340",
00000620 => x"0000034c",
00000621 => x"00000354",
00000622 => x"0000035c",
00000623 => x"00000364",
00000624 => x"0000036c",
00000625 => x"00000288",
00000626 => x"00000288",
00000627 => x"00000288",
00000628 => x"00000288",
00000629 => x"00000384",
00000627 => x"00000374",
00000628 => x"0000037c",
00000629 => x"00000288",
00000630 => x"00000288",
00000631 => x"00000288",
00000632 => x"00000288",
00000633 => x"0000038c",
00000632 => x"00000384",
00000633 => x"00000288",
00000634 => x"00000288",
00000635 => x"00000288",
00000636 => x"00000288",
00000636 => x"0000038c",
00000637 => x"00000288",
00000638 => x"00000394",
00000639 => x"0000039c",
00000640 => x"000003a4",
00000641 => x"000003ac",
00000642 => x"00007830",
00000643 => x"4554523c",
00000644 => x"0000203e",
00000645 => x"74736e49",
00000646 => x"74637572",
00000647 => x"206e6f69",
00000648 => x"72646461",
00000649 => x"20737365",
00000650 => x"6173696d",
00000651 => x"6e67696c",
00000652 => x"00006465",
00000653 => x"74736e49",
00000654 => x"74637572",
00000655 => x"206e6f69",
00000656 => x"65636361",
00000657 => x"66207373",
00000658 => x"746c7561",
00000659 => x"00000000",
00000660 => x"656c6c49",
00000661 => x"206c6167",
00000662 => x"74736e69",
00000663 => x"74637572",
00000664 => x"006e6f69",
00000665 => x"61657242",
00000666 => x"696f706b",
00000667 => x"0000746e",
00000668 => x"64616f4c",
00000669 => x"64646120",
00000670 => x"73736572",
00000671 => x"73696d20",
00000672 => x"67696c61",
00000673 => x"0064656e",
00000674 => x"64616f4c",
00000675 => x"63636120",
00000676 => x"20737365",
00000677 => x"6c756166",
00000678 => x"00000074",
00000679 => x"726f7453",
00000680 => x"64612065",
00000681 => x"73657264",
00000682 => x"696d2073",
00000683 => x"696c6173",
00000684 => x"64656e67",
00000685 => x"00000000",
00000686 => x"726f7453",
00000687 => x"63612065",
00000688 => x"73736563",
00000689 => x"75616620",
00000690 => x"0000746c",
00000691 => x"69766e45",
00000692 => x"6d6e6f72",
00000693 => x"20746e65",
00000694 => x"6c6c6163",
00000695 => x"6f726620",
00000696 => x"2d55206d",
00000697 => x"65646f6d",
00000698 => x"00000000",
00000699 => x"69766e45",
00000700 => x"6d6e6f72",
00000701 => x"20746e65",
00000702 => x"6c6c6163",
00000703 => x"6f726620",
00000704 => x"2d4d206d",
00000705 => x"65646f6d",
00000706 => x"00000000",
00000707 => x"6863614d",
00000708 => x"20656e69",
00000709 => x"74666f73",
00000710 => x"65726177",
00000711 => x"746e6920",
00000712 => x"75727265",
00000713 => x"00007470",
00000714 => x"6863614d",
00000715 => x"20656e69",
00000716 => x"656d6974",
00000717 => x"6e692072",
00000718 => x"72726574",
00000719 => x"00747075",
00000720 => x"6863614d",
00000721 => x"20656e69",
00000722 => x"65747865",
00000723 => x"6c616e72",
00000724 => x"746e6920",
00000725 => x"75727265",
00000726 => x"00007470",
00000727 => x"74736146",
00000728 => x"746e6920",
00000729 => x"75727265",
00000730 => x"30207470",
00000731 => x"00000000",
00000732 => x"74736146",
00000733 => x"746e6920",
00000734 => x"75727265",
00000735 => x"31207470",
00000736 => x"00000000",
00000737 => x"74736146",
00000738 => x"746e6920",
00000739 => x"75727265",
00000740 => x"32207470",
00000741 => x"00000000",
00000742 => x"74736146",
00000743 => x"746e6920",
00000744 => x"75727265",
00000745 => x"33207470",
00000746 => x"00000000",
00000747 => x"6e6b6e55",
00000748 => x"206e776f",
00000749 => x"70617274",
00000750 => x"75616320",
00000751 => x"203a6573",
00000752 => x"00000000",
00000753 => x"50204020",
00000754 => x"00003d43",
00000755 => x"544d202c",
00000756 => x"3d4c4156",
00000757 => x"00000000",
00000758 => x"00000564",
00000759 => x"00000464",
00000760 => x"00000464",
00000761 => x"00000464",
00000762 => x"00000570",
00000638 => x"00000288",
00000639 => x"00000288",
00000640 => x"00000288",
00000641 => x"00000394",
00000642 => x"0000039c",
00000643 => x"000003a4",
00000644 => x"000003ac",
00000645 => x"00007830",
00000646 => x"4554523c",
00000647 => x"0000203e",
00000648 => x"74736e49",
00000649 => x"74637572",
00000650 => x"206e6f69",
00000651 => x"72646461",
00000652 => x"20737365",
00000653 => x"6173696d",
00000654 => x"6e67696c",
00000655 => x"00006465",
00000656 => x"74736e49",
00000657 => x"74637572",
00000658 => x"206e6f69",
00000659 => x"65636361",
00000660 => x"66207373",
00000661 => x"746c7561",
00000662 => x"00000000",
00000663 => x"656c6c49",
00000664 => x"206c6167",
00000665 => x"74736e69",
00000666 => x"74637572",
00000667 => x"006e6f69",
00000668 => x"61657242",
00000669 => x"696f706b",
00000670 => x"0000746e",
00000671 => x"64616f4c",
00000672 => x"64646120",
00000673 => x"73736572",
00000674 => x"73696d20",
00000675 => x"67696c61",
00000676 => x"0064656e",
00000677 => x"64616f4c",
00000678 => x"63636120",
00000679 => x"20737365",
00000680 => x"6c756166",
00000681 => x"00000074",
00000682 => x"726f7453",
00000683 => x"64612065",
00000684 => x"73657264",
00000685 => x"696d2073",
00000686 => x"696c6173",
00000687 => x"64656e67",
00000688 => x"00000000",
00000689 => x"726f7453",
00000690 => x"63612065",
00000691 => x"73736563",
00000692 => x"75616620",
00000693 => x"0000746c",
00000694 => x"69766e45",
00000695 => x"6d6e6f72",
00000696 => x"20746e65",
00000697 => x"6c6c6163",
00000698 => x"6f726620",
00000699 => x"2d55206d",
00000700 => x"65646f6d",
00000701 => x"00000000",
00000702 => x"69766e45",
00000703 => x"6d6e6f72",
00000704 => x"20746e65",
00000705 => x"6c6c6163",
00000706 => x"6f726620",
00000707 => x"2d4d206d",
00000708 => x"65646f6d",
00000709 => x"00000000",
00000710 => x"6863614d",
00000711 => x"20656e69",
00000712 => x"74666f73",
00000713 => x"65726177",
00000714 => x"746e6920",
00000715 => x"75727265",
00000716 => x"00007470",
00000717 => x"6863614d",
00000718 => x"20656e69",
00000719 => x"656d6974",
00000720 => x"6e692072",
00000721 => x"72726574",
00000722 => x"00747075",
00000723 => x"6863614d",
00000724 => x"20656e69",
00000725 => x"65747865",
00000726 => x"6c616e72",
00000727 => x"746e6920",
00000728 => x"75727265",
00000729 => x"00007470",
00000730 => x"74736146",
00000731 => x"746e6920",
00000732 => x"75727265",
00000733 => x"30207470",
00000734 => x"00000000",
00000735 => x"74736146",
00000736 => x"746e6920",
00000737 => x"75727265",
00000738 => x"31207470",
00000739 => x"00000000",
00000740 => x"74736146",
00000741 => x"746e6920",
00000742 => x"75727265",
00000743 => x"32207470",
00000744 => x"00000000",
00000745 => x"74736146",
00000746 => x"746e6920",
00000747 => x"75727265",
00000748 => x"33207470",
00000749 => x"00000000",
00000750 => x"6e6b6e55",
00000751 => x"206e776f",
00000752 => x"70617274",
00000753 => x"75616320",
00000754 => x"203a6573",
00000755 => x"00000000",
00000756 => x"50204020",
00000757 => x"00003d43",
00000758 => x"544d202c",
00000759 => x"3d4c4156",
00000760 => x"00000000",
00000761 => x"00000564",
00000762 => x"00000464",
00000763 => x"00000464",
00000764 => x"00000464",
00000765 => x"00000464",
00000766 => x"0000057c",
00000765 => x"00000570",
00000766 => x"00000464",
00000767 => x"00000464",
00000768 => x"00000464",
00000769 => x"00000464",
00000769 => x"0000057c",
00000770 => x"00000464",
00000771 => x"00000588",
00000772 => x"00000594",
00000773 => x"000005a0",
00000774 => x"000005ac",
00000775 => x"000004ac",
00000776 => x"000004f8",
00000777 => x"00000504",
00000778 => x"00000510",
00000779 => x"0000051c",
00000780 => x"00000528",
00000781 => x"00000534",
00000782 => x"00000540",
00000783 => x"0000054c",
00000784 => x"00000464",
00000785 => x"00000464",
00000786 => x"00000558",
00000787 => x"4554523c",
00000788 => x"4157203e",
00000789 => x"4e494e52",
00000790 => x"43202147",
00000791 => x"43205550",
00000792 => x"73205253",
00000793 => x"65747379",
00000794 => x"6f6e206d",
00000795 => x"76612074",
00000796 => x"616c6961",
00000797 => x"21656c62",
00000798 => x"522f3c20",
00000799 => x"003e4554",
00000800 => x"33323130",
00000801 => x"37363534",
00000802 => x"42413938",
00000803 => x"46454443",
00000771 => x"00000464",
00000772 => x"00000464",
00000773 => x"00000464",
00000774 => x"00000588",
00000775 => x"00000594",
00000776 => x"000005a0",
00000777 => x"000005ac",
00000778 => x"000004ac",
00000779 => x"000004f8",
00000780 => x"00000504",
00000781 => x"00000510",
00000782 => x"0000051c",
00000783 => x"00000528",
00000784 => x"00000534",
00000785 => x"00000540",
00000786 => x"0000054c",
00000787 => x"00000464",
00000788 => x"00000464",
00000789 => x"00000558",
00000790 => x"4554523c",
00000791 => x"4157203e",
00000792 => x"4e494e52",
00000793 => x"43202147",
00000794 => x"43205550",
00000795 => x"73205253",
00000796 => x"65747379",
00000797 => x"6f6e206d",
00000798 => x"76612074",
00000799 => x"616c6961",
00000800 => x"21656c62",
00000801 => x"522f3c20",
00000802 => x"003e4554",
00000803 => x"33323130",
00000804 => x"37363534",
00000805 => x"42413938",
00000806 => x"46454443",
others => x"00000000"
);
 
/rtl/core/neorv32_bootloader_image.vhd
6,7 → 6,7
 
package neorv32_bootloader_image is
 
type bootloader_init_image_t is array (0 to 984) of std_ulogic_vector(31 downto 0);
type bootloader_init_image_t is array (0 to 988) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
44,7 → 44,7
00000033 => x"00158593",
00000034 => x"ff5ff06f",
00000035 => x"00001597",
00000036 => x"ed458593",
00000036 => x"ee458593",
00000037 => x"80010617",
00000038 => x"f6c60613",
00000039 => x"80010697",
103,7 → 103,7
00000092 => x"01612823",
00000093 => x"01712623",
00000094 => x"01812423",
00000095 => x"4c078793",
00000095 => x"4c478793",
00000096 => x"30579073",
00000097 => x"fe002403",
00000098 => x"026267b7",
114,884 → 114,888
00000103 => x"00200513",
00000104 => x"0087f463",
00000105 => x"00400513",
00000106 => x"2f5000ef",
00000106 => x"305000ef",
00000107 => x"00100513",
00000108 => x"3a1000ef",
00000108 => x"3b1000ef",
00000109 => x"00005537",
00000110 => x"00000613",
00000111 => x"00000593",
00000112 => x"b0050513",
00000113 => x"1c9000ef",
00000114 => x"181000ef",
00000115 => x"00245793",
00000116 => x"00a78533",
00000117 => x"00f537b3",
00000118 => x"00b785b3",
00000119 => x"199000ef",
00000120 => x"08000793",
00000121 => x"30479073",
00000122 => x"30046073",
00000123 => x"00000013",
00000110 => x"00000693",
00000111 => x"00000613",
00000112 => x"00000593",
00000113 => x"b0050513",
00000114 => x"1c9000ef",
00000115 => x"181000ef",
00000116 => x"00245793",
00000117 => x"00a78533",
00000118 => x"00f537b3",
00000119 => x"00b785b3",
00000120 => x"199000ef",
00000121 => x"08000793",
00000122 => x"30479073",
00000123 => x"30046073",
00000124 => x"00000013",
00000125 => x"ffff1537",
00000126 => x"e7c50513",
00000127 => x"249000ef",
00000128 => x"f1302573",
00000129 => x"24c000ef",
00000130 => x"ffff1537",
00000131 => x"eb450513",
00000132 => x"235000ef",
00000133 => x"fe002503",
00000134 => x"238000ef",
00000135 => x"ffff1537",
00000136 => x"ebc50513",
00000137 => x"221000ef",
00000138 => x"fe402503",
00000139 => x"224000ef",
00000140 => x"ffff1537",
00000141 => x"ec850513",
00000142 => x"20d000ef",
00000143 => x"30102573",
00000144 => x"210000ef",
00000145 => x"ffff1537",
00000146 => x"ed050513",
00000147 => x"1f9000ef",
00000148 => x"fe802503",
00000149 => x"ffff14b7",
00000150 => x"00341413",
00000151 => x"1f4000ef",
00000152 => x"ffff1537",
00000153 => x"ed850513",
00000154 => x"1dd000ef",
00000155 => x"ff802503",
00000156 => x"1e0000ef",
00000157 => x"ee048513",
00000158 => x"1cd000ef",
00000159 => x"ff002503",
00000160 => x"1d0000ef",
00000161 => x"ffff1537",
00000162 => x"eec50513",
00000163 => x"1b9000ef",
00000164 => x"ffc02503",
00000165 => x"1bc000ef",
00000166 => x"ee048513",
00000167 => x"1a9000ef",
00000168 => x"ff402503",
00000169 => x"1ac000ef",
00000170 => x"ffff1537",
00000171 => x"ef450513",
00000172 => x"195000ef",
00000173 => x"095000ef",
00000174 => x"00a404b3",
00000175 => x"0084b433",
00000176 => x"00b40433",
00000177 => x"fa402783",
00000178 => x"0207d263",
00000179 => x"ffff1537",
00000180 => x"f1c50513",
00000181 => x"171000ef",
00000182 => x"161000ef",
00000183 => x"02300793",
00000184 => x"02f51263",
00000185 => x"00000513",
00000186 => x"0180006f",
00000187 => x"05d000ef",
00000188 => x"fc85eae3",
00000189 => x"00b41463",
00000190 => x"fc9566e3",
00000191 => x"00100513",
00000192 => x"5b8000ef",
00000193 => x"0b4000ef",
00000194 => x"ffff1937",
00000195 => x"ffff19b7",
00000196 => x"02300a13",
00000197 => x"07200a93",
00000198 => x"06800b13",
00000199 => x"07500b93",
00000200 => x"ffff14b7",
00000201 => x"ffff1c37",
00000202 => x"f2890513",
00000203 => x"119000ef",
00000204 => x"0f9000ef",
00000205 => x"00050413",
00000206 => x"0e1000ef",
00000207 => x"e3498513",
00000208 => x"105000ef",
00000209 => x"fb4400e3",
00000210 => x"01541863",
00000211 => x"ffff02b7",
00000212 => x"00028067",
00000213 => x"fd5ff06f",
00000214 => x"01641663",
00000215 => x"05c000ef",
00000216 => x"fc9ff06f",
00000217 => x"00000513",
00000218 => x"03740063",
00000219 => x"07300793",
00000220 => x"00f41663",
00000221 => x"658000ef",
00000222 => x"fb1ff06f",
00000223 => x"06c00793",
00000224 => x"00f41863",
00000225 => x"00100513",
00000226 => x"3f4000ef",
00000227 => x"f9dff06f",
00000228 => x"06500793",
00000229 => x"00f41663",
00000230 => x"02c000ef",
00000231 => x"f8dff06f",
00000232 => x"03f00793",
00000233 => x"f30c0513",
00000234 => x"00f40463",
00000235 => x"f4448513",
00000236 => x"095000ef",
00000237 => x"f75ff06f",
00000238 => x"ffff1537",
00000239 => x"d5850513",
00000240 => x"0850006f",
00000241 => x"800007b7",
00000242 => x"0007a783",
00000243 => x"00079863",
00000244 => x"ffff1537",
00000245 => x"dbc50513",
00000246 => x"06d0006f",
00000247 => x"ff010113",
00000248 => x"00112623",
00000249 => x"30047073",
00000250 => x"00000013",
00000125 => x"00000013",
00000126 => x"ffff1537",
00000127 => x"e8c50513",
00000128 => x"255000ef",
00000129 => x"f1302573",
00000130 => x"24c000ef",
00000131 => x"ffff1537",
00000132 => x"ec450513",
00000133 => x"241000ef",
00000134 => x"fe002503",
00000135 => x"238000ef",
00000136 => x"ffff1537",
00000137 => x"ecc50513",
00000138 => x"22d000ef",
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00000893 => x"58450a0a",
00000894 => x"00282043",
00000895 => x"20402029",
00000896 => x"00007830",
00000897 => x"69617741",
00000898 => x"676e6974",
00000899 => x"6f656e20",
00000900 => x"32337672",
00000901 => x"6578655f",
00000902 => x"6e69622e",
00000903 => x"202e2e2e",
00000904 => x"00000000",
00000905 => x"64616f4c",
00000906 => x"2e676e69",
00000907 => x"00202e2e",
00000908 => x"00004b4f",
00000909 => x"0000000a",
00000910 => x"74697257",
00000911 => x"78302065",
00000912 => x"00000000",
00000913 => x"74796220",
00000914 => x"74207365",
00000915 => x"5053206f",
00000916 => x"6c662049",
00000917 => x"20687361",
00000918 => x"78302040",
00000919 => x"00000000",
00000920 => x"7928203f",
00000921 => x"20296e2f",
00000922 => x"00000000",
00000923 => x"616c460a",
00000924 => x"6e696873",
00000925 => x"2e2e2e67",
00000926 => x"00000020",
00000927 => x"0a0a0a0a",
00000928 => x"4e203c3c",
00000929 => x"56524f45",
00000930 => x"42203233",
00000931 => x"6c746f6f",
00000932 => x"6564616f",
00000933 => x"3e3e2072",
00000934 => x"4c420a0a",
00000935 => x"203a5644",
00000936 => x"20636544",
00000937 => x"32203632",
00000938 => x"0a303230",
00000939 => x"3a565748",
00000940 => x"00002020",
00000941 => x"4b4c430a",
00000942 => x"0020203a",
00000943 => x"0a7a4820",
00000944 => x"52455355",
00000945 => x"0000203a",
00000946 => x"53494d0a",
00000947 => x"00203a41",
00000948 => x"4f52500a",
00000949 => x"00203a43",
00000950 => x"454d490a",
00000951 => x"00203a4d",
00000952 => x"74796220",
00000953 => x"40207365",
00000954 => x"00000020",
00000955 => x"454d440a",
00000956 => x"00203a4d",
00000957 => x"75410a0a",
00000958 => x"6f626f74",
00000959 => x"6920746f",
00000960 => x"7338206e",
00000961 => x"7250202e",
00000962 => x"20737365",
00000963 => x"2079656b",
00000964 => x"61206f74",
00000965 => x"74726f62",
00000966 => x"00000a2e",
00000967 => x"726f6241",
00000968 => x"2e646574",
00000969 => x"00000a0a",
00000970 => x"444d430a",
00000971 => x"00203e3a",
00000972 => x"53207962",
00000973 => x"68706574",
00000974 => x"4e206e61",
00000975 => x"69746c6f",
00000976 => x"0000676e",
00000977 => x"61766e49",
00000978 => x"2064696c",
00000979 => x"00444d43",
00000980 => x"33323130",
00000981 => x"37363534",
00000982 => x"42413938",
00000983 => x"46454443",
00000890 => x"746f6f42",
00000891 => x"2e676e69",
00000892 => x"0a0a2e2e",
00000893 => x"00000000",
00000894 => x"52450a07",
00000895 => x"5f524f52",
00000896 => x"00000000",
00000897 => x"58450a0a",
00000898 => x"00282043",
00000899 => x"20402029",
00000900 => x"00007830",
00000901 => x"69617741",
00000902 => x"676e6974",
00000903 => x"6f656e20",
00000904 => x"32337672",
00000905 => x"6578655f",
00000906 => x"6e69622e",
00000907 => x"202e2e2e",
00000908 => x"00000000",
00000909 => x"64616f4c",
00000910 => x"2e676e69",
00000911 => x"00202e2e",
00000912 => x"00004b4f",
00000913 => x"0000000a",
00000914 => x"74697257",
00000915 => x"78302065",
00000916 => x"00000000",
00000917 => x"74796220",
00000918 => x"74207365",
00000919 => x"5053206f",
00000920 => x"6c662049",
00000921 => x"20687361",
00000922 => x"78302040",
00000923 => x"00000000",
00000924 => x"7928203f",
00000925 => x"20296e2f",
00000926 => x"00000000",
00000927 => x"616c460a",
00000928 => x"6e696873",
00000929 => x"2e2e2e67",
00000930 => x"00000020",
00000931 => x"0a0a0a0a",
00000932 => x"4e203c3c",
00000933 => x"56524f45",
00000934 => x"42203233",
00000935 => x"6c746f6f",
00000936 => x"6564616f",
00000937 => x"3e3e2072",
00000938 => x"4c420a0a",
00000939 => x"203a5644",
00000940 => x"20636544",
00000941 => x"32203932",
00000942 => x"0a303230",
00000943 => x"3a565748",
00000944 => x"00002020",
00000945 => x"4b4c430a",
00000946 => x"0020203a",
00000947 => x"0a7a4820",
00000948 => x"52455355",
00000949 => x"0000203a",
00000950 => x"53494d0a",
00000951 => x"00203a41",
00000952 => x"4f52500a",
00000953 => x"00203a43",
00000954 => x"454d490a",
00000955 => x"00203a4d",
00000956 => x"74796220",
00000957 => x"40207365",
00000958 => x"00000020",
00000959 => x"454d440a",
00000960 => x"00203a4d",
00000961 => x"75410a0a",
00000962 => x"6f626f74",
00000963 => x"6920746f",
00000964 => x"7338206e",
00000965 => x"7250202e",
00000966 => x"20737365",
00000967 => x"2079656b",
00000968 => x"61206f74",
00000969 => x"74726f62",
00000970 => x"00000a2e",
00000971 => x"726f6241",
00000972 => x"2e646574",
00000973 => x"00000a0a",
00000974 => x"444d430a",
00000975 => x"00203e3a",
00000976 => x"53207962",
00000977 => x"68706574",
00000978 => x"4e206e61",
00000979 => x"69746c6f",
00000980 => x"0000676e",
00000981 => x"61766e49",
00000982 => x"2064696c",
00000983 => x"00444d43",
00000984 => x"33323130",
00000985 => x"37363534",
00000986 => x"42413938",
00000987 => x"46454443",
others => x"00000000"
);
 
/rtl/core/neorv32_busswitch.vhd
6,7 → 6,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
90,25 → 90,16
 
architecture neorv32_busswitch_rtl of neorv32_busswitch is
 
-- access buffer --
signal ca_rd_req_buf : std_ulogic;
signal ca_wr_req_buf : std_ulogic;
signal cb_rd_req_buf : std_ulogic;
signal cb_wr_req_buf : std_ulogic;
 
-- access requests --
signal ca_req_current : std_ulogic;
signal cb_req_current : std_ulogic;
signal ca_req_buffered : std_ulogic;
signal cb_req_buffered : std_ulogic;
signal ca_rd_req_buf, ca_wr_req_buf : std_ulogic;
signal cb_rd_req_buf, cb_wr_req_buf : std_ulogic;
signal ca_req_current, ca_req_buffered : std_ulogic;
signal cb_req_current, cb_req_buffered : std_ulogic;
 
-- internal bus lines --
signal ca_bus_ack : std_ulogic;
signal cb_bus_ack : std_ulogic;
signal ca_bus_err : std_ulogic;
signal cb_bus_err : std_ulogic;
signal p_bus_we : std_ulogic;
signal p_bus_re : std_ulogic;
signal ca_bus_ack, cb_bus_ack : std_ulogic;
signal ca_bus_err, cb_bus_err : std_ulogic;
signal p_bus_we, p_bus_re : std_ulogic;
 
-- access arbiter --
type arbiter_state_t is (IDLE, BUSY, RETIRE, BUSY_SWITCHED, RETIRE_SWITCHED);
242,7 → 233,11
if (cb_bus_cancel_i = '1') or -- controller cancels access
(p_bus_err_i = '1') or -- peripheral cancels access
(p_bus_ack_i = '1') then -- normal termination
arbiter.state_nxt <= IDLE;
if (ca_req_buffered = '1') or (ca_req_current = '1') then -- any request from A?
arbiter.state_nxt <= RETIRE;
else
arbiter.state_nxt <= IDLE;
end if;
end if;
 
when RETIRE_SWITCHED => -- retire pending switched access
/rtl/core/neorv32_cpu.vhd
16,7 → 16,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
70,7 → 70,10
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false -- implement PMP?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29)
);
port (
-- global control --
157,7 → 160,9
-- U-extension requires Zicsr extension --
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
-- PMP requires Zicsr extension --
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires CPU_EXTENSION_RISCV_Zicsr extension." severity error;
-- HPM CNT requires Zicsr extension --
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG ERROR! Performance monitors (HMP) require CPU_EXTENSION_RISCV_Zicsr extension." severity error;
 
-- Bus timeout --
assert not (BUS_TIMEOUT < 2) report "NEORV32 CPU CONFIG ERROR! Invalid bus access timeout value <BUS_TIMEOUT>. Has to be >= 2." severity error;
168,15 → 173,19
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports >lr.w< and >sc.w< instructions yet." severity warning;
 
-- PMP regions check --
assert not ((pmp_num_regions_c > pmp_max_r_c) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <pmp_num_regions_c> out of valid range." severity error;
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..64)." severity error;
-- PMP granulartiy --
assert not ((is_power_of_two_f(pmp_min_granularity_c) = false) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be a power of two." severity error;
assert not ((pmp_min_granularity_c < 8) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be >= 8 bytes." severity error;
 
assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be a power of two." severity error;
assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be >= 8 bytes." severity error;
-- PMP notifier --
assert not (PMP_USE = true) report "NEORV32 CPU CONFIG NOTE: Implementing physical memory protection (PMP) with " & integer'image(pmp_num_regions_c) & " regions and " & integer'image(pmp_min_granularity_c) & " bytes minimal region size (granulartiy)." severity note;
assert not (PMP_NUM_REGIONS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing physical memory protection (PMP) with " & integer'image(PMP_NUM_REGIONS) & " regions and a minimal granularity of " & integer'image(PMP_MIN_GRANULARITY) & " bytes." severity note;
 
-- HPM counters check --
assert not (HPM_NUM_CNTS > 29) report "NEORV32 CPU CONFIG ERROR! Number of HPM counters <HPM_NUM_CNTS> out of valid range (0..29)." severity error;
-- HPM counters notifier --
assert not (HPM_NUM_CNTS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing " & integer'image(HPM_NUM_CNTS) & " HPM counters." severity note;
 
 
-- Control Unit ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_control_inst: neorv32_cpu_control
193,7 → 202,10
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Physical memory protection (PMP) --
PMP_USE => PMP_USE -- implement physical memory protection?
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => HPM_NUM_CNTS -- number of inmplemnted HPM counters (0..29)
)
port map (
-- global control --
370,7 → 382,8
generic map (
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
-- Physical memory protection (PMP) --
PMP_USE => PMP_USE, -- implement physical memory protection?
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Bus Timeout --
BUS_TIMEOUT => BUS_TIMEOUT -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
)
/rtl/core/neorv32_cpu_bus.vhd
5,7 → 5,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
45,7 → 45,8
generic (
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
-- Physical memory protection (PMP) --
PMP_USE : boolean := false; -- implement physical memory protection?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Bus Timeout --
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
);
111,7 → 112,7
constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
 
-- PMP granularity --
constant pmp_g_c : natural := index_size_f(pmp_min_granularity_c);
constant pmp_g_c : natural := index_size_f(PMP_MIN_GRANULARITY);
 
-- PMP configuration register bits --
constant pmp_cfg_r_c : natural := 0; -- read permit
143,17 → 144,17
signal i_arbiter, d_arbiter : bus_arbiter_t;
 
-- physical memory protection --
type pmp_addr_t is array (0 to pmp_num_regions_c-1) of std_ulogic_vector(data_width_c-1 downto 0);
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
type pmp_t is record
addr_mask : pmp_addr_t;
region_base : pmp_addr_t; -- region config base address
region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
region_d_addr : pmp_addr_t; -- masked data access base address for comparator
i_match : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region match for instruction interface
d_match : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region match for data interface
if_fault : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region access fault for fetch operation
ld_fault : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region access fault for load operation
st_fault : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region access fault for store operation
i_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface
d_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface
if_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation
ld_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
st_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
end record;
signal pmp : pmp_t;
 
391,7 → 392,7
pmp_masks: process(clk_i)
begin
if rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
for r in 0 to pmp_num_regions_c-1 loop -- iterate over all regions
for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
pmp.addr_mask(r) <= (others => '0');
for i in pmp_g_c to data_width_c-1 loop
pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
403,7 → 404,7
 
-- address access check --
pmp_address_check:
for r in 0 to pmp_num_regions_c-1 generate -- iterate over all regions
for r in 0 to PMP_NUM_REGIONS-1 generate -- iterate over all regions
pmp.region_i_addr(r) <= fetch_pc_i and pmp.addr_mask(r);
pmp.region_d_addr(r) <= mar and pmp.addr_mask(r);
pmp.region_base(r) <= pmp_addr_i(r)(data_width_c+1 downto 2) and pmp.addr_mask(r);
416,7 → 417,7
-- check access type and regions's permissions --
pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
begin
for r in 0 to pmp_num_regions_c-1 loop -- iterate over all regions
for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
432,9 → 433,9
 
 
-- final PMP access fault signals --
if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_USE = true) else '0';
ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_USE = true) else '0';
st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_USE = true) else '0';
if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0';
ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0';
st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0';
 
 
end neorv32_cpu_bus_rtl;
/rtl/core/neorv32_cpu_control.vhd
8,7 → 8,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
58,7 → 58,10
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Physical memory protection (PMP) --
PMP_USE : boolean := false -- implement physical memory protection?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29)
);
port (
-- global control --
108,6 → 111,7
type fetch_engine_t is record
state : fetch_engine_state_t;
state_nxt : fetch_engine_state_t;
state_prev : fetch_engine_state_t;
pc : std_ulogic_vector(data_width_c-1 downto 0);
pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
reset : std_ulogic;
166,6 → 170,7
type execute_engine_t is record
state : execute_engine_state_t;
state_nxt : execute_engine_state_t;
state_prev : execute_engine_state_t;
--
i_reg : std_ulogic_vector(31 downto 0);
i_reg_nxt : std_ulogic_vector(31 downto 0);
231,57 → 236,86
signal bus_fast_ir : std_ulogic;
 
-- RISC-V control and status registers (CSRs) --
type pmp_ctrl_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
type pmp_addr_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(data_width_c-1 downto 0);
type pmp_ctrl_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
type pmp_ctrl_rd_t is array (0 to 63) of std_ulogic_vector(7 downto 0);
type pmp_addr_rd_t is array (0 to 63) of std_ulogic_vector(data_width_c-1 downto 0);
type mhpmevent_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
type mhpmcnt_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(32 downto 0);
type mhpmcnth_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(31 downto 0);
type mhpmevent_rd_t is array (0 to 29) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
type mhpmcnt_rd_t is array (0 to 29) of std_ulogic_vector(32 downto 0);
type mhpmcnth_rd_t is array (0 to 29) of std_ulogic_vector(31 downto 0);
type csr_t is record
addr : std_ulogic_vector(11 downto 0); -- csr address
we : std_ulogic; -- csr write enable
we_nxt : std_ulogic;
re : std_ulogic; -- csr read enable
re_nxt : std_ulogic;
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
addr : std_ulogic_vector(11 downto 0); -- csr address
we : std_ulogic; -- csr write enable
we_nxt : std_ulogic;
re : std_ulogic; -- csr read enable
re_nxt : std_ulogic;
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
--
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
--
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
--
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
mcounteren_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounteren.hpmx: allow mhpmcounterx[h] access from user-mode
--
mcountinhibit_cy : std_ulogic; -- mcounterinhibit.cy: enable auto-increment
mcountinhibit_ir : std_ulogic; -- mcounterinhibit.ir: enable auto-increment
mcountinhibit_cy : std_ulogic; -- mcounterinhibit.cy: enable auto-increment for [m]cycle[h]
mcountinhibit_ir : std_ulogic; -- mcounterinhibit.ir: enable auto-increment for [m]instret[h]
mcountinhibit_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounterinhibit.hpm3: enable auto-increment for mhpmcounterx[h]
--
mip_status : std_ulogic_vector(interrupt_width_c-1 downto 0); -- current buffered IRQs
mip_clear : std_ulogic_vector(interrupt_width_c-1 downto 0); -- set bits clear the according buffered IRQ
mip_status : std_ulogic_vector(interrupt_width_c-1 downto 0); -- current buffered IRQs
mip_clear : std_ulogic_vector(interrupt_width_c-1 downto 0); -- set bits clear the according buffered IRQ
--
privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode
priv_m_mode : std_ulogic; -- CPU in M-mode
priv_u_mode : std_ulogic; -- CPU in u-mode
privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode
priv_m_mode : std_ulogic; -- CPU in M-mode
priv_u_mode : std_ulogic; -- CPU in u-mode
--
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
--
mhpmevent : mhpmevent_t; -- mhpmevent*: machine performance-monitoring event selector (R/W)
mhpmevent_rd : mhpmevent_rd_t; -- mhpmevent*: actual read data
--
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
--
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
--
mhpmcounter : mhpmcnt_t; -- mhpmcounter* (R/W), plus carry bit
mhpmcounterh : mhpmcnth_t; -- mhpmcounter*h (R/W)
mhpmcounter_rd : mhpmcnt_rd_t; -- mhpmcounter* (R/W): actual read data
mhpmcounterh_rd : mhpmcnth_rd_t; -- mhpmcounter*h (R/W): actual read data
--
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
pmpcfg_rd : pmp_ctrl_rd_t; -- physical memory protection - actual read data
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
pmpaddr_rd : pmp_addr_rd_t; -- physical memory protection - actual read data
end record;
signal csr : csr_t;
 
signal mcycle_msb : std_ulogic;
signal minstret_msb : std_ulogic;
-- counter low-to-high-word carry --
signal mcycle_msb : std_ulogic;
signal minstret_msb : std_ulogic;
signal mhpmcounter_msb : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
 
-- (hpm) counter events --
signal cnt_event, cnt_event_nxt : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
signal hpmcnt_trigger : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
 
-- illegal instruction check --
signal illegal_opcode_lsbs : std_ulogic; -- if opcode != rv32
signal illegal_instruction : std_ulogic;
302,8 → 336,9
fetch_engine_fsm_sync: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
fetch_engine.state <= IFETCH_RESET;
fetch_engine.pc <= (others => '0');
fetch_engine.state <= IFETCH_RESET;
fetch_engine.state_prev <= IFETCH_RESET;
fetch_engine.pc <= (others => '0');
elsif rising_edge(clk_i) then
if (fetch_engine.reset = '1') then
fetch_engine.state <= IFETCH_RESET;
310,7 → 345,8
else
fetch_engine.state <= fetch_engine.state_nxt;
end if;
fetch_engine.pc <= fetch_engine.pc_nxt;
fetch_engine.state_prev <= fetch_engine.state;
fetch_engine.pc <= fetch_engine.pc_nxt;
end if;
end process fetch_engine_fsm_sync;
 
638,9 → 674,10
execute_engine_fsm_sync: process(clk_i)
begin
if rising_edge(clk_i) then
execute_engine.i_reg <= execute_engine.i_reg_nxt;
execute_engine.is_ci <= execute_engine.is_ci_nxt;
execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
execute_engine.state_prev <= execute_engine.state;
execute_engine.i_reg <= execute_engine.i_reg_nxt;
execute_engine.is_ci <= execute_engine.is_ci_nxt;
execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
-- next PC (next linear instruction) --
if (execute_engine.state = EXECUTE) then
if (execute_engine.is_ci = '1') then -- compressed instruction?
810,10 → 847,10
when TRAP => -- Start trap environment (also used as cpu sleep state)
-- ------------------------------------------------------------
execute_engine.pc_mux_sel <= "10"; -- csr.mtvec (trap)
fetch_engine.reset <= '1';
execute_engine.if_rst_nxt <= '1'; -- this will be a non-linear PC modification
if (trap_ctrl.env_start = '1') then -- trap triggered?
trap_ctrl.env_start_ack <= '1';
fetch_engine.reset <= '1';
execute_engine.pc_we <= '1';
execute_engine.sleep_nxt <= '0'; -- waky waky
execute_engine.state_nxt <= SYS_WAIT;
1100,7 → 1137,8
-- Illegal CSR Access Check ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
invalid_csr_access_check: process(execute_engine.i_reg, csr)
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
variable csr_mcounteren_hpm_v : std_ulogic_vector(28 downto 0); -- max 29 HPM counters
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
begin
-- is this CSR instruction really going to write/read to/from a CSR? --
1113,57 → 1151,145
-- csr_racc_v := '1'; -- always read CSR
end if;
 
-- low privilege level access to hpm counters? --
csr_mcounteren_hpm_v := (others => '0');
csr_mcounteren_hpm_v(HPM_NUM_CNTS-1 downto 0) := csr.mcounteren_hpm(HPM_NUM_CNTS-1 downto 0);
 
-- check CSR access --
case csr.addr is
-- standard read/write CSRs --
when csr_mstatus_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mstatush_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_misa_c => csr_acc_valid <= csr.priv_m_mode;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
when csr_mie_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mtvec_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mscratch_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mepc_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mcause_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mcounteren_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mtval_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mip_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mstatus_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mstatush_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_misa_c => csr_acc_valid <= csr.priv_m_mode;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
when csr_mie_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mtvec_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mscratch_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mepc_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mcause_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mcounteren_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mtval_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mip_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
--
when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only
when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only
when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
--
when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only
when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 2)) and csr.priv_m_mode; -- M-mode only
when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 3)) and csr.priv_m_mode; -- M-mode only
when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 4)) and csr.priv_m_mode; -- M-mode only
when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only
when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 6)) and csr.priv_m_mode; -- M-mode only
when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 7)) and csr.priv_m_mode; -- M-mode only
when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 8)) and csr.priv_m_mode; -- M-mode only
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c |
csr_pmpaddr8_c | csr_pmpaddr9_c | csr_pmpaddr10_c | csr_pmpaddr11_c | csr_pmpaddr12_c | csr_pmpaddr13_c | csr_pmpaddr14_c | csr_pmpaddr15_c |
csr_pmpaddr16_c | csr_pmpaddr17_c | csr_pmpaddr18_c | csr_pmpaddr19_c | csr_pmpaddr20_c | csr_pmpaddr21_c | csr_pmpaddr22_c | csr_pmpaddr23_c |
csr_pmpaddr24_c | csr_pmpaddr25_c | csr_pmpaddr26_c | csr_pmpaddr27_c | csr_pmpaddr28_c | csr_pmpaddr29_c | csr_pmpaddr30_c | csr_pmpaddr31_c |
csr_pmpaddr32_c | csr_pmpaddr33_c | csr_pmpaddr34_c | csr_pmpaddr35_c | csr_pmpaddr36_c | csr_pmpaddr37_c | csr_pmpaddr38_c | csr_pmpaddr39_c |
csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c |
csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c |
csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
--
when csr_mcountinhibit_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
--
when csr_mcycle_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_minstret_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mhpmevent3_c | csr_mhpmevent4_c | csr_mhpmevent5_c | csr_mhpmevent6_c | csr_mhpmevent7_c | csr_mhpmevent8_c |
csr_mhpmevent9_c | csr_mhpmevent10_c | csr_mhpmevent11_c | csr_mhpmevent12_c | csr_mhpmevent13_c | csr_mhpmevent14_c |
csr_mhpmevent15_c | csr_mhpmevent16_c | csr_mhpmevent17_c | csr_mhpmevent18_c | csr_mhpmevent19_c | csr_mhpmevent20_c |
csr_mhpmevent21_c | csr_mhpmevent22_c | csr_mhpmevent23_c | csr_mhpmevent24_c | csr_mhpmevent25_c | csr_mhpmevent26_c |
csr_mhpmevent27_c | csr_mhpmevent28_c | csr_mhpmevent29_c | csr_mhpmevent30_c | csr_mhpmevent31_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
--
when csr_mcycleh_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_minstreth_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_mcycle_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_minstret_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
--
when csr_mhpmcounter3_c | csr_mhpmcounter4_c | csr_mhpmcounter5_c | csr_mhpmcounter6_c | csr_mhpmcounter7_c | csr_mhpmcounter8_c |
csr_mhpmcounter9_c | csr_mhpmcounter10_c | csr_mhpmcounter11_c | csr_mhpmcounter12_c | csr_mhpmcounter13_c | csr_mhpmcounter14_c |
csr_mhpmcounter15_c | csr_mhpmcounter16_c | csr_mhpmcounter17_c | csr_mhpmcounter18_c | csr_mhpmcounter19_c | csr_mhpmcounter20_c |
csr_mhpmcounter21_c | csr_mhpmcounter22_c | csr_mhpmcounter23_c | csr_mhpmcounter24_c | csr_mhpmcounter25_c | csr_mhpmcounter26_c |
csr_mhpmcounter27_c | csr_mhpmcounter28_c | csr_mhpmcounter29_c | csr_mhpmcounter30_c | csr_mhpmcounter31_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
--
when csr_mcycleh_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
when csr_minstreth_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
--
when csr_mhpmcounter3h_c | csr_mhpmcounter4h_c | csr_mhpmcounter5h_c | csr_mhpmcounter6h_c | csr_mhpmcounter7h_c | csr_mhpmcounter8h_c |
csr_mhpmcounter9h_c | csr_mhpmcounter10h_c | csr_mhpmcounter11h_c | csr_mhpmcounter12h_c | csr_mhpmcounter13h_c | csr_mhpmcounter14h_c |
csr_mhpmcounter15h_c | csr_mhpmcounter16h_c | csr_mhpmcounter17h_c | csr_mhpmcounter18h_c | csr_mhpmcounter19h_c | csr_mhpmcounter20h_c |
csr_mhpmcounter21h_c | csr_mhpmcounter22h_c | csr_mhpmcounter23h_c | csr_mhpmcounter24h_c | csr_mhpmcounter25h_c | csr_mhpmcounter26h_c |
csr_mhpmcounter27h_c | csr_mhpmcounter28h_c | csr_mhpmcounter29h_c | csr_mhpmcounter30h_c | csr_mhpmcounter31h_c =>
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
 
-- standard read-only CSRs --
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
when csr_time_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
when csr_time_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
--
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter3_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(0)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter4_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(1)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter5_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(2)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter6_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(3)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter7_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(4)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter8_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(5)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter9_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(6)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter10_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(7)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter11_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(8)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter12_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(9)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter13_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(10)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter14_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(11)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter15_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(12)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter16_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(13)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter17_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(14)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter18_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(15)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter19_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(16)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter20_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(17)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter21_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(18)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter22_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(19)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter23_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(20)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter24_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(21)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter25_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(22)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter26_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(23)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter27_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(24)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter28_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(25)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter29_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(26)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter30_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(27)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter31_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(28)); -- M-mode, U-mode if authorized, read-only
--
when csr_mvendorid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
when csr_marchid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
when csr_mimpid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
when csr_mhartid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_cy); -- M-mode, U-mode if authorized, read-only
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_tm); -- M-mode, U-mode if authorized, read-only
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr.mcounteren_ir); -- M-mode, U-mode if authorized, read-only
--
when csr_hpmcounter3h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(0)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter4h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(1)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter5h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(2)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter6h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(3)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter7h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(4)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter8h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(5)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter9h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(6)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter10h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(7)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter11h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(8)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter12h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(9)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter13h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(10)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter14h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(11)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter15h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(12)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter16h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(13)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter17h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(14)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter18h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(15)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter19h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(16)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter20h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(17)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter21h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(18)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter22h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(19)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter23h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(20)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter24h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(21)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter25h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(22)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter26h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(23)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter27h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(24)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter28h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(25)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter29h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(26)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter30h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(27)); -- M-mode, U-mode if authorized, read-only
when csr_hpmcounter31h_c => csr_acc_valid <= (not csr_wacc_v) and (csr.priv_m_mode or csr_mcounteren_hpm_v(28)); -- M-mode, U-mode if authorized, read-only
--
when csr_mvendorid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
when csr_marchid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
when csr_mimpid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
when csr_mhartid_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
-- custom read-only CSRs --
when csr_mzext_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
when csr_mzext_c => csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
--
when others => csr_acc_valid <= '0'; -- invalid access
when others => csr_acc_valid <= '0'; -- invalid access
end case;
end process invalid_csr_access_check;
 
1406,7 → 1532,7
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only to continue execution even if permanent IRQ
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
trap_ctrl.exc_ack <= '1'; -- clear execption
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- clear interrupt with interrupt ACK mask
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
end if;
else -- trap waiting to get started
1428,7 → 1554,7
csr.mip_status <= trap_ctrl.irq_buf;
 
 
-- Trap Priority Detector -----------------------------------------------------------------
-- Trap Priority Encoder ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
trap_priority: process(trap_ctrl)
begin
1476,7 → 1602,7
trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
 
 
-- the following traps are caused by *synchronous* exceptions (= classic exceptions)
-- the following traps are caused by *synchronous* exceptions (= 'classic' exceptions)
-- here we do not need a specific acknowledge mask since only one exception (the one
-- with highest priority) is evaluated at once
 
1522,7 → 1648,7
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
trap_ctrl.cause_nxt <= trap_lbe_c;
 
-- undefined / not implemented --
-- not implemented --
else
trap_ctrl.cause_nxt <= (others => '0');
trap_ctrl.irq_ack_nxt <= (others => '0');
1583,6 → 1709,7
-- Control and Status Registers Write Access ----------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_write_access: process(rstn_i, clk_i)
variable pmpaddr_v : std_ulogic_vector(6 downto 0);
begin
if (rstn_i = '0') then
csr.we <= '0';
1598,7 → 1725,7
csr.mtvec <= (others => '0');
csr.mscratch <= x"19880704"; -- :)
csr.mepc <= (others => '0');
-- mcause = TRAP_CODE_RESET (hardware reset, 0x80000000)
-- mcause = TRAP_CODE_RESET (hardware reset, "non-maskable interrupt")
csr.mcause <= (others => '0');
csr.mcause(csr.mcause'left) <= trap_reset_c(trap_reset_c'left);
csr.mcause(trap_reset_c'left-1 downto 0) <= trap_reset_c(trap_reset_c'left-1 downto 0);
1605,21 → 1732,20
--
csr.mtval <= (others => '0');
csr.mip_clear <= (others => '0');
--
csr.pmpcfg <= (others => (others => '0'));
csr.pmpaddr <= (others => (others => '1'));
--
csr.mcounteren_cy <= '0';
csr.mcounteren_tm <= '0';
csr.mcounteren_ir <= '0';
csr.mcountinhibit_cy <= '0';
csr.mcountinhibit_ir <= '0';
csr.mhpmevent <= (others => (others => '0'));
--
csr.mcycle <= (others => '0');
csr.minstret <= (others => '0');
csr.mcycleh <= (others => '0');
csr.minstreth <= (others => '0');
mcycle_msb <= '0';
minstret_msb <= '0';
csr.mcounteren_cy <= '0';
csr.mcounteren_tm <= '0';
csr.mcounteren_ir <= '0';
csr.mcounteren_hpm <= (others => '0');
--
csr.mcountinhibit_cy <= '0';
csr.mcountinhibit_ir <= '0';
csr.mcountinhibit_hpm <= (others => '0');
elsif rising_edge(clk_i) then
-- write access? --
csr.we <= csr.we_nxt;
1657,9 → 1783,10
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
when csr_mcounteren_c => -- R/W: machine counter enable register
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h]
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h]
csr.mcounteren_hpm <= csr.wdata(csr.mcounteren_hpm'left+3 downto 3); -- enable user-level access to mhpmcounterx[h]
 
-- machine trap handling --
-- --------------------------------------------------------------------
1683,62 → 1810,63
csr.mip_clear(interrupt_firq_2_c) <= not csr.wdata(18);
csr.mip_clear(interrupt_firq_3_c) <= not csr.wdata(19);
 
-- physical memory protection - configuration --
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
-- --------------------------------------------------------------------
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - PMP configuration register 0
if (PMP_USE = true) and (pmp_num_regions_c >= 1) then
for j in 0 to 3 loop -- bytes in pmpcfg CSR
if ((j+1) <= pmp_num_regions_c) then
if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access
csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
csr.pmpcfg(0+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
csr.pmpcfg(0+j)(5) <= '0'; -- reserved
csr.pmpcfg(0+j)(6) <= '0'; -- reserved
csr.pmpcfg(0+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode)
end if;
when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
for i in 0 to PMP_NUM_REGIONS-1 loop
if (csr.addr(3 downto 0) = std_ulogic_vector(to_unsigned(i, 4))) then
if (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpcfg access
csr.pmpcfg(i)(0) <= csr.wdata((i mod 4)*8+0); -- R (rights.read)
csr.pmpcfg(i)(1) <= csr.wdata((i mod 4)*8+1); -- W (rights.write)
csr.pmpcfg(i)(2) <= csr.wdata((i mod 4)*8+2); -- X (rights.execute)
csr.pmpcfg(i)(3) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_L
csr.pmpcfg(i)(4) <= csr.wdata((i mod 4)*8+3) and csr.wdata((i mod 4)*8+4); -- A_H - NAPOT/OFF only
csr.pmpcfg(i)(5) <= '0'; -- reserved
csr.pmpcfg(i)(6) <= '0'; -- reserved
csr.pmpcfg(i)(7) <= csr.wdata((i mod 4)*8+7); -- L (locked / rights also enforced in m-mode)
end if;
end loop; -- j (bytes in CSR)
end if;
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - PMP configuration register 1
if (PMP_USE = true) and (pmp_num_regions_c >= 5) then
for j in 0 to 3 loop -- bytes in pmpcfg CSR
if ((j+1+4) <= pmp_num_regions_c) then
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
csr.pmpcfg(4+j)(4) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_H - NAPOT/OFF only
csr.pmpcfg(4+j)(5) <= '0'; -- reserved
csr.pmpcfg(4+j)(6) <= '0'; -- reserved
csr.pmpcfg(4+j)(7) <= csr.wdata(j*8+7); -- L (locked / rights also enforced in m-mode)
end if;
end if;
end loop; -- j (bytes in CSR)
end if;
end if;
end loop; -- i (PMP regions)
 
-- physical memory protection - addresses --
-- physical memory protection: R/W: pmpaddr* - PMP address registers --
-- --------------------------------------------------------------------
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c |
csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c => -- R/W: pmpaddr0..7 - PMP address register 0..7
if (PMP_USE = true) then
for i in 0 to pmp_num_regions_c-1 loop
if (csr.addr(2 downto 0) = std_ulogic_vector(to_unsigned(i, 3))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
csr.pmpaddr(i) <= csr.wdata;
csr.pmpaddr(i)(index_size_f(pmp_min_granularity_c)-4 downto 0) <= (others => '1');
end if;
end loop; -- i (CSRs)
end if;
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c |
csr_pmpaddr8_c | csr_pmpaddr9_c | csr_pmpaddr10_c | csr_pmpaddr11_c | csr_pmpaddr12_c | csr_pmpaddr13_c | csr_pmpaddr14_c | csr_pmpaddr15_c |
csr_pmpaddr16_c | csr_pmpaddr17_c | csr_pmpaddr18_c | csr_pmpaddr19_c | csr_pmpaddr20_c | csr_pmpaddr21_c | csr_pmpaddr22_c | csr_pmpaddr23_c |
csr_pmpaddr24_c | csr_pmpaddr25_c | csr_pmpaddr26_c | csr_pmpaddr27_c | csr_pmpaddr28_c | csr_pmpaddr29_c | csr_pmpaddr30_c | csr_pmpaddr31_c |
csr_pmpaddr32_c | csr_pmpaddr33_c | csr_pmpaddr34_c | csr_pmpaddr35_c | csr_pmpaddr36_c | csr_pmpaddr37_c | csr_pmpaddr38_c | csr_pmpaddr39_c |
csr_pmpaddr40_c | csr_pmpaddr41_c | csr_pmpaddr42_c | csr_pmpaddr43_c | csr_pmpaddr44_c | csr_pmpaddr45_c | csr_pmpaddr46_c | csr_pmpaddr47_c |
csr_pmpaddr48_c | csr_pmpaddr49_c | csr_pmpaddr50_c | csr_pmpaddr51_c | csr_pmpaddr52_c | csr_pmpaddr53_c | csr_pmpaddr54_c | csr_pmpaddr55_c |
csr_pmpaddr56_c | csr_pmpaddr57_c | csr_pmpaddr58_c | csr_pmpaddr59_c | csr_pmpaddr60_c | csr_pmpaddr61_c | csr_pmpaddr62_c | csr_pmpaddr63_c =>
for i in 0 to PMP_NUM_REGIONS-1 loop
pmpaddr_v := std_ulogic_vector(unsigned(csr_pmpaddr0_c(6 downto 0)) + i); -- adapt to *non-aligned* base address (csr_pmpaddr0_c)
if (csr.addr(6 downto 0) = pmpaddr_v) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
csr.pmpaddr(i) <= csr.wdata;
csr.pmpaddr(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1');
end if;
end loop; -- i (PMP regions)
 
-- machine counter setup --
-- --------------------------------------------------------------------
when csr_mcountinhibit_c => -- R/W: mcountinhibit - machine counter-inhibit register
csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter
csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter
csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter
csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter
csr.mcountinhibit_hpm <= csr.wdata(csr.mcountinhibit_hpm'left+3 downto 3); -- enable auto-increment of [m]hpmcounter*[h] counter
 
-- machine performance-monitoring event selector --
-- --------------------------------------------------------------------
when csr_mhpmevent3_c | csr_mhpmevent4_c | csr_mhpmevent5_c | csr_mhpmevent6_c | csr_mhpmevent7_c | csr_mhpmevent8_c |
csr_mhpmevent9_c | csr_mhpmevent10_c | csr_mhpmevent11_c | csr_mhpmevent12_c | csr_mhpmevent13_c | csr_mhpmevent14_c |
csr_mhpmevent15_c | csr_mhpmevent16_c | csr_mhpmevent17_c | csr_mhpmevent18_c | csr_mhpmevent19_c | csr_mhpmevent20_c |
csr_mhpmevent21_c | csr_mhpmevent22_c | csr_mhpmevent23_c | csr_mhpmevent24_c | csr_mhpmevent25_c | csr_mhpmevent26_c |
csr_mhpmevent27_c | csr_mhpmevent28_c | csr_mhpmevent29_c | csr_mhpmevent30_c | csr_mhpmevent31_c => -- R/W: mhpmevent* - machine performance-monitoring event selector
for i in 0 to HPM_NUM_CNTS-1 loop
if (csr.addr(4 downto 0) = std_ulogic_vector(to_unsigned(i+3, 5))) then
csr.mhpmevent(i) <= csr.wdata(csr.mhpmevent(i)'left downto 0);
end if;
end loop; -- i (CSRs)
 
-- undefined --
-- --------------------------------------------------------------------
when others =>
1804,41 → 1932,6
 
end if; -- hardware csr access
 
-- --------------------------------------------------------------------------------
-- Counter CSRs (each counter is split in two 32-bit counters)
-- --------------------------------------------------------------------------------
-- [m]cycle --
if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
csr.mcycle <= '0' & csr.wdata;
mcycle_msb <= '0';
elsif (csr.mcountinhibit_cy = '0') and (execute_engine.sleep = '0') then -- non-inhibited automatic update (if CPU is not in sleep mode)
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
mcycle_msb <= csr.mcycle(csr.mcycle'left);
end if;
 
-- [m]cycleh --
if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
csr.mcycleh <= csr.wdata;
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update (continued)
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
end if;
 
-- [m]instret --
if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
csr.minstret <= '0' & csr.wdata;
minstret_msb <= '0';
elsif (csr.mcountinhibit_ir = '0') and (execute_engine.state = EXECUTE) then -- non-inhibited automatic update (if CPU actually executes an instruction)
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
minstret_msb <= csr.minstret(csr.minstret'left);
end if;
 
-- [m]instreth --
if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
csr.minstreth <= csr.wdata;
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update (continued)
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
end if;
 
end if;
end if;
end process csr_write_access;
1852,16 → 1945,141
begin
pmp_addr_o <= (others => (others => '0'));
pmp_ctrl_o <= (others => (others => '0'));
if (PMP_USE = true) then
for i in 0 to pmp_num_regions_c-1 loop
pmp_addr_o(i) <= csr.pmpaddr(i) & "11";
pmp_addr_o(i)(index_size_f(pmp_min_granularity_c)-4 downto 0) <= (others => '1');
pmp_ctrl_o(i) <= csr.pmpcfg(i);
for i in 0 to PMP_NUM_REGIONS-1 loop
pmp_addr_o(i) <= csr.pmpaddr(i) & "11";
pmp_addr_o(i)(index_size_f(PMP_MIN_GRANULARITY)-4 downto 0) <= (others => '1');
pmp_ctrl_o(i) <= csr.pmpcfg(i);
end loop; -- i
end process pmp_output;
 
-- PMP read dummy --
pmp_rd_dummy: process(csr)
begin
csr.pmpcfg_rd <= (others => (others => '0'));
csr.pmpaddr_rd <= (others => (others => '0'));
for i in 0 to PMP_NUM_REGIONS-1 loop
csr.pmpcfg_rd(i) <= csr.pmpcfg(i);
csr.pmpaddr_rd(i) <= csr.pmpaddr(i);
if (csr.pmpcfg(i)(4 downto 3) = "00") then -- mode = off
csr.pmpaddr_rd(i)(index_size_f(PMP_MIN_GRANULARITY)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end loop; -- i
end process pmp_rd_dummy;
 
 
-- Control and Status Registers - Counters ------------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_counters: process(clk_i)
begin
-- Counter CSRs (each counter is split into two 32-bit counters)
if rising_edge(clk_i) then
 
-- [m]cycle --
if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
csr.mcycle <= '0' & csr.wdata;
mcycle_msb <= '0';
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
mcycle_msb <= csr.mcycle(csr.mcycle'left);
end if;
 
-- [m]cycleh --
if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
csr.mcycleh <= csr.wdata;
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update (continued)
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
end if;
 
-- [m]instret --
if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
csr.minstret <= '0' & csr.wdata;
minstret_msb <= '0';
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') and (cnt_event(hpmcnt_event_cy_c) = '1') then -- non-inhibited automatic update
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
minstret_msb <= csr.minstret(csr.minstret'left);
end if;
 
-- [m]instreth --
if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
csr.minstreth <= csr.wdata;
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update (continued)
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
end if;
 
-- [machine] high performance counters --
for i in 0 to HPM_NUM_CNTS-1 loop
-- [m]hpmcounter* --
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3_c) + i)) then -- write access
csr.mhpmcounter(i) <= '0' & csr.wdata;
mhpmcounter_msb(i) <= '0';
elsif (csr.mcountinhibit_hpm(i) = '0') and (hpmcnt_trigger(i) = '1') then -- non-inhibited automatic update
csr.mhpmcounter(i) <= std_ulogic_vector(unsigned(csr.mhpmcounter(i)) + 1);
mhpmcounter_msb(i) <= csr.mhpmcounter(i)(csr.mhpmcounter(i)'left);
end if;
 
-- [m]hpmcounter*h --
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3h_c) + i)) then -- write access
csr.mhpmcounterh(i) <= csr.wdata;
elsif ((mhpmcounter_msb(i) xor csr.mhpmcounter(i)(csr.mhpmcounter(i)'left)) = '1') then -- automatic update (continued)
csr.mhpmcounterh(i) <= std_ulogic_vector(unsigned(csr.mhpmcounterh(i)) + 1);
end if;
end loop; -- i
 
end if;
end process pmp_output;
end process csr_counters;
 
-- hpm read dummy --
hpm_rd_dummy: process(csr)
begin
csr.mhpmevent_rd <= (others => (others => '0'));
csr.mhpmcounter_rd <= (others => (others => '0'));
csr.mhpmcounterh_rd <= (others => (others => '0'));
for i in 0 to HPM_NUM_CNTS-1 loop
csr.mhpmevent_rd(i) <= csr.mhpmevent(i);
csr.mhpmcounter_rd(i) <= csr.mhpmcounter(i);
csr.mhpmcounterh_rd(i) <= csr.mhpmcounterh(i);
end loop; -- i
end process hpm_rd_dummy;
 
 
-- (HPM) Counter Event Control ------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
hpmcnt_ctrl: process(clk_i)
begin
if rising_edge(clk_i) then
cnt_event <= cnt_event_nxt;
hpmcnt_trigger <= (others => '0'); -- default
for i in 0 to HPM_NUM_CNTS-1 loop
-- enabled selected triggers by ANDing events and configuration bits --
-- OR everything to see if counter should increment --
-- AND with inverted sleep flag to increment only when CPU is awake --
hpmcnt_trigger(i) <= (or_all_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0))) and (not execute_engine.sleep);
end loop; -- i
end if;
end process hpmcnt_ctrl;
 
-- counter event trigger - RISC-V specific --
cnt_event_nxt(hpmcnt_event_cy_c) <= not execute_engine.sleep; -- active cycle
cnt_event_nxt(hpmcnt_event_never_c) <= '0'; -- undefined (never)
cnt_event_nxt(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- retired instruction
 
-- counter event trigger - custom / NEORV32-specific --
cnt_event_nxt(hpmcnt_event_cir_c) <= '1' when (execute_engine.state = EXECUTE) and (execute_engine.is_ci = '1') else '0'; -- retired compressed instruction
cnt_event_nxt(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle
cnt_event_nxt(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH) and (execute_engine.state_prev = DISPATCH) else '0'; -- instruction issue wait cycle
 
cnt_event_nxt(hpmcnt_event_load_c) <= '1' when (execute_engine.state = LOADSTORE_1) and (ctrl(ctrl_bus_rd_c) = '1') else '0'; -- load operation
cnt_event_nxt(hpmcnt_event_store_c) <= '1' when (execute_engine.state = LOADSTORE_1) and (ctrl(ctrl_bus_wr_c) = '1') else '0'; -- store operation
cnt_event_nxt(hpmcnt_event_wait_ls_c) <= '1' when (execute_engine.state = LOADSTORE_2) and (execute_engine.state_prev = LOADSTORE_2) else '0'; -- load/store memory wait cycle
 
cnt_event_nxt(hpmcnt_event_jump_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') else '0'; -- jump (unconditional)
cnt_event_nxt(hpmcnt_event_branch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') else '0'; -- branch (conditional, taken or not taken)
cnt_event_nxt(hpmcnt_event_tbranch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') and (execute_engine.branch_taken = '1') else '0'; -- taken branch (conditional)
 
cnt_event_nxt(hpmcnt_event_trap_c) <= '1' when (trap_ctrl.env_start_ack = '1') else '0'; -- entered trap
cnt_event_nxt(hpmcnt_event_illegal_c) <= '1' when (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause = trap_iil_c) else '0'; -- illegal operation
 
 
-- Control and Status Registers Read Access -----------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_read_access: process(clk_i)
1906,6 → 2124,7
csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
csr.rdata(2) <= csr.mcounteren_ir; -- enable user-level access to instret[h]
csr.rdata(csr.mcounteren_hpm'left+3 downto 3) <= csr.mcounteren_hpm; -- enable user-level access to hpmcounterx[h]
 
-- machine trap handling --
when csr_mscratch_c => -- R/W: mscratch - machine scratch register
1927,94 → 2146,88
csr.rdata(19) <= csr.mip_status(interrupt_firq_3_c);
 
-- physical memory protection - configuration --
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - physical memory protection configuration register 0
if (PMP_USE = true) then
if (pmp_num_regions_c >= 1) then
csr.rdata(07 downto 00) <= csr.pmpcfg(0);
end if;
if (pmp_num_regions_c >= 2) then
csr.rdata(15 downto 08) <= csr.pmpcfg(1);
end if;
if (pmp_num_regions_c >= 3) then
csr.rdata(23 downto 16) <= csr.pmpcfg(2);
end if;
if (pmp_num_regions_c >= 4) then
csr.rdata(31 downto 24) <= csr.pmpcfg(3);
end if;
end if;
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - physical memory protection configuration register 1
if (PMP_USE = true) then
if (pmp_num_regions_c >= 5) then
csr.rdata(07 downto 00) <= csr.pmpcfg(4);
end if;
if (pmp_num_regions_c >= 6) then
csr.rdata(15 downto 08) <= csr.pmpcfg(5);
end if;
if (pmp_num_regions_c >= 7) then
csr.rdata(23 downto 16) <= csr.pmpcfg(6);
end if;
if (pmp_num_regions_c >= 8) then
csr.rdata(31 downto 24) <= csr.pmpcfg(7);
end if;
end if;
when csr_pmpcfg0_c => csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); -- R/W: pmpcfg0
when csr_pmpcfg1_c => csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); -- R/W: pmpcfg1
when csr_pmpcfg2_c => csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); -- R/W: pmpcfg2
when csr_pmpcfg3_c => csr.rdata <= csr.pmpcfg_rd(15) & csr.pmpcfg_rd(14) & csr.pmpcfg_rd(13) & csr.pmpcfg_rd(12); -- R/W: pmpcfg3
when csr_pmpcfg4_c => csr.rdata <= csr.pmpcfg_rd(19) & csr.pmpcfg_rd(18) & csr.pmpcfg_rd(17) & csr.pmpcfg_rd(16); -- R/W: pmpcfg4
when csr_pmpcfg5_c => csr.rdata <= csr.pmpcfg_rd(23) & csr.pmpcfg_rd(22) & csr.pmpcfg_rd(21) & csr.pmpcfg_rd(20); -- R/W: pmpcfg5
when csr_pmpcfg6_c => csr.rdata <= csr.pmpcfg_rd(27) & csr.pmpcfg_rd(26) & csr.pmpcfg_rd(25) & csr.pmpcfg_rd(24); -- R/W: pmpcfg6
when csr_pmpcfg7_c => csr.rdata <= csr.pmpcfg_rd(31) & csr.pmpcfg_rd(30) & csr.pmpcfg_rd(29) & csr.pmpcfg_rd(28); -- R/W: pmpcfg7
when csr_pmpcfg8_c => csr.rdata <= csr.pmpcfg_rd(35) & csr.pmpcfg_rd(34) & csr.pmpcfg_rd(33) & csr.pmpcfg_rd(32); -- R/W: pmpcfg8
when csr_pmpcfg9_c => csr.rdata <= csr.pmpcfg_rd(39) & csr.pmpcfg_rd(38) & csr.pmpcfg_rd(37) & csr.pmpcfg_rd(36); -- R/W: pmpcfg9
when csr_pmpcfg10_c => csr.rdata <= csr.pmpcfg_rd(43) & csr.pmpcfg_rd(42) & csr.pmpcfg_rd(41) & csr.pmpcfg_rd(40); -- R/W: pmpcfg10
when csr_pmpcfg11_c => csr.rdata <= csr.pmpcfg_rd(47) & csr.pmpcfg_rd(46) & csr.pmpcfg_rd(45) & csr.pmpcfg_rd(44); -- R/W: pmpcfg11
when csr_pmpcfg12_c => csr.rdata <= csr.pmpcfg_rd(51) & csr.pmpcfg_rd(50) & csr.pmpcfg_rd(49) & csr.pmpcfg_rd(48); -- R/W: pmpcfg12
when csr_pmpcfg13_c => csr.rdata <= csr.pmpcfg_rd(55) & csr.pmpcfg_rd(54) & csr.pmpcfg_rd(53) & csr.pmpcfg_rd(52); -- R/W: pmpcfg13
when csr_pmpcfg14_c => csr.rdata <= csr.pmpcfg_rd(59) & csr.pmpcfg_rd(58) & csr.pmpcfg_rd(57) & csr.pmpcfg_rd(56); -- R/W: pmpcfg14
when csr_pmpcfg15_c => csr.rdata <= csr.pmpcfg_rd(63) & csr.pmpcfg_rd(62) & csr.pmpcfg_rd(61) & csr.pmpcfg_rd(60); -- R/W: pmpcfg15
 
-- physical memory protection - addresses --
when csr_pmpaddr0_c => -- R/W: pmpaddr0 - physical memory protection address register 0
if (PMP_USE = true) and (pmp_num_regions_c >= 1) then
csr.rdata <= csr.pmpaddr(0);
if (csr.pmpcfg(0)(4 downto 3) = "00") then -- mode = off
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end if;
when csr_pmpaddr1_c => -- R/W: pmpaddr1 - physical memory protection address register 1
if (PMP_USE = true) and (pmp_num_regions_c >= 2) then
csr.rdata <= csr.pmpaddr(1);
if (csr.pmpcfg(1)(4 downto 3) = "00") then -- mode = off
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end if;
when csr_pmpaddr2_c => -- R/W: pmpaddr2 - physical memory protection address register 2
if (PMP_USE = true) and (pmp_num_regions_c >= 3) then
csr.rdata <= csr.pmpaddr(2);
if (csr.pmpcfg(2)(4 downto 3) = "00") then -- mode = off
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end if;
when csr_pmpaddr3_c => -- R/W: pmpaddr3 - physical memory protection address register 3
if (PMP_USE = true) and (pmp_num_regions_c >= 4) then
csr.rdata <= csr.pmpaddr(3);
if (csr.pmpcfg(3)(4 downto 3) = "00") then -- mode = off
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end if;
when csr_pmpaddr4_c => -- R/W: pmpaddr4 - physical memory protection address register 4
if (PMP_USE = true) and (pmp_num_regions_c >= 5) then
csr.rdata <= csr.pmpaddr(4);
if (csr.pmpcfg(4)(4 downto 3) = "00") then -- mode = off
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end if;
when csr_pmpaddr5_c => -- R/W: pmpaddr5 - physical memory protection address register 5
if (PMP_USE = true) and (pmp_num_regions_c >= 6) then
csr.rdata <= csr.pmpaddr(5);
if (csr.pmpcfg(5)(4 downto 3) = "00") then -- mode = off
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end if;
when csr_pmpaddr6_c => -- R/W: pmpaddr6 - physical memory protection address register 6
if (PMP_USE = true) and (pmp_num_regions_c >= 7) then
csr.rdata <= csr.pmpaddr(6);
if (csr.pmpcfg(6)(4 downto 3) = "00") then -- mode = off
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end if;
when csr_pmpaddr7_c => -- R/W: pmpaddr7 - physical memory protection address register 7
if (PMP_USE = true) and (pmp_num_regions_c >= 8) then
csr.rdata <= csr.pmpaddr(7);
if (csr.pmpcfg(7)(4 downto 3) = "00") then -- mode = off
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
end if;
end if;
when csr_pmpaddr0_c => csr.rdata <= csr.pmpaddr_rd(00); -- R/W: pmpaddr0
when csr_pmpaddr1_c => csr.rdata <= csr.pmpaddr_rd(01); -- R/W: pmpaddr1
when csr_pmpaddr2_c => csr.rdata <= csr.pmpaddr_rd(02); -- R/W: pmpaddr2
when csr_pmpaddr3_c => csr.rdata <= csr.pmpaddr_rd(03); -- R/W: pmpaddr3
when csr_pmpaddr4_c => csr.rdata <= csr.pmpaddr_rd(04); -- R/W: pmpaddr4
when csr_pmpaddr5_c => csr.rdata <= csr.pmpaddr_rd(05); -- R/W: pmpaddr5
when csr_pmpaddr6_c => csr.rdata <= csr.pmpaddr_rd(06); -- R/W: pmpaddr6
when csr_pmpaddr7_c => csr.rdata <= csr.pmpaddr_rd(07); -- R/W: pmpaddr7
when csr_pmpaddr8_c => csr.rdata <= csr.pmpaddr_rd(08); -- R/W: pmpaddr8
when csr_pmpaddr9_c => csr.rdata <= csr.pmpaddr_rd(09); -- R/W: pmpaddr9
when csr_pmpaddr10_c => csr.rdata <= csr.pmpaddr_rd(10); -- R/W: pmpaddr10
when csr_pmpaddr11_c => csr.rdata <= csr.pmpaddr_rd(11); -- R/W: pmpaddr11
when csr_pmpaddr12_c => csr.rdata <= csr.pmpaddr_rd(12); -- R/W: pmpaddr12
when csr_pmpaddr13_c => csr.rdata <= csr.pmpaddr_rd(13); -- R/W: pmpaddr13
when csr_pmpaddr14_c => csr.rdata <= csr.pmpaddr_rd(14); -- R/W: pmpaddr14
when csr_pmpaddr15_c => csr.rdata <= csr.pmpaddr_rd(15); -- R/W: pmpaddr15
when csr_pmpaddr16_c => csr.rdata <= csr.pmpaddr_rd(16); -- R/W: pmpaddr16
when csr_pmpaddr17_c => csr.rdata <= csr.pmpaddr_rd(17); -- R/W: pmpaddr17
when csr_pmpaddr18_c => csr.rdata <= csr.pmpaddr_rd(18); -- R/W: pmpaddr18
when csr_pmpaddr19_c => csr.rdata <= csr.pmpaddr_rd(19); -- R/W: pmpaddr19
when csr_pmpaddr20_c => csr.rdata <= csr.pmpaddr_rd(20); -- R/W: pmpaddr20
when csr_pmpaddr21_c => csr.rdata <= csr.pmpaddr_rd(21); -- R/W: pmpaddr21
when csr_pmpaddr22_c => csr.rdata <= csr.pmpaddr_rd(22); -- R/W: pmpaddr22
when csr_pmpaddr23_c => csr.rdata <= csr.pmpaddr_rd(23); -- R/W: pmpaddr23
when csr_pmpaddr24_c => csr.rdata <= csr.pmpaddr_rd(24); -- R/W: pmpaddr24
when csr_pmpaddr25_c => csr.rdata <= csr.pmpaddr_rd(25); -- R/W: pmpaddr25
when csr_pmpaddr26_c => csr.rdata <= csr.pmpaddr_rd(26); -- R/W: pmpaddr26
when csr_pmpaddr27_c => csr.rdata <= csr.pmpaddr_rd(27); -- R/W: pmpaddr27
when csr_pmpaddr28_c => csr.rdata <= csr.pmpaddr_rd(28); -- R/W: pmpaddr28
when csr_pmpaddr29_c => csr.rdata <= csr.pmpaddr_rd(29); -- R/W: pmpaddr29
when csr_pmpaddr30_c => csr.rdata <= csr.pmpaddr_rd(30); -- R/W: pmpaddr30
when csr_pmpaddr31_c => csr.rdata <= csr.pmpaddr_rd(31); -- R/W: pmpaddr31
when csr_pmpaddr32_c => csr.rdata <= csr.pmpaddr_rd(32); -- R/W: pmpaddr32
when csr_pmpaddr33_c => csr.rdata <= csr.pmpaddr_rd(33); -- R/W: pmpaddr33
when csr_pmpaddr34_c => csr.rdata <= csr.pmpaddr_rd(34); -- R/W: pmpaddr34
when csr_pmpaddr35_c => csr.rdata <= csr.pmpaddr_rd(35); -- R/W: pmpaddr35
when csr_pmpaddr36_c => csr.rdata <= csr.pmpaddr_rd(36); -- R/W: pmpaddr36
when csr_pmpaddr37_c => csr.rdata <= csr.pmpaddr_rd(37); -- R/W: pmpaddr37
when csr_pmpaddr38_c => csr.rdata <= csr.pmpaddr_rd(38); -- R/W: pmpaddr38
when csr_pmpaddr39_c => csr.rdata <= csr.pmpaddr_rd(39); -- R/W: pmpaddr39
when csr_pmpaddr40_c => csr.rdata <= csr.pmpaddr_rd(40); -- R/W: pmpaddr40
when csr_pmpaddr41_c => csr.rdata <= csr.pmpaddr_rd(41); -- R/W: pmpaddr41
when csr_pmpaddr42_c => csr.rdata <= csr.pmpaddr_rd(42); -- R/W: pmpaddr42
when csr_pmpaddr43_c => csr.rdata <= csr.pmpaddr_rd(43); -- R/W: pmpaddr43
when csr_pmpaddr44_c => csr.rdata <= csr.pmpaddr_rd(44); -- R/W: pmpaddr44
when csr_pmpaddr45_c => csr.rdata <= csr.pmpaddr_rd(45); -- R/W: pmpaddr45
when csr_pmpaddr46_c => csr.rdata <= csr.pmpaddr_rd(46); -- R/W: pmpaddr46
when csr_pmpaddr47_c => csr.rdata <= csr.pmpaddr_rd(47); -- R/W: pmpaddr47
when csr_pmpaddr48_c => csr.rdata <= csr.pmpaddr_rd(48); -- R/W: pmpaddr48
when csr_pmpaddr49_c => csr.rdata <= csr.pmpaddr_rd(49); -- R/W: pmpaddr49
when csr_pmpaddr50_c => csr.rdata <= csr.pmpaddr_rd(50); -- R/W: pmpaddr50
when csr_pmpaddr51_c => csr.rdata <= csr.pmpaddr_rd(51); -- R/W: pmpaddr51
when csr_pmpaddr52_c => csr.rdata <= csr.pmpaddr_rd(52); -- R/W: pmpaddr52
when csr_pmpaddr53_c => csr.rdata <= csr.pmpaddr_rd(53); -- R/W: pmpaddr53
when csr_pmpaddr54_c => csr.rdata <= csr.pmpaddr_rd(54); -- R/W: pmpaddr54
when csr_pmpaddr55_c => csr.rdata <= csr.pmpaddr_rd(55); -- R/W: pmpaddr55
when csr_pmpaddr56_c => csr.rdata <= csr.pmpaddr_rd(56); -- R/W: pmpaddr56
when csr_pmpaddr57_c => csr.rdata <= csr.pmpaddr_rd(57); -- R/W: pmpaddr57
when csr_pmpaddr58_c => csr.rdata <= csr.pmpaddr_rd(58); -- R/W: pmpaddr58
when csr_pmpaddr59_c => csr.rdata <= csr.pmpaddr_rd(59); -- R/W: pmpaddr59
when csr_pmpaddr60_c => csr.rdata <= csr.pmpaddr_rd(60); -- R/W: pmpaddr60
when csr_pmpaddr61_c => csr.rdata <= csr.pmpaddr_rd(61); -- R/W: pmpaddr61
when csr_pmpaddr62_c => csr.rdata <= csr.pmpaddr_rd(62); -- R/W: pmpaddr62
when csr_pmpaddr63_c => csr.rdata <= csr.pmpaddr_rd(63); -- R/W: pmpaddr63
 
-- machine counter setup --
-- --------------------------------------------------------------------
2021,21 → 2234,114
when csr_mcountinhibit_c => -- R/W: mcountinhibit - machine counter-inhibit register
csr.rdata(0) <= csr.mcountinhibit_cy; -- enable auto-increment of [m]cycle[h] counter
csr.rdata(2) <= csr.mcountinhibit_ir; -- enable auto-increment of [m]instret[h] counter
csr.rdata(csr.mcountinhibit_hpm'left+3 downto 3) <= csr.mcountinhibit_hpm; -- enable auto-increment of [m]hpmcounterx[h] counter
 
-- machine performance-monitoring event selector --
when csr_mhpmevent3_c => csr.rdata(csr.mhpmevent_rd(00)'left downto 0) <= csr.mhpmevent_rd(00); -- R/W: mhpmevent3
when csr_mhpmevent4_c => csr.rdata(csr.mhpmevent_rd(01)'left downto 0) <= csr.mhpmevent_rd(01); -- R/W: mhpmevent4
when csr_mhpmevent5_c => csr.rdata(csr.mhpmevent_rd(02)'left downto 0) <= csr.mhpmevent_rd(02); -- R/W: mhpmevent5
when csr_mhpmevent6_c => csr.rdata(csr.mhpmevent_rd(03)'left downto 0) <= csr.mhpmevent_rd(03); -- R/W: mhpmevent6
when csr_mhpmevent7_c => csr.rdata(csr.mhpmevent_rd(04)'left downto 0) <= csr.mhpmevent_rd(04); -- R/W: mhpmevent7
when csr_mhpmevent8_c => csr.rdata(csr.mhpmevent_rd(05)'left downto 0) <= csr.mhpmevent_rd(05); -- R/W: mhpmevent8
when csr_mhpmevent9_c => csr.rdata(csr.mhpmevent_rd(06)'left downto 0) <= csr.mhpmevent_rd(06); -- R/W: mhpmevent9
when csr_mhpmevent10_c => csr.rdata(csr.mhpmevent_rd(07)'left downto 0) <= csr.mhpmevent_rd(07); -- R/W: mhpmevent10
when csr_mhpmevent11_c => csr.rdata(csr.mhpmevent_rd(08)'left downto 0) <= csr.mhpmevent_rd(08); -- R/W: mhpmevent11
when csr_mhpmevent12_c => csr.rdata(csr.mhpmevent_rd(09)'left downto 0) <= csr.mhpmevent_rd(09); -- R/W: mhpmevent12
when csr_mhpmevent13_c => csr.rdata(csr.mhpmevent_rd(10)'left downto 0) <= csr.mhpmevent_rd(10); -- R/W: mhpmevent13
when csr_mhpmevent14_c => csr.rdata(csr.mhpmevent_rd(11)'left downto 0) <= csr.mhpmevent_rd(11); -- R/W: mhpmevent14
when csr_mhpmevent15_c => csr.rdata(csr.mhpmevent_rd(12)'left downto 0) <= csr.mhpmevent_rd(12); -- R/W: mhpmevent15
when csr_mhpmevent16_c => csr.rdata(csr.mhpmevent_rd(13)'left downto 0) <= csr.mhpmevent_rd(13); -- R/W: mhpmevent16
when csr_mhpmevent17_c => csr.rdata(csr.mhpmevent_rd(14)'left downto 0) <= csr.mhpmevent_rd(14); -- R/W: mhpmevent17
when csr_mhpmevent18_c => csr.rdata(csr.mhpmevent_rd(15)'left downto 0) <= csr.mhpmevent_rd(15); -- R/W: mhpmevent18
when csr_mhpmevent19_c => csr.rdata(csr.mhpmevent_rd(16)'left downto 0) <= csr.mhpmevent_rd(16); -- R/W: mhpmevent19
when csr_mhpmevent20_c => csr.rdata(csr.mhpmevent_rd(17)'left downto 0) <= csr.mhpmevent_rd(17); -- R/W: mhpmevent20
when csr_mhpmevent21_c => csr.rdata(csr.mhpmevent_rd(18)'left downto 0) <= csr.mhpmevent_rd(18); -- R/W: mhpmevent21
when csr_mhpmevent22_c => csr.rdata(csr.mhpmevent_rd(19)'left downto 0) <= csr.mhpmevent_rd(19); -- R/W: mhpmevent22
when csr_mhpmevent23_c => csr.rdata(csr.mhpmevent_rd(20)'left downto 0) <= csr.mhpmevent_rd(20); -- R/W: mhpmevent23
when csr_mhpmevent24_c => csr.rdata(csr.mhpmevent_rd(21)'left downto 0) <= csr.mhpmevent_rd(21); -- R/W: mhpmevent24
when csr_mhpmevent25_c => csr.rdata(csr.mhpmevent_rd(22)'left downto 0) <= csr.mhpmevent_rd(22); -- R/W: mhpmevent25
when csr_mhpmevent26_c => csr.rdata(csr.mhpmevent_rd(23)'left downto 0) <= csr.mhpmevent_rd(23); -- R/W: mhpmevent26
when csr_mhpmevent27_c => csr.rdata(csr.mhpmevent_rd(24)'left downto 0) <= csr.mhpmevent_rd(24); -- R/W: mhpmevent27
when csr_mhpmevent28_c => csr.rdata(csr.mhpmevent_rd(25)'left downto 0) <= csr.mhpmevent_rd(25); -- R/W: mhpmevent28
when csr_mhpmevent29_c => csr.rdata(csr.mhpmevent_rd(26)'left downto 0) <= csr.mhpmevent_rd(26); -- R/W: mhpmevent29
when csr_mhpmevent30_c => csr.rdata(csr.mhpmevent_rd(27)'left downto 0) <= csr.mhpmevent_rd(27); -- R/W: mhpmevent30
when csr_mhpmevent31_c => csr.rdata(csr.mhpmevent_rd(28)'left downto 0) <= csr.mhpmevent_rd(28); -- R/W: mhpmevent31
 
-- counters and timers --
when csr_cycle_c | csr_mcycle_c => -- R/(W): [m]cycle: Cycle counter LOW
when csr_cycle_c | csr_mcycle_c => -- (R)/(W): [m]cycle: Cycle counter LOW
csr.rdata <= csr.mcycle(31 downto 0);
when csr_time_c => -- R/-: time: System time LOW (from MTIME unit)
when csr_time_c => -- (R)/-: time: System time LOW (from MTIME unit)
csr.rdata <= time_i(31 downto 0);
when csr_instret_c | csr_minstret_c => -- R/(W): [m]instret: Instructions-retired counter LOW
when csr_instret_c | csr_minstret_c => -- (R)/(W): [m]instret: Instructions-retired counter LOW
csr.rdata <= csr.minstret(31 downto 0);
when csr_cycleh_c | csr_mcycleh_c => -- R/(W): [m]cycleh: Cycle counter HIGH
when csr_cycleh_c | csr_mcycleh_c => -- (R)/(W): [m]cycleh: Cycle counter HIGH
csr.rdata <= csr.mcycleh(31 downto 0);
when csr_timeh_c => -- R/-: timeh: System time HIGH (from MTIME unit)
when csr_timeh_c => -- (R)/-: timeh: System time HIGH (from MTIME unit)
csr.rdata <= time_i(63 downto 32);
when csr_instreth_c | csr_minstreth_c => -- R/(W): [m]instreth: Instructions-retired counter HIGH
when csr_instreth_c | csr_minstreth_c => -- (R)/(W): [m]instreth: Instructions-retired counter HIGH
csr.rdata <= csr.minstreth(31 downto 0);
 
-- hardware performance counters --
when csr_hpmcounter3_c | csr_mhpmcounter3_c => csr.rdata <= csr.mhpmcounter_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3 - low
when csr_hpmcounter4_c | csr_mhpmcounter4_c => csr.rdata <= csr.mhpmcounter_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4 - low
when csr_hpmcounter5_c | csr_mhpmcounter5_c => csr.rdata <= csr.mhpmcounter_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5 - low
when csr_hpmcounter6_c | csr_mhpmcounter6_c => csr.rdata <= csr.mhpmcounter_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6 - low
when csr_hpmcounter7_c | csr_mhpmcounter7_c => csr.rdata <= csr.mhpmcounter_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7 - low
when csr_hpmcounter8_c | csr_mhpmcounter8_c => csr.rdata <= csr.mhpmcounter_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8 - low
when csr_hpmcounter9_c | csr_mhpmcounter9_c => csr.rdata <= csr.mhpmcounter_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9 - low
when csr_hpmcounter10_c | csr_mhpmcounter10_c => csr.rdata <= csr.mhpmcounter_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10 - low
when csr_hpmcounter11_c | csr_mhpmcounter11_c => csr.rdata <= csr.mhpmcounter_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11 - low
when csr_hpmcounter12_c | csr_mhpmcounter12_c => csr.rdata <= csr.mhpmcounter_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12 - low
when csr_hpmcounter13_c | csr_mhpmcounter13_c => csr.rdata <= csr.mhpmcounter_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13 - low
when csr_hpmcounter14_c | csr_mhpmcounter14_c => csr.rdata <= csr.mhpmcounter_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14 - low
when csr_hpmcounter15_c | csr_mhpmcounter15_c => csr.rdata <= csr.mhpmcounter_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15 - low
when csr_hpmcounter16_c | csr_mhpmcounter16_c => csr.rdata <= csr.mhpmcounter_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16 - low
when csr_hpmcounter17_c | csr_mhpmcounter17_c => csr.rdata <= csr.mhpmcounter_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17 - low
when csr_hpmcounter18_c | csr_mhpmcounter18_c => csr.rdata <= csr.mhpmcounter_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18 - low
when csr_hpmcounter19_c | csr_mhpmcounter19_c => csr.rdata <= csr.mhpmcounter_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19 - low
when csr_hpmcounter20_c | csr_mhpmcounter20_c => csr.rdata <= csr.mhpmcounter_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20 - low
when csr_hpmcounter21_c | csr_mhpmcounter21_c => csr.rdata <= csr.mhpmcounter_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21 - low
when csr_hpmcounter22_c | csr_mhpmcounter22_c => csr.rdata <= csr.mhpmcounter_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22 - low
when csr_hpmcounter23_c | csr_mhpmcounter23_c => csr.rdata <= csr.mhpmcounter_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23 - low
when csr_hpmcounter24_c | csr_mhpmcounter24_c => csr.rdata <= csr.mhpmcounter_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24 - low
when csr_hpmcounter25_c | csr_mhpmcounter25_c => csr.rdata <= csr.mhpmcounter_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25 - low
when csr_hpmcounter26_c | csr_mhpmcounter26_c => csr.rdata <= csr.mhpmcounter_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26 - low
when csr_hpmcounter27_c | csr_mhpmcounter27_c => csr.rdata <= csr.mhpmcounter_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27 - low
when csr_hpmcounter28_c | csr_mhpmcounter28_c => csr.rdata <= csr.mhpmcounter_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28 - low
when csr_hpmcounter29_c | csr_mhpmcounter29_c => csr.rdata <= csr.mhpmcounter_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29 - low
when csr_hpmcounter30_c | csr_mhpmcounter30_c => csr.rdata <= csr.mhpmcounter_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30 - low
when csr_hpmcounter31_c | csr_mhpmcounter31_c => csr.rdata <= csr.mhpmcounter_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31 - low
 
when csr_hpmcounter3h_c | csr_mhpmcounter3h_c => csr.rdata <= csr.mhpmcounterh_rd(00)(31 downto 0); -- (R)/(W): [m]hpmcounter3h - high
when csr_hpmcounter4h_c | csr_mhpmcounter4h_c => csr.rdata <= csr.mhpmcounterh_rd(01)(31 downto 0); -- (R)/(W): [m]hpmcounter4h - high
when csr_hpmcounter5h_c | csr_mhpmcounter5h_c => csr.rdata <= csr.mhpmcounterh_rd(02)(31 downto 0); -- (R)/(W): [m]hpmcounter5h - high
when csr_hpmcounter6h_c | csr_mhpmcounter6h_c => csr.rdata <= csr.mhpmcounterh_rd(03)(31 downto 0); -- (R)/(W): [m]hpmcounter6h - high
when csr_hpmcounter7h_c | csr_mhpmcounter7h_c => csr.rdata <= csr.mhpmcounterh_rd(04)(31 downto 0); -- (R)/(W): [m]hpmcounter7h - high
when csr_hpmcounter8h_c | csr_mhpmcounter8h_c => csr.rdata <= csr.mhpmcounterh_rd(05)(31 downto 0); -- (R)/(W): [m]hpmcounter8h - high
when csr_hpmcounter9h_c | csr_mhpmcounter9h_c => csr.rdata <= csr.mhpmcounterh_rd(06)(31 downto 0); -- (R)/(W): [m]hpmcounter9h - high
when csr_hpmcounter10h_c | csr_mhpmcounter10h_c => csr.rdata <= csr.mhpmcounterh_rd(07)(31 downto 0); -- (R)/(W): [m]hpmcounter10h - high
when csr_hpmcounter11h_c | csr_mhpmcounter11h_c => csr.rdata <= csr.mhpmcounterh_rd(08)(31 downto 0); -- (R)/(W): [m]hpmcounter11h - high
when csr_hpmcounter12h_c | csr_mhpmcounter12h_c => csr.rdata <= csr.mhpmcounterh_rd(09)(31 downto 0); -- (R)/(W): [m]hpmcounter12h - high
when csr_hpmcounter13h_c | csr_mhpmcounter13h_c => csr.rdata <= csr.mhpmcounterh_rd(10)(31 downto 0); -- (R)/(W): [m]hpmcounter13h - high
when csr_hpmcounter14h_c | csr_mhpmcounter14h_c => csr.rdata <= csr.mhpmcounterh_rd(11)(31 downto 0); -- (R)/(W): [m]hpmcounter14h - high
when csr_hpmcounter15h_c | csr_mhpmcounter15h_c => csr.rdata <= csr.mhpmcounterh_rd(12)(31 downto 0); -- (R)/(W): [m]hpmcounter15h - high
when csr_hpmcounter16h_c | csr_mhpmcounter16h_c => csr.rdata <= csr.mhpmcounterh_rd(13)(31 downto 0); -- (R)/(W): [m]hpmcounter16h - high
when csr_hpmcounter17h_c | csr_mhpmcounter17h_c => csr.rdata <= csr.mhpmcounterh_rd(14)(31 downto 0); -- (R)/(W): [m]hpmcounter17h - high
when csr_hpmcounter18h_c | csr_mhpmcounter18h_c => csr.rdata <= csr.mhpmcounterh_rd(15)(31 downto 0); -- (R)/(W): [m]hpmcounter18h - high
when csr_hpmcounter19h_c | csr_mhpmcounter19h_c => csr.rdata <= csr.mhpmcounterh_rd(16)(31 downto 0); -- (R)/(W): [m]hpmcounter19h - high
when csr_hpmcounter20h_c | csr_mhpmcounter20h_c => csr.rdata <= csr.mhpmcounterh_rd(17)(31 downto 0); -- (R)/(W): [m]hpmcounter20h - high
when csr_hpmcounter21h_c | csr_mhpmcounter21h_c => csr.rdata <= csr.mhpmcounterh_rd(18)(31 downto 0); -- (R)/(W): [m]hpmcounter21h - high
when csr_hpmcounter22h_c | csr_mhpmcounter22h_c => csr.rdata <= csr.mhpmcounterh_rd(19)(31 downto 0); -- (R)/(W): [m]hpmcounter22h - high
when csr_hpmcounter23h_c | csr_mhpmcounter23h_c => csr.rdata <= csr.mhpmcounterh_rd(20)(31 downto 0); -- (R)/(W): [m]hpmcounter23h - high
when csr_hpmcounter24h_c | csr_mhpmcounter24h_c => csr.rdata <= csr.mhpmcounterh_rd(21)(31 downto 0); -- (R)/(W): [m]hpmcounter24h - high
when csr_hpmcounter25h_c | csr_mhpmcounter25h_c => csr.rdata <= csr.mhpmcounterh_rd(22)(31 downto 0); -- (R)/(W): [m]hpmcounter25h - high
when csr_hpmcounter26h_c | csr_mhpmcounter26h_c => csr.rdata <= csr.mhpmcounterh_rd(23)(31 downto 0); -- (R)/(W): [m]hpmcounter26h - high
when csr_hpmcounter27h_c | csr_mhpmcounter27h_c => csr.rdata <= csr.mhpmcounterh_rd(24)(31 downto 0); -- (R)/(W): [m]hpmcounter27h - high
when csr_hpmcounter28h_c | csr_mhpmcounter28h_c => csr.rdata <= csr.mhpmcounterh_rd(25)(31 downto 0); -- (R)/(W): [m]hpmcounter28h - high
when csr_hpmcounter29h_c | csr_mhpmcounter29h_c => csr.rdata <= csr.mhpmcounterh_rd(26)(31 downto 0); -- (R)/(W): [m]hpmcounter29h - high
when csr_hpmcounter30h_c | csr_mhpmcounter30h_c => csr.rdata <= csr.mhpmcounterh_rd(27)(31 downto 0); -- (R)/(W): [m]hpmcounter30h - high
when csr_hpmcounter31h_c | csr_mhpmcounter31h_c => csr.rdata <= csr.mhpmcounterh_rd(28)(31 downto 0); -- (R)/(W): [m]hpmcounter31h - high
 
-- machine information registers --
when csr_mvendorid_c => -- R/-: mvendorid - vendor ID
csr.rdata <= (others => '0');
2050,7 → 2356,6
when csr_mzext_c => -- R/-: mzext - available Z* extensions
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension
csr.rdata(2) <= bool_to_ulogic_f(PMP_USE); -- RISC-V physical memory protection
 
-- undefined/unavailable --
when others =>
/rtl/core/neorv32_package.vhd
3,7 → 3,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
52,17 → 52,13
-- CPU core --
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
 
-- physical memory protection (PMP) --
constant pmp_num_regions_c : natural := 2; -- number of regions (1..8)
constant pmp_min_granularity_c : natural := 64*1024; -- minimal region size (granularity), min 8 bytes, has to be a power of 2
 
-- Architecture Constants (do not modify!)= -----------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040904"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01040908"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a physical register that has to be initialized to zero by the HW
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
 
-- Helper Functions -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
82,8 → 78,8
 
-- Internal Types -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
type pmp_ctrl_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
type pmp_addr_if_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(33 downto 0);
type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
 
-- Processor-Internal Address Space Layout ------------------------------------------------
-- -------------------------------------------------------------------------------------------
90,7 → 86,7
-- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
constant imem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
constant dmem_base_c : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
--> memory sizes are configured via top's generics
--> internal data/instruction memory sizes are configured via top's generics
 
-- Internal Bootloader ROM --
constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed!
325,7 → 321,6
constant funct3_csrrw_c : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
constant funct3_csrrs_c : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
constant funct3_csrrc_c : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
--
constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
350,54 → 345,276
-- RISC-V CSR Addresses -------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- read/write CSRs --
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300"; -- mstatus
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301"; -- misa
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304"; -- mie
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305"; -- mtvec
constant csr_mcounteren_c : std_ulogic_vector(11 downto 0) := x"306"; -- mcounteren
constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := x"310"; -- mstatush
constant csr_mstatus_c : std_ulogic_vector(11 downto 0) := x"300";
constant csr_misa_c : std_ulogic_vector(11 downto 0) := x"301";
constant csr_mie_c : std_ulogic_vector(11 downto 0) := x"304";
constant csr_mtvec_c : std_ulogic_vector(11 downto 0) := x"305";
constant csr_mcounteren_c : std_ulogic_vector(11 downto 0) := x"306";
constant csr_mstatush_c : std_ulogic_vector(11 downto 0) := x"310";
--
constant csr_mcountinhibit_c : std_ulogic_vector(11 downto 0) := x"320"; -- mcountinhibit
constant csr_mcountinhibit_c : std_ulogic_vector(11 downto 0) := x"320";
--
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340"; -- mscratch
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341"; -- mepc
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342"; -- mcause
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343"; -- mtval
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344"; -- mip
constant csr_mhpmevent3_c : std_ulogic_vector(11 downto 0) := x"323";
constant csr_mhpmevent4_c : std_ulogic_vector(11 downto 0) := x"324";
constant csr_mhpmevent5_c : std_ulogic_vector(11 downto 0) := x"325";
constant csr_mhpmevent6_c : std_ulogic_vector(11 downto 0) := x"326";
constant csr_mhpmevent7_c : std_ulogic_vector(11 downto 0) := x"327";
constant csr_mhpmevent8_c : std_ulogic_vector(11 downto 0) := x"328";
constant csr_mhpmevent9_c : std_ulogic_vector(11 downto 0) := x"329";
constant csr_mhpmevent10_c : std_ulogic_vector(11 downto 0) := x"32a";
constant csr_mhpmevent11_c : std_ulogic_vector(11 downto 0) := x"32b";
constant csr_mhpmevent12_c : std_ulogic_vector(11 downto 0) := x"32c";
constant csr_mhpmevent13_c : std_ulogic_vector(11 downto 0) := x"32d";
constant csr_mhpmevent14_c : std_ulogic_vector(11 downto 0) := x"32e";
constant csr_mhpmevent15_c : std_ulogic_vector(11 downto 0) := x"32f";
constant csr_mhpmevent16_c : std_ulogic_vector(11 downto 0) := x"330";
constant csr_mhpmevent17_c : std_ulogic_vector(11 downto 0) := x"331";
constant csr_mhpmevent18_c : std_ulogic_vector(11 downto 0) := x"332";
constant csr_mhpmevent19_c : std_ulogic_vector(11 downto 0) := x"333";
constant csr_mhpmevent20_c : std_ulogic_vector(11 downto 0) := x"334";
constant csr_mhpmevent21_c : std_ulogic_vector(11 downto 0) := x"335";
constant csr_mhpmevent22_c : std_ulogic_vector(11 downto 0) := x"336";
constant csr_mhpmevent23_c : std_ulogic_vector(11 downto 0) := x"337";
constant csr_mhpmevent24_c : std_ulogic_vector(11 downto 0) := x"338";
constant csr_mhpmevent25_c : std_ulogic_vector(11 downto 0) := x"339";
constant csr_mhpmevent26_c : std_ulogic_vector(11 downto 0) := x"33a";
constant csr_mhpmevent27_c : std_ulogic_vector(11 downto 0) := x"33b";
constant csr_mhpmevent28_c : std_ulogic_vector(11 downto 0) := x"33c";
constant csr_mhpmevent29_c : std_ulogic_vector(11 downto 0) := x"33d";
constant csr_mhpmevent30_c : std_ulogic_vector(11 downto 0) := x"33e";
constant csr_mhpmevent31_c : std_ulogic_vector(11 downto 0) := x"33f";
--
constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := x"3a0"; -- pmpcfg0
constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := x"3a1"; -- pmpcfg1
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340";
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341";
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342";
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343";
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344";
--
constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := x"3b0"; -- pmpaddr0
constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := x"3b1"; -- pmpaddr1
constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := x"3b2"; -- pmpaddr2
constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := x"3b3"; -- pmpaddr3
constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := x"3b4"; -- pmpaddr4
constant csr_pmpaddr5_c : std_ulogic_vector(11 downto 0) := x"3b5"; -- pmpaddr5
constant csr_pmpaddr6_c : std_ulogic_vector(11 downto 0) := x"3b6"; -- pmpaddr6
constant csr_pmpaddr7_c : std_ulogic_vector(11 downto 0) := x"3b7"; -- pmpaddr7
constant csr_pmpcfg0_c : std_ulogic_vector(11 downto 0) := x"3a0";
constant csr_pmpcfg1_c : std_ulogic_vector(11 downto 0) := x"3a1";
constant csr_pmpcfg2_c : std_ulogic_vector(11 downto 0) := x"3a2";
constant csr_pmpcfg3_c : std_ulogic_vector(11 downto 0) := x"3a3";
constant csr_pmpcfg4_c : std_ulogic_vector(11 downto 0) := x"3a4";
constant csr_pmpcfg5_c : std_ulogic_vector(11 downto 0) := x"3a5";
constant csr_pmpcfg6_c : std_ulogic_vector(11 downto 0) := x"3a6";
constant csr_pmpcfg7_c : std_ulogic_vector(11 downto 0) := x"3a7";
constant csr_pmpcfg8_c : std_ulogic_vector(11 downto 0) := x"3a8";
constant csr_pmpcfg9_c : std_ulogic_vector(11 downto 0) := x"3a9";
constant csr_pmpcfg10_c : std_ulogic_vector(11 downto 0) := x"3aa";
constant csr_pmpcfg11_c : std_ulogic_vector(11 downto 0) := x"3ab";
constant csr_pmpcfg12_c : std_ulogic_vector(11 downto 0) := x"3ac";
constant csr_pmpcfg13_c : std_ulogic_vector(11 downto 0) := x"3ad";
constant csr_pmpcfg14_c : std_ulogic_vector(11 downto 0) := x"3ae";
constant csr_pmpcfg15_c : std_ulogic_vector(11 downto 0) := x"3af";
--
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00"; -- mcycle
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02"; -- minstret
constant csr_pmpaddr0_c : std_ulogic_vector(11 downto 0) := x"3b0";
constant csr_pmpaddr1_c : std_ulogic_vector(11 downto 0) := x"3b1";
constant csr_pmpaddr2_c : std_ulogic_vector(11 downto 0) := x"3b2";
constant csr_pmpaddr3_c : std_ulogic_vector(11 downto 0) := x"3b3";
constant csr_pmpaddr4_c : std_ulogic_vector(11 downto 0) := x"3b4";
constant csr_pmpaddr5_c : std_ulogic_vector(11 downto 0) := x"3b5";
constant csr_pmpaddr6_c : std_ulogic_vector(11 downto 0) := x"3b6";
constant csr_pmpaddr7_c : std_ulogic_vector(11 downto 0) := x"3b7";
constant csr_pmpaddr8_c : std_ulogic_vector(11 downto 0) := x"3b8";
constant csr_pmpaddr9_c : std_ulogic_vector(11 downto 0) := x"3b9";
constant csr_pmpaddr10_c : std_ulogic_vector(11 downto 0) := x"3ba";
constant csr_pmpaddr11_c : std_ulogic_vector(11 downto 0) := x"3bb";
constant csr_pmpaddr12_c : std_ulogic_vector(11 downto 0) := x"3bc";
constant csr_pmpaddr13_c : std_ulogic_vector(11 downto 0) := x"3bd";
constant csr_pmpaddr14_c : std_ulogic_vector(11 downto 0) := x"3be";
constant csr_pmpaddr15_c : std_ulogic_vector(11 downto 0) := x"3bf";
constant csr_pmpaddr16_c : std_ulogic_vector(11 downto 0) := x"3c0";
constant csr_pmpaddr17_c : std_ulogic_vector(11 downto 0) := x"3c1";
constant csr_pmpaddr18_c : std_ulogic_vector(11 downto 0) := x"3c2";
constant csr_pmpaddr19_c : std_ulogic_vector(11 downto 0) := x"3c3";
constant csr_pmpaddr20_c : std_ulogic_vector(11 downto 0) := x"3c4";
constant csr_pmpaddr21_c : std_ulogic_vector(11 downto 0) := x"3c5";
constant csr_pmpaddr22_c : std_ulogic_vector(11 downto 0) := x"3c6";
constant csr_pmpaddr23_c : std_ulogic_vector(11 downto 0) := x"3c7";
constant csr_pmpaddr24_c : std_ulogic_vector(11 downto 0) := x"3c8";
constant csr_pmpaddr25_c : std_ulogic_vector(11 downto 0) := x"3c9";
constant csr_pmpaddr26_c : std_ulogic_vector(11 downto 0) := x"3ca";
constant csr_pmpaddr27_c : std_ulogic_vector(11 downto 0) := x"3cb";
constant csr_pmpaddr28_c : std_ulogic_vector(11 downto 0) := x"3cc";
constant csr_pmpaddr29_c : std_ulogic_vector(11 downto 0) := x"3cd";
constant csr_pmpaddr30_c : std_ulogic_vector(11 downto 0) := x"3ce";
constant csr_pmpaddr31_c : std_ulogic_vector(11 downto 0) := x"3cf";
constant csr_pmpaddr32_c : std_ulogic_vector(11 downto 0) := x"3d0";
constant csr_pmpaddr33_c : std_ulogic_vector(11 downto 0) := x"3d1";
constant csr_pmpaddr34_c : std_ulogic_vector(11 downto 0) := x"3d2";
constant csr_pmpaddr35_c : std_ulogic_vector(11 downto 0) := x"3d3";
constant csr_pmpaddr36_c : std_ulogic_vector(11 downto 0) := x"3d4";
constant csr_pmpaddr37_c : std_ulogic_vector(11 downto 0) := x"3d5";
constant csr_pmpaddr38_c : std_ulogic_vector(11 downto 0) := x"3d6";
constant csr_pmpaddr39_c : std_ulogic_vector(11 downto 0) := x"3d7";
constant csr_pmpaddr40_c : std_ulogic_vector(11 downto 0) := x"3d8";
constant csr_pmpaddr41_c : std_ulogic_vector(11 downto 0) := x"3d9";
constant csr_pmpaddr42_c : std_ulogic_vector(11 downto 0) := x"3da";
constant csr_pmpaddr43_c : std_ulogic_vector(11 downto 0) := x"3db";
constant csr_pmpaddr44_c : std_ulogic_vector(11 downto 0) := x"3dc";
constant csr_pmpaddr45_c : std_ulogic_vector(11 downto 0) := x"3dd";
constant csr_pmpaddr46_c : std_ulogic_vector(11 downto 0) := x"3de";
constant csr_pmpaddr47_c : std_ulogic_vector(11 downto 0) := x"3df";
constant csr_pmpaddr48_c : std_ulogic_vector(11 downto 0) := x"3e0";
constant csr_pmpaddr49_c : std_ulogic_vector(11 downto 0) := x"3e1";
constant csr_pmpaddr50_c : std_ulogic_vector(11 downto 0) := x"3e2";
constant csr_pmpaddr51_c : std_ulogic_vector(11 downto 0) := x"3e3";
constant csr_pmpaddr52_c : std_ulogic_vector(11 downto 0) := x"3e4";
constant csr_pmpaddr53_c : std_ulogic_vector(11 downto 0) := x"3e5";
constant csr_pmpaddr54_c : std_ulogic_vector(11 downto 0) := x"3e6";
constant csr_pmpaddr55_c : std_ulogic_vector(11 downto 0) := x"3e7";
constant csr_pmpaddr56_c : std_ulogic_vector(11 downto 0) := x"3e8";
constant csr_pmpaddr57_c : std_ulogic_vector(11 downto 0) := x"3e9";
constant csr_pmpaddr58_c : std_ulogic_vector(11 downto 0) := x"3ea";
constant csr_pmpaddr59_c : std_ulogic_vector(11 downto 0) := x"3eb";
constant csr_pmpaddr60_c : std_ulogic_vector(11 downto 0) := x"3ec";
constant csr_pmpaddr61_c : std_ulogic_vector(11 downto 0) := x"3ed";
constant csr_pmpaddr62_c : std_ulogic_vector(11 downto 0) := x"3ee";
constant csr_pmpaddr63_c : std_ulogic_vector(11 downto 0) := x"3ef";
--
constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := x"b80"; -- mcycleh
constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := x"b82"; -- minstreth
constant csr_mcycle_c : std_ulogic_vector(11 downto 0) := x"b00";
constant csr_minstret_c : std_ulogic_vector(11 downto 0) := x"b02";
--
constant csr_mhpmcounter3_c : std_ulogic_vector(11 downto 0) := x"b03";
constant csr_mhpmcounter4_c : std_ulogic_vector(11 downto 0) := x"b04";
constant csr_mhpmcounter5_c : std_ulogic_vector(11 downto 0) := x"b05";
constant csr_mhpmcounter6_c : std_ulogic_vector(11 downto 0) := x"b06";
constant csr_mhpmcounter7_c : std_ulogic_vector(11 downto 0) := x"b07";
constant csr_mhpmcounter8_c : std_ulogic_vector(11 downto 0) := x"b08";
constant csr_mhpmcounter9_c : std_ulogic_vector(11 downto 0) := x"b09";
constant csr_mhpmcounter10_c : std_ulogic_vector(11 downto 0) := x"b0a";
constant csr_mhpmcounter11_c : std_ulogic_vector(11 downto 0) := x"b0b";
constant csr_mhpmcounter12_c : std_ulogic_vector(11 downto 0) := x"b0c";
constant csr_mhpmcounter13_c : std_ulogic_vector(11 downto 0) := x"b0d";
constant csr_mhpmcounter14_c : std_ulogic_vector(11 downto 0) := x"b0e";
constant csr_mhpmcounter15_c : std_ulogic_vector(11 downto 0) := x"b0f";
constant csr_mhpmcounter16_c : std_ulogic_vector(11 downto 0) := x"b10";
constant csr_mhpmcounter17_c : std_ulogic_vector(11 downto 0) := x"b11";
constant csr_mhpmcounter18_c : std_ulogic_vector(11 downto 0) := x"b12";
constant csr_mhpmcounter19_c : std_ulogic_vector(11 downto 0) := x"b13";
constant csr_mhpmcounter20_c : std_ulogic_vector(11 downto 0) := x"b14";
constant csr_mhpmcounter21_c : std_ulogic_vector(11 downto 0) := x"b15";
constant csr_mhpmcounter22_c : std_ulogic_vector(11 downto 0) := x"b16";
constant csr_mhpmcounter23_c : std_ulogic_vector(11 downto 0) := x"b17";
constant csr_mhpmcounter24_c : std_ulogic_vector(11 downto 0) := x"b18";
constant csr_mhpmcounter25_c : std_ulogic_vector(11 downto 0) := x"b19";
constant csr_mhpmcounter26_c : std_ulogic_vector(11 downto 0) := x"b1a";
constant csr_mhpmcounter27_c : std_ulogic_vector(11 downto 0) := x"b1b";
constant csr_mhpmcounter28_c : std_ulogic_vector(11 downto 0) := x"b1c";
constant csr_mhpmcounter29_c : std_ulogic_vector(11 downto 0) := x"b1d";
constant csr_mhpmcounter30_c : std_ulogic_vector(11 downto 0) := x"b1e";
constant csr_mhpmcounter31_c : std_ulogic_vector(11 downto 0) := x"b1f";
--
constant csr_mcycleh_c : std_ulogic_vector(11 downto 0) := x"b80";
constant csr_minstreth_c : std_ulogic_vector(11 downto 0) := x"b82";
--
constant csr_mhpmcounter3h_c : std_ulogic_vector(11 downto 0) := x"b83";
constant csr_mhpmcounter4h_c : std_ulogic_vector(11 downto 0) := x"b84";
constant csr_mhpmcounter5h_c : std_ulogic_vector(11 downto 0) := x"b85";
constant csr_mhpmcounter6h_c : std_ulogic_vector(11 downto 0) := x"b86";
constant csr_mhpmcounter7h_c : std_ulogic_vector(11 downto 0) := x"b87";
constant csr_mhpmcounter8h_c : std_ulogic_vector(11 downto 0) := x"b88";
constant csr_mhpmcounter9h_c : std_ulogic_vector(11 downto 0) := x"b89";
constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a";
constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b";
constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c";
constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d";
constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e";
constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f";
constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90";
constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91";
constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92";
constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93";
constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94";
constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95";
constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96";
constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97";
constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98";
constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99";
constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a";
constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b";
constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c";
constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d";
constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e";
constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f";
 
-- read-only CSRs --
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00"; -- cycle
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01"; -- time
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02"; -- instret
constant csr_cycle_c : std_ulogic_vector(11 downto 0) := x"c00";
constant csr_time_c : std_ulogic_vector(11 downto 0) := x"c01";
constant csr_instret_c : std_ulogic_vector(11 downto 0) := x"c02";
--
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80"; -- cycleh
constant csr_timeh_c : std_ulogic_vector(11 downto 0) := x"c81"; -- timeh
constant csr_instreth_c : std_ulogic_vector(11 downto 0) := x"c82"; -- instreth
constant csr_hpmcounter3_c : std_ulogic_vector(11 downto 0) := x"c03";
constant csr_hpmcounter4_c : std_ulogic_vector(11 downto 0) := x"c04";
constant csr_hpmcounter5_c : std_ulogic_vector(11 downto 0) := x"c05";
constant csr_hpmcounter6_c : std_ulogic_vector(11 downto 0) := x"c06";
constant csr_hpmcounter7_c : std_ulogic_vector(11 downto 0) := x"c07";
constant csr_hpmcounter8_c : std_ulogic_vector(11 downto 0) := x"c08";
constant csr_hpmcounter9_c : std_ulogic_vector(11 downto 0) := x"c09";
constant csr_hpmcounter10_c : std_ulogic_vector(11 downto 0) := x"c0a";
constant csr_hpmcounter11_c : std_ulogic_vector(11 downto 0) := x"c0b";
constant csr_hpmcounter12_c : std_ulogic_vector(11 downto 0) := x"c0c";
constant csr_hpmcounter13_c : std_ulogic_vector(11 downto 0) := x"c0d";
constant csr_hpmcounter14_c : std_ulogic_vector(11 downto 0) := x"c0e";
constant csr_hpmcounter15_c : std_ulogic_vector(11 downto 0) := x"c0f";
constant csr_hpmcounter16_c : std_ulogic_vector(11 downto 0) := x"c10";
constant csr_hpmcounter17_c : std_ulogic_vector(11 downto 0) := x"c11";
constant csr_hpmcounter18_c : std_ulogic_vector(11 downto 0) := x"c12";
constant csr_hpmcounter19_c : std_ulogic_vector(11 downto 0) := x"c13";
constant csr_hpmcounter20_c : std_ulogic_vector(11 downto 0) := x"c14";
constant csr_hpmcounter21_c : std_ulogic_vector(11 downto 0) := x"c15";
constant csr_hpmcounter22_c : std_ulogic_vector(11 downto 0) := x"c16";
constant csr_hpmcounter23_c : std_ulogic_vector(11 downto 0) := x"c17";
constant csr_hpmcounter24_c : std_ulogic_vector(11 downto 0) := x"c18";
constant csr_hpmcounter25_c : std_ulogic_vector(11 downto 0) := x"c19";
constant csr_hpmcounter26_c : std_ulogic_vector(11 downto 0) := x"c1a";
constant csr_hpmcounter27_c : std_ulogic_vector(11 downto 0) := x"c1b";
constant csr_hpmcounter28_c : std_ulogic_vector(11 downto 0) := x"c1c";
constant csr_hpmcounter29_c : std_ulogic_vector(11 downto 0) := x"c1d";
constant csr_hpmcounter30_c : std_ulogic_vector(11 downto 0) := x"c1e";
constant csr_hpmcounter31_c : std_ulogic_vector(11 downto 0) := x"c1f";
--
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11"; -- mvendorid
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12"; -- marchid
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13"; -- mimpid
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14"; -- mhartid
constant csr_cycleh_c : std_ulogic_vector(11 downto 0) := x"c80";
constant csr_timeh_c : std_ulogic_vector(11 downto 0) := x"c81";
constant csr_instreth_c : std_ulogic_vector(11 downto 0) := x"c82";
--
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0"; -- mzext (neorv32-custom)
constant csr_hpmcounter3h_c : std_ulogic_vector(11 downto 0) := x"c83";
constant csr_hpmcounter4h_c : std_ulogic_vector(11 downto 0) := x"c84";
constant csr_hpmcounter5h_c : std_ulogic_vector(11 downto 0) := x"c85";
constant csr_hpmcounter6h_c : std_ulogic_vector(11 downto 0) := x"c86";
constant csr_hpmcounter7h_c : std_ulogic_vector(11 downto 0) := x"c87";
constant csr_hpmcounter8h_c : std_ulogic_vector(11 downto 0) := x"c88";
constant csr_hpmcounter9h_c : std_ulogic_vector(11 downto 0) := x"c89";
constant csr_hpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"c8a";
constant csr_hpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"c8b";
constant csr_hpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"c8c";
constant csr_hpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"c8d";
constant csr_hpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"c8e";
constant csr_hpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"c8f";
constant csr_hpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"c90";
constant csr_hpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"c91";
constant csr_hpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"c92";
constant csr_hpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"c93";
constant csr_hpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"c94";
constant csr_hpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"c95";
constant csr_hpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"c96";
constant csr_hpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"c97";
constant csr_hpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"c98";
constant csr_hpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"c99";
constant csr_hpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"c9a";
constant csr_hpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"c9b";
constant csr_hpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"c9c";
constant csr_hpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"c9d";
constant csr_hpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"c9e";
constant csr_hpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"c9f";
--
constant csr_mvendorid_c : std_ulogic_vector(11 downto 0) := x"f11";
constant csr_marchid_c : std_ulogic_vector(11 downto 0) := x"f12";
constant csr_mimpid_c : std_ulogic_vector(11 downto 0) := x"f13";
constant csr_mhartid_c : std_ulogic_vector(11 downto 0) := x"f14";
 
-- custom read-only CSRs --
constant csr_mzext_c : std_ulogic_vector(11 downto 0) := x"fc0";
 
-- Co-Processor Operations ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- cp ids --
486,6 → 703,25
constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
 
-- HPM Event System -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hpmcnt_event_cy_c : natural := 0; -- Active cycle
constant hpmcnt_event_never_c : natural := 1;
constant hpmcnt_event_ir_c : natural := 2; -- Retired instruction
constant hpmcnt_event_cir_c : natural := 3; -- Retired compressed instruction
constant hpmcnt_event_wait_if_c : natural := 4; -- Instruction fetch memory wait cycle
constant hpmcnt_event_wait_ii_c : natural := 5; -- Instruction issue wait cycle
constant hpmcnt_event_load_c : natural := 6; -- Load operation
constant hpmcnt_event_store_c : natural := 7; -- Store operation
constant hpmcnt_event_wait_ls_c : natural := 8; -- Load/store memory wait cycle
constant hpmcnt_event_jump_c : natural := 9; -- Unconditional jump
constant hpmcnt_event_branch_c : natural := 10; -- Conditional branch (taken or not taken)
constant hpmcnt_event_tbranch_c : natural := 11; -- Conditional taken branch
constant hpmcnt_event_trap_c : natural := 12; -- Entered trap
constant hpmcnt_event_illegal_c : natural := 13; -- Illegal instruction exception
--
constant hpmcnt_event_size_c : natural := 14; -- length of this list
 
-- Clock Generator ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant clk_div2_c : natural := 0;
518,7 → 754,10
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
608,7 → 847,10
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false -- implement PMP?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29)
);
port (
-- global control --
667,7 → 909,10
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
-- Physical memory protection (PMP) --
PMP_USE : boolean := false -- implement physical memory protection?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29)
);
port (
-- global control --
797,7 → 1042,8
generic (
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
-- Physical memory protection (PMP) --
PMP_USE : boolean := false; -- implement physical memory protection?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Bus Timeout --
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
);
/rtl/core/neorv32_top.vhd
9,7 → 9,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
64,7 → 64,10
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
343,7 → 346,10
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE => PMP_USE -- implement PMP?
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => HPM_NUM_CNTS -- number of inmplemnted HPM counters (0..29)
)
port map (
-- global control --
/rtl/core/neorv32_uart.vhd
1,8 → 1,8
-- #################################################################################################
-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART) >> #
-- # ********************************************************************************************* #
-- # Fixed frame config: 8-bit, no parity bit, 1 stop bit, programmable BAUD rate (via clock pre- #
-- # scaler and BAUD value config register. #
-- # Frame configuration: 1 start bit, 8 bit data, optional parity bit (even/odd), 1 stop bit, #
-- # programmable BAUD rate via clock pre-scaler and BAUD value config register. #
-- # Interrupt: UART_RX_available or UART_TX_done #
-- # #
-- # SIMULATION: #
104,10 → 104,12
--
constant ctrl_uart_sim_en_c : natural := 12; -- r/w: UART SIMULATION OUTPUT enable
--
constant ctrl_uart_pmode0_c : natural := 22; -- r/w: Parity config (0=even; 1=odd)
constant ctrl_uart_pmode1_c : natural := 23; -- r/w: Enable parity bit
constant ctrl_uart_prsc0_c : natural := 24; -- r/w: UART baud prsc bit 0
constant ctrl_uart_prsc1_c : natural := 25; -- r/w: UART baud prsc bit 1
constant ctrl_uart_prsc2_c : natural := 26; -- r/w: UART baud prsc bit 2
constant ctrl_uart_rxovr_c : natural := 27; -- r/-: UART RX overrun
--
constant ctrl_uart_en_c : natural := 28; -- r/w: UART enable
constant ctrl_uart_rx_irq_c : natural := 29; -- r/w: UART rx done interrupt enable
constant ctrl_uart_tx_irq_c : natural := 30; -- r/w: UART tx done interrupt enable
114,7 → 116,10
constant ctrl_uart_tx_busy_c : natural := 31; -- r/-: UART transmitter is busy
 
-- data register flags --
constant data_rx_avail_c : natural := 31; -- r/-: Rx data available/valid
constant data_rx_avail_c : natural := 31; -- r/-: Rx data available
constant data_rx_overr_c : natural := 30; -- r/-: Rx data overrun
constant data_rx_ferr_c : natural := 29; -- r/-: Rx frame error
constant data_rx_perr_c : natural := 28; -- r/-: Rx parity error
 
-- access control --
signal acc_en : std_ulogic; -- module access enable
125,22 → 130,33
-- clock generator --
signal uart_clk : std_ulogic;
 
-- numbers of bits in transmission frame --
signal num_bits : std_ulogic_vector(03 downto 0);
 
-- uart tx unit --
signal uart_tx_busy : std_ulogic;
signal uart_tx_done : std_ulogic;
signal uart_tx_bitcnt : std_ulogic_vector(03 downto 0);
signal uart_tx_sreg : std_ulogic_vector(09 downto 0) := (others => '1'); -- just for simulation
signal uart_tx_baud_cnt : std_ulogic_vector(11 downto 0);
type uart_tx_t is record
busy : std_ulogic;
done : std_ulogic;
bitcnt : std_ulogic_vector(03 downto 0);
sreg : std_ulogic_vector(10 downto 0);
baud_cnt : std_ulogic_vector(11 downto 0);
end record;
signal uart_tx : uart_tx_t;
 
-- uart rx unit --
signal uart_rx_sync : std_ulogic_vector(04 downto 0);
signal uart_rx_avail : std_ulogic_vector(01 downto 0);
signal uart_rx_busy : std_ulogic;
signal uart_rx_busy_ff : std_ulogic;
signal uart_rx_bitcnt : std_ulogic_vector(03 downto 0);
signal uart_rx_sreg : std_ulogic_vector(08 downto 0);
signal uart_rx_reg : std_ulogic_vector(07 downto 0);
signal uart_rx_baud_cnt : std_ulogic_vector(11 downto 0);
type uart_rx_t is record
sync : std_ulogic_vector(04 downto 0);
avail : std_ulogic_vector(01 downto 0);
busy : std_ulogic;
busy_ff : std_ulogic;
bitcnt : std_ulogic_vector(03 downto 0);
sreg : std_ulogic_vector(09 downto 0);
data : std_ulogic_vector(07 downto 0);
baud_cnt : std_ulogic_vector(11 downto 0);
ferr : std_ulogic; -- frame error (stop bit not set)
perr : std_ulogic; -- parity error
end record;
signal uart_rx : uart_rx_t;
 
begin
 
161,7 → 177,14
-- write access --
if (wr_en = '1') then
if (addr = uart_ctrl_addr_c) then
ctrl <= data_i;
ctrl <= (others => '0');
ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= data_i(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
ctrl(ctrl_uart_sim_en_c) <= data_i(ctrl_uart_sim_en_c);
ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= data_i(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= data_i(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
ctrl(ctrl_uart_en_c) <= data_i(ctrl_uart_en_c);
ctrl(ctrl_uart_rx_irq_c) <= data_i(ctrl_uart_rx_irq_c);
ctrl(ctrl_uart_tx_irq_c) <= data_i(ctrl_uart_tx_irq_c);
end if;
end if;
-- read access --
168,18 → 191,31
data_o <= (others => '0');
if (rd_en = '1') then
if (addr = uart_ctrl_addr_c) then
data_o <= ctrl; -- default
data_o(ctrl_uart_rxovr_c) <= uart_rx_avail(0) and uart_rx_avail(1);
data_o(ctrl_uart_tx_busy_c) <= uart_tx_busy;
data_o(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
data_o(ctrl_uart_sim_en_c) <= ctrl(ctrl_uart_sim_en_c);
data_o(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
data_o(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
data_o(ctrl_uart_rx_irq_c) <= ctrl(ctrl_uart_rx_irq_c);
data_o(ctrl_uart_tx_irq_c) <= ctrl(ctrl_uart_tx_irq_c);
data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
else -- uart_rtx_addr_c
data_o(data_rx_avail_c) <= uart_rx_avail(0);
data_o(07 downto 0) <= uart_rx_reg;
data_o(data_rx_avail_c) <= uart_rx.avail(0);
data_o(data_rx_overr_c) <= uart_rx.avail(0) and uart_rx.avail(1);
data_o(data_rx_ferr_c) <= uart_rx.ferr;
data_o(data_rx_perr_c) <= uart_rx.perr;
data_o(07 downto 0) <= uart_rx.data;
end if;
end if;
end if;
end process rw_access;
 
-- number of bits to be sampled --
-- if parity flag is ENABLED: 11 bit (1 start bit + 8 data bits + 1 parity bit + 1 stop bit)
-- if parity flag is DISABLED: 10 bit (1 start bit + 8 data bits + 1 stop bit)
num_bits <= "1011" when (ctrl(ctrl_uart_pmode1_c) = '1') else "1010";
 
 
-- Clock Selection ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- clock enable --
195,30 → 231,35
begin
if rising_edge(clk_i) then
-- serial engine --
uart_tx_done <= '0';
if (uart_tx_busy = '0') or (ctrl(ctrl_uart_en_c) = '0') or (ctrl(ctrl_uart_sim_en_c) = '1') then -- idle or disabled or in SIM mode
uart_tx_busy <= '0';
uart_tx_baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
uart_tx_bitcnt <= "1010"; -- 10 bit
uart_tx.done <= '0';
if (uart_tx.busy = '0') or (ctrl(ctrl_uart_en_c) = '0') or (ctrl(ctrl_uart_sim_en_c) = '1') then -- idle or disabled or in SIM mode
uart_tx.busy <= '0';
uart_tx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
uart_tx.bitcnt <= num_bits;
uart_tx.sreg(0) <= '1';
if (wr_en = '1') and (ctrl(ctrl_uart_en_c) = '1') and (addr = uart_rtx_addr_c) and (ctrl(ctrl_uart_sim_en_c) = '0') then -- write trigger and not in SIM mode
uart_tx_sreg <= '1' & data_i(7 downto 0) & '0'; -- stopbit & data & startbit
uart_tx_busy <= '1';
if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
uart_tx.sreg <= '1' & (xor_all_f(data_i(7 downto 0)) xor ctrl(ctrl_uart_pmode0_c)) & data_i(7 downto 0) & '0'; -- stopbit & parity bit & data & startbit
else
uart_tx.sreg <= '1' & '1' & data_i(7 downto 0) & '0'; -- (dummy fill-bit &) stopbit & data & startbit
end if;
uart_tx.busy <= '1';
end if;
elsif (uart_clk = '1') then
if (uart_tx_baud_cnt = x"000") then
uart_tx_baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
uart_tx_bitcnt <= std_ulogic_vector(unsigned(uart_tx_bitcnt) - 1);
uart_tx_sreg <= '1' & uart_tx_sreg(9 downto 1);
if (uart_tx_bitcnt = "0000") then
uart_tx_busy <= '0'; -- done
uart_tx_done <= '1';
end if;
if (uart_tx.baud_cnt = x"000") then
uart_tx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
uart_tx.bitcnt <= std_ulogic_vector(unsigned(uart_tx.bitcnt) - 1);
uart_tx.sreg <= '1' & uart_tx.sreg(uart_tx.sreg'left downto 1);
else
uart_tx_baud_cnt <= std_ulogic_vector(unsigned(uart_tx_baud_cnt) - 1);
uart_tx.baud_cnt <= std_ulogic_vector(unsigned(uart_tx.baud_cnt) - 1);
end if;
if (uart_tx.bitcnt = "0000") then
uart_tx.busy <= '0'; -- done
uart_tx.done <= '1';
end if;
end if;
-- transmitter output --
uart_txd_o <= uart_tx_sreg(0);
uart_txd_o <= uart_tx.sreg(0);
end if;
end process uart_tx_unit;
 
229,38 → 270,46
begin
if rising_edge(clk_i) then
-- input synchronizer --
uart_rx_sync <= uart_rxd_i & uart_rx_sync(4 downto 1);
uart_rx.sync <= uart_rxd_i & uart_rx.sync(4 downto 1);
 
-- serial engine --
if (uart_rx_busy = '0') or (ctrl(ctrl_uart_en_c) = '0') then -- idle or disabled
uart_rx_busy <= '0';
uart_rx_baud_cnt <= '0' & ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud01_c); -- half baud rate to sample in middle of bit
uart_rx_bitcnt <= "1001"; -- 9 bit (startbit + 8 data bits, ignore stop bit/s)
if (ctrl(ctrl_uart_en_c) = '0') then
uart_rx_reg <= (others => '0'); -- to ensure defined state when reading
elsif (uart_rx_sync(2 downto 0) = "001") then -- start bit? (falling edge)
uart_rx_busy <= '1';
if (uart_rx.busy = '0') or (ctrl(ctrl_uart_en_c) = '0') then -- idle or disabled
uart_rx.busy <= '0';
uart_rx.baud_cnt <= '0' & ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud01_c); -- half baud delay at the beginning to sample in the middle of each bit
uart_rx.bitcnt <= num_bits;
if (ctrl(ctrl_uart_en_c) = '0') then -- to ensure defined state when reading
uart_rx.perr <= '0';
uart_rx.ferr <= '0';
uart_rx.data <= (others => '0');
elsif (uart_rx.sync(2 downto 0) = "001") then -- start bit? (falling edge)
uart_rx.busy <= '1';
end if;
elsif (uart_clk = '1') then
if (uart_rx_baud_cnt = x"000") then
uart_rx_baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
uart_rx_bitcnt <= std_ulogic_vector(unsigned(uart_rx_bitcnt) - 1);
uart_rx_sreg <= uart_rx_sync(0) & uart_rx_sreg(8 downto 1);
if (uart_rx_bitcnt = "0000") then
uart_rx_busy <= '0'; -- done
uart_rx_reg <= uart_rx_sreg(8 downto 1);
end if;
if (uart_rx.baud_cnt = x"000") then
uart_rx.baud_cnt <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
uart_rx.bitcnt <= std_ulogic_vector(unsigned(uart_rx.bitcnt) - 1);
uart_rx.sreg <= uart_rx.sync(0) & uart_rx.sreg(uart_rx.sreg'left downto 1);
else
uart_rx_baud_cnt <= std_ulogic_vector(unsigned(uart_rx_baud_cnt) - 1);
uart_rx.baud_cnt <= std_ulogic_vector(unsigned(uart_rx.baud_cnt) - 1);
end if;
if (uart_rx.bitcnt = "0000") then
uart_rx.busy <= '0'; -- done
uart_rx.perr <= ctrl(ctrl_uart_pmode1_c) and (xor_all_f(uart_rx.sreg(8 downto 0)) xor ctrl(ctrl_uart_pmode0_c));
uart_rx.ferr <= not uart_rx.sreg(9); -- check stop bit (error if not set)
if (ctrl(ctrl_uart_pmode1_c) = '1') then -- add parity flag
uart_rx.data <= uart_rx.sreg(7 downto 0);
else
uart_rx.data <= uart_rx.sreg(8 downto 1);
end if;
end if;
end if;
 
-- RX available flag --
uart_rx_busy_ff <= uart_rx_busy;
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx_avail(0) = '1') or (uart_rx_avail(1) = '1')) and (rd_en = '1') and (addr = uart_rtx_addr_c)) then
uart_rx_avail <= "00";
elsif (uart_rx_busy_ff = '1') and (uart_rx_busy = '0') then
uart_rx_avail <= uart_rx_avail(0) & '1';
uart_rx.busy_ff <= uart_rx.busy;
if (ctrl(ctrl_uart_en_c) = '0') or (((uart_rx.avail(0) = '1') or (uart_rx.avail(1) = '1')) and (rd_en = '1') and (addr = uart_rtx_addr_c)) then -- off/RX read access
uart_rx.avail <= "00";
elsif (uart_rx.busy_ff = '1') and (uart_rx.busy = '0') then -- RX done
uart_rx.avail <= uart_rx.avail(0) & '1';
end if;
end if;
end process uart_rx_unit;
269,7 → 318,7
-- Interrupt ------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- UART Rx data available [OR] UART Tx complete
uart_irq_o <= (uart_rx_busy_ff and (not uart_rx_busy) and ctrl(ctrl_uart_rx_irq_c)) or (uart_tx_done and ctrl(ctrl_uart_tx_irq_c));
uart_irq_o <= (uart_rx.busy_ff and (not uart_rx.busy) and ctrl(ctrl_uart_rx_irq_c)) or (uart_tx.done and ctrl(ctrl_uart_tx_irq_c));
 
 
-- SIMULATION Output ----------------------------------------------------------------------
/rtl/top_templates/neorv32_cpu_stdlogic.vhd File deleted
/rtl/top_templates/README.md
3,8 → 3,8
The top entity of the NEORV32 processor is `rtl/core/neorv32_top.vhd`. This folder provides additional
top entities/wrappers that instantiate the processor's top entity to provide a different interface.
 
If you want to use one of the provides top entities from this folder, *also* add the according file to the project's
HDL file list and select the according top_template file as top entity or instatiate the top_template file in your design.
If you want to use one of the provided top entities from this folder, *also* add the according file to the project's
HDL file list and select the according top_template file as top entity or instatiate the top_template within in your design.
 
 
### [`neorv32_test_setup.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd)
14,12 → 14,6
of the GPIO output port are propagated to the outer world.
 
 
### [`neorv32_cpu_stdlogic.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_cpu_stdlogic.vhd)
 
Same entity (generics and interface ports) as the default NEORV32 CPU top entity (`rtl/core/neorv32_cpu.vhd`),
but with _resolved_ port signals: All ports are of type `std_logic` or `std_logic_vector`, respectively.
 
 
### [`neorv32_top_axi4lite.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite)
 
This setup provides all the peripheal/IO signals of the default processor top entity, but features an **AXI4-Lite**-compatible bus interface
/rtl/top_templates/neorv32_test_setup.vhd
8,7 → 8,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
74,42 → 74,45
USER_CODE => x"00000000", -- custom user code
HW_THREAD_ID => x"00000000", -- hardware thread id (hartid)
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
-- Extension Options --
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE => true, -- implement PMP?
PMP_NUM_REGIONS => 2, -- number of regions (0..64)
PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => 2, -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
-- Internal Data memory --
MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_USE => false, -- implement instruction cache
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_USE => false, -- implement instruction cache
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
-- External memory interface --
MEM_EXT_USE => false, -- implement external memory bus interface?
MEM_EXT_USE => false, -- implement external memory bus interface?
-- Processor peripherals --
IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE => false, -- implement serial peripheral interface (SPI)?
IO_TWI_USE => false, -- implement two-wire interface (TWI)?
IO_PWM_USE => false, -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE => true, -- implement watch dog timer (WDT)?
IO_TRNG_USE => false, -- implement true random number generator (TRNG)?
IO_CFU0_USE => false, -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE => false -- implement custom functions unit 1 (CFU1)?
IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
IO_SPI_USE => false, -- implement serial peripheral interface (SPI)?
IO_TWI_USE => false, -- implement two-wire interface (TWI)?
IO_PWM_USE => false, -- implement pulse-width modulation unit (PWM)?
IO_WDT_USE => true, -- implement watch dog timer (WDT)?
IO_TRNG_USE => false, -- implement true random number generator (TRNG)?
IO_CFU0_USE => false, -- implement custom functions unit 0 (CFU0)?
IO_CFU1_USE => false -- implement custom functions unit 1 (CFU1)?
)
port map (
-- Global control --
/rtl/top_templates/neorv32_top_axi4lite.vhd
5,7 → 5,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
60,7 → 60,10
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
218,7 → 221,10
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE => PMP_USE, -- implement PMP?
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
/rtl/top_templates/neorv32_top_stdlogic.vhd
3,7 → 3,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
55,10 → 55,13
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE : boolean := false; -- implement PMP?
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
194,7 → 197,10
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE => PMP_USE, -- implement PMP?
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
/sim/ghdl/ghdl_sim.sh
65,12 → 65,11
ghdl -a --work=neorv32 $srcdir_core/neorv32_wdt.vhd
ghdl -a --work=neorv32 $srcdir_core/neorv32_wishbone.vhd
#
ghdl -a --work=neorv32 $srcdir_top_templates/neorv32_cpu_stdlogic.vhd
ghdl -a --work=neorv32 $srcdir_top_templates/neorv32_test_setup.vhd
ghdl -a --work=neorv32 $srcdir_top_templates/neorv32_top_axi4lite.vhd
ghdl -a --work=neorv32 $srcdir_top_templates/neorv32_top_stdlogic.vhd
#
ghdl -a --work=neorv32 $srcdir_sim/*.vhd
ghdl -a --work=neorv32 $srcdir_sim/neorv32_tb.vhd
 
# Prepare simulation output files
touch neorv32.testbench_uart.out
/sim/rtl_modules/neorv32_dmem.vhd
0,0 → 1,118
-- #################################################################################################
-- # << NEORV32 - Processor-internal data memory (DMEM) >> #
-- # ********************************************************************************************* #
-- # This version is intended for SIMULATION ONLY! #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_dmem is
generic (
DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
DMEM_SIZE : natural := 4*1024 -- processor-internal instruction memory size in bytes
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
);
end neorv32_dmem;
 
architecture neorv32_dmem_rtl of neorv32_dmem is
 
-- IO space: module base address --
constant hi_abb_c : natural := 31; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(DMEM_SIZE); -- low address boundary bit
 
-- local signals --
signal acc_en : std_ulogic;
signal rdata : std_ulogic_vector(31 downto 0);
signal rden : std_ulogic;
signal addr : std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0);
 
-- RAM --
type dmem_file_t is array (0 to DMEM_SIZE/4-1) of std_ulogic_vector(31 downto 0);
shared variable dmem_file_sim : dmem_file_t;
 
begin
 
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
addr <= addr_i(index_size_f(DMEM_SIZE/4)+1 downto 2); -- word aligned
 
 
-- Memory Access --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
dmem_file_access: process(clk_i)
begin
if rising_edge(clk_i) then
rden <= rden_i and acc_en;
ack_o <= acc_en and (rden_i or wren_i);
if (acc_en = '1') then -- reduce switching activity when not accessed
-- write --
if (wren_i = '1') then
if (ben_i(0) = '1') then
dmem_file_sim(to_integer(unsigned(addr)))(07 downto 00) := data_i(07 downto 00);
end if;
if (ben_i(1) = '1') then
dmem_file_sim(to_integer(unsigned(addr)))(15 downto 08) := data_i(15 downto 08);
end if;
if (ben_i(2) = '1') then
dmem_file_sim(to_integer(unsigned(addr)))(23 downto 16) := data_i(23 downto 16);
end if;
if (ben_i(3) = '1') then
dmem_file_sim(to_integer(unsigned(addr)))(31 downto 24) := data_i(31 downto 24);
end if;
end if;
-- read --
rdata <= dmem_file_sim(to_integer(unsigned(addr)));
end if;
end if;
end process dmem_file_access;
 
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
 
 
end neorv32_dmem_rtl;
/sim/vivado/neorv32_tb_behav.wcfg
12,15 → 12,15
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="396191834fs"></ZoomStartTime>
<ZoomEndTime time="396390835fs"></ZoomEndTime>
<Cursor1Time time="396225000fs"></Cursor1Time>
<ZoomStartTime time="65908200fs"></ZoomStartTime>
<ZoomEndTime time="65943001fs"></ZoomEndTime>
<Cursor1Time time="65991400fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="203"></NameColumnWidth>
<ValueColumnWidth column_width="124"></ValueColumnWidth>
<ValueColumnWidth column_width="100"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="122" />
<WVObjectSize size="132" />
<wvobject type="divider" fp_name="divider273">
<obj_property name="label">CPU: Control.FETCH</obj_property>
<obj_property name="DisplayName">label</obj_property>
172,6 → 172,11
<obj_property name="ObjectShortName">csr</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_control_inst/cnt_event" type="array">
<obj_property name="ElementShortName">cnt_event[12:0]</obj_property>
<obj_property name="ObjectShortName">cnt_event[12:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider139">
<obj_property name="label">CPU: RegFile</obj_property>
<obj_property name="DisplayName">label</obj_property>
346,21 → 351,17
<obj_property name="ObjectShortName">cpu_d</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/PMP_USE" type="other">
<obj_property name="ElementShortName">PMP_USE</obj_property>
<obj_property name="ObjectShortName">PMP_USE</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/pmp" type="array">
<obj_property name="ElementShortName">pmp</obj_property>
<obj_property name="ObjectShortName">pmp</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/pmp_addr_i" type="array">
<obj_property name="ElementShortName">pmp_addr_i[0:7][33:0]</obj_property>
<obj_property name="ObjectShortName">pmp_addr_i[0:7][33:0]</obj_property>
<obj_property name="ElementShortName">pmp_addr_i[0:63][33:0]</obj_property>
<obj_property name="ObjectShortName">pmp_addr_i[0:63][33:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/pmp_ctrl_i" type="array">
<obj_property name="ElementShortName">pmp_ctrl_i[0:7][7:0]</obj_property>
<obj_property name="ObjectShortName">pmp_ctrl_i[0:7][7:0]</obj_property>
<obj_property name="ElementShortName">pmp_ctrl_i[0:63][7:0]</obj_property>
<obj_property name="ObjectShortName">pmp_ctrl_i[0:63][7:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_cpu_inst/neorv32_cpu_bus_inst/if_pmp_fault" type="logic">
<obj_property name="ElementShortName">if_pmp_fault</obj_property>
375,9 → 376,13
<obj_property name="ObjectShortName">st_pmp_fault</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider298">
<obj_property name="label">I-CACHE</obj_property>
<obj_property name="label">BUSSWITCH</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_busswitch_inst/arbiter" type="array">
<obj_property name="ElementShortName">arbiter</obj_property>
<obj_property name="ObjectShortName">arbiter</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider298">
<obj_property name="label">CPU: MULDIV CP</obj_property>
<obj_property name="DisplayName">label</obj_property>
443,6 → 448,42
<obj_property name="ObjectShortName">mtime_hi[31:0]</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider238">
<obj_property name="label">IO: UART</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_uart_inst_true/neorv32_uart_inst/wr_en" type="logic">
<obj_property name="ElementShortName">wr_en</obj_property>
<obj_property name="ObjectShortName">wr_en</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_uart_inst_true/neorv32_uart_inst/rd_en" type="logic">
<obj_property name="ElementShortName">rd_en</obj_property>
<obj_property name="ObjectShortName">rd_en</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_uart_inst_true/neorv32_uart_inst/uart_txd_o" type="logic">
<obj_property name="ElementShortName">uart_txd_o</obj_property>
<obj_property name="ObjectShortName">uart_txd_o</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_uart_inst_true/neorv32_uart_inst/uart_rxd_i" type="logic">
<obj_property name="ElementShortName">uart_rxd_i</obj_property>
<obj_property name="ObjectShortName">uart_rxd_i</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_uart_inst_true/neorv32_uart_inst/uart_irq_o" type="logic">
<obj_property name="ElementShortName">uart_irq_o</obj_property>
<obj_property name="ObjectShortName">uart_irq_o</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_uart_inst_true/neorv32_uart_inst/ctrl" type="array">
<obj_property name="ElementShortName">ctrl[31:0]</obj_property>
<obj_property name="ObjectShortName">ctrl[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_uart_inst_true/neorv32_uart_inst/uart_tx" type="array">
<obj_property name="ElementShortName">uart_tx</obj_property>
<obj_property name="ObjectShortName">uart_tx</obj_property>
</wvobject>
<wvobject fp_name="/neorv32_tb/neorv32_top_inst/neorv32_uart_inst_true/neorv32_uart_inst/uart_rx" type="array">
<obj_property name="ElementShortName">uart_rx</obj_property>
<obj_property name="ObjectShortName">uart_rx</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider238">
<obj_property name="label">EXT_MEM Interface</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
/sim/README.md
6,7 → 6,7
 
### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)
 
This folder provides additional/alternative simulation components. The the comments in the according files for more information.
This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.
 
### [`vivado`](https://github.com/stnolting/neorv32/tree/master/sim/vivado)
 
/sim/neorv32_tb.vhd
6,7 → 6,7
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
188,7 → 188,10
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_USE => true, -- implement PMP?
PMP_NUM_REGIONS => 5, -- number of regions (0..64)
PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => 12, -- number of inmplemnted HPM counters (0..29)
-- Internal Instruction memory --
MEM_INT_IMEM_USE => int_imem_c , -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
/sw/bootloader/bootloader.c
6,7 → 6,7
// # ********************************************************************************************* #
// # Boot from (internal) instruction memory, UART or SPI Flash. #
// # #
// # UART configuration: 8 data bits, no parity bit, 1 stop bit, 19200 baud #
// # UART configuration: 8 data bits, NO parity bit, 1 stop bit, 19200 baud (19200-8N1) #
// # Boot Flash: 8-bit SPI, 24-bit addresses (like Micron N25Q032A) @ neorv32.spi_csn_o(0) #
// # neorv32.gpio_o(0) is used as high-active status LED (can be disabled via #STATUS_LED_EN). #
// # #
220,13 → 220,13
neorv32_gpio_port_set(1 << STATUS_LED);
}
 
// init UART (no interrupts)
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART (no parity bit, no interrupts)
neorv32_uart_setup(BAUD_RATE, 0, 0, 0);
 
// Configure machine system timer interrupt for ~2Hz
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (clock_speed/4));
 
neorv32_cpu_csr_write(CSR_MIE, 1 << CPU_MIE_MTIE); // activate MTIME IRQ source
neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE); // activate MTIME IRQ source
neorv32_cpu_eint(); // enable global interrupts
 
 
/sw/example/blink_led/main.c
73,8 → 73,8
**************************************************************************/
int main() {
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// check if GPIO unit is implemented at all
if (neorv32_gpio_available() == 0) {
/sw/example/coremark/core_portme.c
81,6 → 81,7
void
start_time(void)
{
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // start all counters
GETMYTIME(&start_time_val);
}
/* Function : stop_time
94,6 → 95,7
void
stop_time(void)
{
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
GETMYTIME(&stop_time_val);
}
/* Function : get_time
123,12 → 125,16
time_in_secs(CORE_TICKS ticks)
{
/* NEORV32-specific */
secs_ret retval = ((secs_ret)ticks) / (secs_ret)SYSINFO_CLK;
secs_ret retval = (secs_ret)(((CORE_TICKS)ticks) / ((CORE_TICKS)SYSINFO_CLK));
return retval;
}
 
ee_u32 default_num_contexts = 1;
 
/* Number of available hardware performance monitors */
uint32_t num_hpm_cnts_global = 0;
 
 
/* Function : portable_init
Target specific initialization code
Test for some common mistakes.
145,7 → 151,7
/* NEORV32-specific */
neorv32_cpu_dint(); // no interrupt, thanks
neorv32_rte_setup(); // capture all exceptions and give debug information
neorv32_uart_setup(BAUD_RATE, 0, 0); // setup UART
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); // init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
 
 
// Disable coremark compilation by default
158,10 → 164,28
while(1);
#endif
 
num_hpm_cnts_global = neorv32_cpu_hpm_get_counters();
 
// try to setup as many HPMs as possible
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT3, 1 << HPMCNT_EVENT_CIR);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT4, 1 << HPMCNT_EVENT_WAIT_IF);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT5, 1 << HPMCNT_EVENT_WAIT_II);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT6, 1 << HPMCNT_EVENT_LOAD);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT7, 1 << HPMCNT_EVENT_STORE);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT8, 1 << HPMCNT_EVENT_WAIT_LS);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT9, 1 << HPMCNT_EVENT_JUMP);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_BRANCH);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_TBRANCH);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_TRAP);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT12, 1 << HPMCNT_EVENT_ILLEGAL);
 
neorv32_uart_printf("NEORV32: Processor running at %u Hz\n", (uint32_t)SYSINFO_CLK);
neorv32_uart_printf("NEORV32: Executing coremark (%u iterations). This may take some time...\n\n", (uint32_t)ITERATIONS);
 
// clear cycle counter
neorv32_cpu_set_mcycle(0);
neorv32_cpu_csr_write(CSR_MCOUNTEREN, -1); // enable access to all counters
 
/*
#error \
"Call board initialization routines in portable init (if needed), in particular initialize UART!\n"
182,6 → 206,8
while(1);
#endif
}
 
 
/* Function : portable_fini
Target specific final code
*/
190,7 → 216,7
{
p->portable_id = 0;
 
/* NORV§"-specific */
/* NEORV32-specific */
 
// show executed instructions, required cycles and resulting average CPI
union {
201,8 → 227,23
exe_time.uint64 = (uint64_t)get_time();
exe_instructions.uint64 = neorv32_cpu_get_instret();
 
neorv32_uart_printf("\nNEORV32: All reported numbers only show the integer results.\n\n");
neorv32_uart_printf("\nNEORV32: All reported numbers only show the integer part of the results.\n\n");
 
neorv32_uart_printf("NEORV32: HPM results\n");
if (num_hpm_cnts_global == 0) {neorv32_uart_printf("no HPMs available\n"); }
if (num_hpm_cnts_global > 0) {neorv32_uart_printf("# Retired compr. instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3)); }
if (num_hpm_cnts_global > 1) {neorv32_uart_printf("# I-fetch wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4)); }
if (num_hpm_cnts_global > 2) {neorv32_uart_printf("# I-issue wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5)); }
if (num_hpm_cnts_global > 3) {neorv32_uart_printf("# Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6)); }
if (num_hpm_cnts_global > 4) {neorv32_uart_printf("# Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7)); }
if (num_hpm_cnts_global > 5) {neorv32_uart_printf("# Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8)); }
if (num_hpm_cnts_global > 6) {neorv32_uart_printf("# Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9)); }
if (num_hpm_cnts_global > 7) {neorv32_uart_printf("# Conditional branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10)); }
if (num_hpm_cnts_global > 8) {neorv32_uart_printf("# Conditional branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11)); }
if (num_hpm_cnts_global > 9) {neorv32_uart_printf("# Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12)); }
if (num_hpm_cnts_global > 10) {neorv32_uart_printf("# Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13)); }
neorv32_uart_printf("\n");
 
neorv32_uart_printf("NEORV32: Executed instructions 0x%x_%x\n", (uint32_t)exe_instructions.uint32[1], (uint32_t)exe_instructions.uint32[0]);
neorv32_uart_printf("NEORV32: CoreMark core clock cycles 0x%x_%x\n", (uint32_t)exe_time.uint32[1], (uint32_t)exe_time.uint32[0]);
 
/sw/example/coremark/core_portme.h
98,15 → 98,15
ee_ptr_int needs to be the data type used to hold pointers, otherwise
coremark may fail!!!
*/
typedef signed short ee_s16;
typedef unsigned short ee_u16;
typedef signed int ee_s32;
typedef double ee_f32;
typedef unsigned char ee_u8;
typedef unsigned int ee_u32;
typedef unsigned long ee_u64;
typedef ee_u32 ee_ptr_int;
typedef size_t ee_size_t;
typedef int16_t ee_s16;
typedef uint16_t ee_u16;
typedef int32_t ee_s32;
typedef double ee_f32;
typedef unsigned char ee_u8;
typedef uint32_t ee_u32;
typedef uint64_t ee_u64;
typedef ee_u32 ee_ptr_int;
typedef size_t ee_size_t;
#define NULL ((void *)0)
/* align_mem :
This macro is used to align an offset to point to a 32b value. It is
/sw/example/cpu_test/main.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
74,6 → 74,8
int cnt_test = 0;
/// Global timestamp for traps (stores mcycle.low on trap enter)
uint32_t trap_timestamp32 = 0;
/// Global numbe rof available HPMs
uint32_t num_hpm_cnts_global = 0;
 
 
/**********************************************************************//**
122,18 → 124,12
int main() {
 
register uint32_t tmp_a, tmp_b;
int i;
volatile uint32_t dummy_dst __attribute__((unused));
 
union {
uint64_t uint64;
uint32_t uint32[sizeof(uint64_t)/2];
} cpu_systime;
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
 
// Disable cpu_test compilation by default
#ifndef RUN_CPUTEST
#warning cpu_test HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CPUTEST clean_all exe<< to compile it.
181,9 → 177,6
// show project credits
neorv32_rte_print_credits();
 
// show project license
neorv32_rte_print_license();
 
// show full HW config report
neorv32_rte_print_hw_config();
 
220,13 → 213,13
}
 
// enable interrupt sources
install_err = neorv32_cpu_irq_enable(CPU_MIE_MSIE); // activate software interrupt
install_err += neorv32_cpu_irq_enable(CPU_MIE_MTIE); // activate timer interrupt
install_err += neorv32_cpu_irq_enable(CPU_MIE_MEIE); // activate external interrupt
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ0E); // activate fast interrupt channel 0
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E); // activate fast interrupt channel 1
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ2E); // activate fast interrupt channel 2
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ3E); // activate fast interrupt channel 3
install_err = neorv32_cpu_irq_enable(CSR_MIE_MSIE); // activate software interrupt
install_err += neorv32_cpu_irq_enable(CSR_MIE_MTIE); // activate timer interrupt
install_err += neorv32_cpu_irq_enable(CSR_MIE_MEIE); // activate external interrupt
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ0E); // activate fast interrupt channel 0
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ1E); // activate fast interrupt channel 1
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ2E); // activate fast interrupt channel 2
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E); // activate fast interrupt channel 3
 
if (install_err) {
neorv32_uart_printf("IRQ enable error (%i)!\n", install_err);
241,63 → 234,6
 
 
// ----------------------------------------------------------
// List all accessible CSRs
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] List all accessible CSRs: ", cnt_test);
 
if ((UART_CT & (1 << UART_CT_SIM_MODE)) == 0) { // check if this is a simulation
 
cnt_test++;
i = 0;
 
neorv32_uart_printf("\n");
 
uint32_t csr_addr_cnt = 0;
 
// create test program in RAM
static const uint32_t csr_access_test_program[2] __attribute__((aligned(8))) = {
0x00006073, // csrrsi, 0x000, 0
0x00008067 // ret (32-bit)
};
 
// base address of program
tmp_a = (uint32_t)&csr_access_test_program;
uint32_t *csr_pnt = (uint32_t*)tmp_a;
 
// iterate through full 12-bit CSR address space
for (csr_addr_cnt=0x000; csr_addr_cnt<=0xfff; csr_addr_cnt++) {
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
// construct and store new CSR access instruction
// 0x00006073 = csrrsi, 0x000, 0
*csr_pnt = 0x00006073 | (csr_addr_cnt << 20); // insert current CSR address into most significant 12 bits
 
// sync instruction stream
asm volatile("fence.i");
 
// execute test program
asm volatile ("jalr ra, %[input_i]" : : [input_i] "r" (tmp_a));
 
// check for access exception
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) { // no exception -> access ok -> CSR exists
neorv32_uart_printf(" + 0x%x\n", csr_addr_cnt);
i++;
}
}
if (i != 0) { // at least one CSR was accessible
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (disabled for simulation)\n");
}
 
 
// ----------------------------------------------------------
// Test standard RISC-V performance counter [m]cycle[h]
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
357,7 → 293,7
 
// inhibit [m]cycle CSR
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
tmp_a |= (1<<CPU_MCOUNTINHIBIT_CY); // inhibit cycle counter auto-increment
tmp_a |= (1<<CSR_MCOUNTINHIBIT_CY); // inhibit cycle counter auto-increment
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a);
 
// get current cycle counter
379,7 → 315,7
 
// re-enable [m]cycle CSR
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
tmp_a &= ~(1<<CPU_MCOUNTINHIBIT_CY); // clear inhibit of cycle counter auto-increment
tmp_a &= ~(1<<CSR_MCOUNTINHIBIT_CY); // clear inhibit of cycle counter auto-increment
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp_a);
 
 
393,7 → 329,7
 
// do not allow user-level code to access cycle[h] CSRs
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
tmp_a &= ~(1<<CPU_MCOUNTEREN_CY); // clear access right
tmp_a &= ~(1<<CSR_MCOUNTEREN_CY); // clear access right
neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
 
// switch to user mode (hart will be back in MACHINE mode when trap handler returns)
420,11 → 356,49
 
// re-allow user-level code to access cycle[h] CSRs
tmp_a = neorv32_cpu_csr_read(CSR_MCOUNTEREN);
tmp_a |= (1<<CPU_MCOUNTEREN_CY); // re-allow access right
tmp_a |= (1<<CSR_MCOUNTEREN_CY); // re-allow access right
neorv32_cpu_csr_write(CSR_MCOUNTEREN, tmp_a);
 
 
// ----------------------------------------------------------
// Test performance counter: setup as many events and counter as feasible
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Initializing HPMs: ", cnt_test);
 
num_hpm_cnts_global = neorv32_cpu_hpm_get_counters();
 
if (num_hpm_cnts_global != 0) {
cnt_test++;
 
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT3, 1 << HPMCNT_EVENT_CIR);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT4, 1 << HPMCNT_EVENT_WAIT_IF);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT5, 1 << HPMCNT_EVENT_WAIT_II);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT6, 1 << HPMCNT_EVENT_LOAD);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT7, 1 << HPMCNT_EVENT_STORE);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT8, 1 << HPMCNT_EVENT_WAIT_LS);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT9, 1 << HPMCNT_EVENT_JUMP);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT10, 1 << HPMCNT_EVENT_BRANCH);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT11, 1 << HPMCNT_EVENT_TBRANCH);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT12, 1 << HPMCNT_EVENT_TRAP);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 0); neorv32_cpu_csr_write(CSR_MHPMEVENT13, 1 << HPMCNT_EVENT_ILLEGAL);
 
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, 0); // enable all counters
 
// make sure there was no exception
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
test_ok();
}
else {
test_fail();
}
}
else {
neorv32_uart_printf("skipped (not implemented)\n");
}
 
 
// ----------------------------------------------------------
// Bus timeout latency estimation
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
435,9 → 409,9
neorv32_cpu_csr_write(CSR_MCYCLE, 0);
 
// this store access will timeout
MMR_UNREACHABLE = 0; // trap handler will stor mcycle.low to "trap_timestamp32"
MMR_UNREACHABLE = 0; // trap handler will store mcycle.low to "trap_timestamp32"
 
// make sure there was a time-out
// make sure there was a timeout
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_S_ACCESS) {
neorv32_uart_printf("~%u cycles ", trap_timestamp32-178); // remove trap handler overhead - empiric value ;)
test_ok();
496,66 → 470,6
 
 
// ----------------------------------------------------------
// Test time (must be == MTIME.TIME)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] Time (MTIME.time vs CSR.time) sync: ", cnt_test);
cnt_test++;
 
cpu_systime.uint64 = neorv32_cpu_get_systime();
uint64_t mtime_systime = neorv32_mtime_get_time();
 
// compute difference
mtime_systime = mtime_systime - cpu_systime.uint64;
 
if (mtime_systime < 4096) { // diff should be pretty small depending on bus latency
test_ok();
}
else {
test_fail();
}
 
 
// ----------------------------------------------------------
// Test fence instructions - make sure CPU does not crash here and throws no exception
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FENCE instruction test: ", cnt_test);
cnt_test++;
asm volatile ("fence");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) != 0) {
test_fail();
}
else {
test_ok();
}
 
 
// ----------------------------------------------------------
// Test fencei instructions - make sure CPU does not crash here and throws no exception
// a more complex test is provided by the RISC-V compliance test
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FENCE.I instruction test: ", cnt_test);
asm volatile ("fence.i");
 
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) {
neorv32_uart_printf("skipped (not implemented)\n");
}
else {
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
asm volatile ("fence.i");
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
test_ok();
}
else {
test_fail();
}
}
 
 
// ----------------------------------------------------------
// Illegal CSR access (CSR not implemented)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
672,7 → 586,7
neorv32_mtime_set_timecmp(-1);
 
 
if (neorv32_cpu_csr_read(CSR_MIP) & (1 << CPU_MIP_MTIP)) { // make sure MTIP is pending
if (neorv32_cpu_csr_read(CSR_MIP) & (1 << CSR_MIP_MTIP)) { // make sure MTIP is pending
 
neorv32_cpu_csr_write(CSR_MIP, 0); // just clear all pending IRQs
neorv32_cpu_eint(); // re-enable global interrupts
704,7 → 618,7
neorv32_uart_printf("[%i] I_ALIGN (instruction alignment) exception test: ", cnt_test);
 
// skip if C-mode is implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_C_EXT)) == 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) == 0) {
 
cnt_test++;
 
776,7 → 690,7
neorv32_uart_printf("[%i] CI_ILLEG (illegal compressed instruction) exception test: ", cnt_test);
 
// skip if C-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_C_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) != 0) {
 
cnt_test++;
 
914,7 → 828,7
neorv32_uart_printf("[%i] ENVCALL (ecall instruction) from U-mode exception test: ", cnt_test);
 
// skip if U-mode is not implemented
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_U_EXT)) {
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U_EXT)) {
 
cnt_test++;
 
1261,7 → 1175,7
neorv32_uart_printf("[%i] Invalid CSR access (mstatus) from user mode test: ", cnt_test);
 
// skip if U-mode is not implemented
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_U_EXT)) {
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U_EXT)) {
 
cnt_test++;
 
1324,7 → 1238,7
neorv32_uart_printf("[%i] Physical memory protection (PMP): ", cnt_test);
 
// check if PMP is implemented
if (neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) {
if (neorv32_cpu_pmp_get_num_regions() != 0) {
 
// Test access to protected region
// ---------------------------------------------
1476,7 → 1390,7
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
 
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
 
cnt_test++;
 
1513,7 → 1427,7
if ((UART_CT & (1 << UART_CT_SIM_MODE)) != 0) { // check if this is a simulation
 
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
 
cnt_test++;
 
1547,7 → 1461,7
 
#ifdef __riscv_atomic
// skip if A-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
 
cnt_test++;
 
1572,6 → 1486,26
 
 
// ----------------------------------------------------------
// HPM reports
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters
neorv32_uart_printf("\n\nHPM results:\n");
if (num_hpm_cnts_global == 0) {neorv32_uart_printf("no HPMs available\n"); }
if (num_hpm_cnts_global > 0) {neorv32_uart_printf("# Retired compr. instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3)); }
if (num_hpm_cnts_global > 1) {neorv32_uart_printf("# I-fetch wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4)); }
if (num_hpm_cnts_global > 2) {neorv32_uart_printf("# I-issue wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5)); }
if (num_hpm_cnts_global > 3) {neorv32_uart_printf("# Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6)); }
if (num_hpm_cnts_global > 4) {neorv32_uart_printf("# Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7)); }
if (num_hpm_cnts_global > 5) {neorv32_uart_printf("# Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8)); }
if (num_hpm_cnts_global > 6) {neorv32_uart_printf("# Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9)); }
if (num_hpm_cnts_global > 7) {neorv32_uart_printf("# Conditional branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10)); }
if (num_hpm_cnts_global > 8) {neorv32_uart_printf("# Conditional branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11)); }
if (num_hpm_cnts_global > 9) {neorv32_uart_printf("# Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12)); }
if (num_hpm_cnts_global > 10) {neorv32_uart_printf("# Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13)); }
neorv32_uart_printf("\n");
 
 
// ----------------------------------------------------------
// Final test reports
// ----------------------------------------------------------
neorv32_uart_printf("\nExecuted instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET));
1600,7 → 1534,7
trap_timestamp32 = neorv32_cpu_csr_read(CSR_MCYCLE);
 
// hack: always come back in MACHINE MODE
register uint32_t mask = (1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L);
register uint32_t mask = (1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L);
asm volatile ("csrrs zero, mstatus, %[input_j]" : : [input_j] "r" (mask));
}
 
/sw/example/demo_freeRTOS/main.c
46,6 → 46,9
* Modified for the NEORV32 processor by Stephan Nolting.
*/
 
/* UART hardware constants. */
#define BAUD_RATE 19200
 
#ifdef RUN_FREERTOS_DEMO
 
#include <stdint.h>
66,9 → 69,6
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1
 
/* UART hardware constants. */
#define BAUD_RATE 19200
 
/*-----------------------------------------------------------*/
 
/*
127,8 → 127,8
// clear GPIO.out port
neorv32_gpio_port_set(0);
 
// configure UART for default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
}
 
/*-----------------------------------------------------------*/
228,7 → 228,8
#include <neorv32.h>
int main() {
 
neorv32_uart_setup(19200, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
neorv32_uart_print("ERROR! FreeRTOS has not been compiled. Use >>make USER_FLAGS+=-DRUN_FREERTOS_DEMO clean_all exe<< to compile it.\n");
return 0;
}
/sw/example/demo_gpio_irq/main.c
72,8 → 72,8
// setup run-time environment for interrupts and exceptions
neorv32_rte_setup();
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
 
// check if GPIO unit is implemented at all
115,7 → 115,7
}
 
// activate fast interrupt channel 1 (which is GPIO_PIN_CHANGE)
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E);
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ1E);
 
// activate GPIO pin-change irq only for input pins 0 to 7
neorv32_gpio_pin_change_config(0x000000ff);
/sw/example/demo_pwm/main.c
73,8 → 73,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// say hello
neorv32_uart_print("PWM demo program\n");
/sw/example/demo_trng/main.c
79,8 → 79,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// intro
neorv32_uart_printf("\n--- TRNG Demo ---\n\n");
/sw/example/demo_twi/main.c
83,8 → 83,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// intro
neorv32_uart_printf("\n--- TWI Bus Explorer ---\n\n");
/sw/example/demo_wdt/main.c
76,8 → 76,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// simple text output via UART (strings only)
neorv32_uart_print("\nWatchdog system reset demo program\n\n");
/sw/example/game_of_life/main.c
97,8 → 97,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
 
while (1) {
/sw/example/hello_world/main.c
61,13 → 61,13
**************************************************************************/
int main() {
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
 
// capture all exceptions and give debug info via UART
// this is not required, but keeps us safe
neorv32_rte_setup();
 
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// print project logo via UART
neorv32_rte_print_logo();
 
/sw/example/hex_viewer/main.c
82,8 → 82,8
neorv32_rte_setup();
 
 
// init UART at default baud rate, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0, 0);
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0);
 
// intro
neorv32_uart_printf("\n--- Hex Viewer ---\n\n");
208,7 → 208,7
char terminal_buffer[16];
uint32_t mem_address, cas_expected, cas_desired;
 
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CPU_MISA_A_EXT)) != 0) {
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) {
 
// enter memory address
neorv32_uart_printf("Enter memory address (8 hex chars): 0x");
/sw/lib/include/neorv32.h
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
52,54 → 52,274
/**********************************************************************//**
* Available CPU Control and Status Registers (CSRs)
**************************************************************************/
enum NEORV32_CPU_CSRS_enum {
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
CSR_MCOUNTEREN = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */
CSR_MSTATUSH = 0x310, /**< 0x310 - mstatush (r/-): Machine status register - high word */
enum NEORV32_CSR_enum {
CSR_MSTATUS = 0x300, /**< 0x300 - mstatus (r/w): Machine status register */
CSR_MISA = 0x301, /**< 0x301 - misa (r/-): CPU ISA and extensions (read-only in NEORV32) */
CSR_MIE = 0x304, /**< 0x304 - mie (r/w): Machine interrupt-enable register */
CSR_MTVEC = 0x305, /**< 0x305 - mtvec (r/w): Machine trap-handler base address (for ALL traps) */
CSR_MCOUNTEREN = 0x306, /**< 0x305 - mcounteren (r/w): Machine counter enable register (controls access rights from U-mode) */
CSR_MSTATUSH = 0x310, /**< 0x310 - mstatush (r/-): Machine status register - high word */
 
CSR_MCOUNTINHIBIT = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */
CSR_MCOUNTINHIBIT = 0x320, /**< 0x320 - mcountinhibit (r/w): Machine counter-inhibit register */
 
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
CSR_MHPMEVENT3 = 0x323, /**< 0x323 - mhpmevent3 (r/w): Machine hardware performance monitor event selector 3 */
CSR_MHPMEVENT4 = 0x324, /**< 0x324 - mhpmevent4 (r/w): Machine hardware performance monitor event selector 4 */
CSR_MHPMEVENT5 = 0x325, /**< 0x325 - mhpmevent5 (r/w): Machine hardware performance monitor event selector 5 */
CSR_MHPMEVENT6 = 0x326, /**< 0x326 - mhpmevent6 (r/w): Machine hardware performance monitor event selector 6 */
CSR_MHPMEVENT7 = 0x327, /**< 0x327 - mhpmevent7 (r/w): Machine hardware performance monitor event selector 7 */
CSR_MHPMEVENT8 = 0x328, /**< 0x328 - mhpmevent8 (r/w): Machine hardware performance monitor event selector 8 */
CSR_MHPMEVENT9 = 0x329, /**< 0x329 - mhpmevent9 (r/w): Machine hardware performance monitor event selector 9 */
CSR_MHPMEVENT10 = 0x32a, /**< 0x32a - mhpmevent10 (r/w): Machine hardware performance monitor event selector 10 */
CSR_MHPMEVENT11 = 0x32b, /**< 0x32b - mhpmevent11 (r/w): Machine hardware performance monitor event selector 11 */
CSR_MHPMEVENT12 = 0x32c, /**< 0x32c - mhpmevent12 (r/w): Machine hardware performance monitor event selector 12 */
CSR_MHPMEVENT13 = 0x32d, /**< 0x32d - mhpmevent13 (r/w): Machine hardware performance monitor event selector 13 */
CSR_MHPMEVENT14 = 0x32e, /**< 0x32e - mhpmevent14 (r/w): Machine hardware performance monitor event selector 14 */
CSR_MHPMEVENT15 = 0x32f, /**< 0x32f - mhpmevent15 (r/w): Machine hardware performance monitor event selector 15 */
CSR_MHPMEVENT16 = 0x330, /**< 0x330 - mhpmevent16 (r/w): Machine hardware performance monitor event selector 16 */
CSR_MHPMEVENT17 = 0x331, /**< 0x331 - mhpmevent17 (r/w): Machine hardware performance monitor event selector 17 */
CSR_MHPMEVENT18 = 0x332, /**< 0x332 - mhpmevent18 (r/w): Machine hardware performance monitor event selector 18 */
CSR_MHPMEVENT19 = 0x333, /**< 0x333 - mhpmevent19 (r/w): Machine hardware performance monitor event selector 19 */
CSR_MHPMEVENT20 = 0x334, /**< 0x334 - mhpmevent20 (r/w): Machine hardware performance monitor event selector 20 */
CSR_MHPMEVENT21 = 0x335, /**< 0x335 - mhpmevent21 (r/w): Machine hardware performance monitor event selector 21 */
CSR_MHPMEVENT22 = 0x336, /**< 0x336 - mhpmevent22 (r/w): Machine hardware performance monitor event selector 22 */
CSR_MHPMEVENT23 = 0x337, /**< 0x337 - mhpmevent23 (r/w): Machine hardware performance monitor event selector 23 */
CSR_MHPMEVENT24 = 0x338, /**< 0x338 - mhpmevent24 (r/w): Machine hardware performance monitor event selector 24 */
CSR_MHPMEVENT25 = 0x339, /**< 0x339 - mhpmevent25 (r/w): Machine hardware performance monitor event selector 25 */
CSR_MHPMEVENT26 = 0x33a, /**< 0x33a - mhpmevent26 (r/w): Machine hardware performance monitor event selector 26 */
CSR_MHPMEVENT27 = 0x33b, /**< 0x33b - mhpmevent27 (r/w): Machine hardware performance monitor event selector 27 */
CSR_MHPMEVENT28 = 0x33c, /**< 0x33c - mhpmevent28 (r/w): Machine hardware performance monitor event selector 28 */
CSR_MHPMEVENT29 = 0x33d, /**< 0x33d - mhpmevent29 (r/w): Machine hardware performance monitor event selector 29 */
CSR_MHPMEVENT30 = 0x33e, /**< 0x33e - mhpmevent30 (r/w): Machine hardware performance monitor event selector 30 */
CSR_MHPMEVENT31 = 0x33f, /**< 0x33f - mhpmevent31 (r/w): Machine hardware performance monitor event selector 31 */
 
CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */
CSR_PMPCFG1 = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */
CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
 
CSR_PMPADDR0 = 0x3b0, /**< 0x3b0 - pmpaddr0 (r/w): Physical memory protection address register 0 */
CSR_PMPADDR1 = 0x3b1, /**< 0x3b1 - pmpaddr1 (r/w): Physical memory protection address register 1 */
CSR_PMPADDR2 = 0x3b2, /**< 0x3b2 - pmpaddr2 (r/w): Physical memory protection address register 2 */
CSR_PMPADDR3 = 0x3b3, /**< 0x3b3 - pmpaddr3 (r/w): Physical memory protection address register 3 */
CSR_PMPADDR4 = 0x3b4, /**< 0x3b4 - pmpaddr4 (r/w): Physical memory protection address register 4 */
CSR_PMPADDR5 = 0x3b5, /**< 0x3b5 - pmpaddr5 (r/w): Physical memory protection address register 5 */
CSR_PMPADDR6 = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */
CSR_PMPADDR7 = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */
CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */
CSR_PMPCFG1 = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */
CSR_PMPCFG2 = 0x3a2, /**< 0x3a2 - pmpcfg2 (r/w): Physical memory protection configuration register 2 */
CSR_PMPCFG3 = 0x3a3, /**< 0x3a3 - pmpcfg3 (r/w): Physical memory protection configuration register 3 */
CSR_PMPCFG4 = 0x3a4, /**< 0x3a4 - pmpcfg4 (r/w): Physical memory protection configuration register 4 */
CSR_PMPCFG5 = 0x3a5, /**< 0x3a5 - pmpcfg5 (r/w): Physical memory protection configuration register 5 */
CSR_PMPCFG6 = 0x3a6, /**< 0x3a6 - pmpcfg6 (r/w): Physical memory protection configuration register 6 */
CSR_PMPCFG7 = 0x3a7, /**< 0x3a7 - pmpcfg7 (r/w): Physical memory protection configuration register 7 */
CSR_PMPCFG8 = 0x3a8, /**< 0x3a8 - pmpcfg8 (r/w): Physical memory protection configuration register 8 */
CSR_PMPCFG9 = 0x3a9, /**< 0x3a9 - pmpcfg9 (r/w): Physical memory protection configuration register 9 */
CSR_PMPCFG10 = 0x3aa, /**< 0x3aa - pmpcfg10 (r/w): Physical memory protection configuration register 10 */
CSR_PMPCFG11 = 0x3ab, /**< 0x3ab - pmpcfg11 (r/w): Physical memory protection configuration register 11 */
CSR_PMPCFG12 = 0x3ac, /**< 0x3ac - pmpcfg12 (r/w): Physical memory protection configuration register 12 */
CSR_PMPCFG13 = 0x3ad, /**< 0x3ad - pmpcfg13 (r/w): Physical memory protection configuration register 13 */
CSR_PMPCFG14 = 0x3ae, /**< 0x3ae - pmpcfg14 (r/w): Physical memory protection configuration register 14 */
CSR_PMPCFG15 = 0x3af, /**< 0x3af - pmpcfg15 (r/w): Physical memory protection configuration register 15 */
 
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
CSR_PMPADDR0 = 0x3b0, /**< 0x3b0 - pmpaddr0 (r/w): Physical memory protection address register 0 */
CSR_PMPADDR1 = 0x3b1, /**< 0x3b1 - pmpaddr1 (r/w): Physical memory protection address register 1 */
CSR_PMPADDR2 = 0x3b2, /**< 0x3b2 - pmpaddr2 (r/w): Physical memory protection address register 2 */
CSR_PMPADDR3 = 0x3b3, /**< 0x3b3 - pmpaddr3 (r/w): Physical memory protection address register 3 */
CSR_PMPADDR4 = 0x3b4, /**< 0x3b4 - pmpaddr4 (r/w): Physical memory protection address register 4 */
CSR_PMPADDR5 = 0x3b5, /**< 0x3b5 - pmpaddr5 (r/w): Physical memory protection address register 5 */
CSR_PMPADDR6 = 0x3b6, /**< 0x3b6 - pmpaddr6 (r/w): Physical memory protection address register 6 */
CSR_PMPADDR7 = 0x3b7, /**< 0x3b7 - pmpaddr7 (r/w): Physical memory protection address register 7 */
CSR_PMPADDR8 = 0x3b8, /**< 0x3b8 - pmpaddr8 (r/w): Physical memory protection address register 8 */
CSR_PMPADDR9 = 0x3b9, /**< 0x3b9 - pmpaddr9 (r/w): Physical memory protection address register 9 */
CSR_PMPADDR10 = 0x3ba, /**< 0x3ba - pmpaddr10 (r/w): Physical memory protection address register 10 */
CSR_PMPADDR11 = 0x3bb, /**< 0x3bb - pmpaddr11 (r/w): Physical memory protection address register 11 */
CSR_PMPADDR12 = 0x3bc, /**< 0x3bc - pmpaddr12 (r/w): Physical memory protection address register 12 */
CSR_PMPADDR13 = 0x3bd, /**< 0x3bd - pmpaddr13 (r/w): Physical memory protection address register 13 */
CSR_PMPADDR14 = 0x3be, /**< 0x3be - pmpaddr14 (r/w): Physical memory protection address register 14 */
CSR_PMPADDR15 = 0x3bf, /**< 0x3bf - pmpaddr15 (r/w): Physical memory protection address register 15 */
CSR_PMPADDR16 = 0x3c0, /**< 0x3c0 - pmpaddr16 (r/w): Physical memory protection address register 16 */
CSR_PMPADDR17 = 0x3c1, /**< 0x3c1 - pmpaddr17 (r/w): Physical memory protection address register 17 */
CSR_PMPADDR18 = 0x3c2, /**< 0x3c2 - pmpaddr18 (r/w): Physical memory protection address register 18 */
CSR_PMPADDR19 = 0x3c3, /**< 0x3c3 - pmpaddr19 (r/w): Physical memory protection address register 19 */
CSR_PMPADDR20 = 0x3c4, /**< 0x3c4 - pmpaddr20 (r/w): Physical memory protection address register 20 */
CSR_PMPADDR21 = 0x3c5, /**< 0x3c5 - pmpaddr21 (r/w): Physical memory protection address register 21 */
CSR_PMPADDR22 = 0x3c6, /**< 0x3c6 - pmpaddr22 (r/w): Physical memory protection address register 22 */
CSR_PMPADDR23 = 0x3c7, /**< 0x3c7 - pmpaddr23 (r/w): Physical memory protection address register 23 */
CSR_PMPADDR24 = 0x3c8, /**< 0x3c8 - pmpaddr24 (r/w): Physical memory protection address register 24 */
CSR_PMPADDR25 = 0x3c9, /**< 0x3c9 - pmpaddr25 (r/w): Physical memory protection address register 25 */
CSR_PMPADDR26 = 0x3ca, /**< 0x3ca - pmpaddr26 (r/w): Physical memory protection address register 26 */
CSR_PMPADDR27 = 0x3cb, /**< 0x3cb - pmpaddr27 (r/w): Physical memory protection address register 27 */
CSR_PMPADDR28 = 0x3cc, /**< 0x3cc - pmpaddr28 (r/w): Physical memory protection address register 28 */
CSR_PMPADDR29 = 0x3cd, /**< 0x3cd - pmpaddr29 (r/w): Physical memory protection address register 29 */
CSR_PMPADDR30 = 0x3ce, /**< 0x3ce - pmpaddr30 (r/w): Physical memory protection address register 30 */
CSR_PMPADDR31 = 0x3cf, /**< 0x3cf - pmpaddr31 (r/w): Physical memory protection address register 31 */
CSR_PMPADDR32 = 0x3d0, /**< 0x3d0 - pmpaddr32 (r/w): Physical memory protection address register 32 */
CSR_PMPADDR33 = 0x3d1, /**< 0x3d1 - pmpaddr33 (r/w): Physical memory protection address register 33 */
CSR_PMPADDR34 = 0x3d2, /**< 0x3d2 - pmpaddr34 (r/w): Physical memory protection address register 34 */
CSR_PMPADDR35 = 0x3d3, /**< 0x3d3 - pmpaddr35 (r/w): Physical memory protection address register 35 */
CSR_PMPADDR36 = 0x3d4, /**< 0x3d4 - pmpaddr36 (r/w): Physical memory protection address register 36 */
CSR_PMPADDR37 = 0x3d5, /**< 0x3d5 - pmpaddr37 (r/w): Physical memory protection address register 37 */
CSR_PMPADDR38 = 0x3d6, /**< 0x3d6 - pmpaddr38 (r/w): Physical memory protection address register 38 */
CSR_PMPADDR39 = 0x3d7, /**< 0x3d7 - pmpaddr39 (r/w): Physical memory protection address register 39 */
CSR_PMPADDR40 = 0x3d8, /**< 0x3d8 - pmpaddr40 (r/w): Physical memory protection address register 40 */
CSR_PMPADDR41 = 0x3d9, /**< 0x3d9 - pmpaddr41 (r/w): Physical memory protection address register 41 */
CSR_PMPADDR42 = 0x3da, /**< 0x3da - pmpaddr42 (r/w): Physical memory protection address register 42 */
CSR_PMPADDR43 = 0x3db, /**< 0x3db - pmpaddr43 (r/w): Physical memory protection address register 43 */
CSR_PMPADDR44 = 0x3dc, /**< 0x3dc - pmpaddr44 (r/w): Physical memory protection address register 44 */
CSR_PMPADDR45 = 0x3dd, /**< 0x3dd - pmpaddr45 (r/w): Physical memory protection address register 45 */
CSR_PMPADDR46 = 0x3de, /**< 0x3de - pmpaddr46 (r/w): Physical memory protection address register 46 */
CSR_PMPADDR47 = 0x3df, /**< 0x3df - pmpaddr47 (r/w): Physical memory protection address register 47 */
CSR_PMPADDR48 = 0x3e0, /**< 0x3e0 - pmpaddr48 (r/w): Physical memory protection address register 48 */
CSR_PMPADDR49 = 0x3e1, /**< 0x3e1 - pmpaddr49 (r/w): Physical memory protection address register 49 */
CSR_PMPADDR50 = 0x3e2, /**< 0x3e2 - pmpaddr50 (r/w): Physical memory protection address register 50 */
CSR_PMPADDR51 = 0x3e3, /**< 0x3e3 - pmpaddr51 (r/w): Physical memory protection address register 51 */
CSR_PMPADDR52 = 0x3e4, /**< 0x3e4 - pmpaddr52 (r/w): Physical memory protection address register 52 */
CSR_PMPADDR53 = 0x3e5, /**< 0x3e5 - pmpaddr53 (r/w): Physical memory protection address register 53 */
CSR_PMPADDR54 = 0x3e6, /**< 0x3e6 - pmpaddr54 (r/w): Physical memory protection address register 54 */
CSR_PMPADDR55 = 0x3e7, /**< 0x3e7 - pmpaddr55 (r/w): Physical memory protection address register 55 */
CSR_PMPADDR56 = 0x3e8, /**< 0x3e8 - pmpaddr56 (r/w): Physical memory protection address register 56 */
CSR_PMPADDR57 = 0x3e9, /**< 0x3e9 - pmpaddr57 (r/w): Physical memory protection address register 57 */
CSR_PMPADDR58 = 0x3ea, /**< 0x3ea - pmpaddr58 (r/w): Physical memory protection address register 58 */
CSR_PMPADDR59 = 0x3eb, /**< 0x3eb - pmpaddr59 (r/w): Physical memory protection address register 59 */
CSR_PMPADDR60 = 0x3ec, /**< 0x3ec - pmpaddr60 (r/w): Physical memory protection address register 60 */
CSR_PMPADDR61 = 0x3ed, /**< 0x3ed - pmpaddr61 (r/w): Physical memory protection address register 61 */
CSR_PMPADDR62 = 0x3ee, /**< 0x3ee - pmpaddr62 (r/w): Physical memory protection address register 62 */
CSR_PMPADDR63 = 0x3ef, /**< 0x3ef - pmpaddr63 (r/w): Physical memory protection address register 63 */
 
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
 
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */
CSR_MHPMCOUNTER3 = 0xb03, /**< 0xb03 - mhpmcounter3 (r/w): Machine hardware performance monitor 3 counter low word */
CSR_MHPMCOUNTER4 = 0xb04, /**< 0xb04 - mhpmcounter4 (r/w): Machine hardware performance monitor 4 counter low word */
CSR_MHPMCOUNTER5 = 0xb05, /**< 0xb05 - mhpmcounter5 (r/w): Machine hardware performance monitor 5 counter low word */
CSR_MHPMCOUNTER6 = 0xb06, /**< 0xb06 - mhpmcounter6 (r/w): Machine hardware performance monitor 6 counter low word */
CSR_MHPMCOUNTER7 = 0xb07, /**< 0xb07 - mhpmcounter7 (r/w): Machine hardware performance monitor 7 counter low word */
CSR_MHPMCOUNTER8 = 0xb08, /**< 0xb08 - mhpmcounter8 (r/w): Machine hardware performance monitor 8 counter low word */
CSR_MHPMCOUNTER9 = 0xb09, /**< 0xb09 - mhpmcounter9 (r/w): Machine hardware performance monitor 9 counter low word */
CSR_MHPMCOUNTER10 = 0xb0a, /**< 0xb0a - mhpmcounter10 (r/w): Machine hardware performance monitor 10 counter low word */
CSR_MHPMCOUNTER11 = 0xb0b, /**< 0xb0b - mhpmcounter11 (r/w): Machine hardware performance monitor 11 counter low word */
CSR_MHPMCOUNTER12 = 0xb0c, /**< 0xb0c - mhpmcounter12 (r/w): Machine hardware performance monitor 12 counter low word */
CSR_MHPMCOUNTER13 = 0xb0d, /**< 0xb0d - mhpmcounter13 (r/w): Machine hardware performance monitor 13 counter low word */
CSR_MHPMCOUNTER14 = 0xb0e, /**< 0xb0e - mhpmcounter14 (r/w): Machine hardware performance monitor 14 counter low word */
CSR_MHPMCOUNTER15 = 0xb0f, /**< 0xb0f - mhpmcounter15 (r/w): Machine hardware performance monitor 15 counter low word */
CSR_MHPMCOUNTER16 = 0xb10, /**< 0xb10 - mhpmcounter16 (r/w): Machine hardware performance monitor 16 counter low word */
CSR_MHPMCOUNTER17 = 0xb11, /**< 0xb11 - mhpmcounter17 (r/w): Machine hardware performance monitor 17 counter low word */
CSR_MHPMCOUNTER18 = 0xb12, /**< 0xb12 - mhpmcounter18 (r/w): Machine hardware performance monitor 18 counter low word */
CSR_MHPMCOUNTER19 = 0xb13, /**< 0xb13 - mhpmcounter19 (r/w): Machine hardware performance monitor 19 counter low word */
CSR_MHPMCOUNTER20 = 0xb14, /**< 0xb14 - mhpmcounter20 (r/w): Machine hardware performance monitor 20 counter low word */
CSR_MHPMCOUNTER21 = 0xb15, /**< 0xb15 - mhpmcounter21 (r/w): Machine hardware performance monitor 21 counter low word */
CSR_MHPMCOUNTER22 = 0xb16, /**< 0xb16 - mhpmcounter22 (r/w): Machine hardware performance monitor 22 counter low word */
CSR_MHPMCOUNTER23 = 0xb17, /**< 0xb17 - mhpmcounter23 (r/w): Machine hardware performance monitor 23 counter low word */
CSR_MHPMCOUNTER24 = 0xb18, /**< 0xb18 - mhpmcounter24 (r/w): Machine hardware performance monitor 24 counter low word */
CSR_MHPMCOUNTER25 = 0xb19, /**< 0xb19 - mhpmcounter25 (r/w): Machine hardware performance monitor 25 counter low word */
CSR_MHPMCOUNTER26 = 0xb1a, /**< 0xb1a - mhpmcounter26 (r/w): Machine hardware performance monitor 26 counter low word */
CSR_MHPMCOUNTER27 = 0xb1b, /**< 0xb1b - mhpmcounter27 (r/w): Machine hardware performance monitor 27 counter low word */
CSR_MHPMCOUNTER28 = 0xb1c, /**< 0xb1c - mhpmcounter28 (r/w): Machine hardware performance monitor 28 counter low word */
CSR_MHPMCOUNTER29 = 0xb1d, /**< 0xb1d - mhpmcounter29 (r/w): Machine hardware performance monitor 29 counter low word */
CSR_MHPMCOUNTER30 = 0xb1e, /**< 0xb1e - mhpmcounter30 (r/w): Machine hardware performance monitor 30 counter low word */
CSR_MHPMCOUNTER31 = 0xb1f, /**< 0xb1f - mhpmcounter31 (r/w): Machine hardware performance monitor 31 counter low word */
 
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
 
CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
CSR_MHPMCOUNTER3H = 0xb83, /**< 0xb83 - mhpmcounter3h (r/w): Machine hardware performance monitor 3 counter high word */
CSR_MHPMCOUNTER4H = 0xb84, /**< 0xb84 - mhpmcounter4h (r/w): Machine hardware performance monitor 4 counter high word */
CSR_MHPMCOUNTER5H = 0xb85, /**< 0xb85 - mhpmcounter5h (r/w): Machine hardware performance monitor 5 counter high word */
CSR_MHPMCOUNTER6H = 0xb86, /**< 0xb86 - mhpmcounter6h (r/w): Machine hardware performance monitor 6 counter high word */
CSR_MHPMCOUNTER7H = 0xb87, /**< 0xb87 - mhpmcounter7h (r/w): Machine hardware performance monitor 7 counter high word */
CSR_MHPMCOUNTER8H = 0xb88, /**< 0xb88 - mhpmcounter8h (r/w): Machine hardware performance monitor 8 counter high word */
CSR_MHPMCOUNTER9H = 0xb89, /**< 0xb89 - mhpmcounter9h (r/w): Machine hardware performance monitor 9 counter high word */
CSR_MHPMCOUNTER10H = 0xb8a, /**< 0xb8a - mhpmcounter10h (r/w): Machine hardware performance monitor 10 counter high word */
CSR_MHPMCOUNTER11H = 0xb8b, /**< 0xb8b - mhpmcounter11h (r/w): Machine hardware performance monitor 11 counter high word */
CSR_MHPMCOUNTER12H = 0xb8c, /**< 0xb8c - mhpmcounter12h (r/w): Machine hardware performance monitor 12 counter high word */
CSR_MHPMCOUNTER13H = 0xb8d, /**< 0xb8d - mhpmcounter13h (r/w): Machine hardware performance monitor 13 counter high word */
CSR_MHPMCOUNTER14H = 0xb8e, /**< 0xb8e - mhpmcounter14h (r/w): Machine hardware performance monitor 14 counter high word */
CSR_MHPMCOUNTER15H = 0xb8f, /**< 0xb8f - mhpmcounter15h (r/w): Machine hardware performance monitor 15 counter high word */
CSR_MHPMCOUNTER16H = 0xb90, /**< 0xb90 - mhpmcounter16h (r/w): Machine hardware performance monitor 16 counter high word */
CSR_MHPMCOUNTER17H = 0xb91, /**< 0xb91 - mhpmcounter17h (r/w): Machine hardware performance monitor 17 counter high word */
CSR_MHPMCOUNTER18H = 0xb92, /**< 0xb92 - mhpmcounter18h (r/w): Machine hardware performance monitor 18 counter high word */
CSR_MHPMCOUNTER19H = 0xb93, /**< 0xb93 - mhpmcounter19h (r/w): Machine hardware performance monitor 19 counter high word */
CSR_MHPMCOUNTER20H = 0xb94, /**< 0xb94 - mhpmcounter20h (r/w): Machine hardware performance monitor 20 counter high word */
CSR_MHPMCOUNTER21H = 0xb95, /**< 0xb95 - mhpmcounter21h (r/w): Machine hardware performance monitor 21 counter high word */
CSR_MHPMCOUNTER22H = 0xb96, /**< 0xb96 - mhpmcounter22h (r/w): Machine hardware performance monitor 22 counter high word */
CSR_MHPMCOUNTER23H = 0xb97, /**< 0xb97 - mhpmcounter23h (r/w): Machine hardware performance monitor 23 counter high word */
CSR_MHPMCOUNTER24H = 0xb98, /**< 0xb98 - mhpmcounter24h (r/w): Machine hardware performance monitor 24 counter high word */
CSR_MHPMCOUNTER25H = 0xb99, /**< 0xb99 - mhpmcounter25h (r/w): Machine hardware performance monitor 25 counter high word */
CSR_MHPMCOUNTER26H = 0xb9a, /**< 0xb9a - mhpmcounter26h (r/w): Machine hardware performance monitor 26 counter high word */
CSR_MHPMCOUNTER27H = 0xb9b, /**< 0xb9b - mhpmcounter27h (r/w): Machine hardware performance monitor 27 counter high word */
CSR_MHPMCOUNTER28H = 0xb9c, /**< 0xb9c - mhpmcounter28h (r/w): Machine hardware performance monitor 28 counter high word */
CSR_MHPMCOUNTER29H = 0xb9d, /**< 0xb9d - mhpmcounter29h (r/w): Machine hardware performance monitor 29 counter high word */
CSR_MHPMCOUNTER30H = 0xb9e, /**< 0xb9e - mhpmcounter30h (r/w): Machine hardware performance monitor 30 counter high word */
CSR_MHPMCOUNTER31H = 0xb9f, /**< 0xb9f - mhpmcounter31h (r/w): Machine hardware performance monitor 31 counter high word */
 
CSR_MZEXT = 0xfc0 /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME_LO) */
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */
 
CSR_HPMCOUNTER3 = 0xc03, /**< 0xc03 - hpmcounter3 (r/w): Hardware performance monitor 3 counter low word */
CSR_HPMCOUNTER4 = 0xc04, /**< 0xc04 - hpmcounter4 (r/w): Hardware performance monitor 4 counter low word */
CSR_HPMCOUNTER5 = 0xc05, /**< 0xc05 - hpmcounter5 (r/w): Hardware performance monitor 5 counter low word */
CSR_HPMCOUNTER6 = 0xc06, /**< 0xc06 - hpmcounter6 (r/w): Hardware performance monitor 6 counter low word */
CSR_HPMCOUNTER7 = 0xc07, /**< 0xc07 - hpmcounter7 (r/w): Hardware performance monitor 7 counter low word */
CSR_HPMCOUNTER8 = 0xc08, /**< 0xc08 - hpmcounter8 (r/w): Hardware performance monitor 8 counter low word */
CSR_HPMCOUNTER9 = 0xc09, /**< 0xc09 - hpmcounter9 (r/w): Hardware performance monitor 9 counter low word */
CSR_HPMCOUNTER10 = 0xc0a, /**< 0xc0a - hpmcounter10 (r/w): Hardware performance monitor 10 counter low word */
CSR_HPMCOUNTER11 = 0xc0b, /**< 0xc0b - hpmcounter11 (r/w): Hardware performance monitor 11 counter low word */
CSR_HPMCOUNTER12 = 0xc0c, /**< 0xc0c - hpmcounter12 (r/w): Hardware performance monitor 12 counter low word */
CSR_HPMCOUNTER13 = 0xc0d, /**< 0xc0d - hpmcounter13 (r/w): Hardware performance monitor 13 counter low word */
CSR_HPMCOUNTER14 = 0xc0e, /**< 0xc0e - hpmcounter14 (r/w): Hardware performance monitor 14 counter low word */
CSR_HPMCOUNTER15 = 0xc0f, /**< 0xc0f - hpmcounter15 (r/w): Hardware performance monitor 15 counter low word */
CSR_HPMCOUNTER16 = 0xc10, /**< 0xc10 - hpmcounter16 (r/w): Hardware performance monitor 16 counter low word */
CSR_HPMCOUNTER17 = 0xc11, /**< 0xc11 - hpmcounter17 (r/w): Hardware performance monitor 17 counter low word */
CSR_HPMCOUNTER18 = 0xc12, /**< 0xc12 - hpmcounter18 (r/w): Hardware performance monitor 18 counter low word */
CSR_HPMCOUNTER19 = 0xc13, /**< 0xc13 - hpmcounter19 (r/w): Hardware performance monitor 19 counter low word */
CSR_HPMCOUNTER20 = 0xc14, /**< 0xc14 - hpmcounter20 (r/w): Hardware performance monitor 20 counter low word */
CSR_HPMCOUNTER21 = 0xc15, /**< 0xc15 - hpmcounter21 (r/w): Hardware performance monitor 21 counter low word */
CSR_HPMCOUNTER22 = 0xc16, /**< 0xc16 - hpmcounter22 (r/w): Hardware performance monitor 22 counter low word */
CSR_HPMCOUNTER23 = 0xc17, /**< 0xc17 - hpmcounter23 (r/w): Hardware performance monitor 23 counter low word */
CSR_HPMCOUNTER24 = 0xc18, /**< 0xc18 - hpmcounter24 (r/w): Hardware performance monitor 24 counter low word */
CSR_HPMCOUNTER25 = 0xc19, /**< 0xc19 - hpmcounter25 (r/w): Hardware performance monitor 25 counter low word */
CSR_HPMCOUNTER26 = 0xc1a, /**< 0xc1a - hpmcounter26 (r/w): Hardware performance monitor 26 counter low word */
CSR_HPMCOUNTER27 = 0xc1b, /**< 0xc1b - hpmcounter27 (r/w): Hardware performance monitor 27 counter low word */
CSR_HPMCOUNTER28 = 0xc1c, /**< 0xc1c - hpmcounter28 (r/w): Hardware performance monitor 28 counter low word */
CSR_HPMCOUNTER29 = 0xc1d, /**< 0xc1d - hpmcounter29 (r/w): Hardware performance monitor 29 counter low word */
CSR_HPMCOUNTER30 = 0xc1e, /**< 0xc1e - hpmcounter30 (r/w): Hardware performance monitor 30 counter low word */
CSR_HPMCOUNTER31 = 0xc1f, /**< 0xc1f - hpmcounter31 (r/w): Hardware performance monitor 31 counter low word */
 
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME_HI) */
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */
 
CSR_HPMCOUNTER3H = 0xc83, /**< 0xc83 - hpmcounter3h (r/w): Hardware performance monitor 3 counter high word */
CSR_HPMCOUNTER4H = 0xc84, /**< 0xc84 - hpmcounter4h (r/w): Hardware performance monitor 4 counter high word */
CSR_HPMCOUNTER5H = 0xc85, /**< 0xc85 - hpmcounter5h (r/w): Hardware performance monitor 5 counter high word */
CSR_HPMCOUNTER6H = 0xc86, /**< 0xc86 - hpmcounter6h (r/w): Hardware performance monitor 6 counter high word */
CSR_HPMCOUNTER7H = 0xc87, /**< 0xc87 - hpmcounter7h (r/w): Hardware performance monitor 7 counter high word */
CSR_HPMCOUNTER8H = 0xc88, /**< 0xc88 - hpmcounter8h (r/w): Hardware performance monitor 8 counter high word */
CSR_HPMCOUNTER9H = 0xc89, /**< 0xc89 - hpmcounter9h (r/w): Hardware performance monitor 9 counter high word */
CSR_HPMCOUNTER10H = 0xc8a, /**< 0xc8a - hpmcounter10h (r/w): Hardware performance monitor 10 counter high word */
CSR_HPMCOUNTER11H = 0xc8b, /**< 0xc8b - hpmcounter11h (r/w): Hardware performance monitor 11 counter high word */
CSR_HPMCOUNTER12H = 0xc8c, /**< 0xc8c - hpmcounter12h (r/w): Hardware performance monitor 12 counter high word */
CSR_HPMCOUNTER13H = 0xc8d, /**< 0xc8d - hpmcounter13h (r/w): Hardware performance monitor 13 counter high word */
CSR_HPMCOUNTER14H = 0xc8e, /**< 0xc8e - hpmcounter14h (r/w): Hardware performance monitor 14 counter high word */
CSR_HPMCOUNTER15H = 0xc8f, /**< 0xc8f - hpmcounter15h (r/w): Hardware performance monitor 15 counter high word */
CSR_HPMCOUNTER16H = 0xc90, /**< 0xc90 - hpmcounter16h (r/w): Hardware performance monitor 16 counter high word */
CSR_HPMCOUNTER17H = 0xc91, /**< 0xc91 - hpmcounter17h (r/w): Hardware performance monitor 17 counter high word */
CSR_HPMCOUNTER18H = 0xc92, /**< 0xc92 - hpmcounter18h (r/w): Hardware performance monitor 18 counter high word */
CSR_HPMCOUNTER19H = 0xc93, /**< 0xc93 - hpmcounter19h (r/w): Hardware performance monitor 19 counter high word */
CSR_HPMCOUNTER20H = 0xc94, /**< 0xc94 - hpmcounter20h (r/w): Hardware performance monitor 20 counter high word */
CSR_HPMCOUNTER21H = 0xc95, /**< 0xc95 - hpmcounter21h (r/w): Hardware performance monitor 21 counter high word */
CSR_HPMCOUNTER22H = 0xc96, /**< 0xc96 - hpmcounter22h (r/w): Hardware performance monitor 22 counter high word */
CSR_HPMCOUNTER23H = 0xc97, /**< 0xc97 - hpmcounter23h (r/w): Hardware performance monitor 23 counter high word */
CSR_HPMCOUNTER24H = 0xc98, /**< 0xc98 - hpmcounter24h (r/w): Hardware performance monitor 24 counter high word */
CSR_HPMCOUNTER25H = 0xc99, /**< 0xc99 - hpmcounter25h (r/w): Hardware performance monitor 25 counter high word */
CSR_HPMCOUNTER26H = 0xc9a, /**< 0xc9a - hpmcounter26h (r/w): Hardware performance monitor 26 counter high word */
CSR_HPMCOUNTER27H = 0xc9b, /**< 0xc9b - hpmcounter27h (r/w): Hardware performance monitor 27 counter high word */
CSR_HPMCOUNTER28H = 0xc9c, /**< 0xc9c - hpmcounter28h (r/w): Hardware performance monitor 28 counter high word */
CSR_HPMCOUNTER29H = 0xc9d, /**< 0xc9d - hpmcounter29h (r/w): Hardware performance monitor 29 counter high word */
CSR_HPMCOUNTER30H = 0xc9e, /**< 0xc9e - hpmcounter30h (r/w): Hardware performance monitor 30 counter high word */
CSR_HPMCOUNTER31H = 0xc9f, /**< 0xc9f - hpmcounter31h (r/w): Hardware performance monitor 31 counter high word */
 
CSR_MVENDORID = 0xf11, /**< 0xf11 - mvendorid (r/-): Vendor ID */
CSR_MARCHID = 0xf12, /**< 0xf12 - marchid (r/-): Architecture ID */
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (always 0) */
 
CSR_MZEXT = 0xfc0 /**< 0xfc0 - mzext (custom CSR) (r/-): Available Z* CPU extensions */
};
 
 
106,12 → 326,12
/**********************************************************************//**
* CPU <b>mstatus</b> CSR (r/w): Machine status (RISC-V spec.)
**************************************************************************/
enum NEORV32_CPU_MSTATUS_enum {
CPU_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */
CPU_MSTATUS_UBE = 6, /**< CPU mstatus CSR (6): UBE - User-mode endianness (little-endian=0, big-endian=1) (r/-) */
CPU_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */
CPU_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
CPU_MSTATUS_MPP_H = 12 /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
enum NEORV32_CSR_MSTATUS_enum {
CSR_MSTATUS_MIE = 3, /**< CPU mstatus CSR (3): MIE - Machine interrupt enable bit (r/w) */
CSR_MSTATUS_UBE = 6, /**< CPU mstatus CSR (6): UBE - User-mode endianness (little-endian=0, big-endian=1) (r/-) */
CSR_MSTATUS_MPIE = 7, /**< CPU mstatus CSR (7): MPIE - Machine previous interrupt enable bit (r/w) */
CSR_MSTATUS_MPP_L = 11, /**< CPU mstatus CSR (11): MPP_L - Machine previous privilege mode bit low (r/w) */
CSR_MSTATUS_MPP_H = 12 /**< CPU mstatus CSR (12): MPP_H - Machine previous privilege mode bit high (r/w) */
};
 
 
118,8 → 338,8
/**********************************************************************//**
* CPU <b>mstatush</b> CSR (r/-): Machine status - high word (RISC-V spec.)
**************************************************************************/
enum NEORV32_CPU_MSTATUSH_enum {
CPU_MSTATUSH_MBE = 5 /**< CPU mstatush CSR (5): MBE - Machine-mode endianness (little-endian=0, big-endian=1) (r/-) */
enum NEORV32_CSR_MSTATUSH_enum {
CSR_MSTATUSH_MBE = 5 /**< CPU mstatush CSR (5): MBE - Machine-mode endianness (little-endian=0, big-endian=1) (r/-) */
};
 
 
126,10 → 346,10
/**********************************************************************//**
* CPU <b>mcounteren</b> CSR (r/w): Machine counter enable (RISC-V spec.)
**************************************************************************/
enum NEORV32_CPU_MCOUNTEREN_enum {
CPU_MCOUNTEREN_CY = 0, /**< CPU mcounteren CSR (0): CY - Allow access to cycle[h] CSRs from U-mode when set (r/w) */
CPU_MCOUNTEREN_TM = 1, /**< CPU mcounteren CSR (1): TM - Allow access to time[h] CSRs from U-mode when set (r/w) */
CPU_MCOUNTEREN_IR = 2 /**< CPU mcounteren CSR (2): IR - Allow access to instret[h] CSRs from U-mode when set (r/w) */
enum NEORV32_CSR_MCOUNTEREN_enum {
CSR_MCOUNTEREN_CY = 0, /**< CPU mcounteren CSR (0): CY - Allow access to cycle[h] CSRs from U-mode when set (r/w) */
CSR_MCOUNTEREN_TM = 1, /**< CPU mcounteren CSR (1): TM - Allow access to time[h] CSRs from U-mode when set (r/w) */
CSR_MCOUNTEREN_IR = 2 /**< CPU mcounteren CSR (2): IR - Allow access to instret[h] CSRs from U-mode when set (r/w) */
};
 
 
136,9 → 356,9
/**********************************************************************//**
* CPU <b>mcountinhibit</b> CSR (r/w): Machine counter-inhibit (RISC-V spec.)
**************************************************************************/
enum NEORV32_CPU_MCOUNTINHIBIT_enum {
CPU_MCOUNTINHIBIT_CY = 0, /**< CPU mcountinhibit CSR (0): CY - Enable auto-increment of [m]cycle[h] CSR when set (r/w) */
CPU_MCOUNTINHIBIT_IR = 2 /**< CPU mcountinhibit CSR (2): IR - Enable auto-increment of [m]instret[h] CSR when set (r/w) */
enum NEORV32_CSR_MCOUNTINHIBIT_enum {
CSR_MCOUNTINHIBIT_CY = 0, /**< CPU mcountinhibit CSR (0): CY - Enable auto-increment of [m]cycle[h] CSR when set (r/w) */
CSR_MCOUNTINHIBIT_IR = 2 /**< CPU mcountinhibit CSR (2): IR - Enable auto-increment of [m]instret[h] CSR when set (r/w) */
};
 
 
145,14 → 365,14
/**********************************************************************//**
* CPU <b>mie</b> CSR (r/w): Machine interrupt enable (RISC-V spec.)
**************************************************************************/
enum NEORV32_CPU_MIE_enum {
CPU_MIE_MSIE = 3, /**< CPU mie CSR (3): MSIE - Machine software interrupt enable (r/w) */
CPU_MIE_MTIE = 7, /**< CPU mie CSR (7): MTIE - Machine timer interrupt enable bit (r/w) */
CPU_MIE_MEIE = 11, /**< CPU mie CSR (11): MEIE - Machine external interrupt enable bit (r/w) */
CPU_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w) */
CPU_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w) */
CPU_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w) */
CPU_MIE_FIRQ3E = 19 /**< CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) */
enum NEORV32_CSR_MIE_enum {
CSR_MIE_MSIE = 3, /**< CPU mie CSR (3): MSIE - Machine software interrupt enable (r/w) */
CSR_MIE_MTIE = 7, /**< CPU mie CSR (7): MTIE - Machine timer interrupt enable bit (r/w) */
CSR_MIE_MEIE = 11, /**< CPU mie CSR (11): MEIE - Machine external interrupt enable bit (r/w) */
CSR_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w) */
CSR_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w) */
CSR_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w) */
CSR_MIE_FIRQ3E = 19 /**< CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) */
};
 
 
159,15 → 379,15
/**********************************************************************//**
* CPU <b>mip</b> CSR (r/-): Machine interrupt pending (RISC-V spec.)
**************************************************************************/
enum NEORV32_CPU_MIP_enum {
CPU_MIP_MSIP = 3, /**< CPU mip CSR (3): MSIP - Machine software interrupt pending (r/-) */
CPU_MIP_MTIP = 7, /**< CPU mip CSR (7): MTIP - Machine timer interrupt pending (r/-) */
CPU_MIP_MEIP = 11, /**< CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) */
enum NEORV32_CSR_MIP_enum {
CSR_MIP_MSIP = 3, /**< CPU mip CSR (3): MSIP - Machine software interrupt pending (r/-) */
CSR_MIP_MTIP = 7, /**< CPU mip CSR (7): MTIP - Machine timer interrupt pending (r/-) */
CSR_MIP_MEIP = 11, /**< CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) */
 
CPU_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/-) */
CPU_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/-) */
CPU_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/-) */
CPU_MIP_FIRQ3P = 19 /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */
CSR_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/-) */
CSR_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/-) */
CSR_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/-) */
CSR_MIP_FIRQ3P = 19 /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */
};
 
 
174,18 → 394,19
/**********************************************************************//**
* CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.)
**************************************************************************/
enum NEORV32_CPU_MISA_enum {
CPU_MISA_A_EXT = 0, /**< CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)*/
CPU_MISA_B_EXT = 1, /**< CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)*/
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (4): E: Embedded CPU extension available (r/-) */
CPU_MISA_F_EXT = 4, /**< CPU misa CSR (5): F: Floating point (single-precision) extension available (r/-) */
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
CPU_MISA_U_EXT = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
enum NEORV32_CSR_MISA_enum {
CSR_MISA_A_EXT = 0, /**< CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)*/
CSR_MISA_B_EXT = 1, /**< CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)*/
CSR_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
CSR_MISA_D_EXT = 3, /**< CPU misa CSR (3): D: Floating point (double-precision) extension available (r/-) */
CSR_MISA_E_EXT = 4, /**< CPU misa CSR (4): E: Embedded CPU extension available (r/-) */
CSR_MISA_F_EXT = 5, /**< CPU misa CSR (5): F: Floating point (single-precision) extension available (r/-) */
CSR_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
CSR_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
CSR_MISA_U_EXT = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
CSR_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
CSR_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
CSR_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
};
 
 
192,14 → 413,36
/**********************************************************************//**
* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
**************************************************************************/
enum NEORV32_CPU_MZEXT_enum {
CPU_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */
CPU_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */
CPU_MZEXT_PMP = 2 /**< CPU mzext CSR (2): PMP extension available when set (r/-) */
enum NEORV32_CSR_MZEXT_enum {
CSR_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */
CSR_MZEXT_ZIFENCEI = 1 /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */
};
 
 
/**********************************************************************//**
* CPU <b>mhpmevent</b> hardware performance monitor events
**************************************************************************/
enum NEORV32_HPMCNT_EVENT_enum {
HPMCNT_EVENT_CY = 0, /**< CPU mhpmevent CSR (0): Active cycle */
HPMCNT_EVENT_IR = 2, /**< CPU mhpmevent CSR (2): Retired instruction */
 
HPMCNT_EVENT_CIR = 3, /**< CPU mhpmevent CSR (3): Retired compressed instruction */
HPMCNT_EVENT_WAIT_IF = 4, /**< CPU mhpmevent CSR (4): Instruction fetch memory wait cycle */
HPMCNT_EVENT_WAIT_II = 5, /**< CPU mhpmevent CSR (5): Instruction issue wait cycle */
HPMCNT_EVENT_LOAD = 6, /**< CPU mhpmevent CSR (6): Load operation */
HPMCNT_EVENT_STORE = 7, /**< CPU mhpmevent CSR (7): Store operation */
HPMCNT_EVENT_WAIT_LS = 8, /**< CPU mhpmevent CSR (8): Load/store memory wait cycle */
 
HPMCNT_EVENT_JUMP = 9, /**< CPU mhpmevent CSR (9): Unconditional jump */
HPMCNT_EVENT_BRANCH = 10, /**< CPU mhpmevent CSR (10): Conditional branch (taken or not taken) */
HPMCNT_EVENT_TBRANCH = 11, /**< CPU mhpmevent CSR (11): Conditional taken branch */
 
HPMCNT_EVENT_TRAP = 12, /**< CPU mhpmevent CSR (12): Entered trap */
HPMCNT_EVENT_ILLEGAL = 13 /**< CPU mhpmevent CSR (13): Illegal instruction exception */
};
 
 
/**********************************************************************//**
* Trap codes from mcause CSR.
**************************************************************************/
enum NEORV32_EXCEPTION_CODES_enum {
386,10 → 629,12
 
UART_CT_SIM_MODE = 12, /**< UART control register(12) (r/w): Simulation output override enable, for use in simulation only */
 
UART_CT_PMODE0 = 22, /**< UART control register(22) (r/w): Parity configuration (0=even; 1=odd) */
UART_CT_PMODE1 = 23, /**< UART control register(23) (r/w): Parity bit enabled when set */
UART_CT_PRSC0 = 24, /**< UART control register(24) (r/w): BAUD rate clock prescaler select bit 0 */
UART_CT_PRSC1 = 25, /**< UART control register(25) (r/w): BAUD rate clock prescaler select bit 1 */
UART_CT_PRSC2 = 26, /**< UART control register(26) (r/w): BAUD rate clock prescaler select bit 2 */
UART_CT_RXOR = 27, /**< UART control register(27) (r/-): RX data overrun when set */
 
UART_CT_EN = 28, /**< UART control register(28) (r/w): UART global enable */
UART_CT_RX_IRQ = 29, /**< UART control register(29) (r/w): Activate interrupt on RX done */
UART_CT_TX_IRQ = 30, /**< UART control register(30) (r/w): Activate interrupt on TX done */
400,7 → 645,10
enum NEORV32_UART_DATA_enum {
UART_DATA_LSB = 0, /**< UART receive/transmit data register(0) (r/w): Receive/transmit data LSB (bit 0) */
UART_DATA_MSB = 7, /**< UART receive/transmit data register(7) (r/w): Receive/transmit data MSB (bit 7) */
UART_DATA_AVAIL = 31 /**< UART receive/transmit data register(31) (r/-): RX data available when set */
UART_DATA_PERR = 28, /**< UART receive/transmit data register(18) (r/-): RX parity error detected when set */
UART_DATA_FERR = 29, /**< UART receive/transmit data register(29) (r/-): RX frame error (not valid stop bit) wdetected when set */
UART_DATA_OVERR = 30, /**< UART receive/transmit data register(30) (r/-): RX data overrun when set */
UART_DATA_AVAIL = 31 /**< UART receive/transmit data register(31) (r/-): RX data available when set */
};
/**@}*/
 
/sw/lib/include/neorv32_cpu.h
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
53,14 → 53,16
void neorv32_cpu_delay_ms(uint32_t time_ms);
void __attribute__((naked)) neorv32_cpu_goto_user_mode(void);
int neorv32_cpu_atomic_cas(uint32_t addr, uint32_t expected, uint32_t desired);
uint32_t neorv32_cpu_pmp_get_num_regions(void);
uint32_t neorv32_cpu_pmp_get_granularity(void);
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config);
uint32_t neorv32_cpu_hpm_get_counters(void);
 
 
/**********************************************************************//**
* Read data from CPU configuration and status register (CSR).
*
* @param[in] csr_id ID of CSR to read. See #NEORV32_CPU_CSRS_enum.
* @param[in] csr_id ID of CSR to read. See #NEORV32_CSR_enum.
* @return Read data (uint32_t).
**************************************************************************/
inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_csr_read(const int csr_id) {
76,7 → 78,7
/**********************************************************************//**
* Write data to CPU configuration and status register (CSR).
*
* @param[in] csr_id ID of CSR to write. See #NEORV32_CPU_CSRS_enum.
* @param[in] csr_id ID of CSR to write. See #NEORV32_CSR_enum.
* @param[in] data Data to write (uint32_t).
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_csr_write(const int csr_id, uint32_t data) {
108,7 → 110,7
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_eint(void) {
 
asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));
asm volatile ("csrrsi zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE));
asm volatile ("nop");
asm volatile ("nop");
}
119,7 → 121,7
**************************************************************************/
inline void __attribute__ ((always_inline)) neorv32_cpu_dint(void) {
 
asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CPU_MSTATUS_MIE));
asm volatile ("csrrci zero, mstatus, %0" : : "i" (1 << CSR_MSTATUS_MIE));
asm volatile ("nop");
asm volatile ("nop");
}
/sw/lib/include/neorv32_uart.h
49,12 → 49,13
 
// prototypes
int neorv32_uart_available(void);
void neorv32_uart_setup(uint32_t baudrate, uint8_t rx_irq, uint8_t tx_irq);
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity, uint8_t rx_irq, uint8_t tx_irq);
void neorv32_uart_disable(void);
void neorv32_uart_putc(char c);
int neorv32_uart_tx_busy(void);
char neorv32_uart_getc(void);
int neorv32_uart_char_received(void);
int neorv32_uart_getc_secure(char *data);
char neorv32_uart_char_received_get(void);
void neorv32_uart_print(const char *s);
void neorv32_uart_printf(const char *format, ...);
/sw/lib/source/neorv32_cpu.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
48,13 → 48,13
*
* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
*
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
* @return 0 if success, 1 if error (invalid irq_sel).
**************************************************************************/
int neorv32_cpu_irq_enable(uint8_t irq_sel) {
 
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
if ((irq_sel != CSR_MIE_MSIE) && (irq_sel != CSR_MIE_MTIE) && (irq_sel != CSR_MIE_MEIE) &&
(irq_sel != CSR_MIE_FIRQ0E) && (irq_sel != CSR_MIE_FIRQ1E) && (irq_sel != CSR_MIE_FIRQ2E) && (irq_sel != CSR_MIE_FIRQ3E)) {
return 1;
}
 
67,13 → 67,13
/**********************************************************************//**
* Disable specific CPU interrupt.
*
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
* @return 0 if success, 1 if error (invalid irq_sel).
**************************************************************************/
int neorv32_cpu_irq_disable(uint8_t irq_sel) {
 
if ((irq_sel != CPU_MIE_MSIE) && (irq_sel != CPU_MIE_MTIE) && (irq_sel != CPU_MIE_MEIE) &&
(irq_sel != CPU_MIE_FIRQ0E) && (irq_sel != CPU_MIE_FIRQ1E) && (irq_sel != CPU_MIE_FIRQ2E) && (irq_sel != CPU_MIE_FIRQ3E)) {
if ((irq_sel != CSR_MIE_MSIE) && (irq_sel != CSR_MIE_MTIE) && (irq_sel != CSR_MIE_MEIE) &&
(irq_sel != CSR_MIE_FIRQ0E) && (irq_sel != CSR_MIE_FIRQ1E) && (irq_sel != CSR_MIE_FIRQ2E) && (irq_sel != CSR_MIE_FIRQ3E)) {
return 1;
}
 
254,7 → 254,7
"li ra, %[input_imm] \n\t" // bit mask to clear the two MPP bits
"csrrc zero, mstatus, ra \n\t" // clear MPP bits -> MPP=u-mode
"mret \n\t" // return and switch to user mode
: : [input_imm] "i" ((1<<CPU_MSTATUS_MPP_H) | (1<<CPU_MSTATUS_MPP_L)));
: : [input_imm] "i" ((1<<CSR_MSTATUS_MPP_H) | (1<<CSR_MSTATUS_MPP_L)));
}
 
 
298,20 → 298,78
 
 
/**********************************************************************//**
* Physical memory protection (PMP): Get number of available regions.
*
* @warning This function overrides all available PMPCFG* CSRs.
* @warning This function requires the PMP CPU extension.
*
* @return Returns number of available PMP regions.
**************************************************************************/
uint32_t neorv32_cpu_pmp_get_num_regions(void) {
 
// try setting R bit in all PMPCFG CSRs
neorv32_cpu_csr_write(CSR_PMPCFG0, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG1, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG2, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG3, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG4, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG5, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG6, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG7, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG8, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG9, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG10, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG11, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG12, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG13, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG14, 0x01010101);
neorv32_cpu_csr_write(CSR_PMPCFG15, 0x01010101);
 
// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
union {
uint32_t uint32;
uint8_t uint8[sizeof(uint32_t)/sizeof(uint8_t)];
} cnt;
 
cnt.uint32 = 0;
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG0);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG1);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG2);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG3);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG4);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG5);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG6);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG7);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG8);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG9);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG10);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG11);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG12);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG13);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG14);
cnt.uint32 += neorv32_cpu_csr_read(CSR_PMPCFG15);
 
// sum up bytes
uint32_t num_regions = 0;
num_regions += (uint32_t)cnt.uint8[0];
num_regions += (uint32_t)cnt.uint8[1];
num_regions += (uint32_t)cnt.uint8[2];
num_regions += (uint32_t)cnt.uint8[3];
 
return num_regions;
}
 
 
/**********************************************************************//**
* Physical memory protection (PMP): Get minimal region size (granularity).
*
* @warning This function overrides PMPCFG0[0] and PMPADDR0 CSRs.
*
* @warning This function requires the PMP CPU extension.
*
* @return Returns minimal region size in bytes; Returns 0 on failure.
* @return Returns minimal region size in bytes.
**************************************************************************/
uint32_t neorv32_cpu_pmp_get_granularity(void) {
 
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) == 0) {
return 0; // PMP not implemented
}
 
// check min granulartiy
uint32_t tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
tmp &= 0xffffff00; // disable entry 0
338,8 → 396,9
* @note Using NAPOT mode - page base address has to be naturally aligned.
*
* @warning This function requires the PMP CPU extension.
* @warning Only use available PMP regions. Check before using neorv32_cpu_pmp_get_regions(void).
*
* @param[in] index Region number (index, 0..max_regions-1).
* @param[in] index Region number (index, 0..PMP_NUM_REGIONS-1).
* @param[in] base Region base address (has to be naturally aligned!).
* @param[in] size Region size, has to be a power of 2 (min 8 bytes or according to HW's PMP.granularity configuration).
* @param[in] config Region configuration (attributes) byte (for PMPCFGx).
347,10 → 406,6
**************************************************************************/
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config) {
 
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) == 0) {
return 1; // PMP not implemented
}
 
if (size < 8) {
return 1; // minimal region size is 8 bytes
}
366,16 → 421,25
config_mask = ~config_mask;
 
// clear old configuration
if (index < 3) {
tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
tmp &= config_mask; // clear old config
neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
switch(index & 15) {
case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, neorv32_cpu_csr_read(CSR_PMPCFG0) & config_mask); break;
case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, neorv32_cpu_csr_read(CSR_PMPCFG1) & config_mask); break;
case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, neorv32_cpu_csr_read(CSR_PMPCFG2) & config_mask); break;
case 3: neorv32_cpu_csr_write(CSR_PMPCFG3, neorv32_cpu_csr_read(CSR_PMPCFG3) & config_mask); break;
case 4: neorv32_cpu_csr_write(CSR_PMPCFG4, neorv32_cpu_csr_read(CSR_PMPCFG4) & config_mask); break;
case 5: neorv32_cpu_csr_write(CSR_PMPCFG5, neorv32_cpu_csr_read(CSR_PMPCFG5) & config_mask); break;
case 6: neorv32_cpu_csr_write(CSR_PMPCFG6, neorv32_cpu_csr_read(CSR_PMPCFG6) & config_mask); break;
case 7: neorv32_cpu_csr_write(CSR_PMPCFG7, neorv32_cpu_csr_read(CSR_PMPCFG7) & config_mask); break;
case 8: neorv32_cpu_csr_write(CSR_PMPCFG8, neorv32_cpu_csr_read(CSR_PMPCFG8) & config_mask); break;
case 9: neorv32_cpu_csr_write(CSR_PMPCFG9, neorv32_cpu_csr_read(CSR_PMPCFG9) & config_mask); break;
case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, neorv32_cpu_csr_read(CSR_PMPCFG10) & config_mask); break;
case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, neorv32_cpu_csr_read(CSR_PMPCFG11) & config_mask); break;
case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, neorv32_cpu_csr_read(CSR_PMPCFG12) & config_mask); break;
case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, neorv32_cpu_csr_read(CSR_PMPCFG13) & config_mask); break;
case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, neorv32_cpu_csr_read(CSR_PMPCFG14) & config_mask); break;
case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, neorv32_cpu_csr_read(CSR_PMPCFG15) & config_mask); break;
default: break;
}
else {
tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);
tmp &= config_mask; // clear old config
neorv32_cpu_csr_write(CSR_PMPCFG1, tmp);
}
 
// set base address and region size
uint32_t addr_mask = ~((size - 1) >> 2);
384,34 → 448,172
tmp = base & addr_mask;
tmp = tmp | size_mask;
 
switch(index & 7) {
case 0: neorv32_cpu_csr_write(CSR_PMPADDR0, tmp); break;
case 1: neorv32_cpu_csr_write(CSR_PMPADDR1, tmp); break;
case 2: neorv32_cpu_csr_write(CSR_PMPADDR2, tmp); break;
case 3: neorv32_cpu_csr_write(CSR_PMPADDR3, tmp); break;
case 4: neorv32_cpu_csr_write(CSR_PMPADDR4, tmp); break;
case 5: neorv32_cpu_csr_write(CSR_PMPADDR5, tmp); break;
case 6: neorv32_cpu_csr_write(CSR_PMPADDR6, tmp); break;
case 7: neorv32_cpu_csr_write(CSR_PMPADDR7, tmp); break;
switch(index & 63) {
case 0: neorv32_cpu_csr_write(CSR_PMPADDR0, tmp); break;
case 1: neorv32_cpu_csr_write(CSR_PMPADDR1, tmp); break;
case 2: neorv32_cpu_csr_write(CSR_PMPADDR2, tmp); break;
case 3: neorv32_cpu_csr_write(CSR_PMPADDR3, tmp); break;
case 4: neorv32_cpu_csr_write(CSR_PMPADDR4, tmp); break;
case 5: neorv32_cpu_csr_write(CSR_PMPADDR5, tmp); break;
case 6: neorv32_cpu_csr_write(CSR_PMPADDR6, tmp); break;
case 7: neorv32_cpu_csr_write(CSR_PMPADDR7, tmp); break;
case 8: neorv32_cpu_csr_write(CSR_PMPADDR8, tmp); break;
case 9: neorv32_cpu_csr_write(CSR_PMPADDR9, tmp); break;
case 10: neorv32_cpu_csr_write(CSR_PMPADDR10, tmp); break;
case 11: neorv32_cpu_csr_write(CSR_PMPADDR11, tmp); break;
case 12: neorv32_cpu_csr_write(CSR_PMPADDR12, tmp); break;
case 13: neorv32_cpu_csr_write(CSR_PMPADDR13, tmp); break;
case 14: neorv32_cpu_csr_write(CSR_PMPADDR14, tmp); break;
case 15: neorv32_cpu_csr_write(CSR_PMPADDR15, tmp); break;
case 16: neorv32_cpu_csr_write(CSR_PMPADDR16, tmp); break;
case 17: neorv32_cpu_csr_write(CSR_PMPADDR17, tmp); break;
case 18: neorv32_cpu_csr_write(CSR_PMPADDR18, tmp); break;
case 19: neorv32_cpu_csr_write(CSR_PMPADDR19, tmp); break;
case 20: neorv32_cpu_csr_write(CSR_PMPADDR20, tmp); break;
case 21: neorv32_cpu_csr_write(CSR_PMPADDR21, tmp); break;
case 22: neorv32_cpu_csr_write(CSR_PMPADDR22, tmp); break;
case 23: neorv32_cpu_csr_write(CSR_PMPADDR23, tmp); break;
case 24: neorv32_cpu_csr_write(CSR_PMPADDR24, tmp); break;
case 25: neorv32_cpu_csr_write(CSR_PMPADDR25, tmp); break;
case 26: neorv32_cpu_csr_write(CSR_PMPADDR26, tmp); break;
case 27: neorv32_cpu_csr_write(CSR_PMPADDR27, tmp); break;
case 28: neorv32_cpu_csr_write(CSR_PMPADDR28, tmp); break;
case 29: neorv32_cpu_csr_write(CSR_PMPADDR29, tmp); break;
case 30: neorv32_cpu_csr_write(CSR_PMPADDR30, tmp); break;
case 31: neorv32_cpu_csr_write(CSR_PMPADDR31, tmp); break;
case 32: neorv32_cpu_csr_write(CSR_PMPADDR32, tmp); break;
case 33: neorv32_cpu_csr_write(CSR_PMPADDR33, tmp); break;
case 34: neorv32_cpu_csr_write(CSR_PMPADDR34, tmp); break;
case 35: neorv32_cpu_csr_write(CSR_PMPADDR35, tmp); break;
case 36: neorv32_cpu_csr_write(CSR_PMPADDR36, tmp); break;
case 37: neorv32_cpu_csr_write(CSR_PMPADDR37, tmp); break;
case 38: neorv32_cpu_csr_write(CSR_PMPADDR38, tmp); break;
case 39: neorv32_cpu_csr_write(CSR_PMPADDR39, tmp); break;
case 40: neorv32_cpu_csr_write(CSR_PMPADDR40, tmp); break;
case 41: neorv32_cpu_csr_write(CSR_PMPADDR41, tmp); break;
case 42: neorv32_cpu_csr_write(CSR_PMPADDR42, tmp); break;
case 43: neorv32_cpu_csr_write(CSR_PMPADDR43, tmp); break;
case 44: neorv32_cpu_csr_write(CSR_PMPADDR44, tmp); break;
case 45: neorv32_cpu_csr_write(CSR_PMPADDR45, tmp); break;
case 46: neorv32_cpu_csr_write(CSR_PMPADDR46, tmp); break;
case 47: neorv32_cpu_csr_write(CSR_PMPADDR47, tmp); break;
case 48: neorv32_cpu_csr_write(CSR_PMPADDR48, tmp); break;
case 49: neorv32_cpu_csr_write(CSR_PMPADDR49, tmp); break;
case 50: neorv32_cpu_csr_write(CSR_PMPADDR50, tmp); break;
case 51: neorv32_cpu_csr_write(CSR_PMPADDR51, tmp); break;
case 52: neorv32_cpu_csr_write(CSR_PMPADDR52, tmp); break;
case 53: neorv32_cpu_csr_write(CSR_PMPADDR53, tmp); break;
case 54: neorv32_cpu_csr_write(CSR_PMPADDR54, tmp); break;
case 55: neorv32_cpu_csr_write(CSR_PMPADDR55, tmp); break;
case 56: neorv32_cpu_csr_write(CSR_PMPADDR56, tmp); break;
case 57: neorv32_cpu_csr_write(CSR_PMPADDR57, tmp); break;
case 58: neorv32_cpu_csr_write(CSR_PMPADDR58, tmp); break;
case 59: neorv32_cpu_csr_write(CSR_PMPADDR59, tmp); break;
case 60: neorv32_cpu_csr_write(CSR_PMPADDR60, tmp); break;
case 61: neorv32_cpu_csr_write(CSR_PMPADDR61, tmp); break;
case 62: neorv32_cpu_csr_write(CSR_PMPADDR62, tmp); break;
case 63: neorv32_cpu_csr_write(CSR_PMPADDR63, tmp); break;
default: break;
}
 
// wait for HW to computer PMP-internal stuff (address masks)
// wait for HW to compute PMP-internal stuff (address masks)
for (tmp=0; tmp<16; tmp++) {
asm volatile ("nop");
}
 
// set new configuration
if (index < 3) {
tmp = neorv32_cpu_csr_read(CSR_PMPCFG0);
tmp |= config_int; // set new config
neorv32_cpu_csr_write(CSR_PMPCFG0, tmp);
switch(index & 15) {
case 0: neorv32_cpu_csr_write(CSR_PMPCFG0, neorv32_cpu_csr_read(CSR_PMPCFG0) | config_int); break;
case 1: neorv32_cpu_csr_write(CSR_PMPCFG1, neorv32_cpu_csr_read(CSR_PMPCFG1) | config_int); break;
case 2: neorv32_cpu_csr_write(CSR_PMPCFG2, neorv32_cpu_csr_read(CSR_PMPCFG2) | config_int); break;
case 3: neorv32_cpu_csr_write(CSR_PMPCFG3, neorv32_cpu_csr_read(CSR_PMPCFG3) | config_int); break;
case 4: neorv32_cpu_csr_write(CSR_PMPCFG4, neorv32_cpu_csr_read(CSR_PMPCFG4) | config_int); break;
case 5: neorv32_cpu_csr_write(CSR_PMPCFG5, neorv32_cpu_csr_read(CSR_PMPCFG5) | config_int); break;
case 6: neorv32_cpu_csr_write(CSR_PMPCFG6, neorv32_cpu_csr_read(CSR_PMPCFG6) | config_int); break;
case 7: neorv32_cpu_csr_write(CSR_PMPCFG7, neorv32_cpu_csr_read(CSR_PMPCFG7) | config_int); break;
case 8: neorv32_cpu_csr_write(CSR_PMPCFG8, neorv32_cpu_csr_read(CSR_PMPCFG8) | config_int); break;
case 9: neorv32_cpu_csr_write(CSR_PMPCFG9, neorv32_cpu_csr_read(CSR_PMPCFG9) | config_int); break;
case 10: neorv32_cpu_csr_write(CSR_PMPCFG10, neorv32_cpu_csr_read(CSR_PMPCFG10) | config_int); break;
case 11: neorv32_cpu_csr_write(CSR_PMPCFG11, neorv32_cpu_csr_read(CSR_PMPCFG11) | config_int); break;
case 12: neorv32_cpu_csr_write(CSR_PMPCFG12, neorv32_cpu_csr_read(CSR_PMPCFG12) | config_int); break;
case 13: neorv32_cpu_csr_write(CSR_PMPCFG13, neorv32_cpu_csr_read(CSR_PMPCFG13) | config_int); break;
case 14: neorv32_cpu_csr_write(CSR_PMPCFG14, neorv32_cpu_csr_read(CSR_PMPCFG14) | config_int); break;
case 15: neorv32_cpu_csr_write(CSR_PMPCFG15, neorv32_cpu_csr_read(CSR_PMPCFG15) | config_int); break;
default: break;
}
else {
tmp = neorv32_cpu_csr_read(CSR_PMPCFG1);
tmp |= config_int; // set new config
neorv32_cpu_csr_write(CSR_PMPCFG1, tmp);
}
 
return 0;
}
 
 
/**********************************************************************//**
* Hardware performance monitors (HPM): Get number of available HPM counters.
*
* @warning This function overrides all available mhpmcounter* CSRs.
*
* @return Returns number of available HPM counters (..29).
**************************************************************************/
uint32_t neorv32_cpu_hpm_get_counters(void) {
 
// try setting all mhpmcounter* CSRs to 1
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER4, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER5, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER6, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER7, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER8, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER9, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER10, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER11, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER12, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER13, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER14, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER15, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER16, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER17, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER18, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER19, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER20, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER21, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER22, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER23, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER24, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER25, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER26, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER27, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER28, 1);
neorv32_cpu_csr_write(CSR_MHPMCOUNTER29, 1);
 
// sum up all written ones (only available PMPCFG* CSRs/entries will return =! 0)
uint32_t num_hpm_cnts = 0;
 
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER3);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER4);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER5);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER6);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER7);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER8);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER9);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER10);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER11);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER12);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER13);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER14);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER15);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER16);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER17);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER18);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER19);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER20);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER21);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER22);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER23);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER24);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER25);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER26);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER27);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER28);
num_hpm_cnts += neorv32_cpu_csr_read(CSR_MHPMCOUNTER29);
 
return num_hpm_cnts;
}
/sw/lib/source/neorv32_rte.c
3,7 → 3,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
288,7 → 288,7
// CPU extensions
neorv32_uart_printf("\nEndianness: ");
if (neorv32_cpu_csr_read(CSR_MSTATUSH) & (1<<CPU_MSTATUSH_MBE)) {
if (neorv32_cpu_csr_read(CSR_MSTATUSH) & (1<<CSR_MSTATUSH_MBE)) {
neorv32_uart_printf("big\n");
}
else {
296,7 → 296,7
}
// CPU extensions
neorv32_uart_printf("\nExtensions: ");
neorv32_uart_printf("Extensions: ");
tmp = neorv32_cpu_csr_read(CSR_MISA);
for (i=0; i<26; i++) {
if (tmp & (1 << i)) {
308,60 → 308,31
// Z* CPU extensions (from custom "mzext" CSR)
tmp = neorv32_cpu_csr_read(CSR_MZEXT);
if (tmp & (1<<CPU_MZEXT_ZICSR)) {
if (tmp & (1<<CSR_MZEXT_ZICSR)) {
neorv32_uart_printf("Zicsr ");
}
if (tmp & (1<<CPU_MZEXT_ZIFENCEI)) {
if (tmp & (1<<CSR_MZEXT_ZIFENCEI)) {
neorv32_uart_printf("Zifencei ");
}
if (tmp & (1<<CPU_MZEXT_PMP)) {
neorv32_uart_printf("PMP ");
}
 
 
// check physical memory protection
neorv32_uart_printf("\n\nPhysical memory protection: ");
if (neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CPU_MZEXT_PMP)) {
neorv32_uart_printf("\nPMP: ");
uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
if (pmp_num_regions != 0) {
// get number of available regions
neorv32_uart_printf("\n- Available regions: %u\n", pmp_num_regions);
 
// get minimal region siz (granulartiy)
neorv32_uart_printf("\n- Minimal granularity: %u bytes per region\n", neorv32_cpu_pmp_get_granularity());
 
// test available modes
neorv32_uart_printf("- Mode TOR: ");
neorv32_cpu_csr_write(CSR_PMPCFG0, 0x08);
if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xFF) == 0x08) {
neorv32_uart_printf("available\n");
}
else {
neorv32_uart_printf("not implemented\n");
}
 
neorv32_uart_printf("- Mode NA4: ");
neorv32_cpu_csr_write(CSR_PMPCFG0, 0x10);
if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xFF) == 0x10) {
neorv32_uart_printf("available\n");
}
else {
neorv32_uart_printf("not implemented\n");
}
 
neorv32_uart_printf("- Mode NAPOT: ");
neorv32_cpu_csr_write(CSR_PMPCFG0, 0x18);
if ((neorv32_cpu_csr_read(CSR_PMPCFG0) & 0xFF) == 0x18) {
neorv32_uart_printf("available\n");
}
else {
neorv32_uart_printf("not implemented\n");
}
 
// deactivate entry
neorv32_cpu_csr_write(CSR_PMPCFG0, 0);
// get minimal region size (granulartiy)
neorv32_uart_printf("- Minimal granularity: %u bytes per region\n", neorv32_cpu_pmp_get_granularity());
}
else {
neorv32_uart_printf("not implemented\n");
}
 
// check physical memory protection
neorv32_uart_printf("HPM Counters: %u\n", neorv32_cpu_hpm_get_counters());
 
 
// Misc - system
neorv32_uart_printf("\n\n---- Processor - General ----\n");
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
378,12 → 349,12
neorv32_uart_printf("Internal IMEM as ROM: ");
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM));
 
neorv32_uart_printf("\nData base address: 0x%x\n", SYSINFO_DSPACE_BASE);
neorv32_uart_printf("Data base address: 0x%x\n", SYSINFO_DSPACE_BASE);
neorv32_uart_printf("Internal DMEM: ");
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM));
neorv32_uart_printf("DMEM size: %u bytes\n", SYSINFO_DMEM_SIZE);
 
neorv32_uart_printf("\nInternal i-cache: ");
neorv32_uart_printf("Internal i-cache: ");
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE));
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE)) {
neorv32_uart_printf("- ");
419,12 → 390,12
}
}
 
neorv32_uart_printf("\nBootloader: ");
neorv32_uart_printf("Bootloader: ");
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
 
neorv32_uart_printf("\nExternal memory bus interface: ");
neorv32_uart_printf("Ext. bus interface: ");
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
neorv32_uart_printf("External memory bus Endianness: ");
neorv32_uart_printf("Ext. bus Endianness: ");
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT_ENDIAN)) {
neorv32_uart_printf("big\n");
}
542,7 → 513,9
**************************************************************************/
void neorv32_rte_print_credits(void) {
 
neorv32_uart_print("The NEORV32 Processor Project by Stephan Nolting\n"
neorv32_uart_print("The NEORV32 Processor Project\n"
"Copyright 2021, Stephan Nolting\n"
"BSD 3-Clause License\n"
"https://github.com/stnolting/neorv32\n\n");
}
 
597,7 → 570,7
"\n"
"BSD 3-Clause License\n"
"\n"
"Copyright (c) 2020, Stephan Nolting. All rights reserved.\n"
"Copyright (c) 2021, Stephan Nolting. All rights reserved.\n"
"\n"
"Redistribution and use in source and binary forms, with or without modification, are\n"
"permitted provided that the following conditions are met:\n"
/sw/lib/source/neorv32_uart.c
75,10 → 75,11
* @warning To enable simulation mode add <USER_FLAGS+=-DUART_SIM_MODE> when compiling.
*
* @param[in] baudrate Targeted BAUD rate (e.g. 9600).
* @param[in] parity PArity configuration (00=off, 10=even, 11=odd).
* @param[in] rx_irq Enable RX interrupt (data received) when 1.
* @param[in] tx_irq Enable TX interrupt (transmission done) when 1.
**************************************************************************/
void neorv32_uart_setup(uint32_t baudrate, uint8_t rx_irq, uint8_t tx_irq) {
void neorv32_uart_setup(uint32_t baudrate, uint8_t parity, uint8_t rx_irq, uint8_t tx_irq) {
 
UART_CT = 0; // reset
 
116,6 → 117,9
uint32_t uart_en = 1;
uart_en = uart_en << UART_CT_EN;
 
uint32_t parity_config = (uint32_t)(parity & 3);
parity_config = parity_config << UART_CT_PMODE0;
 
uint32_t rx_irq_en = (uint32_t)(rx_irq & 1);
rx_irq_en = rx_irq_en << UART_CT_RX_IRQ;
 
123,7 → 127,7
tx_irq_en = tx_irq_en << UART_CT_TX_IRQ;
 
/* Enable the UART for SIM mode. */
/* Only use this for simulation! */
/* USE THIS ONLY FOR SIMULATION! */
#ifdef UART_SIM_MODE
#warning UART_SIM_MODE enabled! Sending all UART.TX data to text.io simulation output instead of real UART transmitter. Use this for simulations only!
uint32_t sim_mode = 1 << UART_CT_SIM_MODE;
131,7 → 135,7
uint32_t sim_mode = 0;
#endif
 
UART_CT = prsc | baud | uart_en | rx_irq_en | tx_irq_en | sim_mode;
UART_CT = prsc | baud | uart_en | parity_config | rx_irq_en | tx_irq_en | sim_mode;
}
 
 
182,7 → 186,7
/**********************************************************************//**
* Get char from UART.
*
* @note This function is blocking.
* @note This function is blocking and does not check for UART frame/parity errors.
*
* @return Received char.
**************************************************************************/
199,8 → 203,48
 
 
/**********************************************************************//**
* Check if UARt has received a char.
* Get char from UART (and check errors).
*
* @note This function is non-blocking and checks for frame and parity errors.
*
* @param[in,out] data Received char.
* @return Status code (0=nothing received, 1: char received without errors; -1: char received with frame error; -2: char received with parity error; -3 char received with frame & parity error).
**************************************************************************/
int neorv32_uart_getc_secure(char *data) {
 
uint32_t uart_rx = UART_DATA;
if (uart_rx & (1<<UART_DATA_AVAIL)) { // char available at all?
 
int status = 0;
 
// check for frame error
if (uart_rx & (1<<UART_DATA_FERR)) {
status -= 1;
}
 
// check for parity error
if (uart_rx & (1<<UART_DATA_PERR)) {
status -= 2;
}
 
if (status == 0) {
status = 1;
}
 
// get received byte
*data = (char)uart_rx;
 
return status;
}
else {
return 0;
}
}
 
 
/**********************************************************************//**
* Check if UART has received a char.
*
* @note This function is non-blocking.
* @note Use neorv32_uart_char_received_get(void) to get the char.
*
/CHANGELOG.md
17,7 → 17,10
 
| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 26.12.2020 | 1.4.9.4 | removed `zicnt_en` option (was used to discard the standard RISC-V counters and timers from implementation); added missing `mcounteren` CSR (to allow read-access from user-level code to `cycle[h]` / `time[h]` / `[m]instret[h]` CSRs); available bits: 0: `CY`, 1: `TM`, 2: `IR`; added missing `mcountinhibit` CSR (to disable auto-increment of `[m]cycle[h]` / `[m]instret[h]` CSRs); available bits: 0: `CY`, 2: `IR` |
| 03.01.2021 | 1.4.9.8 | Added HPM trigger for instruction issue wait cycle (caused by pipeline flush); all HPM counters do not increment if CPU is sleep mode; fixed CoreMark timer overflow issues; `rtl/core/neorv32_busswitch.vhd`: removed wait states, less load/store wait cycles -> faster execution; updated CoreMark results |
| 02.01.2021 | 1.4.9.7 | :sparkles: added RISC-V hardware performance monitors (`HPM`); new CSRs: `mhpmevent*`(3..31), `[m]hpmcounter*[h]`(3..31), amount configurable via top's generic `HPM_NUM_CNTS`; supported counter events: active cycle, retired instruction, retired compressed instruction, instruction fetcch memory wait cycle, load operation, store operation, load/store memory wait cycle, unconditional jump, conditional branche (all), conditional taken branch, entered trap, illegal instruction exception; PMP can now have up to 64 regions; number of regions configured via top's `PMP_NUM_REGIONS` generic; removed obsolete top's `PMP_USE` generic; removed PMP flag from `mzext` CSR; minimal region granularity (in bytes) configured via top's `PMP_MIN_GRANULARITY` generic, has to be a power of two and >= 8 bytes; :bug: fixed bug in sleep (`wfi`) instruction |
| 29.12.2020 | 1.4.9.5 | New UART features: "frame check" (test if stop bit is set), error indicated via `UART_DATA` reg's `UART_DATA_FERR` flag; configurable parity bit (`UART_CT.UART_CT_PMODE1:UART_CT_PMODE0`, 00=no parity; 10=even parity; 11=odd parity); parity error indicated via `UART_DATA` reg's `UART_DATA_PERR` flag; moved UART's RX overrun flag to `UART_DATA.UART_DATA_OVERR` |
| 26.12.2020 | 1.4.9.4 | removed `zicnt_en` option (was used to discard the standard RISC-V counters and timers from implementation); added missing `mcounteren` CSR (to allow read-access from user-level code to `cycle[h]` / `time[h]` / `[m]instret[h]` CSRs); available bits: 0: `CY`, 1: `TM`, 2: `IR`; added missing `mcountinhibit` CSR (to disable auto-increment of `[m]cycle[h]` / `[m]instret[h]` CSRs); available bits: 0: `CY`, 2: `IR`; :warning: renamed CSR bits C-code-aliases: `CPU_*` -> `CSR_*` |
| 25.12.2020 | 1.4.9.3 | Added missing `UBE` flag to `mstatus` CSR, indicates Endianness for load/stores in user mode (always set indicating BIG-endian mode), is a copy of `mstatush.mbe` |
| 23.12.2020 | 1.4.9.2 | :sparkles: added processor-internal instruction cache `rtl/core/neorv32_cache.vhd` (direct mapped); new configuration generics: `ICACHE_USE` (implement cache), `ICACHE_BLOCK_SIZE` (cache block/page/line size), `ICACHE_NUM_BLOCKS` (number of cache blocks); added `SYSINFO_CACHE` register to SYSINFO to check cache configuration by software |
| 20.12.2020 | 1.4.9.1 | :bug: fixed bug in CPU's instruction fetch engine (alignment_errros/bus_errors were not acknowledged correctly); added `BUS_TIMEOUT` generic to CPU (defines the amount of cycles after which an *unacknowledged* bus access will get terminated and raises a bus access fault exception) |
/README.md
92,18 → 92,18
### To-Do / Wish List / Help Wanted
 
* Use LaTeX for data sheet
* Further size and performance optimization *(work in progress)*
* Further size and performance optimization *[work in progress]*
* Add associativity configuration for instruction cache
* Add a data cache
* Add *data* cache
* Burst mode for the external memory/bus interface
* RISC-V `B` extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) *(shelved)*
* RISC-V `F` (using `Zfinx`?) CPU extension (single-precision floating point) *[planning]*
* RISC-V `B` CPU extension ([bitmanipulation](https://github.com/riscv/riscv-bitmanip)) *[shelved]*
* Synthesis results (+ wrappers?) for more/specific platforms
* More support for FreeRTOS
* More support for FreeRTOS (like *all* traps)
* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
* Single-precision floating point unit (`F`) *(planned)*
* Implement further RISC-V (or custom?) CPU extensions
* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))
* Add memory-mapped trigger to testbench to quit simulation (using VHDL2008's `use std.env.finish;`) - but how? :thinking:
* Add memory-mapped trigger to testbench to quit simulation (maybe using VHDL2008's `use std.env.finish`?)
* ...
* [Ideas?](#ContributeFeedbackQuestions)
 
189,8 → 189,8
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
* System instructions: `MRET` `WFI`
* Pseudo-instructions are not listed
* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth` `mcounteren` `mcountinhibit`
* Machine CSRs: `mstatus` `mstatush` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
* Counter CSRs: `[m]cycle[h]` `[m]instret[m]` `time[h]` `[m]hpmcounter*[h]`(3..31, configurable) `mcounteren` `mcountinhibit` `mhpmevent*`(3..31, configurable)
* Machine CSRs: `mstatus[h]` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
* Supported exceptions and interrupts:
* Misaligned instruction address
* Instruction access fault (via unacknowledged bus access after timeout)
214,7 → 214,8
* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
 
**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
* Additional machine CSRs: `pmpcfg0` `pmpcfg1` `pmpaddr0` `pmpaddr1` `pmpaddr2` `pmpaddr3` `pmpaddr4` `pmpaddr5` `pmpaddr6` `pmpaddr7`
* Configurable number of regions
* Additional machine CSRs: `pmpcfg*`(0..15) `pmpaddr*`(0..63)
 
 
### Non-RISC-V-Compliant Issues
221,9 → 222,9
 
* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (non-maskable reset).
* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt").
 
 
### NEORV32-Specific CPU Extensions
243,8 → 244,8
This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
of the CPU's generics is assumed (for example no PMP). No constraints were used at all. The `u` and `Zifencei` extensions have
a negligible impact on the hardware requirements.
of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
No constraints were used at all. The `u` and `Zifencei` extensions have a negligible impact on the hardware requirements.
 
Results generated for hardware version [`1.4.9.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
306,6 → 307,7
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
bootloader to store and automatically boot an application program after reset (both tested successfully).
* The setups with `PMP` implement 2 regions with a minimal granularity of 64kB.
* No HPM counters are implemented.
 
 
 
317,11 → 319,9
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
 
Results generated for hardware version [`1.4.7.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
~~~
**Configuration**
Hardware: 32kB IMEM, 16kB DMEM, no caches, 100MHz clock
Hardware: 32kB IMEM, 16kB DMEM, no caches(!), 100MHz clock
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
Compiler flags: default, see makefile
328,13 → 328,15
Peripherals: UART for printing the results
~~~
 
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
| CPU (including `Zicsr`) | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
| `rv32i` | 27 424 bytes | `-O3` | 35.71 | **0.3571** |
| `rv32im` | 26 232 bytes | `-O3` | 66.66 | **0.6666** |
| `rv32imc` | 20 876 bytes | `-O3` | 66.66 | **0.6666** |
| `rv32imc` + `FAST_MUL_EN` | 20 876 bytes | `-O3` | 83.33 | **0.8333** |
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 20 876 bytes | `-O3` | 86.96 | **0.8696** |
| `rv32i` | 28 756 bytes | `-O3` | 36.36 | **0.3636** |
| `rv32im` | 27 516 bytes | `-O3` | 68.97 | **0.6897** |
| `rv32imc` | 22 008 bytes | `-O3` | 68.97 | **0.6897** |
| `rv32imc` + `FAST_MUL_EN` | 22 008 bytes | `-O3` | 86.96 | **0.8696** |
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 22 008 bytes | `-O3` | 90.91 | **0.9091** |
 
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
347,9 → 349,7
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
CPU extensions.
 
Please note that by default the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
CPU extensions. *By default* the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
`M` extension use a bit-serial approach and require several cycles for completion.
 
The following table shows the performance results for successfully running 2000 CoreMark
357,17 → 357,16
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
 
Results generated for hardware version [`1.4.7.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
| CPU (including `Zicsr`) | Required Clock Cycles | Executed Instructions | Average CPI |
|:--------------------------------------------|----------------------:|----------------------:|:-----------:|
| `rv32i` | 5 648 997 774 | 1 469 233 238 | **3.84** |
| `rv32im` | 3 036 749 774 | 601 871 338 | **5.05** |
| `rv32imc` | 3 036 959 882 | 615 034 616 | **4.94** |
| `rv32imc` + `FAST_MUL_EN` | 2 454 407 882 | 615 034 588 | **3.99** |
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 320 308 322 | 615 034 676 | **3.77** |
| `rv32i` | 5 595 750 503 | 1 466 028 607 | **3.82** |
| `rv32im` | 2 966 086 503 | 598 651 143 | **4.95** |
| `rv32imc` | 2 981 786 734 | 611 814 918 | **4.87** |
| `rv32imc` + `FAST_MUL_EN` | 2 399 234 734 | 611 814 918 | **3.92** |
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 265 135 174 | 611 814 948 | **3.70** |
 
 
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
 
593,7 → 592,7
 
#### BSD 3-Clause License
 
Copyright (c) 2020, Stephan Nolting. All rights reserved.
Copyright (c) 2021, Stephan Nolting. All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are
permitted provided that the following conditions are met:

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