URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Subversion Repositories neorv32
Compare Revisions
- This comparison shows the changes necessary to convert path
/neorv32/trunk
- from Rev 46 to Rev 47
- ↔ Reverse comparison
Rev 46 → Rev 47
/docs/figures/neorv32_processor.png
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svn:mime-type = application/octet-stream
/docs/Doxyfile
976,7 → 976,7
# (index.html). This can be useful if you have a project on for instance GitHub |
# and want to reuse the introduction page also for the doxygen output. |
|
USE_MDFILE_AS_MAINPAGE = ../README.md |
USE_MDFILE_AS_MAINPAGE = |
|
#--------------------------------------------------------------------------- |
# Configuration options related to source browsing |
/docs/NEORV32.pdf
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svn:mime-type = application/octet-stream
/riscv-compliance/README.md
1,7 → 1,5
# NEORV32 RISC-V-Compliance Test Framework |
|
**:sparkles: This setup uses the new [RISC-V Compliance Test Framework v2.1](https://github.com/riscv/riscv-compliance/releases/tag/v2.0) :sparkles:** |
|
## Overview |
|
This sub-project folder tests the [NEORV32 Processor Core](https://github.com/stnolting/neorv32) for **RISC-V compliance** by |
/rtl/core/neorv32_cfu1.vhd
File deleted
/rtl/core/neorv32_cfu0.vhd
File deleted
/rtl/core/neorv32_application_image.vhd
1,5 → 1,5
-- The NEORV32 Processor by Stephan Nolting, https://github.com/stnolting/neorv32 |
-- Auto-generated memory init file (for APPLICATION) from source file <cpu_test/main.bin> |
-- Auto-generated memory init file (for APPLICATION) from source file <blink_led/main.bin> |
|
library ieee; |
use ieee.std_logic_1164.all; |
6,7 → 6,7
|
package neorv32_application_image is |
|
type application_init_image_t is array (0 to 4082) of std_ulogic_vector(31 downto 0); |
type application_init_image_t is array (0 to 1032) of std_ulogic_vector(31 downto 0); |
constant application_init_image : application_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
35,4061 → 35,1011
00000024 => x"00000e93", |
00000025 => x"00000f13", |
00000026 => x"00000f93", |
00000027 => x"05136509", |
00000028 => x"10738005", |
00000029 => x"10733005", |
00000030 => x"21173040", |
00000031 => x"01138000", |
00000032 => x"7113f821", |
00000033 => x"0413ffc1", |
00000034 => x"01970001", |
00000035 => x"81938000", |
00000036 => x"05977761", |
00000037 => x"85930000", |
00000038 => x"907308e5", |
00000039 => x"05933055", |
00000040 => x"a023f800", |
00000041 => x"05910005", |
00000042 => x"feb01de3", |
00000043 => x"81018593", |
00000044 => x"86818613", |
00000045 => x"00c5d663", |
00000046 => x"00058023", |
00000047 => x"bfdd0585", |
00000048 => x"00004597", |
00000049 => x"ef858593", |
00000050 => x"80000617", |
00000051 => x"f3860613", |
00000052 => x"81018693", |
00000053 => x"00d65963", |
00000054 => x"00058703", |
00000055 => x"00e60023", |
00000056 => x"06050585", |
00000057 => x"0513bfc5", |
00000058 => x"05930000", |
00000059 => x"10730000", |
00000060 => x"1073b000", |
00000061 => x"1073b800", |
00000062 => x"1073b020", |
00000063 => x"d073b820", |
00000064 => x"10733063", |
00000065 => x"06373200", |
00000066 => x"10738000", |
00000067 => x"00ef3426", |
00000068 => x"707304e0", |
00000069 => x"00013004", |
00000070 => x"10500073", |
00000071 => x"0001a001", |
00000072 => x"c0221161", |
00000073 => x"2473c226", |
00000074 => x"43633420", |
00000075 => x"24730204", |
00000076 => x"14833410", |
00000077 => x"888d0004", |
00000078 => x"10730409", |
00000079 => x"04133414", |
00000080 => x"17630030", |
00000081 => x"24730094", |
00000082 => x"04093410", |
00000083 => x"34141073", |
00000084 => x"44124482", |
00000085 => x"00730121", |
00000086 => x"00003020", |
00000087 => x"11016515", |
00000088 => x"46014681", |
00000089 => x"05134581", |
00000090 => x"ce06b005", |
00000091 => x"ca26cc22", |
00000092 => x"10efc84a", |
00000093 => x"650938f0", |
00000094 => x"7e850513", |
00000095 => x"411010ef", |
00000096 => x"0513650d", |
00000097 => x"10ef8045", |
00000098 => x"650d4070", |
00000099 => x"82450513", |
00000100 => x"3fd010ef", |
00000101 => x"34202773", |
00000102 => x"800007b7", |
00000103 => x"14f71463", |
00000104 => x"0513650d", |
00000105 => x"00018445", |
00000106 => x"3e5010ef", |
00000107 => x"10ef4501", |
00000108 => x"45012370", |
00000109 => x"10ef4581", |
00000110 => x"45015830", |
00000111 => x"10ef4581", |
00000112 => x"478154b0", |
00000113 => x"32079073", |
00000114 => x"9073479d", |
00000115 => x"45013067", |
00000116 => x"10ef4581", |
00000117 => x"55fd24f0", |
00000118 => x"10ef557d", |
00000119 => x"10ef2830", |
00000120 => x"10ef16f0", |
00000121 => x"10ef1610", |
00000122 => x"650d5c60", |
00000123 => x"87450513", |
00000124 => x"10ef6485", |
00000125 => x"10ef39b0", |
00000126 => x"85934f60", |
00000127 => x"45013464", |
00000128 => x"4ac010ef", |
00000129 => x"8593842a", |
00000130 => x"45053464", |
00000131 => x"4a0010ef", |
00000132 => x"8593942a", |
00000133 => x"45093464", |
00000134 => x"494010ef", |
00000135 => x"8593942a", |
00000136 => x"450d3464", |
00000137 => x"488010ef", |
00000138 => x"8593942a", |
00000139 => x"45113464", |
00000140 => x"47c010ef", |
00000141 => x"8593942a", |
00000142 => x"45153464", |
00000143 => x"470010ef", |
00000144 => x"8593942a", |
00000145 => x"45193464", |
00000146 => x"464010ef", |
00000147 => x"8593942a", |
00000148 => x"451d3464", |
00000149 => x"458010ef", |
00000150 => x"8593942a", |
00000151 => x"45213464", |
00000152 => x"44c010ef", |
00000153 => x"8593942a", |
00000154 => x"45253464", |
00000155 => x"440010ef", |
00000156 => x"8593942a", |
00000157 => x"452d3464", |
00000158 => x"434010ef", |
00000159 => x"8593942a", |
00000160 => x"45293464", |
00000161 => x"428010ef", |
00000162 => x"8593942a", |
00000163 => x"45313464", |
00000164 => x"41c010ef", |
00000165 => x"8593942a", |
00000166 => x"45353464", |
00000167 => x"410010ef", |
00000168 => x"8593942a", |
00000169 => x"45393464", |
00000170 => x"404010ef", |
00000171 => x"8593942a", |
00000172 => x"453d3464", |
00000173 => x"3f8010ef", |
00000174 => x"8593942a", |
00000175 => x"45413464", |
00000176 => x"3ec010ef", |
00000177 => x"00a405b3", |
00000178 => x"650dc195", |
00000179 => x"89450513", |
00000180 => x"2bd010ef", |
00000181 => x"446240f2", |
00000182 => x"494244d2", |
00000183 => x"61054501", |
00000184 => x"00018082", |
00000185 => x"0513650d", |
00000186 => x"bd7d84c5", |
00000187 => x"10ef450d", |
00000188 => x"842a3cb0", |
00000189 => x"10ef451d", |
00000190 => x"942a3c30", |
00000191 => x"10ef452d", |
00000192 => x"942a3bb0", |
00000193 => x"10ef4541", |
00000194 => x"942a3b30", |
00000195 => x"10ef4545", |
00000196 => x"942a3ab0", |
00000197 => x"10ef4549", |
00000198 => x"942a3a30", |
00000199 => x"10ef454d", |
00000200 => x"942a39b0", |
00000201 => x"650dc411", |
00000202 => x"051385a2", |
00000203 => x"b74d8a85", |
00000204 => x"0513650d", |
00000205 => x"10ef8c05", |
00000206 => x"60732570", |
00000207 => x"00013004", |
00000208 => x"10730001", |
00000209 => x"84933424", |
00000210 => x"408c8181", |
00000211 => x"0513650d", |
00000212 => x"10ef8d85", |
00000213 => x"409c23b0", |
00000214 => x"c09c0785", |
00000215 => x"38d010ef", |
00000216 => x"000184aa", |
00000217 => x"10ef0001", |
00000218 => x"84133830", |
00000219 => x"e1998181", |
00000220 => x"3ca4f2e3", |
00000221 => x"342027f3", |
00000222 => x"3a079ee3", |
00000223 => x"7df000ef", |
00000224 => x"90734781", |
00000225 => x"400c3427", |
00000226 => x"0513650d", |
00000227 => x"10ef8fc5", |
00000228 => x"401c1ff0", |
00000229 => x"c01c0785", |
00000230 => x"381010ef", |
00000231 => x"000184aa", |
00000232 => x"10ef0001", |
00000233 => x"e1993770", |
00000234 => x"38a4fae3", |
00000235 => x"342027f3", |
00000236 => x"380796e3", |
00000237 => x"7a7000ef", |
00000238 => x"90734781", |
00000239 => x"400c3427", |
00000240 => x"0513650d", |
00000241 => x"10ef91c5", |
00000242 => x"401c1c70", |
00000243 => x"c01c0785", |
00000244 => x"320027f3", |
00000245 => x"0017e793", |
00000246 => x"32079073", |
00000247 => x"c00027f3", |
00000248 => x"00010001", |
00000249 => x"c0002773", |
00000250 => x"34f71ee3", |
00000251 => x"342027f3", |
00000252 => x"34079ae3", |
00000253 => x"767000ef", |
00000254 => x"320027f3", |
00000255 => x"90739bf9", |
00000256 => x"47813207", |
00000257 => x"34279073", |
00000258 => x"650d400c", |
00000259 => x"93c50513", |
00000260 => x"17d010ef", |
00000261 => x"0785401c", |
00000262 => x"27f3c01c", |
00000263 => x"9bf93060", |
00000264 => x"30679073", |
00000265 => x"325010ef", |
00000266 => x"c00027f3", |
00000267 => x"342026f3", |
00000268 => x"93e34709", |
00000269 => x"9be332e6", |
00000270 => x"00ef3007", |
00000271 => x"00017210", |
00000272 => x"306027f3", |
00000273 => x"0017e793", |
00000274 => x"30679073", |
00000275 => x"90734481", |
00000276 => x"400c3424", |
00000277 => x"0513650d", |
00000278 => x"10ef9745", |
00000279 => x"20ef1330", |
00000280 => x"ae230320", |
00000281 => x"01e380a1", |
00000282 => x"401c3005", |
00000283 => x"c01c0785", |
00000284 => x"b0349073", |
00000285 => x"907347a1", |
00000286 => x"90733237", |
00000287 => x"47c1b044", |
00000288 => x"32479073", |
00000289 => x"b0449073", |
00000290 => x"02000793", |
00000291 => x"32579073", |
00000292 => x"b0549073", |
00000293 => x"04000793", |
00000294 => x"32679073", |
00000295 => x"b0649073", |
00000296 => x"08000793", |
00000297 => x"32779073", |
00000298 => x"b0749073", |
00000299 => x"10000793", |
00000300 => x"32879073", |
00000301 => x"b0849073", |
00000302 => x"20000793", |
00000303 => x"32979073", |
00000304 => x"b0949073", |
00000305 => x"40000793", |
00000306 => x"32a79073", |
00000307 => x"b0a49073", |
00000308 => x"87136785", |
00000309 => x"10738007", |
00000310 => x"907332b7", |
00000311 => x"9073b0b4", |
00000312 => x"907332c7", |
00000313 => x"6789b0c4", |
00000314 => x"32d79073", |
00000315 => x"32049073", |
00000316 => x"342027f3", |
00000317 => x"260796e3", |
00000318 => x"663000ef", |
00000319 => x"90734481", |
00000320 => x"400c3424", |
00000321 => x"0513650d", |
00000322 => x"10ef9ac5", |
00000323 => x"401c0830", |
00000324 => x"c01c0785", |
00000325 => x"b0049073", |
00000326 => x"f0002023", |
00000327 => x"34202773", |
00000328 => x"1be3479d", |
00000329 => x"a58324f7", |
00000330 => x"650d8201", |
00000331 => x"9d450513", |
00000332 => x"f5158593", |
00000333 => x"059010ef", |
00000334 => x"623000ef", |
00000335 => x"90734781", |
00000336 => x"400c3427", |
00000337 => x"0637650d", |
00000338 => x"0513f000", |
00000339 => x"10ef9e05", |
00000340 => x"278303f0", |
00000341 => x"6705fa00", |
00000342 => x"8fe38ff9", |
00000343 => x"27832207", |
00000344 => x"8b89fe80", |
00000345 => x"220782e3", |
00000346 => x"0737401c", |
00000347 => x"0785f000", |
00000348 => x"07b7c01c", |
00000349 => x"87938000", |
00000350 => x"43940007", |
00000351 => x"c31443dc", |
00000352 => x"00e7c35c", |
00000353 => x"27f30007", |
00000354 => x"9be33420", |
00000355 => x"27731e07", |
00000356 => x"47bd3400", |
00000357 => x"1ef716e3", |
00000358 => x"5c3000ef", |
00000359 => x"90734781", |
00000360 => x"400c3427", |
00000361 => x"0513650d", |
00000362 => x"10efa285", |
00000363 => x"401c7e20", |
00000364 => x"c01c0785", |
00000365 => x"fff027f3", |
00000366 => x"34202773", |
00000367 => x"11e34789", |
00000368 => x"00ef1ef7", |
00000369 => x"00015990", |
00000370 => x"90734481", |
00000371 => x"400c3424", |
00000372 => x"0513650d", |
00000373 => x"10efa505", |
00000374 => x"401c7b60", |
00000375 => x"c01c0785", |
00000376 => x"c0149073", |
00000377 => x"34202773", |
00000378 => x"1fe34789", |
00000379 => x"00ef1af7", |
00000380 => x"000156d0", |
00000381 => x"90734781", |
00000382 => x"400c3427", |
00000383 => x"0513650d", |
00000384 => x"10efa805", |
00000385 => x"401c78a0", |
00000386 => x"c01c0785", |
00000387 => x"c0102073", |
00000388 => x"342027f3", |
00000389 => x"18079ee3", |
00000390 => x"543000ef", |
00000391 => x"90734781", |
00000392 => x"400c3427", |
00000393 => x"0513650d", |
00000394 => x"10efabc5", |
00000395 => x"10ef7620", |
00000396 => x"07e35e80", |
00000397 => x"401c1805", |
00000398 => x"c01c0785", |
00000399 => x"30047073", |
00000400 => x"00010001", |
00000401 => x"45814501", |
00000402 => x"614010ef", |
00000403 => x"00010001", |
00000404 => x"55fd557d", |
00000405 => x"608010ef", |
00000406 => x"30046073", |
00000407 => x"00010001", |
00000408 => x"34202773", |
00000409 => x"800007b7", |
00000410 => x"17e3079d", |
00000411 => x"00ef14f7", |
00000412 => x"00014ed0", |
00000413 => x"90734481", |
00000414 => x"400c3424", |
00000415 => x"0513650d", |
00000416 => x"10efae45", |
00000417 => x"10ef70a0", |
00000418 => x"01e35900", |
00000419 => x"401c1605", |
00000420 => x"c01c0785", |
00000421 => x"30047073", |
00000422 => x"00010001", |
00000423 => x"45814501", |
00000424 => x"5bc010ef", |
00000425 => x"00010001", |
00000426 => x"55fd557d", |
00000427 => x"5b0010ef", |
00000428 => x"344027f3", |
00000429 => x"0807f793", |
00000430 => x"120786e3", |
00000431 => x"34449073", |
00000432 => x"30046073", |
00000433 => x"00010001", |
00000434 => x"342027f3", |
00000435 => x"100792e3", |
00000436 => x"48b000ef", |
00000437 => x"30046073", |
00000438 => x"00010001", |
00000439 => x"90734781", |
00000440 => x"400c3427", |
00000441 => x"0513650d", |
00000442 => x"10efb445", |
00000443 => x"27f36a20", |
00000444 => x"8b913010", |
00000445 => x"10079ee3", |
00000446 => x"0785401c", |
00000447 => x"4789c01c", |
00000448 => x"27f39782", |
00000449 => x"9be33420", |
00000450 => x"650d0e07", |
00000451 => x"b7c50513", |
00000452 => x"67c010ef", |
00000453 => x"81418793", |
00000454 => x"07054398", |
00000455 => x"0001c398", |
00000456 => x"90734781", |
00000457 => x"400c3427", |
00000458 => x"0513650d", |
00000459 => x"10efbbc5", |
00000460 => x"401c65e0", |
00000461 => x"c01c0785", |
00000462 => x"f0000793", |
00000463 => x"27739782", |
00000464 => x"47853420", |
00000465 => x"0cf71ee3", |
00000466 => x"413000ef", |
00000467 => x"90734781", |
00000468 => x"400c3427", |
00000469 => x"0513650d", |
00000470 => x"10efbf45", |
00000471 => x"401c6320", |
00000472 => x"c01c0785", |
00000473 => x"fff01073", |
00000474 => x"34202773", |
00000475 => x"1de34789", |
00000476 => x"27730af7", |
00000477 => x"17b73430", |
00000478 => x"8793fff0", |
00000479 => x"15e30737", |
00000480 => x"00ef0af7", |
00000481 => x"00013d90", |
00000482 => x"90734781", |
00000483 => x"400c3427", |
00000484 => x"0513650d", |
00000485 => x"10efc285", |
00000486 => x"27f35f60", |
00000487 => x"8b913010", |
00000488 => x"08078ce3", |
00000489 => x"0785401c", |
00000490 => x"07b7c01c", |
00000491 => x"87938000", |
00000492 => x"80e70087", |
00000493 => x"27730007", |
00000494 => x"47893420", |
00000495 => x"06f71ae3", |
00000496 => x"39b000ef", |
00000497 => x"90734781", |
00000498 => x"400c3427", |
00000499 => x"0513650d", |
00000500 => x"10efc945", |
00000501 => x"401c5ba0", |
00000502 => x"c01c0785", |
00000503 => x"27739002", |
00000504 => x"478d3420", |
00000505 => x"06f712e3", |
00000506 => x"373000ef", |
00000507 => x"90734781", |
00000508 => x"400c3427", |
00000509 => x"0513650d", |
00000510 => x"10efcc45", |
00000511 => x"401c5920", |
00000512 => x"c01c0785", |
00000513 => x"00202003", |
00000514 => x"34202773", |
00000515 => x"11e34791", |
00000516 => x"00ef04f7", |
00000517 => x"00013490", |
00000518 => x"90734781", |
00000519 => x"400c3427", |
00000520 => x"0513650d", |
00000521 => x"10efcfc5", |
00000522 => x"401c5660", |
00000523 => x"c01c0785", |
00000524 => x"f0002783", |
00000525 => x"2773c63e", |
00000526 => x"47953420", |
00000527 => x"00f71ee3", |
00000528 => x"31b000ef", |
00000529 => x"90734781", |
00000530 => x"400c3427", |
00000531 => x"0513650d", |
00000532 => x"10efd2c5", |
00000533 => x"401c53a0", |
00000534 => x"c01c0785", |
00000535 => x"00002123", |
00000536 => x"34202773", |
00000537 => x"1d634799", |
00000538 => x"00ef7ef7", |
00000539 => x"00012f10", |
00000540 => x"90734781", |
00000541 => x"400c3427", |
00000542 => x"0513650d", |
00000543 => x"10efd645", |
00000544 => x"401c50e0", |
00000545 => x"c01c0785", |
00000546 => x"f0002023", |
00000547 => x"34202773", |
00000548 => x"1b63479d", |
00000549 => x"00ef7cf7", |
00000550 => x"00012c50", |
00000551 => x"90734781", |
00000552 => x"400c3427", |
00000553 => x"0513650d", |
00000554 => x"10efd945", |
00000555 => x"401c4e20", |
00000556 => x"c01c0785", |
00000557 => x"00000073", |
00000558 => x"34202773", |
00000559 => x"196347ad", |
00000560 => x"00ef7af7", |
00000561 => x"00012990", |
00000562 => x"90734781", |
00000563 => x"400c3427", |
00000564 => x"0513650d", |
00000565 => x"10efdd45", |
00000566 => x"27f34b60", |
00000567 => x"07373010", |
00000568 => x"8ff90010", |
00000569 => x"78078e63", |
00000570 => x"0785401c", |
00000571 => x"10efc01c", |
00000572 => x"007365a0", |
00000573 => x"27730000", |
00000574 => x"47a13420", |
00000575 => x"76f71e63", |
00000576 => x"25b000ef", |
00000577 => x"90734781", |
00000578 => x"400c3427", |
00000579 => x"0513650d", |
00000580 => x"10efe405", |
00000581 => x"10ef47a0", |
00000582 => x"0f633000", |
00000583 => x"401c7605", |
00000584 => x"45814501", |
00000585 => x"c01c0785", |
00000586 => x"334010ef", |
00000587 => x"00010001", |
00000588 => x"34202773", |
00000589 => x"800007b7", |
00000590 => x"1b63079d", |
00000591 => x"00ef74f7", |
00000592 => x"000121d0", |
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00000704 => x"104000ef", |
00000705 => x"00c12603", |
00000706 => x"00000693", |
00000707 => x"00000593", |
00000708 => x"05c000ef", |
00000709 => x"009504b3", |
00000710 => x"00a4b533", |
00000711 => x"00858433", |
00000712 => x"00850433", |
00000713 => x"f89ff0ef", |
00000714 => x"fe85eee3", |
00000715 => x"00b41463", |
00000716 => x"fe956ae3", |
00000717 => x"01c12083", |
00000718 => x"01812403", |
00000719 => x"01412483", |
00000720 => x"02010113", |
00000721 => x"00008067", |
00000722 => x"00050613", |
00000723 => x"00000513", |
00000724 => x"0015f693", |
00000725 => x"00068463", |
00000726 => x"00c50533", |
00000727 => x"0015d593", |
00000728 => x"00161613", |
00000729 => x"fe0596e3", |
00000730 => x"00008067", |
00000731 => x"00050313", |
00000732 => x"ff010113", |
00000733 => x"00060513", |
00000734 => x"00068893", |
00000735 => x"00112623", |
00000736 => x"00030613", |
00000737 => x"00050693", |
00000738 => x"00000713", |
00000739 => x"00000793", |
00000740 => x"00000813", |
00000741 => x"0016fe13", |
00000742 => x"00171e93", |
00000743 => x"000e0c63", |
00000744 => x"01060e33", |
00000745 => x"010e3833", |
00000746 => x"00e787b3", |
00000747 => x"00f807b3", |
00000748 => x"000e0813", |
00000749 => x"01f65713", |
00000750 => x"0016d693", |
00000751 => x"00eee733", |
00000752 => x"00161613", |
00000753 => x"fc0698e3", |
00000754 => x"00058663", |
00000755 => x"f7dff0ef", |
00000756 => x"00a787b3", |
00000757 => x"00088a63", |
00000758 => x"00030513", |
00000759 => x"00088593", |
00000760 => x"f69ff0ef", |
00000761 => x"00f507b3", |
00000762 => x"00c12083", |
00000763 => x"00080513", |
00000764 => x"00078593", |
00000765 => x"01010113", |
00000766 => x"00008067", |
00000767 => x"06054063", |
00000768 => x"0605c663", |
00000769 => x"00058613", |
00000770 => x"00050593", |
00000771 => x"fff00513", |
00000772 => x"02060c63", |
00000773 => x"00100693", |
00000774 => x"00b67a63", |
00000775 => x"00c05863", |
00000776 => x"00161613", |
00000777 => x"00169693", |
00000778 => x"feb66ae3", |
00000779 => x"00000513", |
00000780 => x"00c5e663", |
00000781 => x"40c585b3", |
00000782 => x"00d56533", |
00000783 => x"0016d693", |
00000784 => x"00165613", |
00000785 => x"fe0696e3", |
00000786 => x"00008067", |
00000787 => x"00008293", |
00000788 => x"fb5ff0ef", |
00000789 => x"00058513", |
00000790 => x"00028067", |
00000791 => x"40a00533", |
00000792 => x"00b04863", |
00000793 => x"40b005b3", |
00000794 => x"f9dff06f", |
00000795 => x"40b005b3", |
00000796 => x"00008293", |
00000797 => x"f91ff0ef", |
00000798 => x"40a00533", |
00000799 => x"00028067", |
00000800 => x"00008293", |
00000801 => x"0005ca63", |
00000802 => x"00054c63", |
00000803 => x"f79ff0ef", |
00000804 => x"00058513", |
00000805 => x"00028067", |
00000806 => x"40b005b3", |
00000807 => x"fe0558e3", |
00000808 => x"40a00533", |
00000809 => x"f61ff0ef", |
00000810 => x"40b00533", |
00000811 => x"00028067", |
00000812 => x"6f727245", |
00000813 => x"4e202172", |
00000814 => x"5047206f", |
00000815 => x"75204f49", |
00000816 => x"2074696e", |
00000817 => x"746e7973", |
00000818 => x"69736568", |
00000819 => x"2164657a", |
00000820 => x"0000000a", |
00000821 => x"6e696c42", |
00000822 => x"676e696b", |
00000823 => x"44454c20", |
00000824 => x"6d656420", |
00000825 => x"7270206f", |
00000826 => x"6172676f", |
00000827 => x"00000a6d", |
00000828 => x"0000032c", |
00000829 => x"00000338", |
00000830 => x"00000344", |
00000831 => x"00000350", |
00000832 => x"0000035c", |
00000833 => x"00000364", |
00000834 => x"0000036c", |
00000835 => x"00000374", |
00000836 => x"0000037c", |
00000837 => x"00000298", |
00000838 => x"00000298", |
00000839 => x"00000384", |
00000840 => x"0000038c", |
00000841 => x"00000298", |
00000842 => x"00000298", |
00000843 => x"00000298", |
00000844 => x"00000394", |
00000845 => x"00000298", |
00000846 => x"00000298", |
00000847 => x"00000298", |
00000848 => x"0000039c", |
00000849 => x"00000298", |
00000850 => x"00000298", |
00000851 => x"00000298", |
00000852 => x"00000298", |
00000853 => x"000003a4", |
00000854 => x"000003ac", |
00000855 => x"000003b4", |
00000856 => x"000003bc", |
00000857 => x"000003c4", |
00000858 => x"000003cc", |
00000859 => x"000003d4", |
00000860 => x"000003dc", |
00000861 => x"00007830", |
00000862 => x"4554523c", |
00000863 => x"0000203e", |
00000864 => x"74736e49", |
00000865 => x"74637572", |
00000866 => x"206e6f69", |
00000867 => x"72646461", |
00000868 => x"20737365", |
00000869 => x"6173696d", |
00000870 => x"6e67696c", |
00000871 => x"00006465", |
00000872 => x"74736e49", |
00000873 => x"74637572", |
00000874 => x"206e6f69", |
00000875 => x"65636361", |
00000876 => x"66207373", |
00000877 => x"746c7561", |
00000878 => x"00000000", |
00000879 => x"656c6c49", |
00000880 => x"206c6167", |
00000881 => x"74736e69", |
00000882 => x"74637572", |
00000883 => x"006e6f69", |
00000884 => x"61657242", |
00000885 => x"696f706b", |
00000886 => x"0000746e", |
00000887 => x"64616f4c", |
00000888 => x"64646120", |
00000889 => x"73736572", |
00000890 => x"73696d20", |
00000891 => x"67696c61", |
00000892 => x"0064656e", |
00000893 => x"64616f4c", |
00000894 => x"63636120", |
00000895 => x"20737365", |
00000896 => x"6c756166", |
00000897 => x"00000074", |
00000898 => x"726f7453", |
00000899 => x"64612065", |
00000900 => x"73657264", |
00000901 => x"696d2073", |
00000902 => x"696c6173", |
00000903 => x"64656e67", |
00000904 => x"00000000", |
00000905 => x"726f7453", |
00000906 => x"63612065", |
00000907 => x"73736563", |
00000908 => x"75616620", |
00000909 => x"0000746c", |
00000910 => x"69766e45", |
00000911 => x"6d6e6f72", |
00000912 => x"20746e65", |
00000913 => x"6c6c6163", |
00000914 => x"6f726620", |
00000915 => x"2d55206d", |
00000916 => x"65646f6d", |
00000917 => x"00000000", |
00000918 => x"69766e45", |
00000919 => x"6d6e6f72", |
00000920 => x"20746e65", |
00000921 => x"6c6c6163", |
00000922 => x"6f726620", |
00000923 => x"2d4d206d", |
00000924 => x"65646f6d", |
00000925 => x"00000000", |
00000926 => x"6863614d", |
00000927 => x"20656e69", |
00000928 => x"74666f73", |
00000929 => x"65726177", |
00000930 => x"746e6920", |
00000931 => x"75727265", |
00000932 => x"00007470", |
00000933 => x"6863614d", |
00000934 => x"20656e69", |
00000935 => x"656d6974", |
00000936 => x"6e692072", |
00000937 => x"72726574", |
00000938 => x"00747075", |
00000939 => x"6863614d", |
00000940 => x"20656e69", |
00000941 => x"65747865", |
00000942 => x"6c616e72", |
00000943 => x"746e6920", |
00000944 => x"75727265", |
00000945 => x"00007470", |
00000946 => x"74736146", |
00000947 => x"746e6920", |
00000948 => x"75727265", |
00000949 => x"00207470", |
00000950 => x"6e6b6e55", |
00000951 => x"206e776f", |
00000952 => x"70617274", |
00000953 => x"75616320", |
00000954 => x"203a6573", |
00000955 => x"00000000", |
00000956 => x"50204020", |
00000957 => x"00003d43", |
00000958 => x"544d202c", |
00000959 => x"3d4c4156", |
00000960 => x"00000000", |
00000961 => x"00000508", |
00000962 => x"00000554", |
00000963 => x"00000560", |
00000964 => x"0000056c", |
00000965 => x"00000578", |
00000966 => x"00000584", |
00000967 => x"00000590", |
00000968 => x"0000059c", |
00000969 => x"000005a8", |
00000970 => x"000004c4", |
00000971 => x"000004c4", |
00000972 => x"000005b4", |
00000973 => x"4554523c", |
00000974 => x"4157203e", |
00000975 => x"4e494e52", |
00000976 => x"43202147", |
00000977 => x"43205550", |
00000978 => x"73205253", |
00000979 => x"65747379", |
00000980 => x"6f6e206d", |
00000981 => x"76612074", |
00000982 => x"616c6961", |
00000983 => x"21656c62", |
00000984 => x"522f3c20", |
00000985 => x"003e4554", |
00000986 => x"5241570a", |
00000987 => x"474e494e", |
00000988 => x"57532021", |
00000989 => x"4153495f", |
00000990 => x"65662820", |
00000991 => x"72757461", |
00000992 => x"72207365", |
00000993 => x"69757165", |
00000994 => x"29646572", |
00000995 => x"20737620", |
00000996 => x"495f5748", |
00000997 => x"28204153", |
00000998 => x"74616566", |
00000999 => x"73657275", |
00001000 => x"61766120", |
00001001 => x"62616c69", |
00001002 => x"2029656c", |
00001003 => x"6d73696d", |
00001004 => x"68637461", |
00001005 => x"57530a21", |
00001006 => x"4153495f", |
00001007 => x"30203d20", |
00001008 => x"20782578", |
00001009 => x"6d6f6328", |
00001010 => x"656c6970", |
00001011 => x"6c662072", |
00001012 => x"29736761", |
00001013 => x"5f57480a", |
00001014 => x"20415349", |
00001015 => x"7830203d", |
00001016 => x"28207825", |
00001017 => x"6173696d", |
00001018 => x"72736320", |
00001019 => x"000a0a29", |
00001020 => x"33323130", |
00001021 => x"37363534", |
00001022 => x"42413938", |
00001023 => x"46454443", |
00001024 => x"33323130", |
00001025 => x"37363534", |
00001026 => x"00003938", |
00001027 => x"33323130", |
00001028 => x"37363534", |
00001029 => x"62613938", |
00001030 => x"66656463", |
00001031 => x"00000000", |
others => x"00000000" |
); |
|
/rtl/core/neorv32_bootloader_image.vhd
6,7 → 6,7
|
package neorv32_bootloader_image is |
|
type bootloader_init_image_t is array (0 to 988) of std_ulogic_vector(31 downto 0); |
type bootloader_init_image_t is array (0 to 999) of std_ulogic_vector(31 downto 0); |
constant bootloader_init_image : bootloader_init_image_t := ( |
00000000 => x"00000093", |
00000001 => x"00000113", |
32,19 → 32,19
00000021 => x"00000597", |
00000022 => x"0a458593", |
00000023 => x"30559073", |
00000024 => x"f8000593", |
00000024 => x"f0000593", |
00000025 => x"0005a023", |
00000026 => x"00458593", |
00000027 => x"feb01ce3", |
00000028 => x"80010597", |
00000029 => x"f9058593", |
00000030 => x"80418613", |
00000030 => x"80818613", |
00000031 => x"00c5d863", |
00000032 => x"00058023", |
00000033 => x"00158593", |
00000034 => x"ff5ff06f", |
00000035 => x"00001597", |
00000036 => x"ee458593", |
00000036 => x"f1058593", |
00000037 => x"80010617", |
00000038 => x"f6c60613", |
00000039 => x"80010697", |
90,912 → 90,923
00000079 => x"00810113", |
00000080 => x"30200073", |
00000081 => x"800007b7", |
00000082 => x"fd010113", |
00000083 => x"0007a023", |
00000084 => x"ffff07b7", |
00000085 => x"02112623", |
00000086 => x"02812423", |
00000087 => x"02912223", |
00000088 => x"03212023", |
00000089 => x"01312e23", |
00000090 => x"01412c23", |
00000091 => x"01512a23", |
00000092 => x"01612823", |
00000093 => x"01712623", |
00000094 => x"01812423", |
00000095 => x"4c478793", |
00000096 => x"30579073", |
00000097 => x"fe002403", |
00000098 => x"026267b7", |
00000099 => x"9ff78793", |
00000100 => x"00000693", |
00000101 => x"00000613", |
00000102 => x"00000593", |
00000103 => x"00200513", |
00000104 => x"0087f463", |
00000105 => x"00400513", |
00000106 => x"305000ef", |
00000107 => x"00100513", |
00000108 => x"3b1000ef", |
00000109 => x"00005537", |
00000110 => x"00000693", |
00000111 => x"00000613", |
00000112 => x"00000593", |
00000113 => x"b0050513", |
00000114 => x"1c9000ef", |
00000115 => x"181000ef", |
00000116 => x"00245793", |
00000117 => x"00a78533", |
00000118 => x"00f537b3", |
00000119 => x"00b785b3", |
00000120 => x"199000ef", |
00000121 => x"08000793", |
00000122 => x"30479073", |
00000123 => x"30046073", |
00000124 => x"00000013", |
00000082 => x"0007a023", |
00000083 => x"fd010113", |
00000084 => x"8001a223", |
00000085 => x"02812423", |
00000086 => x"fe002403", |
00000087 => x"026267b7", |
00000088 => x"02112623", |
00000089 => x"02912223", |
00000090 => x"03212023", |
00000091 => x"01312e23", |
00000092 => x"01412c23", |
00000093 => x"01512a23", |
00000094 => x"01612823", |
00000095 => x"01712623", |
00000096 => x"01812423", |
00000097 => x"9ff78793", |
00000098 => x"00000693", |
00000099 => x"00000613", |
00000100 => x"00000593", |
00000101 => x"00200513", |
00000102 => x"0087f463", |
00000103 => x"00400513", |
00000104 => x"339000ef", |
00000105 => x"00100513", |
00000106 => x"3e5000ef", |
00000107 => x"00005537", |
00000108 => x"00000693", |
00000109 => x"00000613", |
00000110 => x"00000593", |
00000111 => x"b0050513", |
00000112 => x"1f9000ef", |
00000113 => x"1b1000ef", |
00000114 => x"00245793", |
00000115 => x"00a78533", |
00000116 => x"00f537b3", |
00000117 => x"00b785b3", |
00000118 => x"1c9000ef", |
00000119 => x"ffff07b7", |
00000120 => x"4c878793", |
00000121 => x"30579073", |
00000122 => x"08000793", |
00000123 => x"30479073", |
00000124 => x"30046073", |
00000125 => x"00000013", |
00000126 => x"ffff1537", |
00000127 => x"e8c50513", |
00000128 => x"255000ef", |
00000129 => x"f1302573", |
00000130 => x"24c000ef", |
00000131 => x"ffff1537", |
00000132 => x"ec450513", |
00000133 => x"241000ef", |
00000134 => x"fe002503", |
00000135 => x"238000ef", |
00000136 => x"ffff1537", |
00000137 => x"ecc50513", |
00000138 => x"22d000ef", |
00000139 => x"fe402503", |
00000140 => x"224000ef", |
00000141 => x"ffff1537", |
00000142 => x"ed850513", |
00000143 => x"219000ef", |
00000144 => x"30102573", |
00000145 => x"210000ef", |
00000146 => x"ffff1537", |
00000147 => x"ee050513", |
00000148 => x"205000ef", |
00000149 => x"fe802503", |
00000150 => x"ffff14b7", |
00000151 => x"00341413", |
00000152 => x"1f4000ef", |
00000153 => x"ffff1537", |
00000154 => x"ee850513", |
00000155 => x"1e9000ef", |
00000156 => x"ff802503", |
00000157 => x"1e0000ef", |
00000158 => x"ef048513", |
00000159 => x"1d9000ef", |
00000160 => x"ff002503", |
00000161 => x"1d0000ef", |
00000162 => x"ffff1537", |
00000163 => x"efc50513", |
00000164 => x"1c5000ef", |
00000165 => x"ffc02503", |
00000166 => x"1bc000ef", |
00000167 => x"ef048513", |
00000168 => x"1b5000ef", |
00000169 => x"ff402503", |
00000170 => x"1ac000ef", |
00000171 => x"ffff1537", |
00000172 => x"f0450513", |
00000173 => x"1a1000ef", |
00000174 => x"095000ef", |
00000175 => x"00a404b3", |
00000176 => x"0084b433", |
00000177 => x"00b40433", |
00000178 => x"fa402783", |
00000179 => x"0207d263", |
00000180 => x"ffff1537", |
00000181 => x"f2c50513", |
00000182 => x"17d000ef", |
00000183 => x"16d000ef", |
00000184 => x"02300793", |
00000185 => x"02f51263", |
00000186 => x"00000513", |
00000187 => x"0180006f", |
00000188 => x"05d000ef", |
00000189 => x"fc85eae3", |
00000190 => x"00b41463", |
00000191 => x"fc9566e3", |
00000192 => x"00100513", |
00000193 => x"5b8000ef", |
00000194 => x"0b4000ef", |
00000195 => x"ffff1937", |
00000196 => x"ffff19b7", |
00000197 => x"02300a13", |
00000198 => x"07200a93", |
00000199 => x"06800b13", |
00000200 => x"07500b93", |
00000201 => x"ffff14b7", |
00000202 => x"ffff1c37", |
00000203 => x"f3890513", |
00000204 => x"125000ef", |
00000205 => x"105000ef", |
00000206 => x"00050413", |
00000207 => x"0ed000ef", |
00000208 => x"e4498513", |
00000209 => x"111000ef", |
00000210 => x"fb4400e3", |
00000211 => x"01541863", |
00000212 => x"ffff02b7", |
00000213 => x"00028067", |
00000214 => x"fd5ff06f", |
00000215 => x"01641663", |
00000216 => x"05c000ef", |
00000217 => x"fc9ff06f", |
00000218 => x"00000513", |
00000219 => x"03740063", |
00000220 => x"07300793", |
00000221 => x"00f41663", |
00000222 => x"658000ef", |
00000223 => x"fb1ff06f", |
00000224 => x"06c00793", |
00000225 => x"00f41863", |
00000226 => x"00100513", |
00000227 => x"3f4000ef", |
00000228 => x"f9dff06f", |
00000229 => x"06500793", |
00000230 => x"00f41663", |
00000231 => x"02c000ef", |
00000232 => x"f8dff06f", |
00000233 => x"03f00793", |
00000234 => x"f40c0513", |
00000235 => x"00f40463", |
00000236 => x"f5448513", |
00000237 => x"0a1000ef", |
00000238 => x"f75ff06f", |
00000239 => x"ffff1537", |
00000240 => x"d6850513", |
00000241 => x"0910006f", |
00000242 => x"800007b7", |
00000243 => x"0007a783", |
00000244 => x"00079863", |
00000245 => x"ffff1537", |
00000246 => x"dcc50513", |
00000247 => x"0790006f", |
00000248 => x"ff010113", |
00000249 => x"00112623", |
00000250 => x"30047073", |
00000251 => x"00000013", |
00000126 => x"00000013", |
00000127 => x"ffff1537", |
00000128 => x"eb850513", |
00000129 => x"27d000ef", |
00000130 => x"f1302573", |
00000131 => x"24c000ef", |
00000132 => x"ffff1537", |
00000133 => x"ef050513", |
00000134 => x"269000ef", |
00000135 => x"fe002503", |
00000136 => x"238000ef", |
00000137 => x"ffff1537", |
00000138 => x"ef850513", |
00000139 => x"255000ef", |
00000140 => x"fe402503", |
00000141 => x"224000ef", |
00000142 => x"ffff1537", |
00000143 => x"f0450513", |
00000144 => x"241000ef", |
00000145 => x"30102573", |
00000146 => x"210000ef", |
00000147 => x"ffff1537", |
00000148 => x"f0c50513", |
00000149 => x"22d000ef", |
00000150 => x"fe802503", |
00000151 => x"ffff14b7", |
00000152 => x"00341413", |
00000153 => x"1f4000ef", |
00000154 => x"ffff1537", |
00000155 => x"f1450513", |
00000156 => x"211000ef", |
00000157 => x"ff802503", |
00000158 => x"1e0000ef", |
00000159 => x"f1c48513", |
00000160 => x"201000ef", |
00000161 => x"ff002503", |
00000162 => x"1d0000ef", |
00000163 => x"ffff1537", |
00000164 => x"f2850513", |
00000165 => x"1ed000ef", |
00000166 => x"ffc02503", |
00000167 => x"1bc000ef", |
00000168 => x"f1c48513", |
00000169 => x"1dd000ef", |
00000170 => x"ff402503", |
00000171 => x"1ac000ef", |
00000172 => x"ffff1537", |
00000173 => x"f3050513", |
00000174 => x"1c9000ef", |
00000175 => x"0b9000ef", |
00000176 => x"00a404b3", |
00000177 => x"0084b433", |
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00000723 => x"fbdff06f", |
00000724 => x"01c12083", |
00000725 => x"01812403", |
00000726 => x"01412483", |
00000727 => x"01012903", |
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00000729 => x"00812a03", |
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00000734 => x"f9402783", |
00000735 => x"f9002703", |
00000736 => x"f9402683", |
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00000997 => x"42413938", |
00000998 => x"46454443", |
others => x"00000000" |
); |
|
/rtl/core/neorv32_cfs.vhd
0,0 → 1,253
-- ################################################################################################# |
-- # << NEORV32 - Custom Functions Subsystem (CFS) >> # |
-- # ********************************************************************************************* # |
-- # For tightly-coupled custom co-processors. Provides 32x32-bit memory-mapped registers. # |
-- # This is just an "example/illustrating template". Modify this file to implement your custom # |
-- # design logic. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
-- # # |
-- # 1. Redistributions of source code must retain the above copyright notice, this list of # |
-- # conditions and the following disclaimer. # |
-- # # |
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
-- # conditions and the following disclaimer in the documentation and/or other materials # |
-- # provided with the distribution. # |
-- # # |
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
-- # endorse or promote products derived from this software without specific prior written # |
-- # permission. # |
-- # # |
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
-- # OF THE POSSIBILITY OF SUCH DAMAGE. # |
-- # ********************************************************************************************* # |
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
-- ################################################################################################# |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
library neorv32; |
use neorv32.neorv32_package.all; |
|
entity neorv32_cfs is |
generic ( |
CFS_CONFIG : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration conduit generic |
); |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active, use as async |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- word write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
-- clock generator -- |
clkgen_en_o : out std_ulogic; -- enable clock generator |
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs |
-- CPU state -- |
sleep_i : in std_ulogic; -- set if cpu is in sleep mode |
-- interrupt -- |
irq_o : out std_ulogic; -- interrupt request |
irq_ack_i : in std_ulogic; -- interrupt acknowledge |
-- custom io (conduits) -- |
cfs_in_i : in std_ulogic_vector(31 downto 0); -- custom inputs |
cfs_out_o : out std_ulogic_vector(31 downto 0) -- custom outputs |
); |
end neorv32_cfs; |
|
architecture neorv32_cfs_rtl of neorv32_cfs is |
|
-- IO space: module base address (DO NOT MODIFY!) -- |
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(cfs_size_c); -- low address boundary bit |
|
-- access control -- |
signal acc_en : std_ulogic; -- module access enable |
signal addr : std_ulogic_vector(31 downto 0); -- access address |
signal wren : std_ulogic; -- word write enable |
signal rden : std_ulogic; -- read enable |
|
-- default CFS interface registers -- |
type cfs_regs_t is array (0 to 3) of std_ulogic_vector(31 downto 0); -- just implement 4 registers for this example |
signal cfs_reg_wr : cfs_regs_t; -- interface registers for WRITE accesses |
signal cfs_reg_rd : cfs_regs_t; -- interface registers for READ accesses |
|
begin |
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- These assignments are required to check if the CFS is accessed at all. |
-- DO NOT MODIFY this unless you really know what you are doing. |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfs_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
addr <= cfs_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned |
wren <= acc_en and wren_i; -- full 32-bit word write enable |
rden <= acc_en and rden_i; -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU |
|
|
-- CFS Generic ---------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- In its default version, the CFS provides a single generic: CFS_CONFIG. This generic can be set using the processor top's IO_CFS_CONFIG generic. |
-- It is intended as a "conduit" to propagate custom implementation option from the top down to this entiy. |
|
|
-- CFS IOs -------------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- By default, the CFS provides two IO signals (cfs_in_i and cfs_out_o) that are available at the processor top entity. |
-- These are intended as "conduits" to propagate custom signals this entity <=> processor top entity. |
|
cfs_out_o <= (others => '0'); -- not used for this minimal example |
|
|
-- Reset System --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- The CFS can be reset using the global rstn_i signal. This signal should be used as asynchronous reset and is active-low. |
-- Note that rstn_i can be asserted by an external reset and also by a watchdog-cause reset. |
-- |
-- Most default peripheral devices of the NEORV32 do NOT use a dedicated reset at all. Instead, these units are reset by writing ZERO |
-- to a specific "control register" located right at the beginning of the devices's address space (so this register is cleared at first). |
-- The crt0 start-up code write ZERO to every single address in the processor's IO space - including the CFS. |
-- Make sure that this clearing does not cause any unintended actions in the CFS. |
|
|
-- Clock System --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- The processor top unit implements a clock generator providing 8 "derived clocks" |
-- Actually, these signals should not be used as direct clock signals, but as *clock enable* signals. |
-- clkgen_i is always synchronous to the main system clock (clk_i). |
-- |
-- The following clock divider rates are available: |
-- clkgen_i(clk_div2_c) -> MAIN_CLK/2 |
-- clkgen_i(clk_div4_c) -> MAIN_CLK/4 |
-- clkgen_i(clk_div8_c) -> MAIN_CLK/8 |
-- clkgen_i(clk_div64_c) -> MAIN_CLK/64 |
-- clkgen_i(clk_div128_c) -> MAIN_CLK/128 |
-- clkgen_i(clk_div1024_c) -> MAIN_CLK/1024 |
-- clkgen_i(clk_div2048_c) -> MAIN_CLK/2048 |
-- clkgen_i(clk_div4096_c) -> MAIN_CLK/4096 |
-- |
-- For instance, if you want to drive a clock process at MAIN_CLK/8 clock speed you can use the following construct: |
-- |
-- if (rstn_i = '0') then -- async and low-active reset (if required at all) |
-- ... |
-- elsif rising_edge(clk_i) then -- always use the main clock for all clock processes! |
-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable |
-- ... |
-- end if; |
-- end if; |
-- |
-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the UART) requires the clocks generated by the |
-- clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high. |
-- The CFS cannot ensure to deactive the clock generator by setting the clkgen_en_o signal low as other peripherals might still keep the generator activated. |
-- Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to reduce dynamic power consumption. |
|
clkgen_en_o <= '0'; -- not used for this minimal example |
|
|
-- Further Power Optimization ------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- The CFS can decide to go into low-power mode (by disabling all switching activity) when the CPU enters sleep mode. |
-- The sleep_i signal is high when the CPU is in sleep mode. Any interrupt including the CFS's irq_o interrupt request signal |
-- will wake up the CPU again. |
|
|
-- Interrupt ------------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
-- The CFS features a single interrupt signal. This interrupt is connected to the CPU's "fast interrupt" channel 1. |
-- Note that this fast interrupt channel is shared with the GPIO pin-change interrupt. Make sure to disable the GPIO's pin-change interrupt |
-- via the according control register if you want to use this interrupt exclusively for the CFS. |
-- |
-- The interrupt is single-shot. Setting the irq_o signal high for one cycle will generate an interrupt request. |
-- The interrupt is acknowledged by the CPU via the one-shot irq_ack_i signal indicating that the according interrupt handler is starting. |
|
irq_o <= '0'; -- not used for this minimal example |
|
|
-- Read/Write Access ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO |
-- modules of the NEORV32 can only be written in full word mode (32-bit). Any other write access (half-word or byte) |
-- will trigger a store bus access fault exception. |
-- |
-- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide |
-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register> |
-- for issueing commands and a <status register> for status information. |
-- |
-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal. |
-- If no ACK is generated, the bus access will time out and cause a store bus access fault exception. This exception can also be immediatly |
-- triggered by setting err_o high for one cycle (only during a valid bus access). |
|
err_o <= '0'; -- not used for this minimal example |
|
-- Host access: Read and write access to the interface registers + bus transfer acknowledge. |
-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not |
-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged. |
|
host_access: process(clk_i) |
begin |
if rising_edge(clk_i) then -- synchronous interface for reads and writes |
-- transfer/access acknowledge -- |
ack_o <= rden or wren; -- default: required for the CPU to check the CFS is answering a bus read OR write request; all r/w accesses (to any cfs_reg) will succeed |
-- ack_o <= rden; -- use this construct if your CFS is read-only |
-- ack_o <= wren; -- use this construct if your CFS is write-only |
-- ack_o <= ... -- or define the ACK by yourself (example: some registers are read-only, some others can only be written, ...) |
|
-- write access -- |
for i in 0 to 3 loop -- iterate over all 4 bytes in a word |
if (wren = '1') then -- word-wide write-access only! |
case addr is -- make sure to use the internal 'addr' signal for the read/write interface |
when cfs_reg0_addr_c => cfs_reg_wr(0) <= data_i; -- for example: control register |
when cfs_reg1_addr_c => cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo |
when cfs_reg2_addr_c => cfs_reg_wr(2) <= data_i; -- for example: command fifo |
when cfs_reg3_addr_c => cfs_reg_wr(3) <= data_i; -- for example: status register |
when others => NULL; |
end case; |
end if; |
end loop; -- i |
|
-- read access -- |
data_o <= (others => '0'); -- the output has to be zero if there is no actual read access |
if (rden = '1') then -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU |
case addr is -- make sure to use the internal 'addr' signal for the read/write interface |
when cfs_reg0_addr_c => data_o <= cfs_reg_rd(0); |
when cfs_reg1_addr_c => data_o <= cfs_reg_rd(1); |
when cfs_reg2_addr_c => data_o <= cfs_reg_rd(2); |
when cfs_reg3_addr_c => data_o <= cfs_reg_rd(3); |
when others => data_o <= (others => '0'); -- the remaining registers are not implemented and will read as zero |
end case; |
end if; |
end if; |
end process host_access; |
|
|
-- CFS Function Core ---------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- This is where the actual functionality can be implemented. |
-- In this example we are just implementing four r/w registers that invert any value written to them. |
|
cfs_core: process(cfs_reg_wr) |
begin |
cfs_reg_rd(0) <= not cfs_reg_wr(0); -- just invert the written value |
cfs_reg_rd(1) <= not cfs_reg_wr(1); |
cfs_reg_rd(2) <= not cfs_reg_wr(2); |
cfs_reg_rd(3) <= not cfs_reg_wr(3); |
end process cfs_core; |
|
|
end neorv32_cfs_rtl; |
/rtl/core/neorv32_cpu.vhd
2,14 → 2,14
-- # << NEORV32 - CPU Top Entity >> # |
-- # ********************************************************************************************* # |
-- # NEORV32 CPU: # |
-- # * neorv32_cpu.vhd - CPU top entity # |
-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit # |
-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit # |
-- # * neorv32_cpu_cp_muldiv.vhd - MULDIV co-processor # |
-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system # |
-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder # |
-- # * neorv32_cpu_regfile.vhd - Data register file # |
-- # * neorv32_package.vhd - Main CPU/processor package file # |
-- # * neorv32_cpu.vhd - CPU top entity # |
-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit # |
-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit # |
-- # * neorv32_cpu_cp_muldiv.vhd - MULDIV co-processor # |
-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system # |
-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder # |
-- # * neorv32_cpu_regfile.vhd - Data register file # |
-- # * neorv32_package.vhd - Main CPU/processor package file # |
-- # # |
-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf # |
-- # ********************************************************************************************* # |
73,12 → 73,13
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) |
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS : natural := 0 -- number of implemented HPM counters (0..29) |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
sleep_o : out std_ulogic; -- cpu is in sleep mode when set |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
112,7 → 113,8
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0') |
firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); |
firq_ack_o : out std_ulogic_vector(7 downto 0) |
); |
end neorv32_cpu; |
|
120,7 → 122,7
|
-- local signals -- |
signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus |
signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result |
signal comparator : std_ulogic_vector(1 downto 0); -- comparator result |
signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction |
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers |
150,6 → 152,9
signal pmp_addr : pmp_addr_if_t; |
signal pmp_ctrl : pmp_ctrl_if_t; |
|
-- atomic memory access - success? -- |
signal atomic_sc_res: std_ulogic; |
|
begin |
|
-- Sanity Checks -------------------------------------------------------------------------- |
208,7 → 213,7
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) |
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS => HPM_NUM_CNTS -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS => HPM_NUM_CNTS -- number of implemented HPM counters (0..29) |
) |
port map ( |
-- global control -- |
221,7 → 226,7
bus_d_wait_i => bus_d_wait, -- wait for bus |
-- data input -- |
instr_i => instr, -- instruction |
cmp_i => alu_cmp, -- comparator status |
cmp_i => comparator, -- comparator status |
alu_add_i => alu_add, -- ALU address result |
rs1_i => rs1, -- rf source 1 |
-- data output -- |
234,7 → 239,8
mext_irq_i => mext_irq_i, -- machine external interrupt |
mtime_irq_i => mtime_irq_i, -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i => firq_i, |
firq_i => firq_i, -- fast interrupt trigger |
firq_ack_o => firq_ack_o, -- fast interrupt acknowledge mask |
-- system time input from MTIME -- |
time_i => time_i, -- current system time |
-- physical memory protection -- |
250,7 → 256,10
be_store_i => be_store -- bus error on store data access |
); |
|
-- CPU is sleeping? -- |
sleep_o <= ctrl(ctrl_sleep_c); -- set when CPU is sleeping (after WFI) |
|
|
-- Register File -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cpu_regfile_inst: neorv32_cpu_regfile |
267,7 → 276,8
csr_i => csr_rdata, -- CSR read data |
-- data output -- |
rs1_o => rs1, -- operand 1 |
rs2_o => rs2 -- operand 2 |
rs2_o => rs2, -- operand 2 |
cmp_o => comparator -- comparator status |
); |
|
|
289,7 → 299,6
pc2_i => curr_pc, -- delayed PC |
imm_i => imm, -- immediate |
-- data output -- |
cmp_o => alu_cmp, -- comparator status |
res_o => alu_res, -- ALU result |
add_o => alu_add, -- address computation result |
-- co-processor interface -- |
310,7 → 319,7
); |
|
|
-- Co-Processor 0: MULDIV Unit ------------------------------------------------------------ |
-- Co-Processor 0: Integer Multiplication/Division ('M' Extension) ------------------------ |
-- ------------------------------------------------------------------------------------------- |
neorv32_cpu_cp_muldiv_inst_true: |
if (CPU_EXTENSION_RISCV_M = true) generate |
340,29 → 349,28
end generate; |
|
|
-- Co-Processor 1: Atomic Memory Access, SC - store-conditional ('M' extension) ----------- |
-- Co-Processor 1: Atomic Memory Access ('A' Extension) ----------------------------------- |
-- ------------------------------------------------------------------------------------------- |
atomic_op_cp: process(cp1_start, ctrl) |
-- "pseudo" co-processor for atomic operations |
-- used to get the result of a store-conditional operation into the data path |
atomic_op_cp: process(clk_i) |
begin |
-- "fake" co-processor for atomic operations |
-- used to get the result of a store-conditional operation into the data path |
if (CPU_EXTENSION_RISCV_A = true) then |
if rising_edge(clk_i) then |
if (cp1_start = '1') then |
cp1_data <= (others => '0'); |
cp1_data(0) <= not ctrl(ctrl_bus_lock_c); |
cp1_valid <= '1'; |
atomic_sc_res <= not ctrl(ctrl_bus_lock_c); |
else |
cp1_data <= (others => '0'); |
cp1_valid <= '0'; |
atomic_sc_res <= '0'; |
end if; |
else |
cp1_data <= (others => '0'); |
cp1_valid <= cp1_start; -- to make sure CPU does not get stalled if there is an accidental access |
end if; |
end process atomic_op_cp; |
|
-- CP result -- |
cp1_data(data_width_c-1 downto 1) <= (others => '0'); |
cp1_data(0) <= atomic_sc_res when (CPU_EXTENSION_RISCV_A = true) else '0'; |
cp1_valid <= cp1_start; -- always assigned even if A is disabled to make sure CPU does not get stalled if there is an accidental access |
|
-- Co-Processor 2: Not implemented (yet) -------------------------------------------------- |
|
-- Co-Processor 2: Bit Manipulation ('B' Extension) --------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cpu_cp_bitmanip_inst_true: |
if (CPU_EXTENSION_RISCV_B = true) generate |
374,7 → 382,7
ctrl_i => ctrl, -- main control bus |
start_i => cp2_start, -- trigger operation |
-- data input -- |
cmp_i => alu_cmp, -- comparator status |
cmp_i => comparator, -- comparator status |
rs1_i => rs1, -- rf source 1 |
rs2_i => rs2, -- rf source 2 |
-- result and status -- |
390,10 → 398,8
end generate; |
|
|
-- Co-Processor 3: Not implemented (yet) -------------------------------------------------- |
-- Co-Processor 3: Not implemented -------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- control: ctrl cp3_start |
-- inputs: rs1 rs2 alu_cmp |
cp3_data <= (others => '0'); |
cp3_valid <= cp3_start; -- to make sure CPU does not get stalled if there is an accidental access |
|
/rtl/core/neorv32_cpu_alu.vhd
1,7 → 1,7
-- ################################################################################################# |
-- # << NEORV32 - Arithmetical/Logical Unit >> # |
-- # ********************************************************************************************* # |
-- # Main data and address ALU. Includes comparator unit and co-processor interface/arbiter. # |
-- # Main data and address ALU and co-processor interface/arbiter. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
57,7 → 57,6
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC |
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
-- data output -- |
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status |
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result |
-- co-processor interface -- |
90,11 → 89,6
signal arith_res : std_ulogic_vector(data_width_c-1 downto 0); |
signal logic_res : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- comparator -- |
signal cmp_opx : std_ulogic_vector(data_width_c downto 0); |
signal cmp_opy : std_ulogic_vector(data_width_c downto 0); |
signal cmp_sub : std_ulogic_vector(data_width_c downto 0); |
|
-- shifter -- |
type shifter_t is record |
cmd : std_ulogic; |
128,16 → 122,6
opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand) |
|
|
-- Comparator Unit ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i; |
cmp_opy <= (rs2_i(rs2_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2_i; |
cmp_sub <= std_ulogic_vector(signed(cmp_opx) - signed(cmp_opy)); -- less than (x < y) |
|
cmp_o(alu_cmp_equal_c) <= '1' when (rs1_i = rs2_i) else '0'; |
cmp_o(alu_cmp_less_c) <= cmp_sub(cmp_sub'left); -- less = carry (borrow) |
|
|
-- Binary Adder/Subtractor ---------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
binary_arithmetic_core: process(ctrl_i, opa, opb) |
150,7 → 134,6
-- operand sign-extension -- |
op_a_v := (opa(opa'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opa; |
op_b_v := (opb(opb'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & opb; |
|
-- add/sub(slt) select -- |
if (ctrl_i(ctrl_alu_addsub_c) = '1') then -- subtraction |
op_y_v := not op_b_v; |
159,7 → 142,6
op_y_v := op_b_v; |
cin_v(0) := '0'; |
end if; |
|
-- adder core (result + carry/borrow) -- |
addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0))); |
end process binary_arithmetic_core; |
227,7 → 209,6
-- Barrel shifter (huge but fast) |
-- -------------------------------------------------------------------------------- |
else |
|
-- operands and cycle control -- |
if (shifter.start = '1') then -- trigger new shift |
shifter.bs_d_in <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc) |
295,8 → 276,11
shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0'; |
|
|
-- Coprocessor Arbiter -------------------------------------------------------------------- |
-- Co-Processor Arbiter ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- Interface: |
-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data |
-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered |
cp_arbiter: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
326,12 → 310,7
cp_ctrl.halt <= (cp_ctrl.busy and (not (cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i))) or cp_ctrl.start; |
|
-- co-processor result -- |
cp_read_back: process(clk_i) |
begin |
if rising_edge(clk_i) then |
cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0 |
end if; |
end process cp_read_back; |
cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0 |
|
|
-- ALU Logic Core ------------------------------------------------------------------------- |
/rtl/core/neorv32_cpu_bus.vhd
158,7 → 158,12
end record; |
signal pmp : pmp_t; |
|
-- pmp faults anybody? -- |
-- memory control signal buffer (when using PMP) -- |
signal d_bus_we, d_bus_we_buf : std_ulogic; |
signal d_bus_re, d_bus_re_buf : std_ulogic; |
signal i_bus_re, i_bus_re_buf : std_ulogic; |
|
-- pmp faults anyone? -- |
signal if_pmp_fault : std_ulogic; -- pmp instruction access fault |
signal ld_pmp_fault : std_ulogic; -- pmp load access fault |
signal st_pmp_fault : std_ulogic; -- pmp store access fault |
165,6 → 170,11
|
begin |
|
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " & integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) & "). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning; |
|
|
-- Data Interface: Access Address --------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
mem_adr_reg: process(clk_i) |
324,13 → 334,27
d_bus_addr_o <= mar; |
d_bus_wdata_o <= d_bus_wdata; |
d_bus_ben_o <= d_bus_ben; |
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault |
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault |
d_bus_we <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault |
d_bus_re <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault |
d_bus_we_o <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we; |
d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re; |
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c); |
d_bus_rdata <= d_bus_rdata_i; |
d_bus_lock_o <= ctrl_i(ctrl_bus_lock_c); |
|
-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c -- |
pmp_dbus_buffer: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
d_bus_we_buf <= '0'; |
d_bus_re_buf <= '0'; |
elsif rising_edge(clk_i) then |
d_bus_we_buf <= d_bus_we; |
d_bus_re_buf <= d_bus_re; |
end if; |
end process pmp_dbus_buffer; |
|
|
-- Instruction Fetch Arbiter -------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
ifetch_arbiter: process(rstn_i, clk_i) |
375,17 → 399,27
i_bus_wdata_o <= (others => '0'); -- instruction fetch is read-only |
i_bus_ben_o <= (others => '0'); |
i_bus_we_o <= '0'; |
i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault |
i_bus_re <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault |
i_bus_re_o <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re; |
i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c); |
instr_o <= i_bus_rdata_i; |
i_bus_lock_o <= '0'; -- instruction fetch cannot be atomic |
|
|
-- check instruction access -- |
i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension |
'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only |
|
-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c -- |
pmp_ibus_buffer: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
i_bus_re_buf <= '0'; |
elsif rising_edge(clk_i) then |
i_bus_re_buf <= i_bus_re; |
end if; |
end process pmp_ibus_buffer; |
|
|
-- Physical Memory Protection (PMP) ------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- compute address masks (ITERATIVE!!!) -- |
/rtl/core/neorv32_cpu_control.vhd
63,7 → 63,7
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) |
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS : natural := 0 -- number of implemented HPM counters (0..29) |
); |
port ( |
-- global control -- |
89,7 → 89,8
mext_irq_i : in std_ulogic; -- machine external interrupt |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0); |
firq_i : in std_ulogic_vector(7 downto 0); |
firq_ack_o : out std_ulogic_vector(7 downto 0); |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- physical memory protection -- |
213,6 → 214,7
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0); |
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer |
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0); |
firq_sync : std_ulogic_vector(7 downto 0); |
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer |
exc_ack : std_ulogic; -- acknowledge all exceptions |
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt |
275,7 → 277,7
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W) |
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W) |
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W) |
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W) |
mie_firqe : std_ulogic_vector(7 downto 0); -- mie.firq*e: fast interrupt enabled (R/W) |
-- |
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode |
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode |
642,13 → 644,13
begin |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is |
when funct3_beq_c => -- branch if equal |
execute_engine.branch_taken <= cmp_i(alu_cmp_equal_c); |
execute_engine.branch_taken <= cmp_i(cmp_equal_c); |
when funct3_bne_c => -- branch if not equal |
execute_engine.branch_taken <= not cmp_i(alu_cmp_equal_c); |
execute_engine.branch_taken <= not cmp_i(cmp_equal_c); |
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned) |
execute_engine.branch_taken <= cmp_i(alu_cmp_less_c); |
execute_engine.branch_taken <= cmp_i(cmp_less_c); |
when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned) |
execute_engine.branch_taken <= not cmp_i(alu_cmp_less_c); |
execute_engine.branch_taken <= not cmp_i(cmp_less_c); |
when others => -- undefined |
execute_engine.branch_taken <= '0'; |
end case; |
731,14 → 733,22
-- fast bus access requests -- |
ctrl_o(ctrl_bus_if_c) <= bus_fast_ir; |
-- bus error control -- |
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack; |
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack; |
ctrl_o(ctrl_bus_ierr_ack_c) <= fetch_engine.bus_err_ack; -- instruction fetch bus access error ACK |
ctrl_o(ctrl_bus_derr_ack_c) <= trap_ctrl.env_start_ack; -- data access bus error access ACK |
-- memory access size / sign -- |
ctrl_o(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU) |
ctrl_o(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size |
-- alu.shifter -- |
ctrl_o(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right) |
ctrl_o(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift |
-- instruction's function blocks (for co-processors) -- |
ctrl_o(ctrl_ir_opcode7_6_c downto ctrl_ir_opcode7_0_c) <= execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c); |
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c); |
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c); |
-- locked bus operation (for atomica memory operations) -- |
-- locked bus operation (for atomic memory operations) -- |
ctrl_o(ctrl_bus_lock_c) <= atomic_ctrl.lock; -- (bus) lock status |
-- cpu status -- |
ctrl_o(ctrl_sleep_c) <= execute_engine.sleep; -- cpu is in sleep mode |
end process ctrl_output; |
|
|
841,21 → 851,16
|
-- CONTROL DEFAULTS -- |
ctrl_nxt <= (others => '0'); -- default: all off |
-- ALU main control -- |
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I) |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- default ALU function select: arithmetic |
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- default ALU arithmetic operation: ADDSUB |
-- ALU sign control -- |
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU) |
else -- branches |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU) |
end if; |
-- memory access -- |
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU) |
ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size |
-- alu.shifter -- |
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right) |
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift |
-- ALU main control -- |
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I) |
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- default ALU function select: arithmetic |
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- default ALU arithmetic operation: ADDSUB |
|
|
-- state machine -- |
1126,14 → 1131,16
|
when FENCE_OP => -- fence operations - execution |
-- ------------------------------------------------------------ |
execute_engine.state_nxt <= SYS_WAIT; |
execute_engine.pc_mux_sel <= "01"; -- linear next PC = "refetch" next instruction (only relevant for fence.i) |
execute_engine.state_nxt <= SYS_WAIT; |
-- FENCE.I -- |
if (CPU_EXTENSION_RISCV_Zifencei = true) and (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) then |
execute_engine.pc_we <= '1'; |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
fetch_engine.reset <= '1'; |
ctrl_nxt(ctrl_bus_fencei_c) <= '1'; |
if (CPU_EXTENSION_RISCV_Zifencei = true) then |
execute_engine.pc_mux_sel <= "01"; -- linear next PC = start *new* instruction fetch with next instruction (only relevant for fence.i) |
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) then |
execute_engine.pc_we <= '1'; |
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification |
fetch_engine.reset <= '1'; |
ctrl_nxt(ctrl_bus_fencei_c) <= '1'; |
end if; |
end if; |
-- FENCE -- |
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then |
1574,8 → 1581,9
trap_ctrl.irq_buf <= (others => '0'); |
trap_ctrl.exc_ack <= '0'; |
trap_ctrl.irq_ack <= (others => '0'); |
trap_ctrl.env_start <= '0'; |
trap_ctrl.cause <= trap_reset_c; |
trap_ctrl.env_start <= '0'; |
trap_ctrl.firq_sync <= (others => '0'); |
elsif rising_edge(clk_i) then |
if (CPU_EXTENSION_RISCV_Zicsr = true) then |
-- exception buffer: misaligned load/store/instruction address |
1596,10 → 1604,16
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c) or csr.mip_clear(interrupt_mext_irq_c))); |
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c))); |
-- interrupt buffer: custom fast interrupts |
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c) or csr.mip_clear(interrupt_firq_0_c))); |
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not (trap_ctrl.irq_ack(interrupt_firq_1_c) or csr.mip_clear(interrupt_firq_1_c))); |
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not (trap_ctrl.irq_ack(interrupt_firq_2_c) or csr.mip_clear(interrupt_firq_2_c))); |
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not (trap_ctrl.irq_ack(interrupt_firq_3_c) or csr.mip_clear(interrupt_firq_3_c))); |
trap_ctrl.firq_sync <= firq_i; |
-- |
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or trap_ctrl.firq_sync(0)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c) or csr.mip_clear(interrupt_firq_0_c))); |
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or trap_ctrl.firq_sync(1)) and (not (trap_ctrl.irq_ack(interrupt_firq_1_c) or csr.mip_clear(interrupt_firq_1_c))); |
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or trap_ctrl.firq_sync(2)) and (not (trap_ctrl.irq_ack(interrupt_firq_2_c) or csr.mip_clear(interrupt_firq_2_c))); |
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or trap_ctrl.firq_sync(3)) and (not (trap_ctrl.irq_ack(interrupt_firq_3_c) or csr.mip_clear(interrupt_firq_3_c))); |
trap_ctrl.irq_buf(interrupt_firq_4_c) <= csr.mie_firqe(4) and (trap_ctrl.irq_buf(interrupt_firq_4_c) or trap_ctrl.firq_sync(4)) and (not (trap_ctrl.irq_ack(interrupt_firq_4_c) or csr.mip_clear(interrupt_firq_4_c))); |
trap_ctrl.irq_buf(interrupt_firq_5_c) <= csr.mie_firqe(5) and (trap_ctrl.irq_buf(interrupt_firq_5_c) or trap_ctrl.firq_sync(5)) and (not (trap_ctrl.irq_ack(interrupt_firq_5_c) or csr.mip_clear(interrupt_firq_5_c))); |
trap_ctrl.irq_buf(interrupt_firq_6_c) <= csr.mie_firqe(6) and (trap_ctrl.irq_buf(interrupt_firq_6_c) or trap_ctrl.firq_sync(6)) and (not (trap_ctrl.irq_ack(interrupt_firq_6_c) or csr.mip_clear(interrupt_firq_6_c))); |
trap_ctrl.irq_buf(interrupt_firq_7_c) <= csr.mie_firqe(7) and (trap_ctrl.irq_buf(interrupt_firq_7_c) or trap_ctrl.firq_sync(7)) and (not (trap_ctrl.irq_ack(interrupt_firq_7_c) or csr.mip_clear(interrupt_firq_7_c))); |
-- trap control -- |
if (trap_ctrl.env_start = '0') then -- no started trap handler |
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected! |
1627,7 → 1641,10
-- current pending interrupts (for CSR.MIP register) -- |
csr.mip_status <= trap_ctrl.irq_buf; |
|
-- acknowledge mask output -- |
firq_ack_o <= trap_ctrl.irq_ack(interrupt_firq_7_c downto interrupt_firq_0_c); |
|
|
-- Trap Priority Encoder ------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
trap_priority: process(trap_ctrl) |
1675,7 → 1692,27
trap_ctrl.cause_nxt <= trap_firq3_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1'; |
|
-- interrupt: 1.20 fast interrupt channel 4 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_4_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq4_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_4_c) <= '1'; |
|
-- interrupt: 1.21 fast interrupt channel 5 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_5_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq5_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_5_c) <= '1'; |
|
-- interrupt: 1.22 fast interrupt channel 6 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_6_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq6_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_6_c) <= '1'; |
|
-- interrupt: 1.23 fast interrupt channel 7 -- |
elsif (trap_ctrl.irq_buf(interrupt_firq_7_c) = '1') then |
trap_ctrl.cause_nxt <= trap_firq7_c; |
trap_ctrl.irq_ack_nxt(interrupt_firq_7_c) <= '1'; |
|
|
-- the following traps are caused by *synchronous* exceptions (= 'classic' exceptions) |
-- here we do not need a specific acknowledge mask since only one exception (the one |
-- with highest priority) is evaluated at once |
1854,6 → 1891,10
csr.mie_firqe(1) <= csr.wdata(17); -- fast interrupt channel 1 |
csr.mie_firqe(2) <= csr.wdata(18); -- fast interrupt channel 2 |
csr.mie_firqe(3) <= csr.wdata(19); -- fast interrupt channel 3 |
csr.mie_firqe(4) <= csr.wdata(20); -- fast interrupt channel 4 |
csr.mie_firqe(5) <= csr.wdata(21); -- fast interrupt channel 5 |
csr.mie_firqe(6) <= csr.wdata(22); -- fast interrupt channel 6 |
csr.mie_firqe(7) <= csr.wdata(22); -- fast interrupt channel 7 |
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
when csr_mcounteren_c => -- R/W: machine counter enable register |
1883,6 → 1924,10
csr.mip_clear(interrupt_firq_1_c) <= not csr.wdata(17); |
csr.mip_clear(interrupt_firq_2_c) <= not csr.wdata(18); |
csr.mip_clear(interrupt_firq_3_c) <= not csr.wdata(19); |
csr.mip_clear(interrupt_firq_4_c) <= not csr.wdata(20); |
csr.mip_clear(interrupt_firq_5_c) <= not csr.wdata(21); |
csr.mip_clear(interrupt_firq_6_c) <= not csr.wdata(22); |
csr.mip_clear(interrupt_firq_7_c) <= not csr.wdata(23); |
|
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers -- |
-- -------------------------------------------------------------------- |
1938,6 → 1983,7
for i in 0 to HPM_NUM_CNTS-1 loop |
if (csr.addr(4 downto 0) = std_ulogic_vector(to_unsigned(i+3, 5))) then |
csr.mhpmevent(i) <= csr.wdata(csr.mhpmevent(i)'left downto 0); |
csr.mhpmevent(i)(1) <= '0'; -- would be used for "TIME" |
end if; |
end loop; -- i (CSRs) |
|
1976,7 → 2022,7
csr.mtval <= mar_i; -- faulting data access address |
when trap_iil_c => -- illegal instruction |
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself |
when others => -- everything else including interrupts |
when others => -- everything else including all interrupts |
csr.mtval <= (others => '0'); |
end case; |
end if; |
2121,13 → 2167,13
hpmcnt_ctrl: process(clk_i) |
begin |
if rising_edge(clk_i) then |
cnt_event <= cnt_event_nxt; |
-- buffer event sources -- |
cnt_event <= cnt_event_nxt; |
-- enable selected triggers by ANDing actual events and according CSR configuration bits -- |
-- OR everything to see if counter should increment -- |
hpmcnt_trigger <= (others => '0'); -- default |
for i in 0 to HPM_NUM_CNTS-1 loop |
-- enable selected triggers by ANDing events and configuration bits -- |
-- OR everything to see if counter should increment -- |
-- AND with inverted sleep flag to increment only when CPU is awake -- |
hpmcnt_trigger(i) <= (or_all_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0))) and (not execute_engine.sleep); |
hpmcnt_trigger(i) <= or_all_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0)); |
end loop; -- i |
end if; |
end process hpmcnt_ctrl; |
2138,10 → 2184,10
cnt_event_nxt(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- retired instruction |
|
-- counter event trigger - custom / NEORV32-specific -- |
cnt_event_nxt(hpmcnt_event_cir_c) <= '1' when (execute_engine.state = EXECUTE) and (execute_engine.is_ci = '1') else '0'; -- retired compressed instruction |
cnt_event_nxt(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle |
cnt_event_nxt(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH) and (execute_engine.state_prev = DISPATCH) else '0'; -- instruction issue wait cycle |
cnt_event_nxt(hpmcnt_event_wait_mc_c) <= '1' when (execute_engine.state = ALU_WAIT) and (execute_engine.state_prev = ALU_WAIT) else '0'; -- multi-cycle alu-operation wait cycle |
cnt_event_nxt(hpmcnt_event_cir_c) <= '1' when (execute_engine.state = EXECUTE) and (execute_engine.is_ci = '1') else '0'; -- retired compressed instruction |
cnt_event_nxt(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle |
cnt_event_nxt(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH) and (execute_engine.state_prev = DISPATCH) else '0'; -- instruction issue wait cycle |
cnt_event_nxt(hpmcnt_event_wait_mc_c) <= '1' when (execute_engine.state = ALU_WAIT) and (execute_engine.state_prev = ALU_WAIT) else '0'; -- multi-cycle alu-operation wait cycle |
|
cnt_event_nxt(hpmcnt_event_load_c) <= '1' when (execute_engine.state = LOADSTORE_1) and (ctrl(ctrl_bus_rd_c) = '1') else '0'; -- load operation |
cnt_event_nxt(hpmcnt_event_store_c) <= '1' when (execute_engine.state = LOADSTORE_1) and (ctrl(ctrl_bus_wr_c) = '1') else '0'; -- store operation |
2194,6 → 2240,10
csr.rdata(17) <= csr.mie_firqe(1); -- fast interrupt channel 1 |
csr.rdata(18) <= csr.mie_firqe(2); -- fast interrupt channel 2 |
csr.rdata(19) <= csr.mie_firqe(3); -- fast interrupt channel 3 |
csr.rdata(20) <= csr.mie_firqe(4); -- fast interrupt channel 4 |
csr.rdata(21) <= csr.mie_firqe(5); -- fast interrupt channel 5 |
csr.rdata(22) <= csr.mie_firqe(6); -- fast interrupt channel 6 |
csr.rdata(23) <= csr.mie_firqe(7); -- fast interrupt channel 7 |
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions) |
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0 |
when csr_mcounteren_c => -- R/W: machine counter enable register |
2220,6 → 2270,10
csr.rdata(17) <= csr.mip_status(interrupt_firq_1_c); |
csr.rdata(18) <= csr.mip_status(interrupt_firq_2_c); |
csr.rdata(19) <= csr.mip_status(interrupt_firq_3_c); |
csr.rdata(20) <= csr.mip_status(interrupt_firq_4_c); |
csr.rdata(21) <= csr.mip_status(interrupt_firq_5_c); |
csr.rdata(22) <= csr.mip_status(interrupt_firq_6_c); |
csr.rdata(23) <= csr.mip_status(interrupt_firq_7_c); |
|
-- physical memory protection - configuration -- |
when csr_pmpcfg0_c => csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); -- R/W: pmpcfg0 |
/rtl/core/neorv32_cpu_cp_bitmanip.vhd
4,6 → 4,9
-- # The bit manipulation unit is implemted as co-processor that has a processing latency of 1 # |
-- # cycle for logic/arithmetic operations and 3+shamt (=shift amount) cycles for shift(-related) # |
-- # operations. # |
-- # # |
-- # Supported sub-extensions (Zb*): # |
-- # - Zbb: Base instructions (mandatory) # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
164,7 → 167,7
when S_IDLE => -- wait for operation trigger |
-- ------------------------------------------------------------ |
if (start_i = '1') then |
less_ff <= cmp_i(alu_cmp_less_c); |
less_ff <= cmp_i(cmp_less_c); |
cmd_buf <= cmd; |
rs1_reg <= rs1_i; |
rs2_reg <= rs2_i; |
257,8 → 260,7
-- count leading/trailing zeros -- |
res_int(op_clz_c)(data_width_c-1 downto shifter.cnt'left+1) <= (others => '0'); |
res_int(op_clz_c)(shifter.cnt'left downto 0) <= shifter.cnt; |
res_int(op_ctz_c)(data_width_c-1 downto shifter.cnt'left+1) <= (others => '0'); |
res_int(op_ctz_c)(shifter.cnt'left downto 0) <= shifter.cnt; |
res_int(op_ctz_c) <= (others => '0'); -- unused/redundant |
|
-- count set bits -- |
res_int(op_cpop_c)(data_width_c-1 downto shifter.bcnt'left+1) <= (others => '0'); |
265,8 → 267,8
res_int(op_cpop_c)(shifter.bcnt'left downto 0) <= shifter.bcnt; |
|
-- min/max select -- |
res_int(op_min_c) <= rs1_reg when (less_ff = '1') else rs2_reg; |
res_int(op_max_c) <= rs2_reg when (less_ff = '1') else rs1_reg; |
res_int(op_min_c) <= rs1_reg when ((less_ff xor cmd_buf(op_max_c)) = '1') else rs2_reg; |
res_int(op_max_c) <= (others => '0'); -- unused/redundant |
|
-- sign-extension -- |
res_int(op_sextb_c)(data_width_c-1 downto 8) <= (others => rs1_reg(7)); |
298,11 → 300,11
|
-- Output Selector ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
res_out(op_clz_c) <= res_int(op_clz_c) when (cmd_buf(op_clz_c) = '1') else (others => '0'); |
res_out(op_ctz_c) <= res_int(op_ctz_c) when (cmd_buf(op_ctz_c) = '1') else (others => '0'); |
res_out(op_clz_c) <= res_int(op_clz_c) when ((cmd_buf(op_clz_c) or cmd_buf(op_ctz_c)) = '1') else (others => '0'); |
res_out(op_ctz_c) <= (others => '0'); -- unused/redundant |
res_out(op_cpop_c) <= res_int(op_cpop_c) when (cmd_buf(op_cpop_c) = '1') else (others => '0'); |
res_out(op_min_c) <= res_int(op_min_c) when (cmd_buf(op_min_c) = '1') else (others => '0'); |
res_out(op_max_c) <= res_int(op_max_c) when (cmd_buf(op_max_c) = '1') else (others => '0'); |
res_out(op_min_c) <= res_int(op_min_c) when ((cmd_buf(op_min_c) or cmd_buf(op_max_c)) = '1') else (others => '0'); |
res_out(op_max_c) <= (others => '0'); -- unused/redundant |
res_out(op_sextb_c) <= res_int(op_sextb_c) when (cmd_buf(op_sextb_c) = '1') else (others => '0'); |
res_out(op_sexth_c) <= res_int(op_sexth_c) when (cmd_buf(op_sexth_c) = '1') else (others => '0'); |
res_out(op_andn_c) <= res_int(op_andn_c) when (cmd_buf(op_andn_c) = '1') else (others => '0'); |
317,19 → 319,20
|
-- Output Gate ---------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
output_gate: process(valid, res_out) |
output_gate: process(clk_i) |
begin |
if (valid = '1') then |
res_o <= res_out(op_clz_c) or res_out(op_ctz_c) or res_out(op_cpop_c) or |
res_out(op_min_c) or res_out(op_max_c) or |
res_out(op_sextb_c) or res_out(op_sexth_c) or |
res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or |
res_out(op_pack_c) or |
res_out(op_ror_c) or res_out(op_rol_c) or |
res_out(op_rev8_c) or |
res_out(op_orcb_c); |
else |
if rising_edge(clk_i) then |
res_o <= (others => '0'); |
if (valid = '1') then |
res_o <= res_out(op_clz_c) or res_out(op_cpop_c) or -- res_out(op_ctz_c) is unused here |
res_out(op_min_c) or -- res_out(op_max_c) is unused here |
res_out(op_sextb_c) or res_out(op_sexth_c) or |
res_out(op_andn_c) or res_out(op_orn_c) or res_out(op_xnor_c) or |
res_out(op_pack_c) or |
res_out(op_ror_c) or res_out(op_rol_c) or |
res_out(op_rev8_c) or |
res_out(op_orcb_c); |
end if; |
end if; |
end process output_gate; |
|
/rtl/core/neorv32_cpu_cp_muldiv.vhd
302,29 → 302,30
|
-- Data Output ---------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
operation_result: process(valid, cp_op_ff, mul_product, div_res, quotient, opy_is_zero, rs1, remainder) |
operation_result: process(clk_i) |
begin |
if (valid = '1') then |
case cp_op_ff is |
when cp_op_mul_c => |
res_o <= mul_product(31 downto 00); |
when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c => |
res_o <= mul_product(63 downto 32); |
when cp_op_div_c => |
res_o <= div_res; |
when cp_op_divu_c => |
res_o <= quotient; |
when cp_op_rem_c => |
if (opy_is_zero = '0') then |
if rising_edge(clk_i) then |
res_o <= (others => '0'); |
if (valid = '1') then |
case cp_op_ff is |
when cp_op_mul_c => |
res_o <= mul_product(31 downto 00); |
when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c => |
res_o <= mul_product(63 downto 32); |
when cp_op_div_c => |
res_o <= div_res; |
else |
res_o <= rs1; |
end if; |
when others => -- cp_op_remu_c |
res_o <= remainder; |
end case; |
else |
res_o <= (others => '0'); |
when cp_op_divu_c => |
res_o <= quotient; |
when cp_op_rem_c => |
if (opy_is_zero = '0') then |
res_o <= div_res; |
else |
res_o <= rs1; |
end if; |
when others => -- cp_op_remu_c |
res_o <= remainder; |
end case; |
end if; |
end if; |
end process operation_result; |
|
/rtl/core/neorv32_cpu_regfile.vhd
63,7 → 63,8
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
-- data output -- |
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1 |
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2 |
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2 |
cmp_o : out std_ulogic_vector(1 downto 0) -- comparator status |
); |
end neorv32_cpu_regfile; |
|
81,7 → 82,12
signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address |
signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address |
signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address |
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); |
|
-- comparator -- |
signal cmp_opx : std_ulogic_vector(data_width_c downto 0); |
signal cmp_opy : std_ulogic_vector(data_width_c downto 0); |
|
begin |
|
-- Data Input Mux ------------------------------------------------------------------------- |
99,14 → 105,14
if (rf_we = '1') then |
reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_write_data; |
end if; |
rs1_o <= reg_file(to_integer(unsigned(opa_addr(4 downto 0)))); |
rs2_o <= reg_file(to_integer(unsigned(opb_addr(4 downto 0)))); |
rs1 <= reg_file(to_integer(unsigned(opa_addr(4 downto 0)))); |
rs2 <= reg_file(to_integer(unsigned(opb_addr(4 downto 0)))); |
else -- embedded register file with 16 entries |
if (rf_we = '1') then |
reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_write_data; |
end if; |
rs1_o <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))); |
rs2_o <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0)))); |
rs1 <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))); |
rs2 <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0)))); |
end if; |
end if; |
end process rf_access; |
125,5 → 131,18
opa_addr <= dst_addr when (rf_we = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1 |
opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2 |
|
-- data output -- |
rs1_o <= rs1; |
rs2_o <= rs2; |
|
|
-- Comparator Unit (for conditional branches) --------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
cmp_opx <= (rs1(rs1'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1; |
cmp_opy <= (rs2(rs2'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs2; |
|
cmp_o(cmp_equal_c) <= '1' when (rs1 = rs2) else '0'; |
cmp_o(cmp_less_c) <= '1' when (signed(cmp_opx) < signed(cmp_opy)) else '0'; |
|
|
end neorv32_cpu_regfile_rtl; |
/rtl/core/neorv32_gpio.vhd
1,11 → 1,12
-- ################################################################################################# |
-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> # |
-- # ********************************************************************************************* # |
-- # 32-bit parallel input & output unit. Any pin change (HI->LO or LO->HI) triggers an IRQ. # |
-- # 32-bit parallel input & output unit. Any pin change (HI->LO or LO->HI) of an enabled input # |
-- # pin (via irq_en register) triggers an IRQ. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
/rtl/core/neorv32_icache.vhd
1,8 → 1,8
-- ################################################################################################# |
-- # << NEORV32 - Processor-Internal Instruction Cache >> # |
-- # ********************************************************************************************* # |
-- # Direct mapped (CACHE_NUM_SETS = 1) or 2-way set-associative (CACHE_NUM_SETS = 2). # |
-- # Least recently used replacement policy (if CACHE_NUM_SETS > 1). # |
-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2). # |
-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1). # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
44,9 → 44,9
|
entity neorv32_icache is |
generic ( |
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 |
CACHE_NUM_SETS : natural := 1 -- associativity / number of sets (1=direct_mapped), has to be a power of 2 |
ICACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 |
ICACHE_NUM_SETS : natural := 1 -- associativity / number of sets (1=direct_mapped), has to be a power of 2 |
); |
port ( |
-- global control -- |
81,16 → 81,16
architecture neorv32_icache_rtl of neorv32_icache is |
|
-- cache layout -- |
constant cache_offset_size_c : natural := index_size_f(CACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words |
constant cache_index_size_c : natural := index_size_f(CACHE_NUM_BLOCKS); |
constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words |
constant cache_index_size_c : natural := index_size_f(ICACHE_NUM_BLOCKS); |
constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset |
|
-- cache memory -- |
component neorv32_icache_memory |
generic ( |
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 |
CACHE_NUM_SETS : natural := 1 -- associativity; 0=direct-mapped, 1=2-way set-associative |
ICACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 |
ICACHE_NUM_SETS : natural := 1 -- associativity; 0=direct-mapped, 1=2-way set-associative |
); |
port ( |
-- global control -- |
153,12 → 153,12
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- configuration -- |
assert not (is_power_of_two_f(CACHE_NUM_BLOCKS) = false) report "NEORV32 PROCESSOR CONFIG ERROR! Cache number of blocks <NUM_BLOCKS> has to be a power of 2." severity error; |
assert not (is_power_of_two_f(CACHE_BLOCK_SIZE) = false) report "NEORV32 PROCESSOR CONFIG ERROR! Cache block size <BLOCK_SIZE> has to be a power of 2." severity error; |
assert not ((is_power_of_two_f(CACHE_NUM_SETS) = false)) report "NEORV32 PROCESSOR CONFIG ERROR! Cache associativity <CACHE_NUM_SETS> has to be a power of 2." severity error; |
assert not (CACHE_NUM_BLOCKS < 1) report "NEORV32 PROCESSOR CONFIG ERROR! Cache number of blocks <NUM_BLOCKS> has to be >= 1." severity error; |
assert not (CACHE_BLOCK_SIZE < 4) report "NEORV32 PROCESSOR CONFIG ERROR! Cache block size <BLOCK_SIZE> has to be >= 4." severity error; |
assert not ((CACHE_NUM_SETS = 0) or (CACHE_NUM_SETS > 2)) report "NEORV32 PROCESSOR CONFIG ERROR! Cache associativity <CACHE_NUM_SETS> has to be 1 (direct-mapped) or 2 (2-way set-associative)." severity error; |
assert not (is_power_of_two_f(ICACHE_NUM_BLOCKS) = false) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache number of blocks <ICACHE_NUM_BLOCKS> has to be a power of 2." severity error; |
assert not (is_power_of_two_f(ICACHE_BLOCK_SIZE) = false) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache block size <ICACHE_BLOCK_SIZE> has to be a power of 2." severity error; |
assert not ((is_power_of_two_f(ICACHE_NUM_SETS) = false)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity <ICACHE_NUM_SETS> has to be a power of 2." severity error; |
assert not (ICACHE_NUM_BLOCKS < 1) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache number of blocks <ICACHE_NUM_BLOCKS> has to be >= 1." severity error; |
assert not (ICACHE_BLOCK_SIZE < 4) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache block size <ICACHE_BLOCK_SIZE> has to be >= 4." severity error; |
assert not ((ICACHE_NUM_SETS = 0) or (ICACHE_NUM_SETS > 2)) report "NEORV32 PROCESSOR CONFIG ERROR! i-cache associativity <ICACHE_NUM_SETS> has to be 1 (direct-mapped) or 2 (2-way set-associative)." severity error; |
|
|
-- Control Engine FSM Sync ---------------------------------------------------------------- |
326,9 → 326,9
-- ------------------------------------------------------------------------------------------- |
neorv32_icache_memory_inst: neorv32_icache_memory |
generic map ( |
CACHE_NUM_BLOCKS => CACHE_NUM_BLOCKS, -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE => CACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2 |
CACHE_NUM_SETS => CACHE_NUM_SETS -- associativity; 0=direct-mapped, 1=2-way set-associative |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2 |
ICACHE_NUM_SETS => ICACHE_NUM_SETS -- associativity; 0=direct-mapped, 1=2-way set-associative |
) |
port map ( |
-- global control -- |
360,8 → 360,8
-- ################################################################################################# |
-- # << NEORV32 - Cache Memory >> # |
-- # ********************************************************************************************* # |
-- # Direct mapped (CACHE_NUM_SETS = 1) or 2-way set-associative (CACHE_NUM_SETS = 2). # |
-- # Least recently used replacement policy (if CACHE_NUM_SETS > 1). # |
-- # Direct mapped (ICACHE_NUM_SETS = 1) or 2-way set-associative (ICACHE_NUM_SETS = 2). # |
-- # Least recently used replacement policy (if ICACHE_NUM_SETS > 1). # |
-- # Read-only for host, write-only for control. All output signals have one cycle latency. # |
-- # # |
-- # Cache sets are mapped to individual memory components - no multi-dimensional memory arrays # |
407,9 → 407,9
|
entity neorv32_icache_memory is |
generic ( |
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 |
CACHE_NUM_SETS : natural := 1 -- associativity; 1=direct-mapped, 2=2-way set-associative |
ICACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 |
ICACHE_NUM_SETS : natural := 1 -- associativity; 1=direct-mapped, 2=2-way set-associative |
); |
port ( |
-- global control -- |
435,18 → 435,18
architecture neorv32_icache_memory_rtl of neorv32_icache_memory is |
|
-- cache layout -- |
constant cache_offset_size_c : natural := index_size_f(CACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words |
constant cache_index_size_c : natural := index_size_f(CACHE_NUM_BLOCKS); |
constant cache_offset_size_c : natural := index_size_f(ICACHE_BLOCK_SIZE/4); -- offset addresses full 32-bit words |
constant cache_index_size_c : natural := index_size_f(ICACHE_NUM_BLOCKS); |
constant cache_tag_size_c : natural := 32 - (cache_offset_size_c + cache_index_size_c + 2); -- 2 additonal bits for byte offset |
constant cache_entries_c : natural := CACHE_NUM_BLOCKS * (CACHE_BLOCK_SIZE/4); -- number of 32-bit entries (per set) |
constant cache_entries_c : natural := ICACHE_NUM_BLOCKS * (ICACHE_BLOCK_SIZE/4); -- number of 32-bit entries (per set) |
|
-- status flag memory -- |
signal valid_flag_s0 : std_ulogic_vector(CACHE_NUM_BLOCKS-1 downto 0); |
signal valid_flag_s1 : std_ulogic_vector(CACHE_NUM_BLOCKS-1 downto 0); |
signal valid_flag_s0 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0); |
signal valid_flag_s1 : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0); |
signal valid : std_ulogic_vector(1 downto 0); -- valid flag read data |
|
-- tag memory -- |
type tag_mem_t is array (0 to CACHE_NUM_BLOCKS-1) of std_ulogic_vector(cache_tag_size_c-1 downto 0); |
type tag_mem_t is array (0 to ICACHE_NUM_BLOCKS-1) of std_ulogic_vector(cache_tag_size_c-1 downto 0); |
signal tag_mem_s0 : tag_mem_t; |
signal tag_mem_s1 : tag_mem_t; |
type tag_rd_t is array (0 to 1) of std_ulogic_vector(cache_tag_size_c-1 downto 0); |
480,7 → 480,7
-- access history -- |
type history_t is record |
re_ff : std_ulogic; |
last_used_set : std_ulogic_vector(CACHE_NUM_BLOCKS-1 downto 0); |
last_used_set : std_ulogic_vector(ICACHE_NUM_BLOCKS-1 downto 0); |
to_be_replaced : std_ulogic; |
end record; |
signal history : history_t; |
514,7 → 514,7
end process access_history; |
|
-- which set is going to be replaced? -> opposite of last used set = least recently used set -- |
set_select <= '0' when (CACHE_NUM_SETS = 1) else (not history.to_be_replaced); |
set_select <= '0' when (ICACHE_NUM_SETS = 1) else (not history.to_be_replaced); |
|
|
-- Status flag memory --------------------------------------------------------------------- |
570,7 → 570,7
comparator: process(host_acc_addr, tag, valid) |
begin |
hit <= (others => '0'); |
for i in 0 to CACHE_NUM_SETS-1 loop |
for i in 0 to ICACHE_NUM_SETS-1 loop |
if (host_acc_addr.tag = tag(i)) and (valid(i) = '1') then |
hit(i) <= '1'; |
end if; |
600,7 → 600,7
end process cache_mem_access; |
|
-- data output -- |
host_rdata_o <= cache_rdata(0) when (hit(0) = '1') or (CACHE_NUM_SETS = 1) else cache_rdata(1); |
host_rdata_o <= cache_rdata(0) when (hit(0) = '1') or (ICACHE_NUM_SETS = 1) else cache_rdata(1); |
|
-- cache block ram access address -- |
cache_addr <= cache_index & cache_offset; |
/rtl/core/neorv32_package.vhd
52,10 → 52,15
-- CPU core -- |
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2 |
|
-- "critical" number of PMP regions -- |
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically |
-- inserted into the memory interfaces increasing instruction fetch & data access latency by +1 cycle! |
constant pmp_num_regions_critical_c : natural := 8; |
|
-- Architecture Constants (do not modify!)= ----------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant data_width_c : natural := 32; -- data width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050003"; -- no touchy! |
constant data_width_c : natural := 32; -- native data path width - do not change! |
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050009"; -- no touchy! |
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED! |
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off! |
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW |
90,33 → 95,69
|
-- Internal Bootloader ROM -- |
constant boot_rom_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFF0000"; -- bootloader base address, fixed! |
constant boot_rom_size_c : natural := 4*1024; -- bytes |
constant boot_rom_max_size_c : natural := 32*1024; -- bytes, fixed! |
constant boot_rom_size_c : natural := 4*1024; -- module's address space in bytes |
constant boot_rom_max_size_c : natural := 32*1024; -- max module's address space in bytes, fixed! |
|
-- IO: Peripheral Devices ("IO") Area -- |
-- Control register(s) (including the device-enable) should be located at the base address of each device |
constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; |
constant io_size_c : natural := 32*4; -- bytes, fixed! |
constant io_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; |
constant io_size_c : natural := 64*4; -- module's address space in bytes, fixed! |
|
-- Custom Functions Subsystem (CFS) -- |
constant cfs_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; -- base address |
constant cfs_size_c : natural := 32*4; -- module's address space in bytes |
constant cfs_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF00"; |
constant cfs_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF04"; |
constant cfs_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF08"; |
constant cfs_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF0C"; |
constant cfs_reg4_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF10"; |
constant cfs_reg5_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF14"; |
constant cfs_reg6_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF18"; |
constant cfs_reg7_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF1C"; |
constant cfs_reg8_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF20"; |
constant cfs_reg9_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF24"; |
constant cfs_reg10_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF28"; |
constant cfs_reg11_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF2C"; |
constant cfs_reg12_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF30"; |
constant cfs_reg13_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF34"; |
constant cfs_reg14_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF38"; |
constant cfs_reg15_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF3C"; |
constant cfs_reg16_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF40"; |
constant cfs_reg17_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF44"; |
constant cfs_reg18_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF48"; |
constant cfs_reg19_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF4C"; |
constant cfs_reg20_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF50"; |
constant cfs_reg21_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF54"; |
constant cfs_reg22_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF58"; |
constant cfs_reg23_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF5C"; |
constant cfs_reg24_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF60"; |
constant cfs_reg25_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF64"; |
constant cfs_reg26_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF68"; |
constant cfs_reg27_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF6C"; |
constant cfs_reg28_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF70"; |
constant cfs_reg29_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF74"; |
constant cfs_reg30_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF78"; |
constant cfs_reg31_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF7C"; |
|
-- General Purpose Input/Output Unit (GPIO) -- |
constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address, fixed! |
constant gpio_size_c : natural := 2*4; -- bytes |
constant gpio_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; -- base address |
constant gpio_size_c : natural := 2*4; -- module's address space in bytes |
constant gpio_in_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF80"; |
constant gpio_out_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF84"; |
|
-- True Random Number Generator (TRNG) -- |
constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address, fixed! |
constant trng_size_c : natural := 1*4; -- bytes |
constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; -- base address |
constant trng_size_c : natural := 1*4; -- module's address space in bytes |
constant trng_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF88"; |
|
-- Watch Dog Timer (WDT) -- |
constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address, fixed! |
constant wdt_size_c : natural := 1*4; -- bytes |
constant wdt_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; -- base address |
constant wdt_size_c : natural := 1*4; -- module's address space in bytes |
constant wdt_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF8C"; |
|
-- Machine System Timer (MTIME) -- |
constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address, fixed! |
constant mtime_size_c : natural := 4*4; -- bytes |
constant mtime_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; -- base address |
constant mtime_size_c : natural := 4*4; -- module's address space in bytes |
constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF90"; |
constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF94"; |
constant mtime_cmp_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF98"; |
123,48 → 164,36
constant mtime_cmp_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFF9C"; |
|
-- Universal Asynchronous Receiver/Transmitter (UART) -- |
constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address, fixed! |
constant uart_size_c : natural := 2*4; -- bytes |
constant uart_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; -- base address |
constant uart_size_c : natural := 2*4; -- module's address space in bytes |
constant uart_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA0"; |
constant uart_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA4"; |
|
-- Serial Peripheral Interface (SPI) -- |
constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address, fixed! |
constant spi_size_c : natural := 2*4; -- bytes |
constant spi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; -- base address |
constant spi_size_c : natural := 2*4; -- module's address space in bytes |
constant spi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFA8"; |
constant spi_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFAC"; |
|
-- Two Wire Interface (TWI) -- |
constant twi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address, fixed! |
constant twi_size_c : natural := 2*4; -- bytes |
constant twi_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; -- base address |
constant twi_size_c : natural := 2*4; -- module's address space in bytes |
constant twi_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB0"; |
constant twi_rtx_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB4"; |
|
-- Pulse-Width Modulation Controller (PWM) -- |
constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address, fixed! |
constant pwm_size_c : natural := 2*4; -- bytes |
constant pwm_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; -- base address |
constant pwm_size_c : natural := 2*4; -- module's address space in bytes |
constant pwm_ctrl_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFB8"; |
constant pwm_duty_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFBC"; |
|
-- Custom Functions Unit 0 (CFU0) -- |
constant cfu0_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed! |
constant cfu0_size_c : natural := 4*4; -- bytes |
constant cfu0_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; |
constant cfu0_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC4"; |
constant cfu0_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; |
constant cfu0_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC"; |
-- reserved -- |
--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address |
--constant reserved_size_c : natural := 8*4; -- module's address space in bytes |
|
-- Custom Functions Unit 1 (CFU1) -- |
constant cfu1_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; -- base address, fixed! |
constant cfu1_size_c : natural := 4*4; -- bytes |
constant cfu1_reg0_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD0"; |
constant cfu1_reg1_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD4"; |
constant cfu1_reg2_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFD8"; |
constant cfu1_reg3_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFDC"; |
|
-- System Information Memory (SYSINFO) -- |
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed! |
constant sysinfo_size_c : natural := 8*4; -- bytes |
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address |
constant sysinfo_size_c : natural := 8*4; -- module's address space in bytes |
|
-- Main Control Bus ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
243,13 → 272,15
constant ctrl_ir_opcode7_4_c : natural := 66; -- opcode7 bit 4 |
constant ctrl_ir_opcode7_5_c : natural := 67; -- opcode7 bit 5 |
constant ctrl_ir_opcode7_6_c : natural := 68; -- opcode7 bit 6 |
-- CPU status -- |
constant ctrl_sleep_c : natural := 69; -- set when CPU is in sleep mode |
-- control bus size -- |
constant ctrl_width_c : natural := 69; -- control bus size |
constant ctrl_width_c : natural := 70; -- control bus size |
|
-- ALU Comparator Bus --------------------------------------------------------------------- |
-- Comparator Bus ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
constant alu_cmp_equal_c : natural := 0; |
constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons |
constant cmp_equal_c : natural := 0; |
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons |
|
-- RISC-V Opcode Layout ------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
668,32 → 699,40
constant trap_firq1_c : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1 |
constant trap_firq2_c : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2 |
constant trap_firq3_c : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3 |
constant trap_firq4_c : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4 |
constant trap_firq5_c : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5 |
constant trap_firq6_c : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6 |
constant trap_firq7_c : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7 |
|
-- CPU Control Exception System ----------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
-- exception source bits -- |
constant exception_iaccess_c : natural := 0; -- instrution access fault |
constant exception_iillegal_c : natural := 1; -- illegal instrution |
constant exception_ialign_c : natural := 2; -- instrution address misaligned |
constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode |
constant exception_u_envcall_c : natural := 4; -- ENV call from u-mode |
constant exception_break_c : natural := 5; -- breakpoint |
constant exception_salign_c : natural := 6; -- store address misaligned |
constant exception_lalign_c : natural := 7; -- load address misaligned |
constant exception_saccess_c : natural := 8; -- store access fault |
constant exception_laccess_c : natural := 9; -- load access fault |
constant exception_iaccess_c : natural := 0; -- instrution access fault |
constant exception_iillegal_c : natural := 1; -- illegal instrution |
constant exception_ialign_c : natural := 2; -- instrution address misaligned |
constant exception_m_envcall_c : natural := 3; -- ENV call from m-mode |
constant exception_u_envcall_c : natural := 4; -- ENV call from u-mode |
constant exception_break_c : natural := 5; -- breakpoint |
constant exception_salign_c : natural := 6; -- store address misaligned |
constant exception_lalign_c : natural := 7; -- load address misaligned |
constant exception_saccess_c : natural := 8; -- store access fault |
constant exception_laccess_c : natural := 9; -- load access fault |
-- |
constant exception_width_c : natural := 10; -- length of this list in bits |
-- interrupt source bits -- |
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt |
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt |
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt |
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0 |
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1 |
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2 |
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3 |
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt |
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt |
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt |
constant interrupt_firq_0_c : natural := 3; -- fast interrupt channel 0 |
constant interrupt_firq_1_c : natural := 4; -- fast interrupt channel 1 |
constant interrupt_firq_2_c : natural := 5; -- fast interrupt channel 2 |
constant interrupt_firq_3_c : natural := 6; -- fast interrupt channel 3 |
constant interrupt_firq_4_c : natural := 7; -- fast interrupt channel 4 |
constant interrupt_firq_5_c : natural := 8; -- fast interrupt channel 5 |
constant interrupt_firq_6_c : natural := 9; -- fast interrupt channel 6 |
constant interrupt_firq_7_c : natural := 10; -- fast interrupt channel 7 |
-- |
constant interrupt_width_c : natural := 7; -- length of this list in bits |
constant interrupt_width_c : natural := 11; -- length of this list in bits |
|
-- CPU Privilege Modes -------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
756,7 → 795,7
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) |
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) |
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes |
780,8 → 819,8
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? |
IO_CFU0_EN : boolean := false; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN : boolean := false -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? |
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic |
); |
port ( |
-- Global control -- |
818,9 → 857,13
twi_scl_io : inout std_logic; -- twi serial clock line |
-- PWM -- |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels |
-- Custom Functions Subsystem IO -- |
cfs_in_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CSF inputs |
cfs_out_o : out std_ulogic_vector(31 downto 0); -- custom CSF outputs |
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- Interrupts -- |
soc_firq_i : in std_ulogic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
851,12 → 894,13
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) |
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS : natural := 0 -- number of implemented HPM counters (0..29) |
); |
port ( |
-- global control -- |
clk_i : in std_ulogic := '0'; -- global clock, rising edge |
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async |
sleep_o : out std_ulogic; -- cpu is in sleep mode when set |
-- instruction bus interface -- |
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data |
890,7 → 934,8
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0') |
firq_i : in std_ulogic_vector(7 downto 0) := (others => '0'); |
firq_ack_o : out std_ulogic_vector(7 downto 0) |
); |
end component; |
|
914,7 → 959,7
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) |
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS : natural := 0 -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS : natural := 0 -- number of implemented HPM counters (0..29) |
); |
port ( |
-- global control -- |
940,7 → 985,8
mext_irq_i : in std_ulogic; -- machine external interrupt |
mtime_irq_i : in std_ulogic; -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i : in std_ulogic_vector(3 downto 0); |
firq_i : in std_ulogic_vector(7 downto 0); |
firq_ack_o : out std_ulogic_vector(7 downto 0); |
-- system time input from MTIME -- |
time_i : in std_ulogic_vector(63 downto 0); -- current system time |
-- physical memory protection -- |
973,7 → 1019,8
csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data |
-- data output -- |
rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1 |
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2 |
rs2_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2 |
cmp_o : out std_ulogic_vector(1 downto 0) -- comparator status |
); |
end component; |
|
995,7 → 1042,6
pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC |
imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate |
-- data output -- |
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status |
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result |
add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result |
-- co-processor interface -- |
1124,9 → 1170,9
-- ------------------------------------------------------------------------------------------- |
component neorv32_icache |
generic ( |
CACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
CACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 |
CACHE_NUM_SETS : natural := 1 -- associativity / number of sets (1=direct_mapped), has to be a power of 2 |
ICACHE_NUM_BLOCKS : natural := 4; -- number of blocks (min 1), has to be a power of 2 |
ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2 |
ICACHE_NUM_SETS : natural := 1 -- associativity / number of sets (1=direct_mapped), has to be a power of 2 |
); |
port ( |
-- global control -- |
1486,30 → 1532,12
); |
end component; |
|
-- Component: Custom Functions Unit 0 (CFU0) ---------------------------------------------- |
-- Component: Custom Functions Subsystem (CFS) -------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cfu0 |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
rstn_i : in std_ulogic; -- global reset line, low-active, use as async |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o : out std_ulogic; -- enable clock generator |
clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs |
-- custom io -- |
-- ... |
component neorv32_cfs |
generic ( |
CFS_CONFIG : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic |
); |
end component; |
|
-- Component: Custom Functions Unit 1 (CFU1) ---------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
component neorv32_cfu1 |
port ( |
-- host access -- |
clk_i : in std_ulogic; -- global clock line |
1516,15 → 1544,22
rstn_i : in std_ulogic; -- global reset line, low-active, use as async |
addr_i : in std_ulogic_vector(31 downto 0); -- address |
rden_i : in std_ulogic; -- read enable |
wren_i : in std_ulogic; -- write enable |
wren_i : in std_ulogic; -- word write enable |
data_i : in std_ulogic_vector(31 downto 0); -- data in |
data_o : out std_ulogic_vector(31 downto 0); -- data out |
ack_o : out std_ulogic; -- transfer acknowledge |
err_o : out std_ulogic; -- transfer error |
-- clock generator -- |
clkgen_en_o : out std_ulogic; -- enable clock generator |
clkgen_i : in std_ulogic_vector(07 downto 0) -- "clock" inputs |
-- custom io -- |
-- ... |
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs |
-- CPU state -- |
sleep_i : in std_ulogic; -- set if cpu is in sleep mode |
-- interrupt -- |
irq_o : out std_ulogic; -- interrupt request |
irq_ack_i : in std_ulogic; -- interrupt acknowledge |
-- custom io (conduit) -- |
cfs_in_i : in std_ulogic_vector(31 downto 0); -- custom inputs |
cfs_out_o : out std_ulogic_vector(31 downto 0) -- custom outputs |
); |
end component; |
|
1559,8 → 1594,7
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)? |
IO_CFU0_EN : boolean := true; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN : boolean := true -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN : boolean := true -- implement custom functions subsystem (CFS)? |
); |
port ( |
-- host access -- |
/rtl/core/neorv32_sysinfo.vhd
1,7 → 1,7
-- ################################################################################################# |
-- # << NEORV32 - System/Processor Configuration Information Memory (SYSINFO) >> # |
-- # ********************************************************************************************* # |
-- # This unit provides information regarding the 'processor system' configuration - # |
-- # This unit provides information regarding the NEORV32 processor system configuration - # |
-- # mostly derived from the top's configuration generics. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
71,8 → 71,7
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)? |
IO_CFU0_EN : boolean := true; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN : boolean := true -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN : boolean := true -- implement custom functions subsystem (CFS)? |
); |
port ( |
-- host access -- |
138,11 → 137,10
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented? |
sysinfo_mem(2)(21) <= bool_to_ulogic_f(IO_PWM_EN); -- pulse-width modulation unit (PWM) implemented? |
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_EN); -- watch dog timer (WDT) implemented? |
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFU0_EN); -- custom functions unit 0 (CFU0) implemented? |
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS) implemented? |
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented? |
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_CFU1_EN); -- custom functions unit 1 (CFU1) implemented? |
-- |
sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved |
sysinfo_mem(2)(31 downto 25) <= (others => '0'); -- reserved |
|
-- SYSINFO(3): Cache configuration -- |
sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes) |
/rtl/core/neorv32_top.vhd
68,7 → 68,7
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) |
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) |
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes |
92,8 → 92,8
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? |
IO_CFU0_EN : boolean := false; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN : boolean := false -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? |
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic |
); |
port ( |
-- Global control -- |
130,9 → 130,13
twi_scl_io : inout std_logic; -- twi serial clock line |
-- PWM (available if IO_PWM_EN = true) -- |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels |
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- custom CFS inputs conduit |
cfs_out_o : out std_ulogic_vector(31 downto 0); -- custom CFS outputs conduit |
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time |
-- Interrupts -- |
soc_firq_i : in std_ulogic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt |
mext_irq_i : in std_ulogic := '0' -- machine external interrupt |
165,13 → 169,13
signal clk_div : std_ulogic_vector(11 downto 0); |
signal clk_div_ff : std_ulogic_vector(11 downto 0); |
signal clk_gen : std_ulogic_vector(07 downto 0); |
-- |
signal wdt_cg_en : std_ulogic; |
signal uart_cg_en : std_ulogic; |
signal spi_cg_en : std_ulogic; |
signal twi_cg_en : std_ulogic; |
signal pwm_cg_en : std_ulogic; |
signal cfu0_cg_en : std_ulogic; |
signal cfu1_cg_en : std_ulogic; |
signal cfs_cg_en : std_ulogic; |
|
-- bus interface -- |
type bus_interface_t is record |
222,24 → 226,27
signal wdt_ack : std_ulogic; |
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal trng_ack : std_ulogic; |
signal cfu0_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal cfu0_ack : std_ulogic; |
signal cfu1_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal cfu1_ack : std_ulogic; |
signal cfs_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal cfs_err : std_ulogic; |
signal cfs_ack : std_ulogic; |
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0); |
signal sysinfo_ack : std_ulogic; |
|
-- IRQs -- |
signal mtime_irq : std_ulogic; |
signal fast_irq : std_ulogic_vector(3 downto 0); |
signal gpio_irq : std_ulogic; |
signal wdt_irq : std_ulogic; |
signal uart_irq : std_ulogic; |
signal spi_irq : std_ulogic; |
signal twi_irq : std_ulogic; |
-- |
signal fast_irq : std_ulogic_vector(7 downto 0); |
signal fast_irq_ack : std_ulogic_vector(7 downto 0); |
signal gpio_irq : std_ulogic; |
signal wdt_irq : std_ulogic; |
signal uart_irq : std_ulogic; |
signal spi_irq : std_ulogic; |
signal twi_irq : std_ulogic; |
signal cfs_irq : std_ulogic; |
|
-- misc -- |
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME |
signal cpu_sleep : std_ulogic; -- CPU is in sleep mode when set |
|
begin |
|
305,7 → 312,7
clk_div_ff <= (others => '0'); |
elsif rising_edge(clk_i) then |
-- fresh clocks anyone? -- |
if ((wdt_cg_en or uart_cg_en or spi_cg_en or twi_cg_en or pwm_cg_en or cfu0_cg_en or cfu1_cg_en) = '1') then |
if ((wdt_cg_en or uart_cg_en or spi_cg_en or twi_cg_en or pwm_cg_en or cfs_cg_en) = '1') then |
clk_div <= std_ulogic_vector(unsigned(clk_div) + 1); |
end if; |
clk_div_ff <= clk_div; |
352,12 → 359,13
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) |
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS => HPM_NUM_CNTS -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS => HPM_NUM_CNTS -- number of implemented HPM counters (0..29) |
) |
port map ( |
-- global control -- |
clk_i => clk_i, -- global clock, rising edge |
rstn_i => sys_rstn, -- global reset, low-active, async |
sleep_o => cpu_sleep, -- cpu is in sleep mode when set |
-- instruction bus interface -- |
i_bus_addr_o => cpu_i.addr, -- bus access address |
i_bus_rdata_i => cpu_i.rdata, -- bus read data |
391,7 → 399,8
mext_irq_i => mext_irq_i, -- machine external interrupt request |
mtime_irq_i => mtime_irq, -- machine timer interrupt |
-- fast interrupts (custom) -- |
firq_i => fast_irq |
firq_i => fast_irq, -- fast interrupt trigger |
firq_ack_o => fast_irq_ack -- fast interrupt acknowledge mask |
); |
|
-- misc -- |
402,11 → 411,16
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation |
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation |
|
-- fast interrupts -- |
fast_irq(0) <= wdt_irq; -- highest priority, watchdog timeout interrupt |
fast_irq(1) <= gpio_irq; -- GPIO input pin-change interrupt |
fast_irq(2) <= uart_irq; -- UART TX done or RX complete interrupt |
fast_irq(3) <= spi_irq or twi_irq; -- lowest priority, can be triggered by SPI or TWI |
-- fast interrupts - processor-internal -- |
fast_irq(0) <= wdt_irq; -- highest priority, watchdog timeout interrupt |
fast_irq(1) <= gpio_irq or cfs_irq; -- GPIO input pin-change interrupt or custom CFS interrupt |
fast_irq(2) <= uart_irq; -- UART TX done or RX complete interrupt |
fast_irq(3) <= spi_irq or twi_irq; -- lowest priority, can be triggered by SPI or TWI |
-- fast interrupts - platform level (for cutsom use) -- |
fast_irq(4) <= soc_firq_i(0); |
fast_irq(5) <= soc_firq_i(1); |
fast_irq(6) <= soc_firq_i(2); |
fast_irq(7) <= soc_firq_i(3); |
|
|
-- CPU Instruction Cache ------------------------------------------------------------------ |
415,9 → 429,9
if (ICACHE_EN = true) generate |
neorv32_icache_inst: neorv32_icache |
generic map ( |
CACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 2), has to be a power of 2 |
CACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2 |
CACHE_NUM_SETS => ICACHE_ASSOCIATIVITY -- associativity / number of sets (1=direct_mapped), has to be a power of 2 |
ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- number of blocks (min 2), has to be a power of 2 |
ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- block size in bytes (min 4), has to be a power of 2 |
ICACHE_NUM_SETS => ICACHE_ASSOCIATIVITY -- associativity / number of sets (1=direct_mapped), has to be a power of 2 |
) |
port map ( |
-- global control -- |
513,14 → 527,14
|
-- processor bus: CPU data input -- |
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or |
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfu0_rdata or cfu1_rdata or sysinfo_rdata); |
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or sysinfo_rdata); |
|
-- processor bus: CPU data ACK input -- |
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or |
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfu0_ack or cfu1_ack or sysinfo_ack); |
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or sysinfo_ack); |
|
-- processor bus: CPU data bus error input -- |
p_bus.err <= wishbone_err; |
p_bus.err <= wishbone_err or cfs_err; |
|
-- current CPU privilege level -- |
p_bus.priv <= cpu_i.priv; -- cpu_i.priv == cpu_d.priv |
676,10 → 690,54
-- ------------------------------------------------------------------------------------------- |
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0'; |
io_rden <= io_acc and p_bus.re and (not p_bus.src); -- PMA: no_execute for IO region |
-- the peripheral/IO devices in the IO area can only be written in word mode (reduces HW complexity) |
io_wren <= io_acc and p_bus.we and and_all_f(p_bus.ben) and (not p_bus.src); -- PMA: no_execute for IO region |
-- the default NEORV32 peripheral/IO devices in the IO area can only be written in word mode (reduces HW complexity) |
io_wren <= io_acc and p_bus.we and and_all_f(p_bus.ben) and (not p_bus.src); -- PMA: write32 only, no_execute for IO region |
|
|
-- Custom Functions Subsystem (CFS) ------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cfs_inst_true: |
if (IO_CFS_EN = true) generate |
neorv32_cfs_inst: neorv32_cfs |
generic map ( |
CFS_CONFIG => IO_CFS_CONFIG -- custom CFS configuration generic |
) |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active, use as async |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- byte write enable |
data_i => p_bus.wdata, -- data in |
data_o => cfs_rdata, -- data out |
ack_o => cfs_ack, -- transfer acknowledge |
err_o => cfs_err, -- transfer error |
-- clock generator -- |
clkgen_en_o => cfs_cg_en, -- enable clock generator |
clkgen_i => clk_gen, -- "clock" inputs |
-- CPU state -- |
sleep_i => cpu_sleep, -- set if cpu is in sleep mode |
-- interrupt -- |
irq_o => cfs_irq, -- interrupt request |
irq_ack_i => fast_irq_ack(1), -- interrupt acknowledge |
-- custom io (conduit) -- |
cfs_in_i => cfs_in_i, -- custom inputs |
cfs_out_o => cfs_out_o -- custom outputs |
); |
end generate; |
|
neorv32_cfs_inst_false: |
if (IO_CFS_EN = false) generate |
cfs_rdata <= (others => '0'); |
cfs_ack <= '0'; |
cfs_err <= '0'; |
cfs_cg_en <= '0'; |
cfs_irq <= '0'; |
cfs_out_o <= (others => '0'); |
end generate; |
|
|
-- General Purpose Input/Output Port (GPIO) ----------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_gpio_inst_true: |
941,68 → 999,6
end generate; |
|
|
-- Custom Functions Unit 0 (CFU0) --------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cfu0_inst_true: |
if (IO_CFU0_EN = true) generate |
neorv32_cfu0_inst: neorv32_cfu0 |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active, use as async |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
data_i => p_bus.wdata, -- data in |
data_o => cfu0_rdata, -- data out |
ack_o => cfu0_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => cfu0_cg_en, -- enable clock generator |
clkgen_i => clk_gen -- "clock" inputs |
-- custom io -- |
-- ... |
); |
end generate; |
|
neorv32_cfu0_inst_false: |
if (IO_CFU0_EN = false) generate |
cfu0_rdata <= (others => '0'); |
cfu0_ack <= '0'; |
cfu0_cg_en <= '0'; |
end generate; |
|
|
-- Custom Functions Unit 1 (CFU1) --------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_cfu1_inst_true: |
if (IO_CFU1_EN = true) generate |
neorv32_cfu1_inst: neorv32_cfu1 |
port map ( |
-- host access -- |
clk_i => clk_i, -- global clock line |
rstn_i => sys_rstn, -- global reset line, low-active, use as async |
addr_i => p_bus.addr, -- address |
rden_i => io_rden, -- read enable |
wren_i => io_wren, -- write enable |
data_i => p_bus.wdata, -- data in |
data_o => cfu1_rdata, -- data out |
ack_o => cfu1_ack, -- transfer acknowledge |
-- clock generator -- |
clkgen_en_o => cfu1_cg_en, -- enable clock generator |
clkgen_i => clk_gen -- "clock" inputs |
-- custom io -- |
-- ... |
); |
end generate; |
|
neorv32_cfu1_inst_false: |
if (IO_CFU1_EN = false) generate |
cfu1_rdata <= (others => '0'); |
cfu1_ack <= '0'; |
cfu1_cg_en <= '0'; |
end generate; |
|
|
-- System Configuration Information Memory (SYSINFO) -------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_sysinfo_inst: neorv32_sysinfo |
1034,8 → 1030,7
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? |
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? |
IO_CFU0_EN => IO_CFU0_EN, -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN => IO_CFU1_EN -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN => IO_CFS_EN -- implement custom functions subsystem (CFS)? |
) |
port map ( |
-- host access -- |
/rtl/core/neorv32_trng.vhd
1,17 → 1,14
-- ################################################################################################# |
-- # << NEORV32 - True Random Number Generator (TRNG) >> # |
-- # ********************************************************************************************* # |
-- # This unit implements a true random number generator which uses several GARO chain as entropy # |
-- # source. The outputs of all chains are XORed and de-biased using a John von Neumann randomness # |
-- # extractor. The de-biased signal is further processed by a simple LFSR for improved whitening. # |
-- # # |
-- # Sources: # |
-- # - Von Neumann De-Biasing: "Iterating Von Neumann's Post-Processing under Hardware # |
-- # Constraints" by Vladimir Rozic, Bohan Yang, Wim Dehaene and Ingrid Verbauwhede, 2016 # |
-- # This unit implements a *true* random number generator which uses several ring oscillators as # |
-- # entropy source. The outputs of all chains are XORed and de-biased using a John von Neumann # |
-- # randomness extractor. The de-biased signal is further processed by a simple LFSR for improved # |
-- # whitening. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
62,43 → 59,35
|
architecture neorv32_trng_rtl of neorv32_trng is |
|
-- advanced configuration -------------------------------------------------------------------------------- |
constant num_inv_c : natural := 15; -- length of GARO inverter chain (default=15, has to be odd) |
constant num_garos_c : natural := 2; -- number of GARO elements (default=2) |
constant lfsr_taps_c : std_ulogic_vector(7 downto 0) := "10111000"; -- Fibonacci post-processing LFSR feedback taps |
constant lfsr_en_c : boolean := true; -- use LFSR-based post-processing |
type tap_mask_t is array (0 to num_garos_c-1) of std_ulogic_vector(num_inv_c-2 downto 0); |
constant tap_mask : tap_mask_t := ( -- GARO tap masks, sum of set bits has to be even |
"11110000000000", |
"00000011000000" |
); |
-- Advanced Configuration -------------------------------------------------------------------------------- |
constant num_roscs_c : natural := 4; -- total number of ring oscillators |
constant num_inv_start_c : natural := 5; -- number of inverters in FIRST ring oscillator (has to be odd) |
constant num_inv_inc_c : natural := 2; -- number of inverters increment for each next ring oscillator (has to be even) |
constant lfsr_en_c : boolean := true; -- use LFSR-based post-processing |
constant lfsr_taps_c : std_ulogic_vector(7 downto 0) := "10111000"; -- Fibonacci post-processing LFSR feedback taps |
-- ------------------------------------------------------------------------------------------------------- |
|
-- control register bits -- |
constant ctrl_data_lsb_c : natural := 0; -- r/-: Random data bit LSB |
constant ctrl_data_msb_c : natural := 7; -- r/-: Random data bit MSB |
constant ctrl_data_valid_c : natural := 15; -- r/-: Output data valid |
constant ctrl_err_zero_c : natural := 16; -- r/-: stuck at 0 error |
constant ctrl_err_one_c : natural := 17; -- r/-: stuck at 1 error |
constant ctrl_en_c : natural := 31; -- r/w: TRNG enable |
constant ctrl_data_lsb_c : natural := 0; -- r/-: Random data byte LSB |
constant ctrl_data_msb_c : natural := 7; -- r/-: Random data byte MSB |
-- |
constant ctrl_en_c : natural := 30; -- r/w: TRNG enable |
constant ctrl_valid_c : natural := 31; -- r/-: Output data valid |
|
-- IO space: module base address -- |
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(trng_size_c); -- low address boundary bit |
|
-- Component: GARO Element -- |
component neorv32_trng_garo_element |
-- Component: Ring-Oscillator -- |
component neorv32_trng_ring_osc |
generic ( |
NUM_INV : natural := 16 -- number of inverters in chain |
); |
port ( |
clk_i : in std_ulogic; |
enable_i : in std_ulogic; |
enable_o : out std_ulogic; |
mask_i : in std_ulogic_vector(NUM_INV-2 downto 0); |
data_o : out std_ulogic; |
error0_o : out std_ulogic; |
error1_o : out std_ulogic |
enable_i : in std_ulogic; -- enable chain input |
enable_o : out std_ulogic; -- enable chain output |
data_o : out std_ulogic -- sync random bit |
); |
end component; |
|
107,35 → 96,38
signal wren : std_ulogic; -- full word write enable |
signal rden : std_ulogic; -- read enable |
|
-- garo array -- |
signal garo_en_in : std_ulogic_vector(num_garos_c-1 downto 0); |
signal garo_en_out : std_ulogic_vector(num_garos_c-1 downto 0); |
signal garo_data : std_ulogic_vector(num_garos_c-1 downto 0); |
signal garo_err_zero : std_ulogic_vector(num_garos_c-1 downto 0); |
signal garo_err_one : std_ulogic_vector(num_garos_c-1 downto 0); |
signal garo_res : std_ulogic; |
signal garo_err0 : std_ulogic; |
signal garo_err1 : std_ulogic; |
-- ring-oscillator array -- |
signal osc_array_en_in : std_ulogic_vector(num_roscs_c-1 downto 0); |
signal osc_array_en_out : std_ulogic_vector(num_roscs_c-1 downto 0); |
signal osc_array_data : std_ulogic_vector(num_roscs_c-1 downto 0); |
|
-- de-biasing -- |
signal db_data : std_ulogic_vector(2 downto 0); |
signal db_state : std_ulogic; -- process de-biasing every second cycle |
signal rnd_valid : std_ulogic; |
signal rnd_data : std_ulogic; |
-- von-Neumann de-biasing -- |
type debiasing_t is record |
sreg : std_ulogic_vector(1 downto 0); |
state : std_ulogic; -- process de-biasing every second cycle |
valid : std_ulogic; -- de-biased data |
data : std_ulogic; -- de-biased data valid |
end record; |
signal debiasing : debiasing_t; |
|
-- processing core -- |
signal rnd_enable : std_ulogic; |
signal rnd_cnt : std_ulogic_vector(3 downto 0); |
signal rnd_sreg : std_ulogic_vector(7 downto 0); |
signal rnd_output : std_ulogic_vector(7 downto 0); |
signal rnd_ready : std_ulogic; |
-- (post-)processing core -- |
type processing_t is record |
enable : std_ulogic; -- TRNG enable flag |
cnt : std_ulogic_vector(3 downto 0); -- bit counter |
sreg : std_ulogic_vector(7 downto 0); -- data shift register |
output : std_ulogic_vector(7 downto 0); -- output register |
valid : std_ulogic; -- data output valid flag |
end record; |
signal processing : processing_t; |
|
-- health check -- |
signal rnd_error_zero : std_ulogic; -- stuck at zero |
signal rnd_error_one : std_ulogic; -- stuck at one |
|
begin |
|
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
assert not (num_roscs_c = 0) report "NEORV32 PROCESSOR CONFIG NOTE: TRNG - Total number of ring-oscillators has to be >0." severity error; |
assert not ((num_inv_start_c mod 2) = 0) report "NEORV32 PROCESSOR CONFIG NOTE: TRNG - Number of inverters in fisrt ring has to be odd." severity error; |
assert not ((num_inv_inc_c mod 2) /= 0) report "NEORV32 PROCESSOR CONFIG NOTE: TRNG - Number of inverters increment for each next ring has to be even." severity error; |
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
148,19 → 140,17
rw_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
ack_o <= acc_en and (rden_i or wren_i); |
ack_o <= wren or rden; |
-- write access -- |
if (wren = '1') then |
rnd_enable <= data_i(ctrl_en_c); |
processing.enable <= data_i(ctrl_en_c); |
end if; |
-- read access -- |
data_o <= (others => '0'); |
if (rden = '1') then |
data_o(ctrl_data_msb_c downto ctrl_data_lsb_c) <= rnd_output; |
data_o(ctrl_data_valid_c) <= rnd_ready; |
data_o(ctrl_err_zero_c) <= rnd_error_zero; |
data_o(ctrl_err_one_c) <= rnd_error_one; |
data_o(ctrl_en_c) <= rnd_enable; |
data_o(ctrl_data_msb_c downto ctrl_data_lsb_c) <= processing.output; |
data_o(ctrl_en_c) <= processing.enable; |
data_o(ctrl_valid_c) <= processing.valid; |
end if; |
end if; |
end process rw_access; |
168,75 → 158,55
|
-- Entropy Source ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
neorv32_trng_garo_element_inst: |
for i in 0 to num_garos_c-1 generate |
neorv32_trng_garo_element_inst_i: neorv32_trng_garo_element |
neorv32_trng_ring_osc_inst: |
for i in 0 to num_roscs_c-1 generate |
neorv32_trng_ring_osc_inst_i: neorv32_trng_ring_osc |
generic map ( |
NUM_INV => num_inv_c -- number of inverters in chain |
NUM_INV => num_inv_start_c + (i*num_inv_inc_c) -- number of inverters in chain |
) |
port map ( |
clk_i => clk_i, |
enable_i => garo_en_in(i), |
enable_o => garo_en_out(i), |
mask_i => tap_mask(i), |
data_o => garo_data(i), |
error0_o => garo_err_zero(i), |
error1_o => garo_err_one(i) |
enable_i => osc_array_en_in(i), |
enable_o => osc_array_en_out(i), |
data_o => osc_array_data(i) |
); |
end generate; |
|
-- GARO element connection -- |
garo_intercon: process(rnd_enable, garo_en_out, garo_data, garo_err_zero, garo_err_one) |
variable data_v : std_ulogic; |
variable err0_v : std_ulogic; |
variable err1_v : std_ulogic; |
-- RO enable chain -- |
array_intercon: process(processing.enable, osc_array_en_out) |
begin |
-- enable chain -- |
for i in 0 to num_garos_c-1 loop |
if (i = 0) then |
garo_en_in(i) <= rnd_enable; |
for i in 0 to num_roscs_c-1 loop |
if (i = 0) then -- start of enable chain |
osc_array_en_in(i) <= processing.enable; |
else |
garo_en_in(i) <= garo_en_out(i-1); |
osc_array_en_in(i) <= osc_array_en_out(i-1); |
end if; |
end loop; -- i |
-- data & status -- |
data_v := garo_data(0); |
err0_v := garo_err_zero(0); |
err1_v := garo_err_one(0); |
for i in 1 to num_garos_c-1 loop |
data_v := data_v xor garo_data(i); |
err0_v := err0_v or garo_err_zero(i); |
err1_v := err1_v or garo_err_one(i); |
end loop; -- i |
garo_res <= data_v; |
garo_err0 <= err0_v; |
garo_err1 <= err1_v; |
end process garo_intercon; |
end process array_intercon; |
|
|
-- De-Biasing ----------------------------------------------------------------------------- |
-- John von Neumann De-Biasing ------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
jvn_debiasing_sync: process(clk_i) |
neumann_debiasing_sync: process(clk_i) |
begin |
if rising_edge(clk_i) then |
db_data <= db_data(db_data'left-1 downto 0) & garo_res; |
db_state <= (not db_state) and rnd_enable; -- just toggle when enabled -> process in every second cycle |
debiasing.sreg <= debiasing.sreg(debiasing.sreg'left-1 downto 0) & xor_all_f(osc_array_data); |
debiasing.state <= (not debiasing.state) and osc_array_en_out(num_roscs_c-1); -- start toggling when last RO is enabled -> process in every second cycle |
end if; |
end process jvn_debiasing_sync; |
end process neumann_debiasing_sync; |
|
|
-- John von Neumann De-Biasing -- |
jvn_debiasing: process(db_state, db_data) |
-- Edge detector -- |
neumann_debiasing_comb: process(debiasing) |
variable tmp_v : std_ulogic_vector(2 downto 0); |
begin |
-- check groups of two non-overlapping bits from the input stream |
tmp_v := db_state & db_data(db_data'left downto db_data'left-1); |
tmp_v := debiasing.state & debiasing.sreg; |
case tmp_v is |
when "101" => rnd_valid <= '1'; rnd_data <= '1'; -- rising edge -> '1' |
when "110" => rnd_valid <= '1'; rnd_data <= '0'; -- falling edge -> '0' |
when others => rnd_valid <= '0'; rnd_data <= '-'; -- invalid |
when "101" => debiasing.valid <= '1'; debiasing.data <= '1'; -- rising edge -> '1' |
when "110" => debiasing.valid <= '1'; debiasing.data <= '0'; -- falling edge -> '0' |
when others => debiasing.valid <= '0'; debiasing.data <= '0'; -- no valid data |
end case; |
end process jvn_debiasing; |
end process neumann_debiasing_comb; |
|
|
-- Processing Core ------------------------------------------------------------------------ |
244,43 → 214,34
processing_core: process(clk_i) |
begin |
if rising_edge(clk_i) then |
-- sample random data and apply post-processing -- |
if (rnd_enable = '0') then |
rnd_cnt <= (others => '0'); |
rnd_sreg <= (others => '0'); |
elsif (rnd_valid = '1') and (garo_en_out(garo_en_out'left) = '1') then -- valid random sample and GAROs ready? |
if (rnd_cnt = "1000") then |
rnd_cnt <= (others => '0'); |
-- sample random data bit and apply post-processing -- |
if (processing.enable = '0') then |
processing.cnt <= (others => '0'); |
processing.sreg <= (others => '0'); |
elsif (debiasing.valid = '1') then -- valid random sample? |
if (processing.cnt = "1000") then |
processing.cnt <= (others => '0'); |
else |
rnd_cnt <= std_ulogic_vector(unsigned(rnd_cnt) + 1); |
processing.cnt <= std_ulogic_vector(unsigned(processing.cnt) + 1); |
end if; |
if (lfsr_en_c = true) then -- LFSR post-processing |
rnd_sreg <= rnd_sreg(rnd_sreg'left-1 downto 0) & (xnor_all_f(rnd_sreg and lfsr_taps_c) xnor rnd_data); |
processing.sreg <= processing.sreg(processing.sreg'left-1 downto 0) & (xnor_all_f(processing.sreg and lfsr_taps_c) xnor debiasing.data); |
else -- NO post-processing |
rnd_sreg <= rnd_sreg(rnd_sreg'left-1 downto 0) & rnd_data; |
processing.sreg <= processing.sreg(processing.sreg'left-1 downto 0) & debiasing.data; |
end if; |
end if; |
|
-- data output register -- |
if (rnd_cnt = "1000") then |
rnd_output <= rnd_sreg; |
if (processing.cnt = "1000") then |
processing.output <= processing.sreg; |
end if; |
|
-- health check error -- |
if (rnd_enable = '0') then |
rnd_error_zero <= '0'; |
rnd_error_one <= '0'; |
else |
rnd_error_zero <= rnd_error_zero or garo_err0; |
rnd_error_one <= rnd_error_one or garo_err1; |
-- data ready/valid flag -- |
if (processing.cnt = "1000") then -- new sample ready? |
processing.valid <= '1'; |
elsif (processing.enable = '0') or (rden = '1') then -- clear when deactivated or on data read |
processing.valid <= '0'; |
end if; |
|
-- data ready flag -- |
if (rnd_cnt = "1000") then -- new sample ready? |
rnd_ready <= '1'; |
elsif (rnd_enable = '0') or (rden = '1') then -- clear when deactivated or on data read |
rnd_ready <= '0'; |
end if; |
end if; |
end process processing_core; |
|
293,25 → 254,18
|
|
-- ################################################################################################# |
-- # << NEORV32 - True Random Number Generator (TRNG) - GARO Chain-Based Entropy Source >> # |
-- # << NEORV32 - True Random Number Generator (TRNG) - Ring-Oscillator-Based Entropy Source >> # |
-- # ********************************************************************************************* # |
-- # An inverter chain (ring oscillator) is used as entropy source. The inverter chain is # |
-- # constructed as GARO (Galois Ring Oscillator) TRNG, which is an "asynchronous" LFSR. The # |
-- # single inverters are connected via latches that are used to enbale/disable the TRNG. Also, # |
-- # these latches are used as additional delay element. By using unique enable signals for each # |
-- # latch, the synthesis tool cannot "optimize" (=remove) any of the inverters out of the design. # |
-- # Furthermore, the latches prevent the synthesis tool from detecting combinatorial loops. # |
-- # # |
-- # Sources: # |
-- # - GARO: "Experimental Assessment of FIRO- and GARO-based Noise Sources for Digital TRNG # |
-- # Designs on FPGAs" by Martin Schramm, Reiner Dojen and Michael Heigly, 2017 # |
-- # - Latches for platform independence: "Extended Abstract: The Butterfly PUF Protecting IP # |
-- # on every FPGA" by Sandeep S. Kumar, Jorge Guajardo, Roel Maesyz, Geert-Jan Schrijen and # |
-- # Pim Tuyls, Philips Research Europe, 2008 # |
-- # An inverter chain (ring oscillator) is used as entropy source. # |
-- # The inverter chain is constructed as an "asynchronous" LFSR. The single inverters are # |
-- # connected via latches that are used to enable/disable the TRNG. Also, these latches are used # |
-- # as additional delay element. By using unique enable signals for each latch, the synthesis # |
-- # tool cannot "optimize" (=remove) any of the inverters out of the design. Furthermore, the # |
-- # latches prevent the synthesis tool from detecting combinatorial loops. # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. # |
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
-- # # |
-- # Redistribution and use in source and binary forms, with or without modification, are # |
-- # permitted provided that the following conditions are met: # |
347,71 → 301,51
library neorv32; |
use neorv32.neorv32_package.all; |
|
entity neorv32_trng_garo_element is |
entity neorv32_trng_ring_osc is |
generic ( |
NUM_INV : natural := 15 -- number of inverters in chain |
); |
port ( |
clk_i : in std_ulogic; |
enable_i : in std_ulogic; |
enable_o : out std_ulogic; |
mask_i : in std_ulogic_vector(NUM_INV-2 downto 0); |
data_o : out std_ulogic; |
error0_o : out std_ulogic; |
error1_o : out std_ulogic |
enable_i : in std_ulogic; -- enable chain input |
enable_o : out std_ulogic; -- enable chain output |
data_o : out std_ulogic -- sync random bit |
); |
end neorv32_trng_garo_element; |
end neorv32_trng_ring_osc; |
|
architecture neorv32_trng_garo_element_rtl of neorv32_trng_garo_element is |
architecture neorv32_trng_ring_osc_rtl of neorv32_trng_ring_osc is |
|
-- debugging -- |
constant is_sim_c : boolean := false; |
|
signal inv_chain : std_ulogic_vector(NUM_INV-1 downto 0); -- oscillator chain |
signal enable_sreg : std_ulogic_vector(NUM_INV-1 downto 0); -- enable shift register |
signal sync_ff : std_ulogic_vector(2 downto 0); -- synchronizer |
signal sync_ff : std_ulogic_vector(1 downto 0); -- output signal synchronizer |
|
signal cnt_zero, cnt_one : std_ulogic_vector(5 downto 0); -- stuck-at-0/1 counters |
|
begin |
|
-- Sanity Check --------------------------------------------------------------------------- |
-- Sanity Checks -------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
assert ((NUM_INV mod 2) /= 0) report "NEORV32 TRNG.GARO_element: NUM_INV has to be odd." severity error; |
assert not ((NUM_INV mod 2) = 0) report "NEORV32 PROCESSOR CONFIG NOTE: TNRG.ring_oscillator - Number of inverters in ring has to be odd." severity error; |
|
|
-- Entropy Source ------------------------------------------------------------------------- |
-- Ring Oscillator ------------------------------------------------------------------------ |
-- ------------------------------------------------------------------------------------------- |
garo_chain: process(clk_i, enable_i, enable_sreg, mask_i, inv_chain) |
ring_osc: process(enable_i, enable_sreg, inv_chain) |
begin |
if (is_sim_c = false) then |
for i in 0 to NUM_INV-1 loop -- inverters in chain |
if (enable_i = '0') then -- start with a defined state (latch reset) |
inv_chain(i) <= '0'; |
-- Using individual enable signals for each inverter - derived from a shift register - to prevent the synthesis tool |
-- from removing all but one inverter (since they implement "logical identical functions"). |
-- This also allows to make the TRNG platform independent. |
elsif (enable_sreg(i) = '1') then |
-- here we have the inverter chain -- |
if (i = NUM_INV-1) then -- left-most inverter? |
inv_chain(i) <= not inv_chain(0); -- direct input of right most inverter (= output signal) |
else |
-- if tap switch is ON: use final output XORed with previous inverter's output |
-- if tap switch is OFF: just use previous inverter's output |
inv_chain(i) <= not (inv_chain(i+1) xor (inv_chain(0) and mask_i(i))); |
end if; |
end if; |
end loop; -- i |
else -- simulate as simple LFSR |
if rising_edge(clk_i) then |
if (enable_i = '0') then |
inv_chain <= (others => '0'); |
-- Using individual enable signals for each inverter - derived from a shift register - to prevent the synthesis tool |
-- from removing all but one inverter (since they implement "logical identical functions"). |
-- This also allows to make the TRNG platform independent. |
for i in 0 to NUM_INV-1 loop -- inverters in chain |
if (enable_i = '0') then -- start with a defined state (latch reset) |
inv_chain(i) <= '0'; |
elsif (enable_sreg(i) = '1') then |
-- here we have the inverter chain -- |
if (i = NUM_INV-1) then -- left-most inverter? |
inv_chain(i) <= not inv_chain(0); |
else |
inv_chain(NUM_INV-1 downto 0) <= inv_chain(inv_chain'left-1 downto 0) & xnor_all_f(inv_chain(NUM_INV-2 downto 0) and mask_i); |
inv_chain(i) <= not inv_chain(i+1); |
end if; |
end if; |
end if; |
end process garo_chain; |
end loop; -- i |
end process ring_osc; |
|
|
-- Control -------------------------------------------------------------------------------- |
420,7 → 354,7
begin |
if rising_edge(clk_i) then |
enable_sreg <= enable_sreg(enable_sreg'left-1 downto 0) & enable_i; -- activate right-most inverter first |
sync_ff <= sync_ff(sync_ff'left-1 downto 0) & inv_chain(0); -- synchronize to prevent metastability |
sync_ff <= sync_ff(0) & inv_chain(0); -- synchronize to prevent metastability |
end if; |
end process ctrl_unit; |
|
428,43 → 362,7
enable_o <= enable_sreg(enable_sreg'left); |
|
-- rnd output -- |
data_o <= sync_ff(sync_ff'left); |
data_o <= sync_ff(1); |
|
|
-- Health Check --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
health_check: process(clk_i) |
begin |
if rising_edge(clk_i) then |
if (enable_sreg(enable_sreg'left) = '0') then |
cnt_zero <= (others => '0'); |
cnt_one <= (others => '0'); |
else |
-- stuck-at-zero -- |
if (and_all_f(cnt_zero) = '0') then -- max not reached yet |
error0_o <= '0'; |
if (sync_ff(sync_ff'left) = '0') then |
cnt_zero <= std_ulogic_vector(unsigned(cnt_zero) + 1); |
else |
cnt_zero <= (others => '0'); |
end if; |
else |
error0_o <= '1'; |
end if; |
-- stuck-at-one -- |
if (and_all_f(cnt_one) = '0') then -- max not reached yet |
error1_o <= '0'; |
if (sync_ff(sync_ff'left) = '1') then |
cnt_one <= std_ulogic_vector(unsigned(cnt_one) + 1); |
else |
cnt_one <= (others => '0'); |
end if; |
else |
error1_o <= '1'; |
end if; |
end if; |
end if; |
end process health_check; |
|
|
end neorv32_trng_garo_element_rtl; |
end neorv32_trng_ring_osc_rtl; |
/rtl/core/neorv32_wdt.vhd
1,12 → 1,13
-- ################################################################################################# |
-- # << NEORV32 - Watch Dog Timer (WDT) >> # |
-- # ********************************************************************************************* # |
-- # The internal counter is 20 bit wide and increases using 1 out of 8 available clock # |
-- # prescalers. When the counter overflows, either a hardware reset (mode = 1) is performed or an # |
-- # interrupt (mode = 0) is triggered. The WDT can only operate when the enable bit is set. A # |
-- # write access to the WDT can only be performed, if the higher byte of the written data # |
-- # contains the specific WDT password (0x47). For a write access with a wrong password # |
-- # a HW reset or IRQ (depending on mode) is triggered, but only if the WDT is enabled. # |
-- # Watchdog counter to trigger an action if the CPU gets stuck. # |
-- # The internal counter is 20-bit wide. If this counter overflows one of two possible actions is # |
-- # triggered: Generate an IRQ or force a hardware reset of the system. # |
-- # A WDT action can also be triggered manually at any time by setting the FORCE bit. # |
-- # # |
-- # Access to the control register can be permanently locked by setting the lock bit. This bit # |
-- # can only be cleared by a hardware reset (external or caused by the watchdog itself). # |
-- # ********************************************************************************************* # |
-- # BSD 3-Clause License # |
-- # # |
72,136 → 73,152
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit |
constant lo_abb_c : natural := index_size_f(wdt_size_c); -- low address boundary bit |
|
-- Watchdog access password -- |
constant wdt_password_c : std_ulogic_vector(07 downto 0) := x"47"; |
|
-- Control register bits -- |
constant ctrl_clksel0_c : natural := 0; -- r/w: prescaler select bit 0 |
constant ctrl_clksel1_c : natural := 1; -- r/w: prescaler select bit 1 |
constant ctrl_clksel2_c : natural := 2; -- r/w: prescaler select bit 2 |
constant ctrl_enable_c : natural := 3; -- r/w: WDT enable |
constant ctrl_mode_c : natural := 4; -- r/w: 0: timeout causes interrupt, 1: timeout causes hard reset |
constant ctrl_cause_c : natural := 5; -- r/-: action (reset/IRQ) cause (0: external, 1: watchdog) |
constant ctrl_pwfail_c : natural := 6; -- r/-: watchdog action (reset/IRQ) caused by wrong password access when '1' |
constant ctrl_enable_c : natural := 0; -- r/w: WDT enable |
constant ctrl_clksel0_c : natural := 1; -- r/w: prescaler select bit 0 |
constant ctrl_clksel1_c : natural := 2; -- r/w: prescaler select bit 1 |
constant ctrl_clksel2_c : natural := 3; -- r/w: prescaler select bit 2 |
constant ctrl_mode_c : natural := 4; -- r/w: 0: WDT timeout triggers interrupt, 1: WDT timeout triggers hard reset |
constant ctrl_rcause_c : natural := 5; -- r/-: cause of last action (reset/IRQ): 0=external reset, 1=watchdog overflow |
constant ctrl_reset_c : natural := 6; -- -/w: reset WDT if set |
constant ctrl_force_c : natural := 7; -- -/w: force WDT action |
constant ctrl_lock_c : natural := 8; -- r/w: lock access to control register when set |
|
-- access control -- |
signal acc_en : std_ulogic; -- module access enable |
signal pwd_ok : std_ulogic; -- password correct |
signal fail, fail_ff : std_ulogic; -- unauthorized access |
signal wren : std_ulogic; |
signal acc_en : std_ulogic; -- module access enable |
signal wren : std_ulogic; |
signal rden : std_ulogic; |
|
-- accessible regs -- |
signal source : std_ulogic; -- source of wdt action: '0' = external, '1' = watchdog |
signal pw_fail : std_ulogic; -- watchdog action caused by wrong password access |
signal enable : std_ulogic; |
signal mode : std_ulogic; |
signal clk_sel : std_ulogic_vector(02 downto 0); |
-- control register -- |
type ctrl_reg_t is record |
enable : std_ulogic; -- 1=WDT enabled |
clk_sel : std_ulogic_vector(2 downto 0); |
mode : std_ulogic; -- 0=trigger IRQ on overflow; 1=trigger hard reset on overflow |
rcause : std_ulogic; -- cause of last system reset: '0' = external, '1' = watchdog |
reset : std_ulogic; -- reset WDT |
force : std_ulogic; -- force action |
lock : std_ulogic; -- lock control register |
end record; |
signal ctrl_reg : ctrl_reg_t; |
|
-- reset counter -- |
signal cnt : std_ulogic_vector(20 downto 0); |
signal rst_gen : std_ulogic_vector(03 downto 0); |
signal rst_sync : std_ulogic_vector(01 downto 0); |
|
-- prescaler clock generator -- |
signal prsc_tick : std_ulogic; |
|
-- WDT core -- |
signal wdt_cnt : std_ulogic_vector(20 downto 0); |
signal hw_rst : std_ulogic; |
signal rst_gen : std_ulogic_vector(03 downto 0); |
|
-- internal reset (sync, low-active) -- |
signal rstn_sync : std_ulogic; |
|
begin |
|
-- Access Control ------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0'; |
pwd_ok <= '1' when (data_i(15 downto 8) = wdt_password_c) else '0'; -- password check |
wren <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '1')) else '0'; -- write access ok |
fail <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '0')) else '0'; -- write access fail! |
wren <= acc_en and wren_i; |
rden <= acc_en and rden_i; |
|
|
-- Write Access, Reset Generator ---------------------------------------------------------- |
-- Write Access --------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
wdt_core: process(clk_i) |
write_access: process(rstn_i, clk_i) |
begin |
if rising_edge(clk_i) then |
if (rstn_i = '0') or (rst_sync(1) = '0') then -- external or internal reset |
enable <= '0'; -- disable WDT |
mode <= '0'; -- trigger interrupt if watchdog timeouts |
clk_sel <= (others => '1'); -- slowest clock rst_source |
rst_gen <= (others => '1'); -- do NOT fire on reset! |
if (rstn_i = '0') then |
ctrl_reg.reset <= '0'; |
ctrl_reg.force <= '0'; |
ctrl_reg.enable <= '0'; -- disable WDT |
ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow |
ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source |
ctrl_reg.lock <= '0'; |
elsif rising_edge(clk_i) then |
if (rstn_sync = '0') then -- internal reset |
ctrl_reg.reset <= '0'; |
ctrl_reg.force <= '0'; |
ctrl_reg.enable <= '0'; -- disable WDT |
ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow |
ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source |
ctrl_reg.lock <= '0'; |
else |
-- control register write access -- |
if (wren = '1') then -- allow write if password is correct |
enable <= data_i(ctrl_enable_c); |
clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c); |
mode <= data_i(ctrl_mode_c); |
-- auto-clear WDT reset and WDT force flags -- |
ctrl_reg.reset <= '0'; |
ctrl_reg.force <= '0'; |
-- actual write access -- |
if (wren = '1') then |
ctrl_reg.reset <= data_i(ctrl_reset_c); |
ctrl_reg.force <= data_i(ctrl_force_c); |
if (ctrl_reg.lock = '0') then -- update configuration only if unlocked |
ctrl_reg.enable <= data_i(ctrl_enable_c); |
ctrl_reg.mode <= data_i(ctrl_mode_c); |
ctrl_reg.clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c); |
ctrl_reg.lock <= data_i(ctrl_lock_c); |
end if; |
end if; |
-- trigger system reset when enabled AND reset mode AND timeout OR unauthorized access -- |
if (enable = '1') and (mode = '1') and ((cnt(cnt'left) = '1') or (fail_ff = '1')) then |
rst_gen <= (others => '0'); |
else |
rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1'; |
end if; |
end if; |
end if; |
end process wdt_core; |
end process write_access; |
|
-- enable external clock generator -- |
clkgen_en_o <= enable; |
-- clock generator -- |
clkgen_en_o <= ctrl_reg.enable; -- enable clock generator |
prsc_tick <= clkgen_i(to_integer(unsigned(ctrl_reg.clk_sel))); -- clock enable tick |
|
|
-- Counter Update ------------------------------------------------------------------------- |
-- Watchdog Counter ----------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
cnt_sync: process(clk_i) |
wdt_counter: process(clk_i) |
begin |
if rising_edge(clk_i) then |
-- clock_en buffer -- |
prsc_tick <= clkgen_i(to_integer(unsigned(clk_sel))); |
-- unauthorized access buffer -- |
fail_ff <= fail; |
-- reset synchronizer -- |
rst_sync <= rst_sync(0) & rst_gen(rst_gen'left); |
-- IRQ mode -- |
irq_o <= '0'; |
if (enable = '1') and (mode = '0') and ((cnt(cnt'left) = '1') or (fail_ff = '1')) then |
irq_o <= '1'; -- trigger interrupt if watchdog timeout and MODE=0 |
if (ctrl_reg.reset = '1') then -- watchdog reset |
wdt_cnt <= (others => '0'); |
elsif (ctrl_reg.enable = '1') and (prsc_tick = '1') then |
wdt_cnt <= std_ulogic_vector(unsigned(wdt_cnt) + 1); |
end if; |
-- counter update -- |
if (wren = '1') then -- clear counter on write access (manual watchdog reset) |
cnt <= (others => '0'); |
elsif (enable = '1') and (prsc_tick = '1') then |
cnt <= std_ulogic_vector(unsigned('0' & cnt(cnt'left-1 downto 0)) + 1); |
end if; |
end if; |
end process cnt_sync; |
end process wdt_counter; |
|
-- system reset -- |
rstn_o <= rst_sync(1); |
-- action trigger -- |
irq_o <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.force) and (not ctrl_reg.mode); -- mode 0: IRQ |
hw_rst <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.force) and ( ctrl_reg.mode); -- mode 1: RESET |
|
|
-- Reset Cause Indicator ------------------------------------------------------------------ |
-- Reset Generator & Action Cause Indicator ----------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
rst_cause: process(rstn_i, clk_i) |
reset_generator: process(rstn_i, clk_i) |
begin |
if (rstn_i = '0') then |
source <= '0'; |
pw_fail <= '0'; |
ctrl_reg.rcause <= '0'; |
rst_gen <= (others => '1'); -- do NOT fire on reset! |
rstn_sync <= '1'; |
elsif rising_edge(clk_i) then |
source <= source or (cnt(cnt'left) and enable) or (fail_ff and enable); -- set on WDT timeout or access error |
pw_fail <= (pw_fail or (fail_ff and enable)) and (not (cnt(cnt'left) and enable)); -- set on failed access, clear on WDT timeout |
ctrl_reg.rcause <= ctrl_reg.rcause or hw_rst; -- sticky-set on WDT timeout/force |
if (hw_rst = '1') then |
rst_gen <= (others => '0'); |
else |
rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1'; |
end if; |
rstn_sync <= rst_gen(rst_gen'left); |
end if; |
end process rst_cause; |
end process reset_generator; |
|
-- system reset -- |
rstn_o <= rst_gen(rst_gen'left); |
|
|
-- Read Access ---------------------------------------------------------------------------- |
-- ------------------------------------------------------------------------------------------- |
read_access: process(clk_i) |
begin |
if rising_edge(clk_i) then |
ack_o <= acc_en and (rden_i or wren_i); |
data_o <= (others => '0'); |
if (acc_en = '1') and (rden_i = '1') then |
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= clk_sel; |
data_o(ctrl_enable_c) <= enable; |
data_o(ctrl_cause_c) <= source; |
data_o(ctrl_pwfail_c) <= pw_fail; |
data_o(ctrl_mode_c) <= mode; |
ack_o <= rden or wren; |
if (rden = '1') then |
data_o(ctrl_enable_c) <= ctrl_reg.enable; |
data_o(ctrl_mode_c) <= ctrl_reg.mode; |
data_o(ctrl_rcause_c) <= ctrl_reg.rcause; |
data_o(ctrl_clksel2_c downto ctrl_clksel0_c) <= ctrl_reg.clk_sel; |
data_o(ctrl_lock_c) <= ctrl_reg.lock; |
else |
data_o <= (others => '0'); |
end if; |
end if; |
end process read_access; |
/rtl/top_templates/neorv32_test_setup.vhd
89,7 → 89,7
PMP_NUM_REGIONS => 2, -- number of regions (0..64) |
PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS => 2, -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS => 2, -- number of implemented HPM counters (0..29) |
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes |
113,8 → 113,8
IO_PWM_EN => false, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN => true, -- implement watch dog timer (WDT)? |
IO_TRNG_EN => false, -- implement true random number generator (TRNG)? |
IO_CFU0_EN => false, -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN => false -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN => false, -- implement custom functions subsystem (CFS)? |
IO_CFS_CONFIG => (others => '0') -- custom CFS configuration generic |
) |
port map ( |
-- Global control -- |
151,9 → 151,13
twi_scl_io => open, -- twi serial clock line |
-- PWM -- |
pwm_o => open, -- pwm channels |
-- Custom Functions Subsystem IO -- |
cfs_in_i => (others => '0'), -- custom inputs |
cfs_out_o => open, -- custom outputs |
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i => (others => '0'), -- current system time |
-- Interrupts -- |
soc_firq_i => (others => '0'), -- fast interrupt channels |
mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i => '0', -- machine software interrupt |
mext_irq_i => '0' -- machine external interrupt |
/rtl/top_templates/neorv32_top_axi4lite.vhd
64,7 → 64,7
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) |
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) |
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes |
86,8 → 86,8
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? |
IO_CFU0_EN : boolean := false; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN : boolean := false -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? |
IO_CFS_CONFIG : std_logic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic |
); |
port ( |
-- AXI Lite-Compatible Master Interface -- |
135,7 → 135,11
twi_scl_io : inout std_logic; -- twi serial clock line |
-- PWM -- |
pwm_o : out std_logic_vector(03 downto 0); -- pwm channels |
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i : in std_logic_vector(31 downto 0); -- custom inputs |
cfs_out_o : out std_logic_vector(31 downto 0); -- custom outputs |
-- Interrupts -- |
soc_firq_i : in std_logic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_logic := '0'; -- machine software interrupt |
mext_irq_i : in std_logic := '0' -- machine external interrupt |
145,8 → 149,9
architecture neorv32_top_axi4lite_rtl of neorv32_top_axi4lite is |
|
-- type conversion -- |
constant USER_CODE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(USER_CODE); |
constant HW_THREAD_ID_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(HW_THREAD_ID); |
constant USER_CODE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(USER_CODE); |
constant HW_THREAD_ID_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(HW_THREAD_ID); |
constant IO_CFS_CONFIG_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(IO_CFS_CONFIG); |
-- |
signal clk_i_int : std_ulogic; |
signal rstn_i_int : std_ulogic; |
164,6 → 169,10
-- |
signal pwm_o_int : std_ulogic_vector(03 downto 0); |
-- |
signal cfs_in_i_int : std_ulogic_vector(31 downto 0); |
signal cfs_out_o_int : std_ulogic_vector(31 downto 0); |
-- |
signal soc_firq_i_int : std_ulogic_vector(3 downto 0); |
signal mtime_irq_i_int : std_ulogic; |
signal msw_irq_i_int : std_ulogic; |
signal mext_irq_i_int : std_ulogic; |
227,7 → 236,7
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) |
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) |
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
251,8 → 260,8
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? |
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? |
IO_CFU0_EN => IO_CFU0_EN, -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN => IO_CFU1_EN -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? |
IO_CFS_CONFIG => IO_CFS_CONFIG_INT -- custom CFS configuration generic |
) |
port map ( |
-- Global control -- |
289,9 → 298,13
twi_scl_io => twi_scl_io, -- twi serial clock line |
-- PWM -- |
pwm_o => pwm_o_int, -- pwm channels |
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i => cfs_in_i_int, -- custom inputs |
cfs_out_o => cfs_out_o_int, -- custom outputs |
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i => (others => '0'), -- current system time |
-- Interrupts -- |
soc_firq_i => soc_firq_i_int, -- fast interrupt channels |
mtime_irq_i => mtime_irq_i_int, -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i => msw_irq_i_int, -- machine software interrupt |
mext_irq_i => mext_irq_i_int -- machine external interrupt |
311,6 → 324,10
|
pwm_o <= std_logic_vector(pwm_o_int); |
|
cfs_in_i_int <= std_ulogic_vector(cfs_in_i); |
cfs_out_o <= std_logic_vector(cfs_out_o_int); |
|
soc_firq_i_int <= std_ulogic_vector(soc_firq_i); |
msw_irq_i_int <= std_ulogic(msw_irq_i); |
mext_irq_i_int <= std_ulogic(mext_irq_i); |
|
/rtl/top_templates/neorv32_top_stdlogic.vhd
62,7 → 62,7
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64) |
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS : natural := 0; -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) |
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes |
86,8 → 86,8
IO_PWM_EN : boolean := true; -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? |
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? |
IO_CFU0_EN : boolean := false; -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN : boolean := false -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? |
IO_CFS_CONFIG : std_logic_vector(31 downto 0) := (others => '0') -- custom CFS configuration generic |
); |
port ( |
-- Global control -- |
124,9 → 124,13
twi_scl_io : inout std_logic; -- twi serial clock line |
-- PWM (available if IO_PWM_EN = true) -- |
pwm_o : out std_logic_vector(03 downto 0); -- pwm channels |
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i : in std_logic_vector(31 downto 0); -- custom inputs |
cfs_out_o : out std_logic_vector(31 downto 0); -- custom outputs |
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i : in std_logic_vector(63 downto 0) := (others => '0'); -- current system time |
-- Interrupts -- |
soc_firq_i : in std_logic_vector(3 downto 0) := (others => '0'); -- fast interrupt channels |
mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i : in std_logic := '0'; -- machine software interrupt |
mext_irq_i : in std_logic := '0' -- machine external interrupt |
136,8 → 140,9
architecture neorv32_top_stdlogic_rtl of neorv32_top_stdlogic is |
|
-- type conversion -- |
constant USER_CODE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(USER_CODE); |
constant HW_THREAD_ID_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(HW_THREAD_ID); |
constant USER_CODE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(USER_CODE); |
constant HW_THREAD_ID_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(HW_THREAD_ID); |
constant IO_CFS_CONFIG_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(IO_CFS_CONFIG); |
-- |
signal clk_i_int : std_ulogic; |
signal rstn_i_int : std_ulogic; |
170,8 → 175,12
-- |
signal pwm_o_int : std_ulogic_vector(03 downto 0); |
-- |
signal cfs_in_i_int : std_ulogic_vector(31 downto 0); |
signal cfs_out_o_int : std_ulogic_vector(31 downto 0); |
-- |
signal mtime_i_int : std_ulogic_vector(63 downto 0); |
-- |
signal soc_firq_i_int : std_ulogic_vector(3 downto 0); |
signal mtime_irq_i_int : std_ulogic; |
signal msw_irq_i_int : std_ulogic; |
signal mext_irq_i_int : std_ulogic; |
203,7 → 212,7
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64) |
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of inmplemnted HPM counters (0..29) |
HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) |
-- Internal Instruction memory -- |
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory |
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes |
227,8 → 236,8
IO_PWM_EN => IO_PWM_EN, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? |
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? |
IO_CFU0_EN => IO_CFU0_EN, -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN => IO_CFU1_EN -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? |
IO_CFS_CONFIG => IO_CFS_CONFIG_INT -- custom CFS configuration generic |
) |
port map ( |
-- Global control -- |
265,9 → 274,13
twi_scl_io => twi_scl_io, -- twi serial clock line |
-- PWM -- |
pwm_o => pwm_o_int, -- pwm channels |
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- |
cfs_in_i => cfs_in_i_int, -- custom inputs |
cfs_out_o => cfs_out_o_int, -- custom outputs |
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i => mtime_i_int, -- current system time |
-- Interrupts -- |
soc_firq_i => soc_firq_i_int, -- fast interrupt channels |
mtime_irq_i => mtime_irq_i_int, -- machine timer interrupt, available if IO_MTIME_EN = false |
msw_irq_i => msw_irq_i_int, -- machine software interrupt |
mext_irq_i => mext_irq_i_int -- machine external interrupt |
305,8 → 318,12
|
pwm_o <= std_logic_vector(pwm_o_int); |
|
cfs_in_i_int <= std_ulogic_vector(cfs_in_i); |
cfs_out_o <= std_logic_vector(cfs_out_o_int); |
|
mtime_i_int <= std_ulogic_vector(mtime_i); |
|
soc_firq_i_int <= std_ulogic_vector(soc_firq_i); |
msw_irq_i_int <= std_ulogic(msw_irq_i); |
mext_irq_i_int <= std_ulogic(mext_irq_i); |
|
/sim/ghdl/ghdl_sim.sh
42,8 → 42,7
ghdl -a --work=neorv32 $srcdir_core/neorv32_boot_rom.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_busswitch.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_icache.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfu0.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfu1.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cfs.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_alu.vhd |
ghdl -a --work=neorv32 $srcdir_core/neorv32_cpu_bus.vhd |
/sim/neorv32_tb.vhd
73,9 → 73,8
constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area) |
constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes |
constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay |
-- machine interrupt triggers -- |
constant msi_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000000"; -- machine software interrupt |
constant mei_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000004"; -- machine external interrupt |
-- simulation interrupt trigger -- |
constant irq_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000000"; |
-- ------------------------------------------------------------------------------------------- |
|
-- internals - hands off! -- |
109,6 → 108,7
|
-- irq -- |
signal msi_ring, mei_ring : std_ulogic; |
signal soc_firq_ring : std_ulogic_vector(3 downto 0); |
|
-- Wishbone bus -- |
type wishbone_t is record |
124,7 → 124,7
tag : std_ulogic_vector(2 downto 0); -- tag |
lock : std_ulogic; -- locked/exclusive bus access |
end record; |
signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_msi, wb_mei : wishbone_t; |
signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t; |
|
-- Wishbone memories -- |
type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0); |
190,7 → 190,7
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier |
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations |
-- Physical Memory Protection (PMP) -- |
PMP_NUM_REGIONS => 5, -- number of regions (0..64) |
PMP_NUM_REGIONS => 4, -- number of regions (0..64) |
PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes |
-- Hardware Performance Monitors (HPM) -- |
HPM_NUM_CNTS => 12, -- number of inmplemnted HPM counters (0..29) |
217,8 → 217,8
IO_PWM_EN => true, -- implement pulse-width modulation unit (PWM)? |
IO_WDT_EN => true, -- implement watch dog timer (WDT)? |
IO_TRNG_EN => false, -- trng cannot be simulated |
IO_CFU0_EN => true, -- implement custom functions unit 0 (CFU0)? |
IO_CFU1_EN => true -- implement custom functions unit 1 (CFU1)? |
IO_CFS_EN => true, -- implement custom functions subsystem (CFS)? |
IO_CFS_CONFIG => (others => '0') -- custom CFS configuration generic |
) |
port map ( |
-- Global control -- |
255,9 → 255,13
twi_scl_io => twi_scl, -- twi serial clock line |
-- PWM -- |
pwm_o => open, -- pwm channels |
-- Custom Functions Subsystem IO -- |
cfs_in_i => (others => '0'), -- custom CFS inputs |
cfs_out_o => open, -- custom CFS outputs |
-- system time input from external MTIME (available if IO_MTIME_EN = false) -- |
mtime_i => (others => '0'), -- current system time |
-- Interrupts -- |
soc_firq_i => soc_firq_ring, -- fast interrupt channels |
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false |
msw_irq_i => msi_ring, -- machine software interrupt |
mext_irq_i => mei_ring -- machine external interrupt |
347,33 → 351,24
wb_mem_c.cyc <= wb_cpu.cyc; |
wb_mem_c.lock <= wb_cpu.lock; |
|
wb_msi.addr <= wb_cpu.addr; |
wb_msi.wdata <= wb_cpu.wdata; |
wb_msi.we <= wb_cpu.we; |
wb_msi.sel <= wb_cpu.sel; |
wb_msi.tag <= wb_cpu.tag; |
wb_msi.cyc <= wb_cpu.cyc; |
wb_msi.lock <= wb_cpu.lock; |
wb_irq.addr <= wb_cpu.addr; |
wb_irq.wdata <= wb_cpu.wdata; |
wb_irq.we <= wb_cpu.we; |
wb_irq.sel <= wb_cpu.sel; |
wb_irq.tag <= wb_cpu.tag; |
wb_irq.cyc <= wb_cpu.cyc; |
wb_irq.lock <= wb_cpu.lock; |
|
wb_mei.addr <= wb_cpu.addr; |
wb_mei.wdata <= wb_cpu.wdata; |
wb_mei.we <= wb_cpu.we; |
wb_mei.sel <= wb_cpu.sel; |
wb_mei.tag <= wb_cpu.tag; |
wb_mei.cyc <= wb_cpu.cyc; |
wb_mei.lock <= wb_cpu.lock; |
|
-- CPU read-back signals (no mux here since peripherals have "output gates") -- |
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_mei.rdata or wb_msi.rdata; |
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_mei.ack or wb_msi.ack; |
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_mei.err or wb_msi.err; |
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata; |
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack; |
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err; |
|
-- peripheral select via STROBE signal -- |
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0'; |
wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0'; |
wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0'; |
wb_msi.stb <= wb_cpu.stb when (wb_cpu.addr = msi_trigger_c) else '0'; |
wb_mei.stb <= wb_cpu.stb when (wb_cpu.addr = mei_trigger_c) else '0'; |
wb_irq.stb <= wb_cpu.stb when (wb_cpu.addr = irq_trigger_c) else '0'; |
|
|
-- Wishbone Memory A (simulated external IMEM) -------------------------------------------- |
503,27 → 498,22
irq_trigger: process(clk_gen) |
begin |
if rising_edge(clk_gen) then |
-- default -- |
msi_ring <= '0'; |
wb_msi.rdata <= (others => '0'); |
wb_msi.ack <= '0'; |
wb_msi.err <= '0'; |
mei_ring <= '0'; |
wb_mei.rdata <= (others => '0'); |
wb_mei.ack <= '0'; |
wb_mei.err <= '0'; |
|
-- machine software interrupt -- |
if ((wb_msi.cyc and wb_msi.stb and wb_msi.we) = '1') then |
msi_ring <= '1'; |
wb_msi.ack <= '1'; |
-- bus interface -- |
wb_irq.rdata <= (others => '0'); |
wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we; |
wb_irq.err <= '0'; |
-- trigger IRQ using CSR.MIE bit layout -- |
msi_ring <= '0'; |
mei_ring <= '0'; |
soc_firq_ring <= (others => '0'); |
if ((wb_irq.cyc and wb_irq.stb and wb_irq.we) = '1') then |
msi_ring <= wb_irq.wdata(03); -- machine software interrupt |
mei_ring <= wb_irq.wdata(11); -- machine software interrupt |
soc_firq_ring(0) <= wb_irq.wdata(20); -- fast interrupt channel 4 |
soc_firq_ring(1) <= wb_irq.wdata(21); -- fast interrupt channel 5 |
soc_firq_ring(2) <= wb_irq.wdata(22); -- fast interrupt channel 6 |
soc_firq_ring(3) <= wb_irq.wdata(22); -- fast interrupt channel 7 |
end if; |
|
-- machine external interrupt -- |
if ((wb_mei.cyc and wb_mei.stb and wb_mei.we) = '1') then |
mei_ring <= '1'; |
wb_mei.ack <= '1'; |
end if; |
end if; |
end process irq_trigger; |
|
/sw/bootloader/bootloader.c
153,9 → 153,15
* This global variable keeps the size of the available executable in bytes. |
* If =0 no executable is available (yet). |
**************************************************************************/ |
uint32_t exe_available = 0; |
volatile uint32_t exe_available = 0; |
|
|
/**********************************************************************//** |
* Only set during executable fetch (required for cpaturing STORE-BUS-TIMOUT exception). |
**************************************************************************/ |
volatile uint32_t getting_exe = 0; |
|
|
// Function prototypes |
void __attribute__((__interrupt__)) bootloader_trap_handler(void); |
void fast_upload(int src); |
187,19 → 193,10
#warning In order to allow the bootloader to run on any CPU configuration it should be compiled using the base ISA (rv32i/e) only. |
#endif |
|
// global variable for executable size; 0 means there is no exe available |
exe_available = 0; |
exe_available = 0; // global variable for executable size; 0 means there is no exe available |
getting_exe = 0; // we are not trying to get an executable yet |
|
// ------------------------------------------------ |
// Minimal CPU hardware initialization |
// - all IO devices are reset and disabled by the crt0 code |
// ------------------------------------------------ |
|
// confiure trap handler (bare-metal, no neorv32 rte available) |
neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&bootloader_trap_handler)); |
|
|
// ------------------------------------------------ |
// Minimal processor hardware initialization |
// - all IO devices are reset and disabled by the crt0 code |
// ------------------------------------------------ |
226,6 → 223,10
// Configure machine system timer interrupt for ~2Hz |
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (clock_speed/4)); |
|
// confiure trap handler (bare-metal, no neorv32 rte available) |
neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&bootloader_trap_handler)); |
|
// active timer IRQ |
neorv32_cpu_csr_write(CSR_MIE, 1 << CSR_MIE_MTIE); // activate MTIME IRQ source |
neorv32_cpu_eint(); // enable global interrupts |
|
405,12 → 406,13
|
/**********************************************************************//** |
* Bootloader trap handler. Used for the MTIME tick and to capture any other traps. |
* @warning Since we have no runtime environment, we have to use the interrupt attribute here. Here, and only here! |
* @warning Since we have no runtime environment, we have to use the interrupt attribute here. Here and only here! |
**************************************************************************/ |
void __attribute__((__interrupt__)) bootloader_trap_handler(void) { |
|
uint32_t cause = neorv32_cpu_csr_read(CSR_MCAUSE); |
|
// make sure this was caused by MTIME IRQ |
uint32_t cause = neorv32_cpu_csr_read(CSR_MCAUSE); |
if (cause == TRAP_CODE_MTI) { // raw exception code for MTI |
if (STATUS_LED_EN == 1) { |
// toggle status LED |
419,17 → 421,20
// set time for next IRQ |
neorv32_mtime_set_timecmp(neorv32_mtime_get_time() + (SYSINFO_CLK/4)); |
} |
|
else if (cause == TRAP_CODE_S_ACCESS) { // seems like executable is too large |
system_error(ERROR_SIZE); |
} |
|
else { |
neorv32_uart_print("\n\nEXC ("); |
print_hex_word(cause); |
neorv32_uart_print(") @ 0x"); |
print_hex_word(neorv32_cpu_csr_read(CSR_MEPC)); |
system_error(ERROR_SYSTEM); |
// store bus access error during get_exe |
// -> seems like executable is too large |
if ((cause == TRAP_CODE_S_ACCESS) && (getting_exe)) { |
system_error(ERROR_SIZE); |
} |
// unknown error |
else { |
neorv32_uart_print("\n\nEXC ("); |
print_hex_word(cause); |
neorv32_uart_print(") @ 0x"); |
print_hex_word(neorv32_cpu_csr_read(CSR_MEPC)); |
system_error(ERROR_SYSTEM); |
} |
} |
} |
|
441,6 → 446,8
**************************************************************************/ |
void get_exe(int src) { |
|
getting_exe = 1; // to inform trap handler we were trying to get an executable |
|
// is MEM implemented and read-only? |
if ((SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM)) && |
(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM))) { |
493,6 → 500,8
neorv32_uart_print("OK"); |
exe_available = size; // store exe size |
} |
|
getting_exe = 0; // to inform trap handler we are done getting an executable |
} |
|
|
/sw/common/crt0.S
39,7 → 39,7
|
|
// IO region |
.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region |
.equ IO_BEGIN, 0xFFFFFF00 // start of processor-internal IO region |
|
|
_start: |
/sw/example/bit_manipulation/main.c
1,5 → 1,5
// ################################################################################################# |
// # << NEORV32 - Bit manipulation 'B.Zbb' test program >> # |
// # << NEORV32 - RISC-V Bit Manipulation 'B.Zbb' Extension Test Program >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
55,7 → 55,7
|
// Prototypes |
uint32_t xorshift32(void); |
uint32_t check_result(uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res); |
uint32_t check_result(uint32_t num, uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res); |
void print_report(int num_err, int num_tests); |
|
|
69,8 → 69,8
int main() { |
|
uint32_t opa = 0, opb = 0, res_hw = 0, res_sw = 0; |
int i = 0, err_cnt = 0; |
const int num_tests = (int)NUM_TEST_CASES; |
uint32_t i = 0, err_cnt = 0; |
const uint32_t num_tests = (int)NUM_TEST_CASES; |
|
// capture all exceptions and give debug info via UART |
neorv32_rte_setup(); |
94,7 → 94,7
opa = xorshift32(); |
res_sw = riscv_emulate_clz(opa); |
res_hw = riscv_intrinsic_clz(opa); |
err_cnt += check_result(opa, 0, res_sw, res_hw); |
err_cnt += check_result(i, opa, 0, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
105,7 → 105,7
opa = xorshift32(); |
res_sw = riscv_emulate_ctz(opa); |
res_hw = riscv_intrinsic_ctz(opa); |
err_cnt += check_result(opa, 0, res_sw, res_hw); |
err_cnt += check_result(i, opa, 0, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
116,7 → 116,7
opa = xorshift32(); |
res_sw = riscv_emulate_cpop(opa); |
res_hw = riscv_intrinsic_cpop(opa); |
err_cnt += check_result(opa, 0, res_sw, res_hw); |
err_cnt += check_result(i, opa, 0, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
127,7 → 127,7
opa = xorshift32(); |
res_sw = riscv_emulate_sextb(opa); |
res_hw = riscv_intrinsic_sextb(opa); |
err_cnt += check_result(opa, 0, res_sw, res_hw); |
err_cnt += check_result(i, opa, 0, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
138,7 → 138,7
opa = xorshift32(); |
res_sw = riscv_emulate_sexth(opa); |
res_hw = riscv_intrinsic_sexth(opa); |
err_cnt += check_result(opa, 0, res_sw, res_hw); |
err_cnt += check_result(i, opa, 0, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
150,7 → 150,7
opb = xorshift32(); |
res_sw = riscv_emulate_min(opa, opb); |
res_hw = riscv_intrinsic_min(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
162,7 → 162,7
opb = xorshift32(); |
res_sw = riscv_emulate_minu(opa, opb); |
res_hw = riscv_intrinsic_minu(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
174,7 → 174,7
opb = xorshift32(); |
res_sw = riscv_emulate_max(opa, opb); |
res_hw = riscv_intrinsic_max(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
186,7 → 186,7
opb = xorshift32(); |
res_sw = riscv_emulate_maxu(opa, opb); |
res_hw = riscv_intrinsic_maxu(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
198,7 → 198,7
opb = xorshift32(); |
res_sw = riscv_emulate_pack(opa, opb); |
res_hw = riscv_intrinsic_pack(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
210,7 → 210,7
opb = xorshift32(); |
res_sw = riscv_emulate_andn(opa, opb); |
res_hw = riscv_intrinsic_andn(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
222,7 → 222,7
opb = xorshift32(); |
res_sw = riscv_emulate_orn(opa, opb); |
res_hw = riscv_intrinsic_orn(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
234,7 → 234,7
opb = xorshift32(); |
res_sw = riscv_emulate_xnor(opa, opb); |
res_hw = riscv_intrinsic_xnor(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
246,7 → 246,7
opb = xorshift32(); |
res_sw = riscv_emulate_rol(opa, opb); |
res_hw = riscv_intrinsic_rol(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
258,7 → 258,7
opb = xorshift32(); |
res_sw = riscv_emulate_ror(opa, opb); |
res_hw = riscv_intrinsic_ror(opa, opb); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
269,7 → 269,7
opa = xorshift32(); |
res_sw = riscv_emulate_ror(opa, 20); |
res_hw = riscv_intrinsic_rori20(opa); |
err_cnt += check_result(opa, opb, res_sw, res_hw); |
err_cnt += check_result(i, opa, opb, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
280,7 → 280,7
opa = xorshift32(); |
res_sw = riscv_emulate_orcb(opa); |
res_hw = riscv_intrinsic_orcb(opa); |
err_cnt += check_result(opa, 0, res_sw, res_hw); |
err_cnt += check_result(i, opa, 0, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
291,7 → 291,7
opa = xorshift32(); |
res_sw = riscv_emulate_rev8(opa); |
res_hw = riscv_intrinsic_rev8(opa); |
err_cnt += check_result(opa, 0, res_sw, res_hw); |
err_cnt += check_result(i, opa, 0, res_sw, res_hw); |
} |
print_report(err_cnt, num_tests); |
|
322,6 → 322,7
/**********************************************************************//** |
* Check results (reference (SW) vs actual hardware). |
* |
* @param[in] num Test case number |
* @param[in] opa Operand 1 |
* @param[in] opb Operand 2 |
* @param[in] ref Software reference |
328,10 → 329,10
* @param[in] res Actual results |
* @return zero if results are equal. |
**************************************************************************/ |
uint32_t check_result(uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res) { |
uint32_t check_result(uint32_t num, uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res) { |
|
if (ref != res) { |
neorv32_uart_printf("opa = 0x%x, opb = 0x%x : ref = 0x%x vs res = 0x%x ", opa, opb, ref, res); |
neorv32_uart_printf("%u: opa = 0x%x, opb = 0x%x : ref = 0x%x vs res = 0x%x ", num, opa, opb, ref, res); |
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27); |
return 1; |
} |
/sw/example/cpu_test/main.c
36,7 → 36,7
/**********************************************************************//** |
* @file cpu_test/main.c |
* @author Stephan Nolting |
* @brief Simple CPU test program. |
* @brief CPU/Processor test program. |
**************************************************************************/ |
|
#include <neorv32.h> |
51,8 → 51,8
#define BAUD_RATE 19200 |
//** Reachable unaligned address */ |
#define ADDR_UNALIGNED 0x00000002 |
//** Unreachable aligned address */ |
#define ADDR_UNREACHABLE 0xFFFFFF00 |
//** Unreachable word-aligned address */ |
#define ADDR_UNREACHABLE (IO_BASE_ADDRESS-4) |
//* external memory base address */ |
#define EXT_MEM_BASE 0xF0000000 |
/**@}*/ |
59,8 → 59,7
|
|
// Prototypes |
void sim_trigger_msi(void); |
void sim_trigger_mei(void); |
void sim_irq_trigger(uint32_t sel); |
void global_trap_handler(void); |
void test_ok(void); |
void test_fail(void); |
96,24 → 95,6
|
|
/**********************************************************************//** |
* Simulation-based function to trigger CPU MSI (machine software interrupt). |
**************************************************************************/ |
void sim_trigger_msi(void) { |
|
*(IO_REG32 (0xFF000000)) = 1; |
} |
|
|
/**********************************************************************//** |
* Simulation-based function to trigger CPU MEI (machine external interrupt). |
**************************************************************************/ |
void sim_trigger_mei(void) { |
|
*(IO_REG32 (0xFF000004)) = 1; |
} |
|
|
/**********************************************************************//** |
* This program uses mostly synthetic case to trigger all implemented exceptions. |
* Each exception is captured and evaluated for correct detection. |
* |
140,7 → 121,7
return 0; |
#endif |
|
neorv32_uart_printf("\n<< PROCESSOR/CPU TEST >>\n"); |
neorv32_uart_printf("\n<< CPU/PROCESSOR TEST >>\n"); |
neorv32_uart_printf("build: "__DATE__" "__TIME__"\n"); |
|
// check if we came from hardware reset |
149,7 → 130,7
neorv32_uart_printf("yes\n"); |
} |
else { |
neorv32_uart_printf("unknown (mcause != TRAP_CODE_RESET)\n"); |
neorv32_uart_printf("unknown\n"); |
} |
|
// check available hardware extensions and compare with compiler flags |
208,20 → 189,28
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_1, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_2, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_3, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_4, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_5, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_6, global_trap_handler); |
install_err += neorv32_rte_exception_install(RTE_TRAP_FIRQ_7, global_trap_handler); |
|
if (install_err) { |
neorv32_uart_printf("RTE error (%i)!\n", install_err); |
neorv32_uart_printf("RTE install error (%i)!\n", install_err); |
return 0; |
} |
|
// enable interrupt sources |
install_err = neorv32_cpu_irq_enable(CSR_MIE_MSIE); // activate software interrupt |
install_err += neorv32_cpu_irq_enable(CSR_MIE_MTIE); // activate timer interrupt |
install_err += neorv32_cpu_irq_enable(CSR_MIE_MEIE); // activate external interrupt |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ0E); // activate fast interrupt channel 0 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ1E); // activate fast interrupt channel 1 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ2E); // activate fast interrupt channel 2 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E); // activate fast interrupt channel 3 |
install_err = neorv32_cpu_irq_enable(CSR_MIE_MSIE); // machine software interrupt |
install_err += neorv32_cpu_irq_enable(CSR_MIE_MTIE); // machine timer interrupt |
install_err += neorv32_cpu_irq_enable(CSR_MIE_MEIE); // machine external interrupt |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ0E); // fast interrupt channel 0 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ1E); // fast interrupt channel 1 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ2E); // fast interrupt channel 2 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ3E); // fast interrupt channel 3 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ4E); // fast interrupt channel 4 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ5E); // fast interrupt channel 5 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ6E); // fast interrupt channel 6 |
install_err += neorv32_cpu_irq_enable(CSR_MIE_FIRQ7E); // fast interrupt channel 7 |
|
if (install_err) { |
neorv32_uart_printf("IRQ enable error (%i)!\n", install_err); |
472,7 → 461,7
|
|
// ---------------------------------------------------------- |
// Test FENCE.I instruction (clear & reload i-cache) |
// Test FENCE.I instruction (instruction buffer / i-cache clear & reload) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Testing FENCE.I operation: ", cnt_test); |
662,7 → 651,7
} |
} |
else { |
neorv32_uart_printf("skipped (not possible when C extension is enabled)\n"); |
neorv32_uart_printf("skipped (n.a. with C-ext)\n"); |
} |
|
|
738,7 → 727,7
} |
} |
else { |
neorv32_uart_printf("skipped (not possible when C-EXT disabled)\n"); |
neorv32_uart_printf("skipped (n.a. with C-ext)\n"); |
} |
|
|
874,7 → 863,7
|
} |
else { |
neorv32_uart_printf("skipped (not possible when U-EXT disabled)\n"); |
neorv32_uart_printf("skipped (n.a. without U-ext)\n"); |
} |
|
|
919,7 → 908,7
cnt_test++; |
|
// trigger IRQ |
sim_trigger_msi(); |
sim_irq_trigger(1 << CSR_MIE_MSIE); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
947,7 → 936,7
cnt_test++; |
|
// trigger IRQ |
sim_trigger_mei(); |
sim_irq_trigger(1 << CSR_MIE_MEIE); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
969,14 → 958,14
// Fast interrupt channel 0 (WDT) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ0 (fast IRQ0) interrupt test (via WDT): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ0 (fast interrupt 0) test (via WDT): ", cnt_test); |
|
if (neorv32_wdt_available()) { |
cnt_test++; |
|
// configure WDT |
neorv32_wdt_setup(CLK_PRSC_2, 0); // lowest clock prescaler, trigger IRQ on timeout |
neorv32_wdt_reset(); // reset watchdog |
neorv32_wdt_setup(CLK_PRSC_4096, 0, 1); // highest clock prescaler, trigger IRQ on timeout, lock access |
WDT_CT = 0; // try to deactivate WDT (should fail as access is loced) |
neorv32_wdt_force(); // force watchdog into action |
|
// wait some time for the IRQ to arrive the CPU |
1002,7 → 991,7
// Fast interrupt channel 1 (GPIO) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ1 (fast IRQ1) interrupt test (via GPIO): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ1 (fast interrupt 1) test (via GPIO): ", cnt_test); |
|
if (UART_CT & (1 << UART_CT_SIM_MODE)) { // check if this is a simulation |
if (neorv32_gpio_available()) { |
1048,7 → 1037,7
// Fast interrupt channel 2 (UART) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ2 (fast IRQ2) interrupt test (via UART): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ2 (fast interrupt 2) test (via UART): ", cnt_test); |
|
if (neorv32_uart_available()) { |
cnt_test++; |
1098,7 → 1087,7
// Fast interrupt channel 3 (SPI) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ3 (fast IRQ3) interrupt test (via SPI): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ3 (fast interrupt 3) test (via SPI): ", cnt_test); |
|
if (neorv32_spi_available()) { |
cnt_test++; |
1133,7 → 1122,7
// Fast interrupt channel 3 (TWI) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ3 (fast IRQ3) interrupt test (via TWI): ", cnt_test); |
neorv32_uart_printf("[%i] FIRQ3 (fast interrupt 3) test (via TWI): ", cnt_test); |
|
if (neorv32_twi_available()) { |
cnt_test++; |
1166,6 → 1155,42
|
|
// ---------------------------------------------------------- |
// Fast interrupt channel 4..7 (SoC fast IRQ) |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] FIRQ4..7 (SoC fast interrupt 0..3, via testbench) test: ", cnt_test); |
|
cnt_test++; |
|
// trigger all SoC Fast interrupts at once |
neorv32_cpu_dint(); // do not fire yet! |
sim_irq_trigger((1 << CSR_MIE_FIRQ4E) | (1 << CSR_MIE_FIRQ5E) | (1 << CSR_MIE_FIRQ6E) | (1 << CSR_MIE_FIRQ7E)); |
|
// wait some time for the IRQ to arrive the CPU |
asm volatile("nop"); |
asm volatile("nop"); |
|
// make sure all SoC FIRQs have been triggered |
tmp_a = (1 << CSR_MIP_FIRQ4P) | (1 << CSR_MIP_FIRQ5P) | (1 << CSR_MIP_FIRQ6P) | (1 << CSR_MIP_FIRQ7P); |
if (neorv32_cpu_csr_read(CSR_MIP) == tmp_a) { |
neorv32_cpu_eint(); // allow IRQs to fire again |
asm volatile ("nop"); |
asm volatile ("nop"); // irq should kick in HERE |
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_7) { // make sure FIRQ7 was last IRQ to be handled |
test_ok(); |
} |
else { |
test_fail(); |
} |
} |
else { |
test_fail(); |
} |
|
neorv32_cpu_eint(); // re-enable IRQs globally |
|
|
// ---------------------------------------------------------- |
// Test WFI ("sleep") instructions, wakeup via MTIME |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
1227,7 → 1252,7
|
} |
else { |
neorv32_uart_printf("skipped (not possible when U-EXT disabled)\n"); |
neorv32_uart_printf("skipped (n.a. without U-ext)\n"); |
} |
|
|
1480,56 → 1505,25
|
|
// ---------------------------------------------------------- |
// Test AMO atomic operation - should raise illegal instruction exception |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCAUSE, 0); |
neorv32_uart_printf("[%i] Atomic AMOSWAP test (should raise illegal CMD exception): ", cnt_test); |
|
#ifdef __riscv_atomic |
// skip if A-mode is not implemented |
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_A_EXT)) != 0) { |
|
cnt_test++; |
|
// AMO operations are not implemented! |
// this should cause an illegal instruction exception |
asm volatile ("amoswap.w x0, x0, (x0)"); |
|
// atomic compare-and-swap |
if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_I_ILLEGAL) { |
test_ok(); |
} |
else { |
test_fail(); |
} |
} |
else { |
neorv32_uart_printf("skipped (not implemented)\n"); |
} |
#else |
neorv32_uart_printf("skipped (not implemented)\n"); |
#endif |
|
|
// ---------------------------------------------------------- |
// HPM reports |
// ---------------------------------------------------------- |
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, -1); // stop all counters |
neorv32_uart_printf("\n\n-- HPM reports (%u HPMs available) --\n", num_hpm_cnts_global); |
neorv32_uart_printf("#IR - Total number of instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = HPM_0 |
neorv32_uart_printf("#CY - Total number of clock cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = HPM_2 |
neorv32_uart_printf("#03 - Retired compr. instructions: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3)); |
neorv32_uart_printf("#04 - I-fetch wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4)); |
neorv32_uart_printf("#05 - I-issue wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5)); |
neorv32_uart_printf("#06 - Multi-cycle ALU wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6)); |
neorv32_uart_printf("#07 - Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7)); |
neorv32_uart_printf("#08 - Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8)); |
neorv32_uart_printf("#09 - Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9)); |
neorv32_uart_printf("#10 - Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10)); |
neorv32_uart_printf("#11 - Conditional branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11)); |
neorv32_uart_printf("#12 - Conditional branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12)); |
neorv32_uart_printf("#13 - Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13)); |
neorv32_uart_printf("#14 - Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14)); |
neorv32_uart_printf("#IR - Total number of instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_INSTRET)); // = HPM_0 |
//neorv32_uart_printf("#TM - Current system time: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_TIME)); // = HPM_1 |
neorv32_uart_printf("#CY - Total number of clk cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_CYCLE)); // = HPM_2 |
neorv32_uart_printf("#03 - Retired compr. instr.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER3)); |
neorv32_uart_printf("#04 - I-fetch wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER4)); |
neorv32_uart_printf("#05 - I-issue wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER5)); |
neorv32_uart_printf("#06 - Multi-cyc. ALU wait cyc.: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER6)); |
neorv32_uart_printf("#07 - Load operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER7)); |
neorv32_uart_printf("#08 - Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8)); |
neorv32_uart_printf("#09 - Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9)); |
neorv32_uart_printf("#10 - Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10)); |
neorv32_uart_printf("#11 - Cond. branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11)); |
neorv32_uart_printf("#12 - Cond. branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12)); |
neorv32_uart_printf("#13 - Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13)); |
neorv32_uart_printf("#14 - Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14)); |
|
|
// ---------------------------------------------------------- |
1550,6 → 1544,17
|
|
/**********************************************************************//** |
* Simulation-based function to trigger CPU interrupts (MSI, MEI, FIRQ4..7). |
* |
* @param[in] sel IRQ select mask (bit positions according to #NEORV32_CSR_MIE_enum). |
**************************************************************************/ |
void sim_irq_trigger(uint32_t sel) { |
|
*(IO_REG32 (0xFF000000)) = sel; |
} |
|
|
/**********************************************************************//** |
* Trap handler for ALL exceptions/interrupts. |
**************************************************************************/ |
void global_trap_handler(void) { |
/sw/example/demo_trng/main.c
36,7 → 36,7
/**********************************************************************//** |
* @file demo_trng/main.c |
* @author Stephan Nolting |
* @brief TRNG demo program. |
* @brief True random number generator demo program. |
**************************************************************************/ |
|
#include <neorv32.h> |
51,9 → 51,13
/**@}*/ |
|
|
// prototypes |
void print_random_data(void); |
void generate_histogram(void); |
|
|
/**********************************************************************//** |
* This program generates a simple dimming sequence for PWM channel 0,1,2. |
* Simple true random number test/demo program. |
* |
* @note This program requires the UART and the TRNG to be synthesized. |
* |
61,14 → 65,6
**************************************************************************/ |
int main(void) { |
|
uint8_t lucky_numbers_5of50[5]; |
uint8_t lucky_numbers_2of10[2]; |
|
int err; |
uint8_t i, j, probe; |
uint8_t trng_data; |
unsigned int num_samples; |
|
// check if UART unit is implemented at all |
if (neorv32_uart_available() == 0) { |
return 0; |
102,7 → 98,7
// main menu |
neorv32_uart_printf("\nCommands:\n" |
" n: Print 8-bit random numbers (abort by pressing any key)\n" |
" l: Print your lucky numbers\n"); |
" h: Generate and print histogram\n"); |
|
neorv32_uart_printf("CMD:> "); |
char cmd = neorv32_uart_getc(); |
109,104 → 105,101
neorv32_uart_putc(cmd); // echo |
neorv32_uart_printf("\n"); |
|
// output RND data |
if (cmd == 'n') { |
num_samples = 0; |
while(1) { |
err = neorv32_trng_get(&trng_data); |
if (err) { |
neorv32_uart_printf("\nTRNG error (%i)!\n", err); |
break; |
} |
neorv32_uart_printf("%u ", (uint32_t)(trng_data)); |
num_samples++; |
if (neorv32_uart_char_received()) { // abort when key pressed |
neorv32_uart_printf("\nPrinted samples: %u", num_samples); |
break; |
} |
} |
print_random_data(); |
} |
else if (cmd == 'h') { |
generate_histogram(); |
} |
else { |
neorv32_uart_printf("Invalid command.\n"); |
} |
} |
|
// print lucky numbers |
if (cmd == 'l') { |
// reset arrays |
for (i=0; i<5; i++) { |
lucky_numbers_5of50[i] = 0; |
} |
lucky_numbers_2of10[0] = 0; |
lucky_numbers_2of10[1] = 0; |
return 0; |
} |
|
// get numbers |
i = 0; |
while (i<5) { |
err = neorv32_trng_get(&trng_data); |
if (err) { |
neorv32_uart_printf("\nTRNG error (%i)!\n", err); |
break; |
} |
// valid range? |
if ((trng_data == 0) || (trng_data > 50)) { |
continue; |
} |
// already sampled? |
probe = 0; |
for (j=0; j<5; j++) { |
if (lucky_numbers_5of50[j] == trng_data) { |
probe++; |
} |
} |
if (probe) { |
continue; |
} |
else { |
lucky_numbers_5of50[i] = trng_data; |
i++; |
} |
} |
|
// get numbers part 2 |
i = 0; |
while (i<2) { |
err = neorv32_trng_get(&trng_data); |
if (err) { |
neorv32_uart_printf("\nTRNG error (%i)!\n", err); |
break; |
} |
// valid range? |
if ((trng_data == 0) || (trng_data > 10)) { |
continue; |
} |
// already sampled? |
probe = 0; |
for (j=0; j<2; j++) { |
if (lucky_numbers_2of10[j] == trng_data) { |
probe++; |
} |
} |
if (probe) { |
continue; |
} |
else { |
lucky_numbers_2of10[i] = trng_data; |
i++; |
} |
} |
/**********************************************************************//** |
* Print random numbers until a key is pressed. |
**************************************************************************/ |
void print_random_data(void) { |
|
// output |
neorv32_uart_printf("\n"); |
for (j=0; j<5; j++) { |
if (i==4) { |
neorv32_uart_printf("%u", (uint32_t)lucky_numbers_5of50[j]); |
} |
else { |
neorv32_uart_printf("%u, ", (uint32_t)lucky_numbers_5of50[j]); |
} |
} |
neorv32_uart_printf("\nLucky numbers: %u, %u\n", (uint32_t)lucky_numbers_2of10[0], (uint32_t)lucky_numbers_2of10[1]); |
|
uint32_t num_samples = 0; |
int err = 0; |
uint8_t trng_data; |
|
while(1) { |
err = neorv32_trng_get(&trng_data); |
if (err) { |
neorv32_uart_printf("\nTRNG error!\n"); |
break; |
} |
neorv32_uart_printf("%u ", (uint32_t)(trng_data)); |
num_samples++; |
if (neorv32_uart_char_received()) { // abort when key pressed |
break; |
} |
} |
neorv32_uart_printf("\nPrinted samples: %u\n", num_samples); |
} |
|
return 0; |
|
/**********************************************************************//** |
* Generate and print histogram. Samples random data until a key is pressed. |
**************************************************************************/ |
void generate_histogram(void) { |
|
uint32_t hist[256]; |
uint32_t i; |
uint32_t cnt = 0; |
int err = 0; |
uint8_t trng_data; |
|
neorv32_uart_printf("Press any key to start.\n"); |
|
while(neorv32_uart_char_received() == 0); |
neorv32_uart_printf("Sampling... Press any key to stop.\n"); |
|
// clear histogram |
for (i=0; i<256; i++) { |
hist[i] = 0; |
} |
|
// sample random data |
while(1) { |
|
err = neorv32_trng_get(&trng_data); |
hist[trng_data & 0xff]++; |
cnt++; |
|
if (err) { |
neorv32_uart_printf("\nTRNG error!\n"); |
break; |
} |
|
if (neorv32_uart_char_received()) { // abort when key pressed |
break; |
} |
|
if (cnt & 0x80000000UL) { // to prevent overflow |
break; |
} |
} |
|
// print histogram |
neorv32_uart_printf("Histogram [random data value] : [# occurences]\n"); |
for (i=0; i<256; i++) { |
neorv32_uart_printf("%u: %u\n", (uint32_t)i, hist[i]); |
} |
|
neorv32_uart_printf("\nSamples: %u\n", cnt); |
|
// average |
uint64_t average = 0; |
for (i=0; i<256; i++) { |
average += (uint64_t)hist[i] * i; |
} |
average = average / ((uint64_t)cnt); |
neorv32_uart_printf("Average value: %u\n", (uint32_t)average); |
} |
|
/sw/example/demo_wdt/main.c
75,7 → 75,6
// this is not required, but keeps us safe |
neorv32_rte_setup(); |
|
|
// init UART at default baud rate, no parity bits, no rx interrupt, no tx interrupt |
neorv32_uart_setup(BAUD_RATE, 0b00, 0, 0); |
|
90,25 → 89,23
neorv32_uart_print("Cause of last processor reset: "); |
uint8_t wdt_cause = neorv32_wdt_get_cause(); |
|
if (wdt_cause == 1) { |
if (wdt_cause == 0) { |
neorv32_uart_print("External reset\n"); |
} |
else if (wdt_cause == 2) { |
neorv32_uart_print("Watchdog timeout\n"); |
else if (wdt_cause == 1) { |
neorv32_uart_print("Watchdog\n"); |
} |
else if (wdt_cause == 3) { |
neorv32_uart_print("Watchdog access fault\n"); |
} |
else { |
neorv32_uart_print("Undefined\n"); |
} |
|
|
// the watchod has a 20-bit counter, which trigger either an interrupt or a system reset |
// the watchod has a 20-bit counter, which triggers either an interrupt or a system reset |
// when overflowing |
|
// init watchdog (watchdog timer increment = cpu_clock/64, trigger reset on overflow) |
neorv32_wdt_setup(CLK_PRSC_64, 1); |
// init watchdog (watchdog timer increment = cpu_clock/64, trigger reset on overflow, lock |
// access so nobody can alter the configuration until next reset) |
neorv32_wdt_setup(CLK_PRSC_64, 1, 1); |
|
|
|
/sw/lib/include/neorv32_cfu.h
File deleted
/sw/lib/include/neorv32.h
372,7 → 372,11
CSR_MIE_FIRQ0E = 16, /**< CPU mie CSR (16): FIRQ0E - Fast interrupt channel 0 enable bit (r/w) */ |
CSR_MIE_FIRQ1E = 17, /**< CPU mie CSR (17): FIRQ1E - Fast interrupt channel 1 enable bit (r/w) */ |
CSR_MIE_FIRQ2E = 18, /**< CPU mie CSR (18): FIRQ2E - Fast interrupt channel 2 enable bit (r/w) */ |
CSR_MIE_FIRQ3E = 19 /**< CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) */ |
CSR_MIE_FIRQ3E = 19, /**< CPU mie CSR (19): FIRQ3E - Fast interrupt channel 3 enable bit (r/w) */ |
CSR_MIE_FIRQ4E = 20, /**< CPU mie CSR (20): FIRQ4E - Fast interrupt channel 4 enable bit (r/w) */ |
CSR_MIE_FIRQ5E = 21, /**< CPU mie CSR (21): FIRQ5E - Fast interrupt channel 5 enable bit (r/w) */ |
CSR_MIE_FIRQ6E = 22, /**< CPU mie CSR (22): FIRQ6E - Fast interrupt channel 6 enable bit (r/w) */ |
CSR_MIE_FIRQ7E = 23 /**< CPU mie CSR (23): FIRQ7E - Fast interrupt channel 7 enable bit (r/w) */ |
}; |
|
|
387,7 → 391,11
CSR_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/-) */ |
CSR_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/-) */ |
CSR_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/-) */ |
CSR_MIP_FIRQ3P = 19 /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */ |
CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/-) */ |
CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/-) */ |
CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/-) */ |
CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/-) */ |
CSR_MIP_FIRQ7P = 23 /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/-) */ |
}; |
|
|
463,7 → 471,11
TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */ |
TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */ |
TRAP_CODE_FIRQ_2 = 0x80000012, /**< 1.18: Fast interrupt channel 2 */ |
TRAP_CODE_FIRQ_3 = 0x80000013 /**< 1.19: Fast interrupt channel 3 */ |
TRAP_CODE_FIRQ_3 = 0x80000013, /**< 1.19: Fast interrupt channel 3 */ |
TRAP_CODE_FIRQ_4 = 0x80000014, /**< 1.20: Fast interrupt channel 4 */ |
TRAP_CODE_FIRQ_5 = 0x80000015, /**< 1.21: Fast interrupt channel 5 */ |
TRAP_CODE_FIRQ_6 = 0x80000016, /**< 1.22: Fast interrupt channel 6 */ |
TRAP_CODE_FIRQ_7 = 0x80000017 /**< 1.23: Fast interrupt channel 7 */ |
}; |
|
|
471,14 → 483,14
* Processor clock prescalers |
**************************************************************************/ |
enum NEORV32_CLOCK_PRSC_enum { |
CLK_PRSC_2 = 0, /**< CPU_CLK / 2 */ |
CLK_PRSC_4 = 1, /**< CPU_CLK / 4 */ |
CLK_PRSC_8 = 2, /**< CPU_CLK / 8 */ |
CLK_PRSC_64 = 3, /**< CPU_CLK / 64 */ |
CLK_PRSC_128 = 4, /**< CPU_CLK / 128 */ |
CLK_PRSC_1024 = 5, /**< CPU_CLK / 1024 */ |
CLK_PRSC_2048 = 6, /**< CPU_CLK / 2048 */ |
CLK_PRSC_4096 = 7 /**< CPU_CLK / 4096 */ |
CLK_PRSC_2 = 0, /**< CPU_CLK (from clk_i top signal) / 2 */ |
CLK_PRSC_4 = 1, /**< CPU_CLK (from clk_i top signal) / 4 */ |
CLK_PRSC_8 = 2, /**< CPU_CLK (from clk_i top signal) / 8 */ |
CLK_PRSC_64 = 3, /**< CPU_CLK (from clk_i top signal) / 64 */ |
CLK_PRSC_128 = 4, /**< CPU_CLK (from clk_i top signal) / 128 */ |
CLK_PRSC_1024 = 5, /**< CPU_CLK (from clk_i top signal) / 1024 */ |
CLK_PRSC_2048 = 6, /**< CPU_CLK (from clk_i top signal) / 2048 */ |
CLK_PRSC_4096 = 7 /**< CPU_CLK (from clk_i top signal) / 4096 */ |
}; |
|
|
523,11 → 535,82
/** bootloader memory base address (r/-/x) */ |
#define BOOTLOADER_BASE_ADDRESS (0xFFFF0000UL) |
/** peripheral/IO devices memory base address (r/w/x) */ |
#define IO_BASE_ADDRESS (0xFFFFFF80UL) |
#define IO_BASE_ADDRESS (0xFFFFFF00UL) |
/**@}*/ |
|
|
/**********************************************************************//** |
* @name IO Device: Custom Functions Subsystem (CFS) |
**************************************************************************/ |
/**@{*/ |
/** custom CFS register 0 */ |
#define CFS_REG_0 (*(IO_REG32 0xFFFFFF00UL)) // /**< (r)/(w): CFS register 0, user-defined */ |
/** custom CFS register 1 */ |
#define CFS_REG_1 (*(IO_REG32 0xFFFFFF04UL)) // /**< (r)/(w): CFS register 1, user-defined */ |
/** custom CFS register 2 */ |
#define CFS_REG_2 (*(IO_REG32 0xFFFFFF08UL)) // /**< (r)/(w): CFS register 2, user-defined */ |
/** custom CFS register 3 */ |
#define CFS_REG_3 (*(IO_REG32 0xFFFFFF0CUL)) // /**< (r)/(w): CFS register 3, user-defined */ |
/** custom CFS register 4 */ |
#define CFS_REG_4 (*(IO_REG32 0xFFFFFF10UL)) // /**< (r)/(w): CFS register 4, user-defined */ |
/** custom CFS register 5 */ |
#define CFS_REG_5 (*(IO_REG32 0xFFFFFF14UL)) // /**< (r)/(w): CFS register 5, user-defined */ |
/** custom CFS register 6 */ |
#define CFS_REG_6 (*(IO_REG32 0xFFFFFF18UL)) // /**< (r)/(w): CFS register 6, user-defined */ |
/** custom CFS register 7 */ |
#define CFS_REG_7 (*(IO_REG32 0xFFFFFF1CUL)) // /**< (r)/(w): CFS register 7, user-defined */ |
/** custom CFS register 8 */ |
#define CFS_REG_8 (*(IO_REG32 0xFFFFFF20UL)) // /**< (r)/(w): CFS register 8, user-defined */ |
/** custom CFS register 9 */ |
#define CFS_REG_9 (*(IO_REG32 0xFFFFFF24UL)) // /**< (r)/(w): CFS register 9, user-defined */ |
/** custom CFS register 10 */ |
#define CFS_REG_10 (*(IO_REG32 0xFFFFFF28UL)) // /**< (r)/(w): CFS register 10, user-defined */ |
/** custom CFS register 11 */ |
#define CFS_REG_11 (*(IO_REG32 0xFFFFFF2CUL)) // /**< (r)/(w): CFS register 11, user-defined */ |
/** custom CFS register 12 */ |
#define CFS_REG_12 (*(IO_REG32 0xFFFFFF30UL)) // /**< (r)/(w): CFS register 12, user-defined */ |
/** custom CFS register 13 */ |
#define CFS_REG_13 (*(IO_REG32 0xFFFFFF34UL)) // /**< (r)/(w): CFS register 13, user-defined */ |
/** custom CFS register 14 */ |
#define CFS_REG_14 (*(IO_REG32 0xFFFFFF38UL)) // /**< (r)/(w): CFS register 14, user-defined */ |
/** custom CFS register 15 */ |
#define CFS_REG_15 (*(IO_REG32 0xFFFFFF3CUL)) // /**< (r)/(w): CFS register 15, user-defined */ |
/** custom CFS register 16 */ |
#define CFS_REG_16 (*(IO_REG32 0xFFFFFF40UL)) // /**< (r)/(w): CFS register 16, user-defined */ |
/** custom CFS register 17 */ |
#define CFS_REG_17 (*(IO_REG32 0xFFFFFF44UL)) // /**< (r)/(w): CFS register 17, user-defined */ |
/** custom CFS register 18 */ |
#define CFS_REG_18 (*(IO_REG32 0xFFFFFF48UL)) // /**< (r)/(w): CFS register 18, user-defined */ |
/** custom CFS register 19 */ |
#define CFS_REG_19 (*(IO_REG32 0xFFFFFF4CUL)) // /**< (r)/(w): CFS register 19, user-defined */ |
/** custom CFS register 20 */ |
#define CFS_REG_20 (*(IO_REG32 0xFFFFFF50UL)) // /**< (r)/(w): CFS register 20, user-defined */ |
/** custom CFS register 21 */ |
#define CFS_REG_21 (*(IO_REG32 0xFFFFFF54UL)) // /**< (r)/(w): CFS register 21, user-defined */ |
/** custom CFS register 22 */ |
#define CFS_REG_22 (*(IO_REG32 0xFFFFFF58UL)) // /**< (r)/(w): CFS register 22, user-defined */ |
/** custom CFS register 23 */ |
#define CFS_REG_23 (*(IO_REG32 0xFFFFFF5CUL)) // /**< (r)/(w): CFS register 23, user-defined */ |
/** custom CFS register 24 */ |
#define CFS_REG_24 (*(IO_REG32 0xFFFFFF60UL)) // /**< (r)/(w): CFS register 24, user-defined */ |
/** custom CFS register 25 */ |
#define CFS_REG_25 (*(IO_REG32 0xFFFFFF64UL)) // /**< (r)/(w): CFS register 25, user-defined */ |
/** custom CFS register 26 */ |
#define CFS_REG_26 (*(IO_REG32 0xFFFFFF68UL)) // /**< (r)/(w): CFS register 26, user-defined */ |
/** custom CFS register 27 */ |
#define CFS_REG_27 (*(IO_REG32 0xFFFFFF6CUL)) // /**< (r)/(w): CFS register 27, user-defined */ |
/** custom CFS register 28 */ |
#define CFS_REG_28 (*(IO_REG32 0xFFFFFF70UL)) // /**< (r)/(w): CFS register 28, user-defined */ |
/** custom CFS register 29 */ |
#define CFS_REG_29 (*(IO_REG32 0xFFFFFF74UL)) // /**< (r)/(w): CFS register 29, user-defined */ |
/** custom CFS register 30 */ |
#define CFS_REG_30 (*(IO_REG32 0xFFFFFF78UL)) // /**< (r)/(w): CFS register 30, user-defined */ |
/** custom CFS register 31 */ |
#define CFS_REG_31 (*(IO_REG32 0xFFFFFF7CUL)) // /**< (r)/(w): CFS register 31, user-defined */ |
/**@}*/ |
|
|
/**********************************************************************//** |
* @name IO Device: General Purpose Input/Output Port Unit (GPIO) |
**************************************************************************/ |
/**@{*/ |
547,12 → 630,11
|
/** TRNG control/data register bits */ |
enum NEORV32_TRNG_CT_enum { |
TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data (8-bit) LSB */ |
TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data (8-bit) MSB */ |
TRNG_CT_VALID = 15, /**< TRNG data/control register(15) (r/-): Random data output valid */ |
TRNG_CT_ERROR_0 = 16, /**< TRNG data/control register(16) (r/-): Stuck-at-zero error */ |
TRNG_CT_ERROR_1 = 17, /**< TRNG data/control register(17) (r/-): Stuck-at-one error */ |
TRNG_CT_EN = 31 /**< TRNG data/control register(31) (r/w): TRNG enable */ |
TRNG_CT_DATA_LSB = 0, /**< TRNG data/control register(0) (r/-): Random data byte LSB */ |
TRNG_CT_DATA_MSB = 7, /**< TRNG data/control register(7) (r/-): Random data byte MSB */ |
|
TRNG_CT_EN = 30, /**< TRNG data/control register(30) (r/w): TRNG enable */ |
TRNG_CT_VALID = 31 /**< TRNG data/control register(31) (r/-): Random data output valid */ |
}; |
/**@}*/ |
|
566,20 → 648,16
|
/** WTD control register bits */ |
enum NEORV32_WDT_CT_enum { |
WDT_CT_CLK_SEL0 = 0, /**< WDT control register(0) (r/w): Clock prescaler select bit 0 */ |
WDT_CT_CLK_SEL1 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 1 */ |
WDT_CT_CLK_SEL2 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 2 */ |
WDT_CT_EN = 3, /**< WDT control register(3) (r/w): Watchdog enable */ |
WDT_CT_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode; when 0: timeout causes interrupt; when 1: timeout causes processor reset */ |
WDT_CT_CAUSE = 5, /**< WDT control register(5) (r/-): Last action (reset/IRQ) cause (0: external reset, 1: watchdog timeout) */ |
WDT_CT_PWFAIL = 6, /**< WDT control register(6) (r/-): Last Watchdog action (reset/IRQ) caused by wrong password when 1 */ |
|
WDT_CT_PASSWORD_LSB = 8, /**< WDT control register(8) (-/w): First bit / position begin for watchdog access password */ |
WDT_CT_PASSWORD_MSB = 15 /**< WDT control register(15) (-/w): Last bit / position end for watchdog access password */ |
WDT_CT_EN = 0, /**< WDT control register(0) (r/w): Watchdog enable */ |
WDT_CT_CLK_SEL0 = 1, /**< WDT control register(1) (r/w): Clock prescaler select bit 0 */ |
WDT_CT_CLK_SEL1 = 2, /**< WDT control register(2) (r/w): Clock prescaler select bit 1 */ |
WDT_CT_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */ |
WDT_CT_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */ |
WDT_CT_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */ |
WDT_CT_RESET = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */ |
WDT_CT_FORCE = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */ |
WDT_CT_LOCK = 8 /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */ |
}; |
|
/** Watchdog access passwort, must be set in WDT_CT bits 15:8 for every control register access */ |
#define WDT_PASSWORD 0x47 |
/**@}*/ |
|
|
645,6 → 723,7
enum NEORV32_UART_DATA_enum { |
UART_DATA_LSB = 0, /**< UART receive/transmit data register(0) (r/w): Receive/transmit data LSB (bit 0) */ |
UART_DATA_MSB = 7, /**< UART receive/transmit data register(7) (r/w): Receive/transmit data MSB (bit 7) */ |
|
UART_DATA_PERR = 28, /**< UART receive/transmit data register(18) (r/-): RX parity error detected when set */ |
UART_DATA_FERR = 29, /**< UART receive/transmit data register(29) (r/-): RX frame error (not valid stop bit) wdetected when set */ |
UART_DATA_OVERR = 30, /**< UART receive/transmit data register(30) (r/-): RX data overrun when set */ |
752,36 → 831,6
|
|
/**********************************************************************//** |
* @name IO Device: Custom Functions Unit 0 (CFU0) |
**************************************************************************/ |
/**@{*/ |
/** CFU0 register 0 ((r)/(w)) */ |
#define CFU0_REG_0 (*(IO_REG32 0xFFFFFFC0UL)) // (r)/(w): CFU0 register 0, user-defined |
/** CFU0 register 1 ((r)/(w)) */ |
#define CFU0_REG_1 (*(IO_REG32 0xFFFFFFC4UL)) // (r)/(w): CFU0 register 1, user-defined |
/** CFU0 register 2 ((r)/(w)) */ |
#define CFU0_REG_2 (*(IO_REG32 0xFFFFFFC8UL)) // (r)/(w): CFU0 register 2, user-defined |
/** CFU0 register 3 ((r)/(w)) */ |
#define CFU0_REG_3 (*(IO_REG32 0xFFFFFFCCUL)) // (r)/(w): CFU0 register 3, user-defined |
/**@}*/ |
|
|
/**********************************************************************//** |
* @name IO Device: Custom Functions Unit 1 (CFU1) |
**************************************************************************/ |
/**@{*/ |
/** CFU1 register 0 ((r)/(w)) */ |
#define CFU1_REG_0 (*(IO_REG32 0xFFFFFFD0UL)) // (r)/(w): CFU1 register 0, user-defined |
/** CFU1 register 1 ((r)/(w)) */ |
#define CFU1_REG_1 (*(IO_REG32 0xFFFFFFD4UL)) // (r)/(w): CFU1 register 1, user-defined |
/** CFU1 register 2 ((r)/(w)) */ |
#define CFU1_REG_2 (*(IO_REG32 0xFFFFFFD8UL)) // (r)/(w): CFU1 register 2, user-defined |
/** CFU1 register 3 ((r)/(w)) */ |
#define CFU1_REG_3 (*(IO_REG32 0xFFFFFFDCUL)) // (r)/(w): CFU1 register 3, user-defined |
/**@}*/ |
|
|
/**********************************************************************//** |
* @name IO Device: System Configuration Info Memory (SYSINFO) |
**************************************************************************/ |
/**@{*/ |
822,9 → 871,8
SYSINFO_FEATURES_IO_TWI = 20, /**< SYSINFO_FEATURES (20) (r/-): Two-wire interface implemented when 1 (via IO_TWI_EN generic) */ |
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */ |
SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */ |
SYSINFO_FEATURES_IO_CFU0 = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions unit 0 implemented when 1 (via IO_CFU0_EN generic) */ |
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */ |
SYSINFO_FEATURES_IO_CFU1 = 25 /**< SYSINFO_FEATURES (25) (r/-): Custom functions unit 1 implemented when 1 (via IO_CFU1_EN generic) */ |
SYSINFO_FEATURES_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */ |
SYSINFO_FEATURES_IO_TRNG = 24 /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */ |
}; |
|
/**********************************************************************//** |
863,7 → 911,7
#include "neorv32_rte.h" |
|
// io/peripheral devices |
#include "neorv32_cfu.h" |
#include "neorv32_cfs.h" |
#include "neorv32_gpio.h" |
#include "neorv32_mtime.h" |
#include "neorv32_pwm.h" |
/sw/lib/include/neorv32_cfs.h
0,0 → 1,53
// ################################################################################################# |
// # << NEORV32: neorv32_cfs.h - Custom Functions Subsystem (CFS)) HW Driver (stub) >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
// # # |
// # Redistribution and use in source and binary forms, with or without modification, are # |
// # permitted provided that the following conditions are met: # |
// # # |
// # 1. Redistributions of source code must retain the above copyright notice, this list of # |
// # conditions and the following disclaimer. # |
// # # |
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
// # conditions and the following disclaimer in the documentation and/or other materials # |
// # provided with the distribution. # |
// # # |
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
// # endorse or promote products derived from this software without specific prior written # |
// # permission. # |
// # # |
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
// # OF THE POSSIBILITY OF SUCH DAMAGE. # |
// # ********************************************************************************************* # |
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
// ################################################################################################# |
|
|
/**********************************************************************//** |
* @file neorv32_cfs.h |
* @author Stephan Nolting |
* @brief Custom Functions Subsystem (CFS)) HW driver header file. |
* |
* @warning There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware. |
* @warning Hence, the CFS designer has to provide the actual driver functions. |
* |
* @note These functions should only be used if the CFS was synthesized (IO_CFS_EN = true). |
**************************************************************************/ |
|
#ifndef neorv32_cfs_h |
#define neorv32_cfs_h |
|
// prototypes |
int neorv32_cfs_available(void); |
|
#endif // neorv32_cfs_h |
/sw/lib/include/neorv32_rte.h
62,7 → 62,11
RTE_TRAP_FIRQ_0 = 13, /**< Fast interrupt channel 0 */ |
RTE_TRAP_FIRQ_1 = 14, /**< Fast interrupt channel 1 */ |
RTE_TRAP_FIRQ_2 = 15, /**< Fast interrupt channel 2 */ |
RTE_TRAP_FIRQ_3 = 16 /**< Fast interrupt channel 3 */ |
RTE_TRAP_FIRQ_3 = 16, /**< Fast interrupt channel 3 */ |
RTE_TRAP_FIRQ_4 = 17, /**< Fast interrupt channel 4 */ |
RTE_TRAP_FIRQ_5 = 18, /**< Fast interrupt channel 5 */ |
RTE_TRAP_FIRQ_6 = 19, /**< Fast interrupt channel 6 */ |
RTE_TRAP_FIRQ_7 = 20 /**< Fast interrupt channel 7 */ |
}; |
|
// prototypes |
/sw/lib/include/neorv32_wdt.h
46,10 → 46,10
|
// prototypes |
int neorv32_wdt_available(void); |
void neorv32_wdt_setup(uint8_t clk_prsc, uint8_t timeout_mode); |
void neorv32_wdt_disable(void); |
void neorv32_wdt_setup(uint8_t prsc, uint8_t mode, uint8_t lock); |
int neorv32_wdt_disable(void); |
void neorv32_wdt_reset(void); |
uint8_t neorv32_wdt_get_cause(void); |
int neorv32_wdt_get_cause(void); |
void neorv32_wdt_force(void); |
|
#endif // neorv32_wdt_h |
/sw/lib/source/neorv32_cfu.c
File deleted
/sw/lib/source/neorv32_cfs.c
0,0 → 1,65
// ################################################################################################# |
// # << NEORV32: neorv32_cfs.c - Custom Functions Subsystem (CFS) HW Driver (stub) >> # |
// # ********************************************************************************************* # |
// # BSD 3-Clause License # |
// # # |
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. # |
// # # |
// # Redistribution and use in source and binary forms, with or without modification, are # |
// # permitted provided that the following conditions are met: # |
// # # |
// # 1. Redistributions of source code must retain the above copyright notice, this list of # |
// # conditions and the following disclaimer. # |
// # # |
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # |
// # conditions and the following disclaimer in the documentation and/or other materials # |
// # provided with the distribution. # |
// # # |
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # |
// # endorse or promote products derived from this software without specific prior written # |
// # permission. # |
// # # |
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # |
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # |
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # |
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # |
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # |
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # |
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # |
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # |
// # OF THE POSSIBILITY OF SUCH DAMAGE. # |
// # ********************************************************************************************* # |
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # |
// ################################################################################################# |
|
|
/**********************************************************************//** |
* @file neorv32_cfs.c |
* @author Stephan Nolting |
* @brief Custom Functions Subsystem (CFS) HW driver source file. |
* |
* @warning There are no "real" CFS driver functions available here, because these functions are defined by the actual hardware. |
* @warning Hence, the CFS designer has to provide the actual driver functions. |
* |
* @note These functions should only be used if the CFS was synthesized (IO_CFS_EN = true). |
**************************************************************************/ |
|
#include "neorv32.h" |
#include "neorv32_cfs.h" |
|
|
/**********************************************************************//** |
* Check if custom functions unit 0 was synthesized. |
* |
* @return 0 if CFS was not synthesized, 1 if CFS is available. |
**************************************************************************/ |
int neorv32_cfs_available(void) { |
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_IO_CFS)) { |
return 1; |
} |
else { |
return 0; |
} |
} |
|
/sw/lib/source/neorv32_cpu.c
47,11 → 47,31
/**********************************************************************//** |
* >Private< helper functions. |
**************************************************************************/ |
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel); |
static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index); |
static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data); |
|
|
/**********************************************************************//** |
* Private function: Check IRQ id. |
* |
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum. |
* @return 0 if success, 1 if error (invalid irq_sel). |
**************************************************************************/ |
static int __neorv32_cpu_irq_id_check(uint8_t irq_sel) { |
|
if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) || |
(irq_sel == CSR_MIE_FIRQ0E) || (irq_sel == CSR_MIE_FIRQ1E) || (irq_sel == CSR_MIE_FIRQ2E) || (irq_sel == CSR_MIE_FIRQ3E) || |
(irq_sel == CSR_MIE_FIRQ4E) || (irq_sel == CSR_MIE_FIRQ5E) || (irq_sel == CSR_MIE_FIRQ6E) || (irq_sel == CSR_MIE_FIRQ7E)) { |
return 0; |
} |
else { |
return 1; |
} |
} |
|
|
/**********************************************************************//** |
* Enable specific CPU interrupt. |
* |
* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too. |
61,8 → 81,8
**************************************************************************/ |
int neorv32_cpu_irq_enable(uint8_t irq_sel) { |
|
if ((irq_sel != CSR_MIE_MSIE) && (irq_sel != CSR_MIE_MTIE) && (irq_sel != CSR_MIE_MEIE) && |
(irq_sel != CSR_MIE_FIRQ0E) && (irq_sel != CSR_MIE_FIRQ1E) && (irq_sel != CSR_MIE_FIRQ2E) && (irq_sel != CSR_MIE_FIRQ3E)) { |
// check IRQ id |
if (__neorv32_cpu_irq_id_check(irq_sel)) { |
return 1; |
} |
|
80,8 → 100,8
**************************************************************************/ |
int neorv32_cpu_irq_disable(uint8_t irq_sel) { |
|
if ((irq_sel != CSR_MIE_MSIE) && (irq_sel != CSR_MIE_MTIE) && (irq_sel != CSR_MIE_MEIE) && |
(irq_sel != CSR_MIE_FIRQ0E) && (irq_sel != CSR_MIE_FIRQ1E) && (irq_sel != CSR_MIE_FIRQ2E) && (irq_sel != CSR_MIE_FIRQ3E)) { |
// check IRQ id |
if (__neorv32_cpu_irq_id_check(irq_sel)) { |
return 1; |
} |
|
/sw/lib/source/neorv32_rte.c
45,7 → 45,7
/**********************************************************************//** |
* The >private< trap vector look-up table of the NEORV32 RTE. |
**************************************************************************/ |
static uint32_t __neorv32_rte_vector_lut[17] __attribute__((unused)); // trap handler vector table |
static uint32_t __neorv32_rte_vector_lut[21] __attribute__((unused)); // trap handler vector table |
|
// private functions |
static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(16))) __attribute__((unused)); |
52,6 → 52,7
static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused)); |
static void __neorv32_rte_print_true_false(int state) __attribute__((unused)); |
static void __neorv32_rte_print_hex_word(uint32_t num); |
static int __neorv32_rte_check_exc_id(uint32_t id); |
|
|
/**********************************************************************//** |
93,14 → 94,8
int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) { |
|
// id valid? |
if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) || |
(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) || |
(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) || (id == RTE_TRAP_UENV_CALL) || |
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) || |
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) { |
|
if (__neorv32_rte_check_exc_id(id) == 0) { |
__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler |
|
return 0; |
} |
return 1; |
120,14 → 115,8
int neorv32_rte_exception_uninstall(uint8_t id) { |
|
// id valid? |
if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) || |
(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) || |
(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) || (id == RTE_TRAP_UENV_CALL) || |
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) || |
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) { |
|
if (__neorv32_rte_check_exc_id(id) == 0) { |
__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered |
|
return 0; |
} |
return 1; |
186,6 → 175,10
case TRAP_CODE_FIRQ_1: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_1]; break; |
case TRAP_CODE_FIRQ_2: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_2]; break; |
case TRAP_CODE_FIRQ_3: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_3]; break; |
case TRAP_CODE_FIRQ_4: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_4]; break; |
case TRAP_CODE_FIRQ_5: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_5]; break; |
case TRAP_CODE_FIRQ_6: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_6]; break; |
case TRAP_CODE_FIRQ_7: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_7]; break; |
default: break; |
} |
|
221,10 → 214,14
case TRAP_CODE_MSI: neorv32_uart_print("Machine software interrupt"); break; |
case TRAP_CODE_MTI: neorv32_uart_print("Machine timer interrupt"); break; |
case TRAP_CODE_MEI: neorv32_uart_print("Machine external interrupt"); break; |
case TRAP_CODE_FIRQ_0: neorv32_uart_print("Fast interrupt 0"); break; |
case TRAP_CODE_FIRQ_1: neorv32_uart_print("Fast interrupt 1"); break; |
case TRAP_CODE_FIRQ_2: neorv32_uart_print("Fast interrupt 2"); break; |
case TRAP_CODE_FIRQ_3: neorv32_uart_print("Fast interrupt 3"); break; |
case TRAP_CODE_FIRQ_0: |
case TRAP_CODE_FIRQ_1: |
case TRAP_CODE_FIRQ_2: |
case TRAP_CODE_FIRQ_3: |
case TRAP_CODE_FIRQ_4: |
case TRAP_CODE_FIRQ_5: |
case TRAP_CODE_FIRQ_6: |
case TRAP_CODE_FIRQ_7: neorv32_uart_print("Fast interrupt "); neorv32_uart_putc((char)('0' + (trap_cause & 0x7))); break; |
default: neorv32_uart_print("Unknown trap cause: "); __neorv32_rte_print_hex_word(trap_cause); break; |
} |
|
431,11 → 428,8
neorv32_uart_printf("TRNG - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG)); |
|
neorv32_uart_printf("CFU0 - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFU0)); |
|
neorv32_uart_printf("CFU1 - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFU1)); |
neorv32_uart_printf("CFS - "); |
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFS)); |
} |
|
|
476,7 → 470,31
} |
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Private function to check exception id |
* as 8-digit hexadecimal value (with "0x" suffix). |
* |
* @param[in] id Exception id (#NEORV32_RTE_TRAP_enum). |
* @return Return 0 if id is valid |
**************************************************************************/ |
static int __neorv32_rte_check_exc_id(uint32_t id) { |
|
// id valid? |
if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) || |
(id == RTE_TRAP_BREAKPOINT) || (id == RTE_TRAP_L_MISALIGNED) || (id == RTE_TRAP_L_ACCESS) || |
(id == RTE_TRAP_S_MISALIGNED) || (id == RTE_TRAP_S_ACCESS) || (id == RTE_TRAP_MENV_CALL) || (id == RTE_TRAP_UENV_CALL) || |
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) || |
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3) || |
(id == RTE_TRAP_FIRQ_4) || (id == RTE_TRAP_FIRQ_5) || (id == RTE_TRAP_FIRQ_6) || (id == RTE_TRAP_FIRQ_7)) { |
return 0; |
} |
else { |
return 1; |
} |
} |
|
|
|
/**********************************************************************//** |
* NEORV32 runtime environment: Print the processor version in human-readable format. |
**************************************************************************/ |
547,12 → 565,13
for (v=0; v<4; v++) { |
tmp = logo_data_c[u][v]; |
for (w=0; w<32; w++){ |
if (tmp & (1 << (31-w))) { |
if (tmp & 0x80000000UL) { // check MSB |
neorv32_uart_putc('#'); |
} |
else { |
neorv32_uart_putc(' '); |
} |
tmp <<= 1; |
} |
} |
} |
/sw/lib/source/neorv32_trng.c
70,13 → 70,13
|
TRNG_CT = 0; // reset |
|
for (i=0; i<1000; i++) { |
for (i=0; i<256; i++) { |
asm volatile ("nop"); |
} |
|
TRNG_CT = 1 << TRNG_CT_EN; // activate |
|
for (i=0; i<1000; i++) { |
for (i=0; i<256; i++) { |
asm volatile ("nop"); |
} |
} |
87,37 → 87,32
**************************************************************************/ |
void neorv32_trng_disable(void) { |
|
TRNG_CT &= ~((uint32_t)(1 << TRNG_CT_EN)); |
TRNG_CT = 0; |
} |
|
|
/**********************************************************************//** |
* Get random data from TRNG. |
* Get random data byte from TRNG. |
* |
* @note The TRNG is automatically reset if a stuck-at-one/stuck-at-zero error is detected. |
* |
* @param[in,out] data uint8_t pointer for storing random data word |
* @return Data is valid when 0, stuck-at-zero error when 1, stuck-at-one error when 2, data not (yet) valid when 3 |
* @param[in,out] data uint8_t pointer for storing random data byte. |
* @return Data is valid when 0 and invalid otherwise. |
**************************************************************************/ |
int neorv32_trng_get(uint8_t *data) { |
|
uint32_t trng_ct_reg = TRNG_CT; |
const int retries = 3; |
int i; |
uint32_t ct_reg; |
|
if (trng_ct_reg & (1<<TRNG_CT_ERROR_0)) { // stuck at zero error |
neorv32_trng_enable(); // reset TRNG |
return 1; |
} |
for (i=0; i<retries; i++) { |
ct_reg = TRNG_CT; |
|
if (trng_ct_reg & (1<<TRNG_CT_ERROR_1)) { // stuck at one error |
neorv32_trng_enable(); // reset TRNG |
return 2; |
} |
if ((ct_reg & (1<<TRNG_CT_VALID)) == 0) { // output data valid? |
continue; |
} |
|
if ((trng_ct_reg & (1<<TRNG_CT_VALID)) == 0) { // output data valid (yet)? |
return 3; |
*data = (uint8_t)(ct_reg >> TRNG_CT_DATA_LSB); |
return 0; // valid data |
} |
|
*data = (uint8_t)(trng_ct_reg >> TRNG_CT_DATA_LSB); |
return 0; // valid data |
return -1; // no valid data available |
} |
|
/sw/lib/source/neorv32_uart.c
71,9 → 71,11
/**********************************************************************//** |
* Enable and configure UART. |
* |
* @warning The 'UART_SIM_MODE' compiler flag will configure UART for simulation mode: all UART TX data will be redirected to simulation output. Use this for simulations only! |
* @warning To enable simulation mode add <USER_FLAGS+=-DUART_SIM_MODE> when compiling. |
* @note The 'UART_SIM_MODE' compiler flag will configure UART for simulation mode: all UART TX data will be redirected to simulation output. Use this for simulations only! |
* @note To enable simulation mode add <USER_FLAGS+=-DUART_SIM_MODE> when compiling. |
* |
* @warning The baud rate is computed using INTEGER operations (truncation errors might occur). |
* |
* @param[in] baudrate Targeted BAUD rate (e.g. 9600). |
* @param[in] parity PArity configuration (00=off, 10=even, 11=odd). |
* @param[in] rx_irq Enable RX interrupt (data received) when 1. |
99,7 → 101,7
} |
#endif |
|
// find clock prsc |
// find baud prescaler (12-bit wide)) |
while (i >= 0x0fff) { |
if ((p == 2) || (p == 4)) |
i >>= 3; |
108,11 → 110,12
p++; |
} |
|
uint32_t prsc = (uint32_t)p; |
prsc = prsc << UART_CT_PRSC0; |
uint32_t clk_prsc = (uint32_t)p; |
clk_prsc = clk_prsc << UART_CT_PRSC0; |
|
uint32_t baud = (uint32_t)i; |
baud = baud << UART_CT_BAUD00; |
uint32_t baud_prsc = (uint32_t)i; |
baud_prsc = baud_prsc - 1; |
baud_prsc = baud_prsc << UART_CT_BAUD00; |
|
uint32_t uart_en = 1; |
uart_en = uart_en << UART_CT_EN; |
135,7 → 138,7
uint32_t sim_mode = 0; |
#endif |
|
UART_CT = prsc | baud | uart_en | parity_config | rx_irq_en | tx_irq_en | sim_mode; |
UART_CT = clk_prsc | baud_prsc | uart_en | parity_config | rx_irq_en | tx_irq_en | sim_mode; |
} |
|
|
/sw/lib/source/neorv32_wdt.c
62,34 → 62,48
|
|
/**********************************************************************//** |
* Enable and configure watchdog timer. The WDT control register bits are listed in #NEORV32_WDT_CT_enum. |
* Configure and enable watchdog timer. The WDT control register bits are listed in #NEORV32_WDT_CT_enum. |
* |
* @param[in] clk_prsc Clock prescaler to selet timeout interval. See #NEORV32_CLOCK_PRSC_enum. |
* @param[in] timeout_mode Trigger system reset on timeout when 1, trigger interrupt on timeout when 0. |
* @param[in] prsc Clock prescaler to selet timeout interval. See #NEORV32_CLOCK_PRSC_enum. |
* @param[in] mode Trigger system reset on timeout when 1, trigger interrupt on timeout when 0. |
* @param[in] lock Control register will be locked when 1 (unitl next reset). |
**************************************************************************/ |
void neorv32_wdt_setup(uint8_t clk_prsc, uint8_t timeout_mode) { |
void neorv32_wdt_setup(uint8_t prsc, uint8_t mode, uint8_t lock) { |
|
uint32_t prsc = (uint32_t)(clk_prsc & 0x07); |
prsc = prsc << WDT_CT_CLK_SEL0; |
WDT_CT = (1 << WDT_CT_RESET); // reset WDT counter |
|
uint32_t mode = (uint32_t)(timeout_mode & 0x01); |
mode = mode << WDT_CT_MODE; |
uint32_t prsc_int = (uint32_t)(prsc & 0x07); |
prsc_int = prsc_int << WDT_CT_CLK_SEL0; |
|
uint32_t password = (uint32_t)(WDT_PASSWORD); |
password = password << WDT_CT_PASSWORD_LSB; |
uint32_t mode_int = (uint32_t)(mode & 0x01); |
mode_int = mode_int << WDT_CT_MODE; |
|
uint32_t enable = (uint32_t)(1 << WDT_CT_EN); |
uint32_t lock_int = (uint32_t)(lock & 0x01); |
lock_int = lock_int << WDT_CT_LOCK; |
|
WDT_CT = password | enable | mode | prsc; |
const uint32_t enable = (uint32_t)(1 << WDT_CT_EN); |
|
// update WDT control register |
WDT_CT = enable | mode_int | prsc_int | lock_int; |
} |
|
|
/**********************************************************************//** |
* Disable watchdog timer. |
* |
* @return Returns 0 if WDT is really deativated, -1 otherwise. |
**************************************************************************/ |
void neorv32_wdt_disable(void) { |
int neorv32_wdt_disable(void) { |
|
WDT_CT = 0; |
|
WDT_CT = ((uint32_t)(WDT_PASSWORD << WDT_CT_PASSWORD_LSB)) | ((uint32_t)(0 << WDT_CT_EN)); |
// check if wdt is really off |
if (WDT_CT & (1 << WDT_CT_EN)) { |
return -1; // WDT still active |
} |
else { |
return 0; |
} |
} |
|
|
98,38 → 112,30
**************************************************************************/ |
void neorv32_wdt_reset(void) { |
|
WDT_CT = WDT_CT | ((uint32_t)(WDT_PASSWORD << WDT_CT_PASSWORD_LSB)); |
WDT_CT = (1 << WDT_CT_RESET); |
} |
|
|
/**********************************************************************//** |
* Get cause of last watchdog action. |
* Get cause of last system reset. |
* |
* @return Cause of last reset/IRQ (0: undefined, 1: external reset, 2: watchdog timeout, 3: watchdog access error (wrong password)). |
* @return Cause of last reset/IRQ (0: external reset, 1: watchdog timeout). |
**************************************************************************/ |
uint8_t neorv32_wdt_get_cause(void) { |
int neorv32_wdt_get_cause(void) { |
|
uint8_t cause = 0; |
uint32_t ctrl = WDT_CT; |
if (ctrl & (1 << WDT_CT_CAUSE)) { // reset/IRQ casued by watchdog |
if (ctrl & (1 << WDT_CT_PWFAIL)) { // reset/IRQ due to wrong password |
cause = 3; |
} |
else { // reset/IRQ due to timeout |
cause = 2; |
} |
if (WDT_CT & (1 << WDT_CT_RCAUSE)) { // reset caused by watchdog |
return 1; |
} |
else { // external reset |
cause = 1; |
return 0; |
} |
return cause; |
} |
|
|
/**********************************************************************//** |
* Force watchdog action (reset/IRQ) via wrong-password access. |
* Force immediate watchdog action (reset/IRQ). |
**************************************************************************/ |
void neorv32_wdt_force(void) { |
|
WDT_CT = 0; // invalid access |
WDT_CT = WDT_CT | (1 << WDT_CT_FORCE); |
} |
/CHANGELOG.md
15,6 → 15,12
|
| Date (*dd.mm.yyyy*) | Version | Comment | |
|:----------:|:-------:|:--------| |
| 29.01.2021 | 1.5.0.9 | removed custom function units `CFU0` & `CFU1`; :sparkles: replaced them by new *Custom Functions Subsystem `CFS`*, which provides up to 32x32-bit memory-mapped registers; new configuration generics: `IO_CFS_EN`, `IO_CFS_CONFIG`; new top entity signals: `cfs_in_i`, `cfs_out_o`; increased processor's IO area from 128 bytes to 256 bytes, now starting at `0xFFFFFF00` | |
| 28.01.2021 | 1.5.0.8 | added *critical limit* for number of implemented PMP regions: When implementing more PMP regions that a certain critical limit an additional register stage is automatically inserted into the CPU’s memory interfaces increasing the latency of instruction fetches and data access by +1 cycle. The critical limit can be adapted for custom use by a constant from the main VHDL package file (rtl/core/neorv32_package.vhd). The default value is 8: `constant pmp_num_regions_critical_c : natural := 8;` | |
| 27.01.2021 | 1.5.0.7 | added four additional *fast interrupt* channels `FIRQ4..7`, available via processor's top `soc_firq_i(3:0)` signal for custom platform use; fixed minor error in UART setup function (baud rate prescaler calculation for very high baud rates) | |
| 26.01.2021 | 1.5.0.6 | minor logic optimization of CPU's `B` extension co-processor (reducing area); minor logic optimization or `HPM` triggers (reducing area); reworked CPU's co-processor interface; minor logic optimiztation of branch condition check (to shorten critical path) | |
| 23.01.2021 | 1.5.0.5 | reworked true random number generator `TRNG`: architecture is now based on several simple ring oscillators with incrementing length; changed control register bits; updated according driver functions and demo program | |
| 22.01.2021 | 1.5.0.4 | :bug: fixed BUG in bootloader (that caused it to immediately crash after reset if SPI/MTIME/GPIO peripherals were not implemented); reworked watchdog timer `WDT`: removed watchdog access password, added option to lock configuration until next system reset, changed control register bits - updated driver functions and demo/test programs | |
| 17.01.2021 | 1.5.0.3 | CPU data register file can now be mapped to a **single** "true dual-port" block RAM by the synthesizer (requiring only 1024 memory bits instead of 2048); :bug: fixed typo error in `sim/rtl_modules/neorv32_imem.vhd`; modified `M` co-processor (due to register file read access modification), reduced switching activity when co-processor is idle; logic/arithmetic operations of `B` extension only require 3 cycles now, reduced switching activity when co-processor is idle | |
| 15.01.2021 | 1.5.0.2 | added instruction cache associativity configuration (number of sets); new configuration generic: `ICACHE_ASSOCIATIVITY` -> number of sets (1 = direct mapped, 2 = 2-way set-associative), has to be a power of two; if associativity is > 1 the used replacement policy is *least recently used (LRU)*; :bug: fixed bug in `sw/lib/source/neorv32_cpu.c` PMP.CFG configuration function | |
| 14.01.2021 | 1.5.0.1 | added new HPM trigger event: multi-cycle ALU operation wait cycle (`HPMCNT_EVENT_WAIT_MC`); renamed `neorv32_cache.vhd` -> `neorv32_icache.vhd` | |
/README.md
8,7 → 8,7
[](https://github.com/stnolting/neorv32/releases) |
|
* [Overview](#Overview) |
* [Project Status](#Status) |
* [Status](#Status) |
* [Features](#Features) |
* [FPGA Implementation Results](#FPGA-Implementation-Results) |
* [Performance](#Performance) |
25,35 → 25,38
on the RISC-V-compliant NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC |
designs or as stand-alone custom microcontroller. |
|
The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository. |
:label: The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository. |
To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases). |
|
The documentation of the software framework is available online on [GitHub-pages](https://stnolting.github.io/neorv32/files.html). |
For more detailed information take a look at the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf). |
:books: The doxygen-based documentation of the software framework is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html). |
|
:page_facing_up: For more detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
|
### Key Features |
|
* RISC-V-[compliant](#Status) 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to |
* RISC-V 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to |
* Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf) |
* Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf) |
* Passes the [offcial RISC-V compliance tests](#Status) |
* Configurable RISC-V-compliant CPU extensions |
* `A` - atomic memory access instructions (optional) |
* `B` - Bit manipulation instructions (optional) |
* `C` - compressed instructions (16-bit) (optional) |
* `E` - embedded CPU (reduced register file (optional) |
* `I` - base integer instruction set (always enabled) |
* `M` - integer multiplication and division hardware (optional) |
* `U` - less-privileged *user mode* (optional) |
* `X` - NEORV32_specific extensions (always enabled) |
* `Zicsr` - control and status register access instructions (+ exception/irq system) (optional) |
* `Zifencei` - instruction stream synchronization (optional) |
* `PMP` - physical memory protection (optional) |
* `HPM` - hardware performance monitors (optional) |
* [`A`](#Atomic-memory-access-a-extension) - atomic memory access instructions (optional) |
* [`B`](#Bit-manipulation-instructions-B-extension) - Bit manipulation instructions (optional) |
* [`C`](#Compressed-instructions-C-extension) - compressed instructions (16-bit) (optional) |
* [`E`](#Embedded-CPU-version-E-extension) - embedded CPU (reduced register file size) (optional) |
* [`I`](#Integer-base-instruction-set-I-extension) - base integer instruction set (always enabled) |
* [`M`](#Integer-multiplication-and-division-hardware-M-extension) - integer multiplication and division hardware (optional) |
* [`U`](#Privileged-architecture---User-mode-U-extension) - less-privileged *user mode* (optional) |
* [`X`](#NEORV32-specific-CPU-extensions-X-extension) - NEORV32-specific extensions (always enabled) |
* [`Zicsr`](#Privileged-architecture---CSR-access-Zicsr-extension) - control and status register access instructions (+ exception/irq system) (optional) |
* [`Zifencei`](#Privileged-architecture---Instruction-stream-synchronization-Zifencei-extension) - instruction stream synchronization (optional) |
* [`PMP`](#Privileged-architecture---Physical-memory-protection-PMP) - physical memory protection (optional) |
* [`HPM`](#Privileged-architecture---Hardware-performance-monitors-HPM-extension) - hardware performance monitors (optional) |
* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules |
* optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches |
* timers (watch dog, RISC-V-compliant machine timer) |
* serial interfaces (SPI, TWI, UART) and general purpose IO |
* serial interfaces (SPI, TWI, UART) |
* general purpose IO and PWM channels |
* external bus interface (Wishbone / [AXI4](#AXI4-Connectivity)) |
* [more ...](#NEORV32-Processor-Features) |
* Software framework |
87,8 → 90,9
The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute |
all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark). |
|
The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei` |
[RISC-V compliance tests (new framework v2)](https://github.com/riscv/riscv-compliance). |
**RISC-V Compliance**: The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei` |
[RISC-V compliance](https://github.com/riscv/riscv-compliance) tests. More information regarding the NEORV32 port of the compliance framework can be found in |
[`riscv-compliance/README.md`](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md). |
|
| Project component | CI status | |
|:----------------- |:----------| |
142,8 → 146,8
* 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode |
* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity)) |
* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**) |
* GARO-based true random number generator (**TRNG**) |
* custom functions units (**CFU0** and **CFU1**) for tightly-coupled custom co-processors |
* ring-oscillator-based true random number generator (**TRNG**) |
* custom functions subsystem (**CFS**) for tightly-coupled custom co-processor extensions |
* system configuration information memory to check hardware configuration by software (**SYSINFO**, mandatory - not *optional*) |
|
|
159,7 → 163,8
the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
|
**General**: |
#### General Features |
|
* Modified Harvard architecture (separate CPU interfaces for data and instructions; NEORV32 processor: Single processor-internal bus via I/D mux) |
* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme |
* No hardware support of unaligned accesses - they will trigger an exception |
169,14 → 174,23
* Official [RISC-V open-source architecture ID](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) |
|
|
**RV32I base instruction set** (`I` extension): |
* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND` |
* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU` |
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW` |
* System instructions: `ECALL` `EBREAK` `FENCE` |
* Pseudo-instructions are not listed |
#### Atomic memory access (`A` extension) |
|
**Compressed instructions** (`C` extension): |
* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional) |
|
|
#### Bit manipulation instructions (`B` extension) |
|
* :warning: Extension is not officially ratified yet by the RISC-V foundation! |
* Implies `Zbb` extension (base bit manipulation instruction set) |
* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec |
* Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)) |
* Only the `Zbb` base instructions subset is supported yet |
* Supported instructions: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR` `RORI` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`) |
|
|
#### Compressed instructions (`C` extension) |
|
* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP` |
* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ` |
* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP` |
183,26 → 197,44
* System instructions: `C.EBREAK` (only with `Zicsr` extension) |
* Pseudo-instructions are not listed |
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**Embedded CPU version** (`E` extension): |
#### Embedded CPU version (`E` extension) |
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* Reduced register file (only the 16 lowest registers) |
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**Integer multiplication and division hardware** (`M` extension): |
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#### Integer base instruction set (`I` extension) |
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND` |
* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU` |
* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW` |
* System instructions: `ECALL` `EBREAK` `FENCE` |
* Pseudo-instructions are not listed |
|
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#### Integer multiplication and division hardware (`M` extension) |
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU` |
* Division instructions: `DIV` `DIVU` `REM` `REMU` |
* By default, the multiplier and divider cores use an iterative bit-serial processing scheme |
* Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance |
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**Atomic memory access** (`A` extension): |
* Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional) |
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**Bit manipulation instructions** (`B` extension implying `Zbb` extension): |
* :warning: RISC-V `B` extension is not officially ratified yet! |
* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec |
* Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)) |
* Only the `Zbb` base instructions subset is supported yet |
* Supported instructions: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR` `RORI` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`) |
#### Privileged architecture - User mode (`U` extension) |
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**Privileged architecture / CSR access** (`Zicsr` extension): |
* Requires `Zicsr` extension |
* Privilege levels: `M` (machine mode) + less-privileged `U` (user mode) |
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#### NEORV32-specific CPU extensions (`X` extension) |
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* The NEORV32-specific extensions are always enabled and are indicated via the `X` bit set in the `misa` CSR. |
* Eight *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause` |
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`) |
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception |
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#### Privileged architecture - CSR access (`Zicsr` extension) |
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* Privilege levels: `M-mode` (Machine mode) |
* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI` |
* System instructions: `MRET` `WFI` |
223,19 → 255,24
* Machine timer interrupt `mti` (via processor's MTIME unit / external signal) |
* Machine software interrupt `msi` (via external signal) |
* Machine external interrupt `mei` (via external signal) |
* Four fast interrupt requests (custom extension) |
* Eight fast interrupt requests (custom extension) |
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension): |
* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode) |
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**Privileged architecture / Instruction stream synchronization** (`Zifencei` extension): |
#### Privileged architecture - Instruction stream synchronization (`Zifencei` extension) |
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* System instructions: `FENCE.I` (among others, used to clear and reload instruction cache) |
|
**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension): |
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#### Privileged architecture - Physical memory protection (`PMP`) |
|
* Requires `Zicsr` extension |
* Configurable number of regions (0..63) |
* Additional machine CSRs: `pmpcfg*`(0..15) `pmpaddr*`(0..63) |
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**Privileged architecture / Hardware performance monitors** (`HPM`, requires `Zicsr` extension): |
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#### Privileged architecture - Hardware performance monitors (`HPM` extension) |
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* Requires `Zicsr` extension |
* Configurable number of counters (0..29) |
* Additional machine CSRs: `mhpmevent*`(3..31) `[m]hpmcounter*[h]`(3..31) |
|
249,16 → 286,8
* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt") |
* The bit manipulation extension is not yet officially ratified, but is expected to stay unchanged. There is no software support in the upstream GCC RISC-V port yet. However, an intrinsic library is provided to utilize the provided bit manipulation extension from C-language code (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)). NEORV32's `B`/`Zbb` extension is compliant to spec. version "0.94-draft". |
|
### NEORV32-Specific CPU Extensions |
|
The NEORV32-specific extensions are always enabled and are indicated via the `X` bit in the `misa` CSR. |
|
* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause` |
* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`) |
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception |
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|
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## FPGA Implementation Results |
|
### NEORV32 CPU |
278,7 → 307,7
| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2471 | 1148 | 1024 | 0 | 120 MHz | |
| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2716 | 1165 | 1024 | 0 | 120 MHz | |
| `rv32imac` + `u` + `Zicsr` + `Zifencei` | 2736 | 1168 | 1024 | 0 | 120 MHz | |
| `rv32imacb` + `u` + `Zicsr` + `Zifencei` | 3045 | 1260 | 1024 | 0 | 114 MHz | |
| `rv32imacb` + `u` + `Zicsr` + `Zifencei` | 3045 | 1260 | 1024 | 0 | 116 MHz | |
|
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half. |
|
292,8 → 321,7
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 | |
| BUSSWITCH | Mux for CPU I & D interfaces | 65 | 8 | 0 | 0 | |
| i-CACHE | Proc.-int. nstruction cache (default 1x4x64 bytes) | 234 | 156 | 8 192 | 0 | |
| CFU0 | Custom functions unit 0 | - | - | - | - | |
| CFU1 | Custom functions unit 1 | - | - | - | - | |
| CFS | Custom functions subsystem | - | - | - | - | |
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 | |
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 | |
| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 | |
310,7 → 338,7
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### NEORV32 Processor - Exemplary FPGA Setups |
|
Exemplary processor implementation results for different FPGA platforms. The processor setup uses *the default peripheral configuration* (like no _CFUs_ and no _TRNG_), |
Exemplary processor implementation results for different FPGA platforms. The processor setup uses *the default peripheral configuration* (like no _CFS_ and no _TRNG_), |
no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the |
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals |
to FPGA pins - except for the Wishbone bus and the interrupt signals. The "default" strategy of each toolchain is used. |
412,14 → 440,14
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### Using the CPU in Stand-Alone Mode |
|
If you do not want to use the NEORV32 processor setup, you can also use the CPU in stand-alone mode and build your own system around it. |
If you *do not* want to use the NEORV32 processor setup, you can also use the CPU in stand-alone mode and build your own system around it. |
The top entity of the stand-alone **NEORV32 CPU** is [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd). |
Note that the CPU uses a proprietary interface for accessing data and instruction memory. More information can be found in the |
[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf). |
|
:warning: It is recommended to use the processor setup even if you only want to use the CPU. Simply disable all the processor-internal modules via the generics |
and you will get a "CPU wrapper" that provides a minimal CPU environment and an external memory interface (like AXI4). This setup also allows to further use the default |
bootloader and application makefiles. From this base you can start building your own processor system. |
:information_source: It is recommended to use the processor setup even if you only want to use the CPU. Simply disable all the processor-internal modules via the generics |
and you will get a "CPU wrapper" that already provides a minimal CPU environment and an external memory interface (like AXI4). This setup also allows to further use the default |
bootloader and software framework. From this base you can start building your own processor system. |
|
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### Alternative Top Entities |