OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /neorv32/trunk
    from Rev 54 to Rev 55
    ↔ Reverse comparison
  •

Rev 54 → Rev 55

/docs/figures/neorv32_processor.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/docs/Doxyfile
32,7 → 32,7
# title of most generated pages and in a few other places.
# The default value is: My Project.
 
PROJECT_NAME = "The NEORV32 RISC-V Processor - Software Framework"
PROJECT_NAME = "The NEORV32 RISC-V Processor - Software Framework Documentation"
 
# The PROJECT_NUMBER tag can be used to enter a project or revision number. This
# could be handy for archiving the generated documentation or if some version
/docs/NEORV32.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/rtl/core/neorv32_application_image.vhd
6,7 → 6,7
 
package neorv32_application_image is
 
type application_init_image_t is array (0 to 1066) of std_ulogic_vector(31 downto 0);
type application_init_image_t is array (0 to 1068) of std_ulogic_vector(31 downto 0);
constant application_init_image : application_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
60,7 → 60,7
00000049 => x"00158593",
00000050 => x"ff5ff06f",
00000051 => x"00001597",
00000052 => x"fdc58593",
00000052 => x"fe458593",
00000053 => x"80000617",
00000054 => x"f2c60613",
00000055 => x"80000697",
111,19 → 111,19
00000100 => x"00000593",
00000101 => x"b0050513",
00000102 => x"00112623",
00000103 => x"730000ef",
00000104 => x"15d000ef",
00000103 => x"248000ef",
00000104 => x"201000ef",
00000105 => x"02050063",
00000106 => x"4a8000ef",
00000106 => x"151000ef",
00000107 => x"00000513",
00000108 => x"4fc000ef",
00000108 => x"1a5000ef",
00000109 => x"00001537",
00000110 => x"d3c50513",
00000111 => x"780000ef",
00000110 => x"d4450513",
00000111 => x"298000ef",
00000112 => x"020000ef",
00000113 => x"00001537",
00000114 => x"d1850513",
00000115 => x"770000ef",
00000114 => x"d2050513",
00000115 => x"288000ef",
00000116 => x"00c12083",
00000117 => x"00000513",
00000118 => x"01010113",
133,947 → 133,949
00000122 => x"00812423",
00000123 => x"00112623",
00000124 => x"00000413",
00000125 => x"119000ef",
00000125 => x"1bd000ef",
00000126 => x"0ff47513",
00000127 => x"111000ef",
00000127 => x"1b5000ef",
00000128 => x"0c800513",
00000129 => x"13d000ef",
00000129 => x"43c000ef",
00000130 => x"00140413",
00000131 => x"fedff06f",
00000132 => x"fc010113",
00000133 => x"02112e23",
00000134 => x"02512c23",
00000135 => x"02612a23",
00000136 => x"02712823",
00000137 => x"02a12623",
00000138 => x"02b12423",
00000139 => x"02c12223",
00000140 => x"02d12023",
00000141 => x"00e12e23",
00000142 => x"00f12c23",
00000143 => x"01012a23",
00000144 => x"01112823",
00000145 => x"01c12623",
00000146 => x"01d12423",
00000147 => x"01e12223",
00000148 => x"01f12023",
00000149 => x"34102773",
00000150 => x"34071073",
00000151 => x"342027f3",
00000152 => x"0807c863",
00000153 => x"00071683",
00000154 => x"00300593",
00000155 => x"0036f693",
00000156 => x"00270613",
00000157 => x"00b69463",
00000158 => x"00470613",
00000159 => x"34161073",
00000160 => x"00b00713",
00000161 => x"04f77a63",
00000162 => x"48c00793",
00000163 => x"000780e7",
00000164 => x"03c12083",
00000165 => x"03812283",
00000166 => x"03412303",
00000167 => x"03012383",
00000168 => x"02c12503",
00000169 => x"02812583",
00000170 => x"02412603",
00000171 => x"02012683",
00000172 => x"01c12703",
00000173 => x"01812783",
00000174 => x"01412803",
00000175 => x"01012883",
00000176 => x"00c12e03",
00000177 => x"00812e83",
00000178 => x"00412f03",
00000179 => x"00012f83",
00000180 => x"04010113",
00000181 => x"30200073",
00000182 => x"00001737",
00000183 => x"00279793",
00000184 => x"d5870713",
00000185 => x"00e787b3",
00000186 => x"0007a783",
00000187 => x"00078067",
00000188 => x"80000737",
00000189 => x"ffd74713",
00000190 => x"00e787b3",
00000191 => x"01c00713",
00000192 => x"f8f764e3",
00000193 => x"00001737",
00000194 => x"00279793",
00000195 => x"d8870713",
00000196 => x"00e787b3",
00000197 => x"0007a783",
00000198 => x"00078067",
00000199 => x"800007b7",
00000200 => x"0007a783",
00000201 => x"f69ff06f",
00000202 => x"800007b7",
00000203 => x"0047a783",
00000204 => x"f5dff06f",
00000205 => x"800007b7",
00000206 => x"0087a783",
00000207 => x"f51ff06f",
00000208 => x"800007b7",
00000209 => x"00c7a783",
00000210 => x"f45ff06f",
00000211 => x"8101a783",
00000212 => x"f3dff06f",
00000213 => x"8141a783",
00000214 => x"f35ff06f",
00000215 => x"8181a783",
00000216 => x"f2dff06f",
00000217 => x"81c1a783",
00000218 => x"f25ff06f",
00000219 => x"8201a783",
00000220 => x"f1dff06f",
00000221 => x"8241a783",
00000222 => x"f15ff06f",
00000223 => x"8281a783",
00000224 => x"f0dff06f",
00000225 => x"82c1a783",
00000226 => x"f05ff06f",
00000227 => x"8301a783",
00000228 => x"efdff06f",
00000229 => x"8341a783",
00000230 => x"ef5ff06f",
00000231 => x"8381a783",
00000232 => x"eedff06f",
00000233 => x"83c1a783",
00000234 => x"ee5ff06f",
00000235 => x"8401a783",
00000236 => x"eddff06f",
00000237 => x"8441a783",
00000238 => x"ed5ff06f",
00000239 => x"8481a783",
00000240 => x"ecdff06f",
00000241 => x"84c1a783",
00000242 => x"ec5ff06f",
00000243 => x"8501a783",
00000244 => x"ebdff06f",
00000245 => x"8541a783",
00000246 => x"eb5ff06f",
00000247 => x"8581a783",
00000248 => x"eadff06f",
00000249 => x"85c1a783",
00000250 => x"ea5ff06f",
00000251 => x"8601a783",
00000252 => x"e9dff06f",
00000253 => x"8641a783",
00000254 => x"e95ff06f",
00000255 => x"8681a783",
00000256 => x"e8dff06f",
00000257 => x"86c1a783",
00000258 => x"e85ff06f",
00000259 => x"8701a783",
00000260 => x"e7dff06f",
00000261 => x"00000000",
00000262 => x"00000000",
00000263 => x"fe010113",
00000264 => x"01212823",
00000265 => x"00050913",
00000266 => x"00001537",
00000267 => x"00912a23",
00000268 => x"dfc50513",
00000269 => x"000014b7",
00000270 => x"00812c23",
00000271 => x"01312623",
00000272 => x"00112e23",
00000273 => x"01c00413",
00000274 => x"4f4000ef",
00000275 => x"07848493",
00000276 => x"ffc00993",
00000277 => x"008957b3",
00000278 => x"00f7f793",
00000279 => x"00f487b3",
00000280 => x"0007c503",
00000281 => x"ffc40413",
00000282 => x"478000ef",
00000283 => x"ff3414e3",
00000284 => x"01c12083",
00000285 => x"01812403",
00000286 => x"01412483",
00000287 => x"01012903",
00000288 => x"00c12983",
00000289 => x"02010113",
00000290 => x"00008067",
00000291 => x"00001537",
00000292 => x"ff010113",
00000293 => x"e0050513",
00000294 => x"00112623",
00000295 => x"00812423",
00000296 => x"00912223",
00000297 => x"498000ef",
00000298 => x"34202473",
00000299 => x"00900713",
00000300 => x"00f47793",
00000301 => x"05778493",
00000302 => x"00f76463",
00000303 => x"03078493",
00000304 => x"00b00793",
00000305 => x"0087ee63",
00000306 => x"00001737",
00000307 => x"00241793",
00000308 => x"f8c70713",
00000309 => x"00e787b3",
00000310 => x"0007a783",
00000311 => x"00078067",
00000312 => x"800007b7",
00000313 => x"00b78713",
00000314 => x"12e40663",
00000315 => x"02876663",
00000316 => x"00378713",
00000317 => x"10e40463",
00000318 => x"00778793",
00000319 => x"10f40663",
00000320 => x"00001537",
00000321 => x"f6050513",
00000322 => x"434000ef",
00000323 => x"00040513",
00000324 => x"f0dff0ef",
00000325 => x"0380006f",
00000326 => x"ff07c793",
00000327 => x"00f407b3",
00000328 => x"00f00713",
00000329 => x"fcf76ee3",
00000330 => x"00001537",
00000331 => x"f5050513",
00000332 => x"40c000ef",
00000333 => x"00048513",
00000334 => x"3a8000ef",
00000335 => x"0100006f",
00000336 => x"00001537",
00000337 => x"e0850513",
00000338 => x"3f4000ef",
00000339 => x"00001537",
00000340 => x"f7850513",
00000341 => x"3e8000ef",
00000342 => x"34002573",
00000343 => x"ec1ff0ef",
00000344 => x"00001537",
00000345 => x"f8050513",
00000346 => x"3d4000ef",
00000347 => x"34302573",
00000348 => x"eadff0ef",
00000349 => x"00812403",
00000350 => x"00c12083",
00000351 => x"00412483",
00000352 => x"00001537",
00000353 => x"fe850513",
00000354 => x"01010113",
00000355 => x"3b00006f",
00000356 => x"00001537",
00000357 => x"e2850513",
00000358 => x"fb1ff06f",
00000359 => x"00001537",
00000360 => x"e4450513",
00000361 => x"fa5ff06f",
00000362 => x"00001537",
00000363 => x"e5850513",
00000364 => x"f99ff06f",
00000365 => x"00001537",
00000366 => x"e6450513",
00000367 => x"f8dff06f",
00000368 => x"00001537",
00000369 => x"e7c50513",
00000370 => x"f81ff06f",
00000371 => x"00001537",
00000372 => x"e9050513",
00000373 => x"f75ff06f",
00000374 => x"00001537",
00000375 => x"eac50513",
00000376 => x"f69ff06f",
00000377 => x"00001537",
00000378 => x"ec050513",
00000379 => x"f5dff06f",
00000380 => x"00001537",
00000381 => x"ee050513",
00000382 => x"f51ff06f",
00000383 => x"00001537",
00000384 => x"f0050513",
00000385 => x"f45ff06f",
00000386 => x"00001537",
00000387 => x"f1c50513",
00000388 => x"f39ff06f",
00000389 => x"00001537",
00000390 => x"f3450513",
00000391 => x"f2dff06f",
00000392 => x"01f00793",
00000393 => x"02a7e263",
00000394 => x"800007b7",
00000395 => x"00078793",
00000396 => x"00251513",
00000397 => x"00a78533",
00000398 => x"48c00793",
00000399 => x"00f52023",
00000400 => x"00000513",
00000401 => x"00008067",
00000402 => x"00100513",
00000403 => x"00008067",
00000404 => x"ff010113",
00000405 => x"00112623",
00000406 => x"00812423",
00000407 => x"00912223",
00000408 => x"301027f3",
00000409 => x"00079863",
00000410 => x"00001537",
00000411 => x"fbc50513",
00000412 => x"2cc000ef",
00000413 => x"21000793",
00000414 => x"30579073",
00000415 => x"00000413",
00000416 => x"01d00493",
00000417 => x"00040513",
00000418 => x"00140413",
00000419 => x"0ff47413",
00000420 => x"f91ff0ef",
00000421 => x"fe9418e3",
00000422 => x"00c12083",
00000423 => x"00812403",
00000424 => x"00412483",
00000425 => x"01010113",
00000426 => x"00008067",
00000427 => x"ff010113",
00000428 => x"00112623",
00000429 => x"00812423",
00000430 => x"30102673",
00000431 => x"400005b7",
00000432 => x"10058593",
00000433 => x"00b677b3",
00000434 => x"00000413",
00000435 => x"00b78c63",
00000436 => x"00100413",
00000437 => x"00051863",
00000438 => x"00001537",
00000439 => x"ff050513",
00000440 => x"3e8000ef",
00000441 => x"00c12083",
00000442 => x"00040513",
00000443 => x"00812403",
00000444 => x"01010113",
00000445 => x"00008067",
00000446 => x"fd010113",
00000447 => x"02812423",
00000448 => x"02912223",
00000449 => x"03212023",
00000450 => x"01312e23",
00000451 => x"01412c23",
00000452 => x"02112623",
00000453 => x"01512a23",
00000454 => x"00001a37",
00000455 => x"00050493",
00000456 => x"00058413",
00000457 => x"00058523",
00000458 => x"00000993",
00000459 => x"00410913",
00000460 => x"088a0a13",
00000461 => x"00a00593",
00000462 => x"00048513",
00000463 => x"578000ef",
00000464 => x"00aa0533",
00000465 => x"00054783",
00000466 => x"01390ab3",
00000467 => x"00048513",
00000468 => x"00fa8023",
00000469 => x"00a00593",
00000470 => x"514000ef",
00000471 => x"00198993",
00000472 => x"00a00793",
00000473 => x"00050493",
00000474 => x"fcf996e3",
00000475 => x"00090693",
00000476 => x"00900713",
00000477 => x"03000613",
00000478 => x"0096c583",
00000479 => x"00070793",
00000480 => x"fff70713",
00000481 => x"01071713",
00000482 => x"01075713",
00000483 => x"00c59a63",
00000484 => x"000684a3",
00000485 => x"fff68693",
00000486 => x"fe0710e3",
00000487 => x"00000793",
00000488 => x"00f907b3",
00000489 => x"00000593",
00000490 => x"0007c703",
00000491 => x"00070c63",
00000492 => x"00158693",
00000493 => x"00b405b3",
00000494 => x"00e58023",
00000495 => x"01069593",
00000496 => x"0105d593",
00000497 => x"fff78713",
00000498 => x"02f91863",
00000499 => x"00b40433",
00000500 => x"00040023",
00000501 => x"02c12083",
00000502 => x"02812403",
00000503 => x"02412483",
00000504 => x"02012903",
00000505 => x"01c12983",
00000506 => x"01812a03",
00000507 => x"01412a83",
00000508 => x"03010113",
00000509 => x"00008067",
00000510 => x"00070793",
00000511 => x"fadff06f",
00000512 => x"00001637",
00000513 => x"00758693",
00000514 => x"00000713",
00000515 => x"09460613",
00000516 => x"02000813",
00000517 => x"00e557b3",
00000518 => x"00f7f793",
00000519 => x"00f607b3",
00000520 => x"0007c783",
00000521 => x"00470713",
00000522 => x"fff68693",
00000523 => x"00f680a3",
00000524 => x"ff0712e3",
00000525 => x"00058423",
00000526 => x"00008067",
00000527 => x"fa002023",
00000528 => x"fe002703",
00000529 => x"00151513",
00000530 => x"00000793",
00000531 => x"04a77463",
00000532 => x"000016b7",
00000533 => x"00000713",
00000534 => x"ffe68693",
00000535 => x"04f6e663",
00000536 => x"00367613",
00000537 => x"0035f593",
00000538 => x"fff78793",
00000539 => x"01461613",
00000540 => x"00c7e7b3",
00000541 => x"01659593",
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00000553 => x"fa9ff06f",
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00000555 => x"0fd57513",
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00000560 => x"f9dff06f",
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00000806 => x"00c5e663",
00000807 => x"40c585b3",
00000808 => x"00d56533",
00000809 => x"0016d693",
00000810 => x"00165613",
00000811 => x"fe0696e3",
00000812 => x"00008067",
00000813 => x"00008293",
00000814 => x"fb5ff0ef",
00000815 => x"00058513",
00000816 => x"00028067",
00000817 => x"40a00533",
00000818 => x"00b04863",
00000819 => x"40b005b3",
00000820 => x"f9dff06f",
00000748 => x"f8a02223",
00000749 => x"00008067",
00000750 => x"00050613",
00000751 => x"00000513",
00000752 => x"0015f693",
00000753 => x"00068463",
00000754 => x"00c50533",
00000755 => x"0015d593",
00000756 => x"00161613",
00000757 => x"fe0596e3",
00000758 => x"00008067",
00000759 => x"00050313",
00000760 => x"ff010113",
00000761 => x"00060513",
00000762 => x"00068893",
00000763 => x"00112623",
00000764 => x"00030613",
00000765 => x"00050693",
00000766 => x"00000713",
00000767 => x"00000793",
00000768 => x"00000813",
00000769 => x"0016fe13",
00000770 => x"00171e93",
00000771 => x"000e0c63",
00000772 => x"01060e33",
00000773 => x"010e3833",
00000774 => x"00e787b3",
00000775 => x"00f807b3",
00000776 => x"000e0813",
00000777 => x"01f65713",
00000778 => x"0016d693",
00000779 => x"00eee733",
00000780 => x"00161613",
00000781 => x"fc0698e3",
00000782 => x"00058663",
00000783 => x"f7dff0ef",
00000784 => x"00a787b3",
00000785 => x"00088a63",
00000786 => x"00030513",
00000787 => x"00088593",
00000788 => x"f69ff0ef",
00000789 => x"00f507b3",
00000790 => x"00c12083",
00000791 => x"00080513",
00000792 => x"00078593",
00000793 => x"01010113",
00000794 => x"00008067",
00000795 => x"06054063",
00000796 => x"0605c663",
00000797 => x"00058613",
00000798 => x"00050593",
00000799 => x"fff00513",
00000800 => x"02060c63",
00000801 => x"00100693",
00000802 => x"00b67a63",
00000803 => x"00c05863",
00000804 => x"00161613",
00000805 => x"00169693",
00000806 => x"feb66ae3",
00000807 => x"00000513",
00000808 => x"00c5e663",
00000809 => x"40c585b3",
00000810 => x"00d56533",
00000811 => x"0016d693",
00000812 => x"00165613",
00000813 => x"fe0696e3",
00000814 => x"00008067",
00000815 => x"00008293",
00000816 => x"fb5ff0ef",
00000817 => x"00058513",
00000818 => x"00028067",
00000819 => x"40a00533",
00000820 => x"00b04863",
00000821 => x"40b005b3",
00000822 => x"00008293",
00000823 => x"f91ff0ef",
00000824 => x"40a00533",
00000825 => x"00028067",
00000826 => x"00008293",
00000827 => x"0005ca63",
00000828 => x"00054c63",
00000829 => x"f79ff0ef",
00000830 => x"00058513",
00000831 => x"00028067",
00000832 => x"40b005b3",
00000833 => x"fe0558e3",
00000834 => x"40a00533",
00000835 => x"f61ff0ef",
00000836 => x"40b00533",
00000837 => x"00028067",
00000838 => x"6f727245",
00000839 => x"4e202172",
00000840 => x"5047206f",
00000841 => x"75204f49",
00000842 => x"2074696e",
00000843 => x"746e7973",
00000844 => x"69736568",
00000845 => x"2164657a",
00000846 => x"0000000a",
00000847 => x"6e696c42",
00000848 => x"676e696b",
00000849 => x"44454c20",
00000850 => x"6d656420",
00000851 => x"7270206f",
00000852 => x"6172676f",
00000853 => x"00000a6d",
00000854 => x"0000031c",
00000855 => x"00000328",
00000856 => x"00000334",
00000857 => x"00000340",
00000858 => x"0000034c",
00000859 => x"00000354",
00000860 => x"0000035c",
00000861 => x"00000364",
00000862 => x"0000036c",
00000863 => x"00000288",
00000864 => x"00000288",
00000865 => x"00000374",
00000866 => x"0000037c",
00000867 => x"00000288",
00000868 => x"00000288",
00000869 => x"00000288",
00000870 => x"00000384",
00000871 => x"00000288",
00000872 => x"00000288",
00000873 => x"00000288",
00000874 => x"0000038c",
00000875 => x"00000288",
00000876 => x"00000288",
00000877 => x"00000288",
00000878 => x"00000288",
00000879 => x"00000394",
00000880 => x"0000039c",
00000881 => x"000003a4",
00000882 => x"000003ac",
00000883 => x"000003b4",
00000884 => x"000003bc",
00000885 => x"000003c4",
00000886 => x"000003cc",
00000887 => x"000003d4",
00000888 => x"000003dc",
00000889 => x"000003e4",
00000890 => x"000003ec",
00000891 => x"000003f4",
00000892 => x"000003fc",
00000893 => x"00000404",
00000894 => x"0000040c",
00000895 => x"00007830",
00000896 => x"4554523c",
00000897 => x"0000203e",
00000898 => x"74736e49",
00000899 => x"74637572",
00000900 => x"206e6f69",
00000901 => x"72646461",
00000902 => x"20737365",
00000903 => x"6173696d",
00000904 => x"6e67696c",
00000905 => x"00006465",
00000906 => x"74736e49",
00000907 => x"74637572",
00000908 => x"206e6f69",
00000909 => x"65636361",
00000910 => x"66207373",
00000911 => x"746c7561",
00000912 => x"00000000",
00000913 => x"656c6c49",
00000914 => x"206c6167",
00000915 => x"74736e69",
00000916 => x"74637572",
00000917 => x"006e6f69",
00000918 => x"61657242",
00000919 => x"696f706b",
00000920 => x"0000746e",
00000921 => x"64616f4c",
00000922 => x"64646120",
00000923 => x"73736572",
00000924 => x"73696d20",
00000925 => x"67696c61",
00000926 => x"0064656e",
00000927 => x"64616f4c",
00000928 => x"63636120",
00000929 => x"20737365",
00000930 => x"6c756166",
00000931 => x"00000074",
00000932 => x"726f7453",
00000933 => x"64612065",
00000934 => x"73657264",
00000935 => x"696d2073",
00000936 => x"696c6173",
00000937 => x"64656e67",
00000938 => x"00000000",
00000939 => x"726f7453",
00000940 => x"63612065",
00000941 => x"73736563",
00000942 => x"75616620",
00000943 => x"0000746c",
00000944 => x"69766e45",
00000945 => x"6d6e6f72",
00000946 => x"20746e65",
00000947 => x"6c6c6163",
00000948 => x"6f726620",
00000949 => x"2d55206d",
00000950 => x"65646f6d",
00000951 => x"00000000",
00000952 => x"69766e45",
00000953 => x"6d6e6f72",
00000954 => x"20746e65",
00000955 => x"6c6c6163",
00000956 => x"6f726620",
00000957 => x"2d4d206d",
00000958 => x"65646f6d",
00000959 => x"00000000",
00000960 => x"6863614d",
00000961 => x"20656e69",
00000962 => x"74666f73",
00000963 => x"65726177",
00000964 => x"746e6920",
00000965 => x"75727265",
00000966 => x"00007470",
00000967 => x"6863614d",
00000968 => x"20656e69",
00000969 => x"656d6974",
00000970 => x"6e692072",
00000971 => x"72726574",
00000972 => x"00747075",
00000973 => x"6863614d",
00000974 => x"20656e69",
00000975 => x"65747865",
00000976 => x"6c616e72",
00000977 => x"746e6920",
00000978 => x"75727265",
00000979 => x"00007470",
00000980 => x"74736146",
00000981 => x"746e6920",
00000982 => x"75727265",
00000983 => x"00207470",
00000984 => x"6e6b6e55",
00000985 => x"206e776f",
00000986 => x"70617274",
00000987 => x"75616320",
00000988 => x"203a6573",
00000989 => x"00000000",
00000990 => x"50204020",
00000991 => x"00003d43",
00000992 => x"544d202c",
00000993 => x"3d4c4156",
00000994 => x"00000000",
00000995 => x"00000540",
00000996 => x"00000590",
00000997 => x"0000059c",
00000998 => x"000005a8",
00000999 => x"000005b4",
00001000 => x"000005c0",
00001001 => x"000005cc",
00001002 => x"000005d8",
00001003 => x"000005e4",
00001004 => x"00000500",
00001005 => x"00000500",
00001006 => x"000005f0",
00001007 => x"4554523c",
00001008 => x"4157203e",
00001009 => x"4e494e52",
00001010 => x"43202147",
00001011 => x"43205550",
00001012 => x"73205253",
00001013 => x"65747379",
00001014 => x"6f6e206d",
00001015 => x"76612074",
00001016 => x"616c6961",
00001017 => x"21656c62",
00001018 => x"522f3c20",
00001019 => x"003e4554",
00001020 => x"5241570a",
00001021 => x"474e494e",
00001022 => x"57532021",
00001023 => x"4153495f",
00001024 => x"65662820",
00001025 => x"72757461",
00001026 => x"72207365",
00001027 => x"69757165",
00001028 => x"29646572",
00001029 => x"20737620",
00001030 => x"495f5748",
00001031 => x"28204153",
00001032 => x"74616566",
00001033 => x"73657275",
00001034 => x"61766120",
00001035 => x"62616c69",
00001036 => x"2029656c",
00001037 => x"6d73696d",
00001038 => x"68637461",
00001039 => x"57530a21",
00001040 => x"4153495f",
00001041 => x"30203d20",
00001042 => x"20782578",
00001043 => x"6d6f6328",
00001044 => x"656c6970",
00001045 => x"6c662072",
00001046 => x"29736761",
00001047 => x"5f57480a",
00001048 => x"20415349",
00001049 => x"7830203d",
00001050 => x"28207825",
00001051 => x"6173696d",
00001052 => x"72736320",
00001053 => x"000a0a29",
00001054 => x"33323130",
00001055 => x"37363534",
00001056 => x"42413938",
00001057 => x"46454443",
00001058 => x"33323130",
00001059 => x"37363534",
00001060 => x"00003938",
00001061 => x"33323130",
00001062 => x"37363534",
00001063 => x"62613938",
00001064 => x"66656463",
00001065 => x"00000000",
00000822 => x"f9dff06f",
00000823 => x"40b005b3",
00000824 => x"00008293",
00000825 => x"f91ff0ef",
00000826 => x"40a00533",
00000827 => x"00028067",
00000828 => x"00008293",
00000829 => x"0005ca63",
00000830 => x"00054c63",
00000831 => x"f79ff0ef",
00000832 => x"00058513",
00000833 => x"00028067",
00000834 => x"40b005b3",
00000835 => x"fe0558e3",
00000836 => x"40a00533",
00000837 => x"f61ff0ef",
00000838 => x"40b00533",
00000839 => x"00028067",
00000840 => x"6f727245",
00000841 => x"4e202172",
00000842 => x"5047206f",
00000843 => x"75204f49",
00000844 => x"2074696e",
00000845 => x"746e7973",
00000846 => x"69736568",
00000847 => x"2164657a",
00000848 => x"0000000a",
00000849 => x"6e696c42",
00000850 => x"676e696b",
00000851 => x"44454c20",
00000852 => x"6d656420",
00000853 => x"7270206f",
00000854 => x"6172676f",
00000855 => x"00000a6d",
00000856 => x"33323130",
00000857 => x"37363534",
00000858 => x"00003938",
00000859 => x"33323130",
00000860 => x"37363534",
00000861 => x"62613938",
00000862 => x"66656463",
00000863 => x"00000000",
00000864 => x"000007c0",
00000865 => x"000007cc",
00000866 => x"000007d8",
00000867 => x"000007e4",
00000868 => x"000007f0",
00000869 => x"000007f8",
00000870 => x"00000800",
00000871 => x"00000808",
00000872 => x"00000810",
00000873 => x"00000728",
00000874 => x"00000728",
00000875 => x"00000818",
00000876 => x"00000820",
00000877 => x"00000728",
00000878 => x"00000728",
00000879 => x"00000728",
00000880 => x"00000828",
00000881 => x"00000728",
00000882 => x"00000728",
00000883 => x"00000728",
00000884 => x"00000830",
00000885 => x"00000728",
00000886 => x"00000728",
00000887 => x"00000728",
00000888 => x"00000728",
00000889 => x"00000838",
00000890 => x"00000840",
00000891 => x"00000848",
00000892 => x"00000850",
00000893 => x"00000858",
00000894 => x"00000860",
00000895 => x"00000868",
00000896 => x"00000870",
00000897 => x"00000878",
00000898 => x"00000880",
00000899 => x"00000888",
00000900 => x"00000890",
00000901 => x"00000898",
00000902 => x"000008a0",
00000903 => x"000008a8",
00000904 => x"000008b0",
00000905 => x"00007830",
00000906 => x"4554523c",
00000907 => x"0000203e",
00000908 => x"74736e49",
00000909 => x"74637572",
00000910 => x"206e6f69",
00000911 => x"72646461",
00000912 => x"20737365",
00000913 => x"6173696d",
00000914 => x"6e67696c",
00000915 => x"00006465",
00000916 => x"74736e49",
00000917 => x"74637572",
00000918 => x"206e6f69",
00000919 => x"65636361",
00000920 => x"66207373",
00000921 => x"746c7561",
00000922 => x"00000000",
00000923 => x"656c6c49",
00000924 => x"206c6167",
00000925 => x"74736e69",
00000926 => x"74637572",
00000927 => x"006e6f69",
00000928 => x"61657242",
00000929 => x"696f706b",
00000930 => x"0000746e",
00000931 => x"64616f4c",
00000932 => x"64646120",
00000933 => x"73736572",
00000934 => x"73696d20",
00000935 => x"67696c61",
00000936 => x"0064656e",
00000937 => x"64616f4c",
00000938 => x"63636120",
00000939 => x"20737365",
00000940 => x"6c756166",
00000941 => x"00000074",
00000942 => x"726f7453",
00000943 => x"64612065",
00000944 => x"73657264",
00000945 => x"696d2073",
00000946 => x"696c6173",
00000947 => x"64656e67",
00000948 => x"00000000",
00000949 => x"726f7453",
00000950 => x"63612065",
00000951 => x"73736563",
00000952 => x"75616620",
00000953 => x"0000746c",
00000954 => x"69766e45",
00000955 => x"6d6e6f72",
00000956 => x"20746e65",
00000957 => x"6c6c6163",
00000958 => x"6f726620",
00000959 => x"2d55206d",
00000960 => x"65646f6d",
00000961 => x"00000000",
00000962 => x"69766e45",
00000963 => x"6d6e6f72",
00000964 => x"20746e65",
00000965 => x"6c6c6163",
00000966 => x"6f726620",
00000967 => x"2d4d206d",
00000968 => x"65646f6d",
00000969 => x"00000000",
00000970 => x"6863614d",
00000971 => x"20656e69",
00000972 => x"74666f73",
00000973 => x"65726177",
00000974 => x"746e6920",
00000975 => x"75727265",
00000976 => x"00007470",
00000977 => x"6863614d",
00000978 => x"20656e69",
00000979 => x"656d6974",
00000980 => x"6e692072",
00000981 => x"72726574",
00000982 => x"00747075",
00000983 => x"6863614d",
00000984 => x"20656e69",
00000985 => x"65747865",
00000986 => x"6c616e72",
00000987 => x"746e6920",
00000988 => x"75727265",
00000989 => x"00007470",
00000990 => x"74736146",
00000991 => x"746e6920",
00000992 => x"75727265",
00000993 => x"00207470",
00000994 => x"6e6b6e55",
00000995 => x"206e776f",
00000996 => x"70617274",
00000997 => x"75616320",
00000998 => x"203a6573",
00000999 => x"00000000",
00001000 => x"50204020",
00001001 => x"00003d43",
00001002 => x"544d202c",
00001003 => x"3d4c4156",
00001004 => x"00000000",
00001005 => x"000009e4",
00001006 => x"00000a34",
00001007 => x"00000a40",
00001008 => x"00000a4c",
00001009 => x"00000a58",
00001010 => x"00000a64",
00001011 => x"00000a70",
00001012 => x"00000a7c",
00001013 => x"00000a88",
00001014 => x"000009a4",
00001015 => x"000009a4",
00001016 => x"00000a94",
00001017 => x"4554523c",
00001018 => x"4157203e",
00001019 => x"4e494e52",
00001020 => x"43202147",
00001021 => x"43205550",
00001022 => x"73205253",
00001023 => x"65747379",
00001024 => x"6f6e206d",
00001025 => x"76612074",
00001026 => x"616c6961",
00001027 => x"21656c62",
00001028 => x"522f3c20",
00001029 => x"003e4554",
00001030 => x"5241570a",
00001031 => x"474e494e",
00001032 => x"57532021",
00001033 => x"4153495f",
00001034 => x"65662820",
00001035 => x"72757461",
00001036 => x"72207365",
00001037 => x"69757165",
00001038 => x"29646572",
00001039 => x"20737620",
00001040 => x"495f5748",
00001041 => x"28204153",
00001042 => x"74616566",
00001043 => x"73657275",
00001044 => x"61766120",
00001045 => x"62616c69",
00001046 => x"2029656c",
00001047 => x"6d73696d",
00001048 => x"68637461",
00001049 => x"57530a21",
00001050 => x"4153495f",
00001051 => x"30203d20",
00001052 => x"20782578",
00001053 => x"6d6f6328",
00001054 => x"656c6970",
00001055 => x"6c662072",
00001056 => x"29736761",
00001057 => x"5f57480a",
00001058 => x"20415349",
00001059 => x"7830203d",
00001060 => x"28207825",
00001061 => x"6173696d",
00001062 => x"72736320",
00001063 => x"000a0a29",
00001064 => x"33323130",
00001065 => x"37363534",
00001066 => x"42413938",
00001067 => x"46454443",
others => x"00000000"
);
 
/rtl/core/neorv32_bootloader_image.vhd
6,7 → 6,7
 
package neorv32_bootloader_image is
 
type bootloader_init_image_t is array (0 to 1003) of std_ulogic_vector(31 downto 0);
type bootloader_init_image_t is array (0 to 1009) of std_ulogic_vector(31 downto 0);
constant bootloader_init_image : bootloader_init_image_t := (
00000000 => x"00000093",
00000001 => x"00000113",
44,7 → 44,7
00000033 => x"00158593",
00000034 => x"ff5ff06f",
00000035 => x"00001597",
00000036 => x"f2058593",
00000036 => x"f3858593",
00000037 => x"80010617",
00000038 => x"f6c60613",
00000039 => x"80010697",
111,22 → 111,22
00000100 => x"00200513",
00000101 => x"0087f463",
00000102 => x"00400513",
00000103 => x"359000ef",
00000103 => x"36d000ef",
00000104 => x"00100513",
00000105 => x"3f9000ef",
00000105 => x"40d000ef",
00000106 => x"00005537",
00000107 => x"00000613",
00000108 => x"00000593",
00000109 => x"b0050513",
00000110 => x"295000ef",
00000111 => x"1b1000ef",
00000110 => x"2a9000ef",
00000111 => x"1c5000ef",
00000112 => x"00245793",
00000113 => x"00a78533",
00000114 => x"00f537b3",
00000115 => x"00b785b3",
00000116 => x"1c9000ef",
00000116 => x"1dd000ef",
00000117 => x"ffff07b7",
00000118 => x"4c078793",
00000118 => x"4d478793",
00000119 => x"30579073",
00000120 => x"08000793",
00000121 => x"30479073",
134,883 → 134,889
00000123 => x"00000013",
00000124 => x"00000013",
00000125 => x"ffff1537",
00000126 => x"ec850513",
00000127 => x"2f5000ef",
00000126 => x"edc50513",
00000127 => x"309000ef",
00000128 => x"f1302573",
00000129 => x"24c000ef",
00000129 => x"260000ef",
00000130 => x"ffff1537",
00000131 => x"f0050513",
00000132 => x"2e1000ef",
00000131 => x"f1450513",
00000132 => x"2f5000ef",
00000133 => x"fe002503",
00000134 => x"238000ef",
00000134 => x"24c000ef",
00000135 => x"ffff1537",
00000136 => x"f0850513",
00000137 => x"2cd000ef",
00000136 => x"f1c50513",
00000137 => x"2e1000ef",
00000138 => x"fe402503",
00000139 => x"224000ef",
00000139 => x"238000ef",
00000140 => x"ffff1537",
00000141 => x"f1450513",
00000142 => x"2b9000ef",
00000141 => x"f2450513",
00000142 => x"2cd000ef",
00000143 => x"30102573",
00000144 => x"210000ef",
00000144 => x"224000ef",
00000145 => x"ffff1537",
00000146 => x"f1c50513",
00000147 => x"2a5000ef",
00000148 => x"fe802503",
00000149 => x"ffff14b7",
00000150 => x"00341413",
00000151 => x"1f4000ef",
00000152 => x"ffff1537",
00000153 => x"f2450513",
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00000982 => x"2079656b",
00000983 => x"61206f74",
00000984 => x"74726f62",
00000985 => x"00000a2e",
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00000924 => x"32337672",
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00000928 => x"00000000",
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00000935 => x"78302065",
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00000942 => x"78302040",
00000943 => x"00000000",
00000944 => x"7928203f",
00000945 => x"20296e2f",
00000946 => x"00000000",
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00000950 => x"00000020",
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00000963 => x"3a565748",
00000964 => x"00002020",
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00000966 => x"0020203a",
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00000982 => x"75410a0a",
00000983 => x"6f626f74",
00000984 => x"6920746f",
00000985 => x"7338206e",
00000986 => x"7250202e",
00000987 => x"20737365",
00000988 => x"2079656b",
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00000990 => x"74726f62",
00000991 => x"00000a2e",
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00000993 => x"2e646574",
00000994 => x"00000a0a",
00000995 => x"444d430a",
00000996 => x"00203e3a",
00000997 => x"53207962",
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00000999 => x"4e206e61",
00001000 => x"69746c6f",
00001001 => x"0000676e",
00001002 => x"61766e49",
00001003 => x"2064696c",
00001004 => x"00444d43",
00001005 => x"33323130",
00001006 => x"37363534",
00001007 => x"42413938",
00001008 => x"46454443",
others => x"00000000"
);
 
/rtl/core/neorv32_cpu.vhd
73,7 → 73,7
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0 -- number of implemented HPM counters (0..29)
185,8 → 185,8
-- FIXME: Bit manipulation warning --
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still HIGHLY EXPERIMENTAL (and spec. is not ratified yet)." severity warning;
 
-- FIXME: Floating-point extension (Zfinx) warning --
assert not (CPU_EXTENSION_RISCV_Zfinx = true) report "NEORV32 CPU CONFIG WARNING! 32-bit floating-point extension (F/Zfinx) is WORK-IN-PROGRESS and NOT OPERATIONAL yet." severity warning;
-- Co-processor timeout counter (for debugging only) --
assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
 
-- PMP regions check --
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out xf valid range (0..64)." severity error;
/rtl/core/neorv32_cpu_alu.vhd
97,11 → 97,12
 
-- co-processor arbiter and interface --
type cp_ctrl_t is record
cmd : std_ulogic;
cmd_ff : std_ulogic;
busy : std_ulogic;
start : std_ulogic;
halt : std_ulogic;
cmd : std_ulogic;
cmd_ff : std_ulogic;
busy : std_ulogic;
start : std_ulogic;
halt : std_ulogic;
timeout : std_ulogic_vector(9 downto 0);
end record;
signal cp_ctrl : cp_ctrl_t;
 
275,15 → 276,25
cp_arbiter: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
cp_ctrl.cmd_ff <= '0';
cp_ctrl.busy <= '0';
cp_ctrl.cmd_ff <= '0';
cp_ctrl.busy <= '0';
cp_ctrl.timeout <= (others => '0');
elsif rising_edge(clk_i) then
cp_ctrl.cmd_ff <= cp_ctrl.cmd;
if (or_all_f(cp_valid_i) = '1') then -- cp computation done?
cp_ctrl.busy <= '0';
elsif (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout
assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning;
cp_ctrl.busy <= '0';
elsif (cp_ctrl.start = '1') then
cp_ctrl.busy <= '1';
end if;
-- timeout counter --
if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then
cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1);
else
cp_ctrl.timeout <= (others => '0');
end if;
end if;
end process cp_arbiter;
 
/rtl/core/neorv32_cpu_control.vhd
1090,7 → 1090,7
 
when opcode_fop_c => -- floating-point operations
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zfinx = true) then
if (CPU_EXTENSION_RISCV_Zfinx = true) and (decode_aux.is_float_op = '1') then
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- use FPU CP
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
2110,7 → 2110,7
 
-- floating-point (FPU) exception flags --
-- --------------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zfinx = true) and (execute_engine.state = ALU_WAIT) then
if (CPU_EXTENSION_RISCV_Zfinx = true) then
csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags")
end if;
 
/rtl/core/neorv32_cpu_cp_fpu.vhd
1,19 → 1,22
-- #################################################################################################
-- # << NEORV32 - CPU Co-Processor: Single-Prec. Floating Point Unit (RISC-V "Zfinx" Extension) >> #
-- # ********************************************************************************************* #
-- # #
-- # !!! WORK-IN-PROGRESS !!! #
-- # !!! THIS UNIT IS NOT FUNCTIONAL YET !!! #
-- # #
-- # ********************************************************************************************* #
-- # The Zfinx floating-point extension uses the integer register file (x) for all FP operations. #
-- # See the official RISC-V specs (https://github.com/riscv/riscv-zfinx) for more information. #
-- # #
-- # Design Notes: #
-- # * This FPU is based on a multi-cycle architecture and is NOT suited for pipelined operations. #
-- # * The hardware design goal was SIZE (performance comes second). All shift operations are done #
-- # using an iterative approach (one bit per clock cycle, no barrel shifters!). #
-- # * Multiplication (FMUL instruction) will infer DSP blocks (if available). #
-- # * Subnormal numbers are not supported yet - they are "flushed to zero" before entering the #
-- # actual FPU core. #
-- # * Division and sqare root operations (FDIV, FSQRT) and fused multiply-accumulate operations #
-- # (F[N]MADD) are not supported yet - they will raise an illegal instruction exception. #
-- # * Rounding mode <100> ("round to nearest, ties to max magnitude") is not supported yet. #
-- # * Signaling NaNs (sNaN) will not be generated by the hardware at all. However, if inserted by #
-- # the programmer they are handled correctly. #
-- # ********************************************************************************************* #
-- # !! Enabling the Zfinx extension does not has an effect on the CPU. If F is enabled, there !! #
-- # !! will be no traps when trying to execute floating-point instructions, since the main !! #
-- # !! CPU control unit allready provides all necessary Zfinx-extension infrastructure. !! #
-- # !! However, all Zfinx instructions will always return zero. !! #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
72,13 → 75,1727
 
architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is
 
-- FPU core functions --
constant op_class_c : std_ulogic_vector(2 downto 0) := "000";
constant op_comp_c : std_ulogic_vector(2 downto 0) := "001";
constant op_i2f_c : std_ulogic_vector(2 downto 0) := "010";
constant op_f2i_c : std_ulogic_vector(2 downto 0) := "011";
constant op_sgnj_c : std_ulogic_vector(2 downto 0) := "100";
constant op_minmax_c : std_ulogic_vector(2 downto 0) := "101";
constant op_addsub_c : std_ulogic_vector(2 downto 0) := "110";
constant op_mul_c : std_ulogic_vector(2 downto 0) := "111";
 
-- float-to-integer unit --
component neorv32_cpu_cp_fpu_f2i
port (
-- control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
start_i : in std_ulogic; -- trigger operation
rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode
funct_i : in std_ulogic; -- 0=signed, 1=unsigned
-- input --
sign_i : in std_ulogic; -- sign
exponent_i : in std_ulogic_vector(07 downto 0); -- exponent
mantissa_i : in std_ulogic_vector(22 downto 0); -- mantissa
class_i : in std_ulogic_vector(09 downto 0); -- operand class
-- output --
result_o : out std_ulogic_vector(31 downto 0); -- integer result
flags_o : out std_ulogic_vector(04 downto 0); -- exception flags
done_o : out std_ulogic -- operation done
);
end component;
 
-- normalizer + rounding unit --
component neorv32_cpu_cp_fpu_normalizer
port (
-- control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
start_i : in std_ulogic; -- trigger operation
rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode
funct_i : in std_ulogic; -- operating mode (0=norm&round, 1=int-to-float)
-- input --
sign_i : in std_ulogic; -- sign
exponent_i : in std_ulogic_vector(08 downto 0); -- extended exponent
mantissa_i : in std_ulogic_vector(47 downto 0); -- extended mantissa
integer_i : in std_ulogic_vector(31 downto 0); -- integer input
class_i : in std_ulogic_vector(09 downto 0); -- input number class
flags_i : in std_ulogic_vector(04 downto 0); -- exception flags input
-- output --
result_o : out std_ulogic_vector(31 downto 0); -- result (float or int)
flags_o : out std_ulogic_vector(04 downto 0); -- exception flags
done_o : out std_ulogic -- operation done
);
end component;
 
-- commands (one-hot) --
type cmd_t is record
instr_class : std_ulogic;
instr_sgnj : std_ulogic;
instr_comp : std_ulogic;
instr_i2f : std_ulogic;
instr_f2i : std_ulogic;
instr_minmax : std_ulogic;
instr_addsub : std_ulogic;
instr_mul : std_ulogic;
funct : std_ulogic_vector(2 downto 0);
end record;
signal cmd : cmd_t;
signal funct_ff : std_ulogic_vector(2 downto 0);
 
-- co-processor control engine --
type ctrl_state_t is (S_IDLE, S_BUSY);
type ctrl_engine_t is record
state : ctrl_state_t;
start : std_ulogic;
valid : std_ulogic;
end record;
signal ctrl_engine : ctrl_engine_t;
 
-- floating-point operands --
type op_data_t is array (0 to 1) of std_ulogic_vector(31 downto 0);
type op_class_t is array (0 to 1) of std_ulogic_vector(09 downto 0);
type fpu_operands_t is record
rs1 : std_ulogic_vector(31 downto 0); -- operand 1
rs1_class : std_ulogic_vector(09 downto 0); -- operand 1 number class
rs2 : std_ulogic_vector(31 downto 0); -- operand 2
rs2_class : std_ulogic_vector(09 downto 0); -- operand 2 number class
frm : std_ulogic_vector(02 downto 0); -- rounding mode
end record;
signal op_data : op_data_t;
signal op_class : op_class_t;
signal fpu_operands : fpu_operands_t;
 
-- floating-point comparator --
signal comp_equal_ff : std_ulogic;
signal comp_less_ff : std_ulogic;
signal comp_less : std_ulogic;
 
-- functional units interface --
type fu_interface_t is record
result : std_ulogic_vector(31 downto 0);
flags : std_ulogic_vector(04 downto 0);
start : std_ulogic;
done : std_ulogic;
end record;
signal fu_classify : fu_interface_t;
signal fu_compare : fu_interface_t;
signal fu_sign_inject : fu_interface_t;
signal fu_min_max : fu_interface_t;
signal fu_conv_f2i : fu_interface_t;
signal fu_addsub : fu_interface_t;
signal fu_mul : fu_interface_t;
signal fu_core_done : std_ulogic; -- FU operation completed
 
-- integer-to-float --
type fu_i2f_interface_t is record
result : std_ulogic_vector(31 downto 0);
sign : std_ulogic;
start : std_ulogic;
done : std_ulogic;
end record;
signal fu_conv_i2f : fu_i2f_interface_t; -- float result
 
-- multiplier unit --
type multiplier_t is record
opa : unsigned(23 downto 0); -- mantissa A plus hidden one
opb : unsigned(23 downto 0); -- mantissa B plus hidden one
buf_ff : unsigned(47 downto 0); -- product buffer
sign : std_ulogic; -- resulting sign
product : std_ulogic_vector(47 downto 0); -- product
exp_sum : std_ulogic_vector(08 downto 0); -- incl 1x overflow/underflow bit
exp_res : std_ulogic_vector(09 downto 0); -- resulting exponent incl 2x overflow/underflow bit
--
res_class : std_ulogic_vector(09 downto 0);
flags : std_ulogic_vector(04 downto 0); -- exception flags
--
start : std_ulogic;
latency : std_ulogic_vector(02 downto 0); -- unit latency
done : std_ulogic;
end record;
signal multiplier : multiplier_t;
 
-- adder/subtractor unit --
type addsub_t is record
-- input comparison --
exp_comp : std_ulogic_vector(01 downto 0); -- equal & less
small_exp : std_ulogic_vector(07 downto 0);
small_man : std_ulogic_vector(23 downto 0); -- mantissa + hiden one
large_exp : std_ulogic_vector(07 downto 0);
large_man : std_ulogic_vector(23 downto 0); -- mantissa + hiden one
-- smaller mantissa alginment --
man_sreg : std_ulogic_vector(23 downto 0); -- mantissa + hidden one
man_g_ext : std_ulogic;
man_r_ext : std_ulogic;
man_s_ext : std_ulogic;
exp_cnt : std_ulogic_vector(08 downto 0);
-- adder/subtractor stage --
man_comp : std_ulogic;
man_s : std_ulogic_vector(26 downto 0); -- mantissa + hiden one + GRS
man_l : std_ulogic_vector(26 downto 0); -- mantissa + hiden one + GRS
add_stage : std_ulogic_vector(27 downto 0); -- adder result incl. overflow
-- result --
res_sign : std_ulogic;
res_sum : std_ulogic_vector(27 downto 0); -- mantissa sum (+1 bit) + GRS bits (for rounding)
res_class : std_ulogic_vector(09 downto 0);
flags : std_ulogic_vector(04 downto 0); -- exception flags
-- arbitration --
start : std_ulogic;
latency : std_ulogic_vector(04 downto 0); -- unit latency
done : std_ulogic;
end record;
signal addsub : addsub_t;
 
-- normalizer interface (normalization & rounding and int-to-float) --
type normalizer_t is record
start : std_ulogic;
mode : std_ulogic;
sign : std_ulogic;
xexp : std_ulogic_vector(08 downto 0);
xmantissa : std_ulogic_vector(47 downto 0);
result : std_ulogic_vector(31 downto 0);
class : std_ulogic_vector(09 downto 0);
flags_in : std_ulogic_vector(04 downto 0);
flags_out : std_ulogic_vector(04 downto 0);
done : std_ulogic;
end record;
signal normalizer : normalizer_t;
 
begin
 
-- There is nothing to see here yet -------------------------------------------------------
-- ****************************************************************************************************************************
-- Control
-- ****************************************************************************************************************************
 
-- Instruction Decoding -------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
res_o <= (others => '0');
fflags_o <= (others => '0');
valid_o <= start_i;
-- one-hot re-encoding --
cmd.instr_class <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11100") else '0';
cmd.instr_comp <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "10100") else '0';
cmd.instr_i2f <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11010") else '0';
cmd.instr_f2i <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "11000") else '0';
cmd.instr_sgnj <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00100") else '0';
cmd.instr_minmax <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00101") else '0';
cmd.instr_addsub <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_8_c) = "0000") else '0';
cmd.instr_mul <= '1' when (ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_7_c) = "00010") else '0';
 
-- binary re-encoding --
cmd.funct <= op_mul_c when (cmd.instr_mul = '1') else
op_addsub_c when (cmd.instr_addsub = '1') else
op_minmax_c when (cmd.instr_minmax = '1') else
op_sgnj_c when (cmd.instr_sgnj = '1') else
op_f2i_c when (cmd.instr_f2i = '1') else
op_i2f_c when (cmd.instr_i2f = '1') else
op_comp_c when (cmd.instr_comp = '1') else
op_class_c;--when (cmd.instr_class = '1') else (others => '-');
 
 
-- Input Operands: Check for subnormal numbers (flush to zero) ----------------------------
-- -------------------------------------------------------------------------------------------
-- Subnormal numbers are not supported and are "flushed to zero"! FIXME / TODO
-- rs1 --
op_data(0)(31) <= rs1_i(31);
op_data(0)(30 downto 23) <= rs1_i(30 downto 23);
op_data(0)(22 downto 00) <= (others => '0') when (rs1_i(30 downto 23) = "00000000") else rs1_i(22 downto 0); -- flush mantissa to zero if subnormal
-- rs2 --
op_data(1)(31) <= rs2_i(31);
op_data(1)(30 downto 23) <= rs2_i(30 downto 23);
op_data(1)(22 downto 00) <= (others => '0') when (rs2_i(30 downto 23) = "00000000") else rs2_i(22 downto 0); -- flush mantissa to zero if subnormal
 
 
-- Number Classifier ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
number_classifier: process(op_data)
variable op_m_all_zero_v, op_e_all_zero_v, op_e_all_one_v : std_ulogic;
variable op_is_zero_v, op_is_inf_v, op_is_denorm_v, op_is_nan_v : std_ulogic;
begin
for i in 0 to 1 loop -- for rs1 and rs2 inputs
-- check for all-zero/all-one --
op_m_all_zero_v := not or_all_f(op_data(i)(22 downto 00));
op_e_all_zero_v := not or_all_f(op_data(i)(30 downto 23));
op_e_all_one_v := and_all_f(op_data(i)(30 downto 23));
 
-- check special cases --
op_is_zero_v := op_e_all_zero_v and op_m_all_zero_v; -- zero
op_is_inf_v := op_e_all_one_v and op_m_all_zero_v; -- infinity
op_is_denorm_v := '0'; -- FIXME / TODO op_e_all_zero_v and (not op_m_all_zero_v); -- subnormal
op_is_nan_v := op_e_all_one_v and (not op_m_all_zero_v); -- NaN
 
-- actual attributes --
op_class(i)(fp_class_neg_inf_c) <= op_data(i)(31) and op_is_inf_v; -- negative infinity
op_class(i)(fp_class_neg_norm_c) <= op_data(i)(31) and (not op_is_denorm_v) and (not op_is_nan_v) and (not op_is_inf_v) and (not op_is_zero_v); -- negative normal number
op_class(i)(fp_class_neg_denorm_c) <= op_data(i)(31) and op_is_denorm_v; -- negative subnormal number
op_class(i)(fp_class_neg_zero_c) <= op_data(i)(31) and op_is_zero_v; -- negative zero
op_class(i)(fp_class_pos_zero_c) <= (not op_data(i)(31)) and op_is_zero_v; -- positive zero
op_class(i)(fp_class_pos_denorm_c) <= (not op_data(i)(31)) and op_is_denorm_v; -- positive subnormal number
op_class(i)(fp_class_pos_norm_c) <= (not op_data(i)(31)) and (not op_is_denorm_v) and (not op_is_nan_v) and (not op_is_inf_v) and (not op_is_zero_v); -- positive normal number
op_class(i)(fp_class_pos_inf_c) <= (not op_data(i)(31)) and op_is_inf_v; -- positive infinity
op_class(i)(fp_class_snan_c) <= op_is_nan_v and (not op_data(i)(22)); -- signaling NaN
op_class(i)(fp_class_qnan_c) <= op_is_nan_v and ( op_data(i)(22)); -- quiet NaN
end loop; -- i
end process number_classifier;
 
 
-- Co-Processor Control Engine ------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
control_engine_fsm: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl_engine.state <= S_IDLE;
ctrl_engine.start <= '0';
fpu_operands.frm <= (others => '0');
fpu_operands.rs1 <= (others => '0');
fpu_operands.rs1_class <= (others => '0');
fpu_operands.rs2 <= (others => '0');
fpu_operands.rs2_class <= (others => '0');
funct_ff <= (others => '0');
elsif rising_edge(clk_i) then
-- arbiter defaults --
ctrl_engine.valid <= '0';
ctrl_engine.start <= '0';
 
-- state machine --
case ctrl_engine.state is
 
when S_IDLE => -- waiting for operation trigger
-- ------------------------------------------------------------
funct_ff <= cmd.funct; -- actual operation to execute
-- rounding mode --
-- TODO / FIXME "round to nearest, ties to max magnitude" (0b100) is not supported yet
if (ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) = "111") then
fpu_operands.frm <= '0' & frm_i(1 downto 0);
else
fpu_operands.frm <= '0' & ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c);
end if;
--
if (start_i = '1') then
-- operand data --
fpu_operands.rs1 <= op_data(0);
fpu_operands.rs1_class <= op_class(0);
fpu_operands.rs2 <= op_data(1);
fpu_operands.rs2_class <= op_class(1);
-- execute! --
ctrl_engine.start <= '1';
ctrl_engine.state <= S_BUSY;
end if;
 
when S_BUSY => -- operation in progress (multi-cycle)
-- -----------------------------------------------------------
if (fu_core_done = '1') then -- processing done?
ctrl_engine.valid <= '1';
ctrl_engine.state <= S_IDLE;
end if;
 
when others => -- undefined
-- ------------------------------------------------------------
ctrl_engine.state <= S_IDLE;
 
end case;
end if;
end process control_engine_fsm;
 
-- operation done / valid output --
valid_o <= ctrl_engine.valid;
 
 
-- Functional Unit Interface (operation-start trigger) ------------------------------------
-- -------------------------------------------------------------------------------------------
fu_classify.start <= ctrl_engine.start and cmd.instr_class;
fu_compare.start <= ctrl_engine.start and cmd.instr_comp;
fu_sign_inject.start <= ctrl_engine.start and cmd.instr_sgnj;
fu_min_max.start <= ctrl_engine.start and cmd.instr_minmax;
fu_conv_i2f.start <= ctrl_engine.start and cmd.instr_i2f;
fu_conv_f2i.start <= ctrl_engine.start and cmd.instr_f2i;
fu_addsub.start <= ctrl_engine.start and cmd.instr_addsub;
fu_mul.start <= ctrl_engine.start and cmd.instr_mul;
 
 
-- ****************************************************************************************************************************
-- FPU Core - Functional Units
-- ****************************************************************************************************************************
 
-- Number Classifier (FCLASS) -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
fu_classify.flags <= (others => '0'); -- does not generate flags at all
fu_classify.result(31 downto 10) <= (others => '0');
fu_classify.result(09 downto 00) <= fpu_operands.rs1_class;
fu_classify.done <= fu_classify.start;
 
 
-- Floating-Point Comparator --------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
float_comparator: process(clk_i)
variable cond_v : std_ulogic_vector(1 downto 0);
begin
if rising_edge(clk_i) then
-- equal --
if ((fpu_operands.rs1_class(fp_class_pos_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_inf_c) = '1')) or -- +inf == +inf
((fpu_operands.rs1_class(fp_class_neg_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_inf_c) = '1')) or -- -inf == -inf
(((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs1_class(fp_class_neg_zero_c) = '1')) and
((fpu_operands.rs2_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1'))) or -- +/-zero == +/-zero
(fpu_operands.rs1 = fpu_operands.rs2) then -- identical in every way
comp_equal_ff <= '1';
else
comp_equal_ff <= '0';
end if;
 
-- less than --
if ((fpu_operands.rs1_class(fp_class_pos_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_inf_c) = '1')) or -- +inf !< +inf
((fpu_operands.rs1_class(fp_class_neg_inf_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_inf_c) = '1')) or -- -inf !< -inf
(((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs1_class(fp_class_neg_zero_c) = '1')) and
((fpu_operands.rs2_class(fp_class_pos_zero_c) = '1') or (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1'))) then -- +/-zero !< +/-zero
comp_less_ff <= '0';
else
cond_v := fpu_operands.rs1(31) & fpu_operands.rs2(31);
case cond_v is
when "10" => comp_less_ff <= '1'; -- rs1 negative, rs2 positive
when "01" => comp_less_ff <= '0'; -- rs1 positive, rs2 negative
when "00" => comp_less_ff <= comp_less; -- both positive
when "11" => comp_less_ff <= not comp_less; -- both negative
when others => comp_less_ff <= '0'; -- undefined
end case;
end if;
 
-- comparator latency --
fu_compare.done <= fu_compare.start; -- for actual comparison operation
fu_min_max.done <= fu_min_max.start; -- for min/max operations
end if;
end process float_comparator;
 
-- less than - only compare the "magnitude" part - sign bit has to be handled separately --
comp_less <= '1' when (unsigned(fpu_operands.rs1(30 downto 0)) < unsigned(fpu_operands.rs2(30 downto 0))) else '0';
 
 
-- Comparison (FEQ/FLT/FLE) ---------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
float_comparison: process(fpu_operands, ctrl_i, comp_equal_ff, comp_less_ff)
variable snan_v : std_ulogic; -- at least one input is sNaN
variable qnan_v : std_ulogic; -- at least one input is qNaN
begin
-- check for NaN --
snan_v := fpu_operands.rs1_class(fp_class_snan_c) or fpu_operands.rs2_class(fp_class_snan_c);
qnan_v := fpu_operands.rs1_class(fp_class_qnan_c) or fpu_operands.rs2_class(fp_class_qnan_c);
 
-- condition evaluation --
fu_compare.result <= (others => '0');
case ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) is
when "00" => -- FLE: less than or equal
fu_compare.result(0) <= (comp_less_ff or comp_equal_ff) and (not (snan_v or qnan_v)); -- result is zero if either input is NaN
when "01" => -- FLT: less than
fu_compare.result(0) <= comp_less_ff and (not (snan_v or qnan_v)); -- result is zero if either input is NaN
when "10" => -- FEQ: equal
fu_compare.result(0) <= comp_equal_ff and (not (snan_v or qnan_v)); -- result is zero if either input is NaN
when others => -- undefined
fu_compare.result(0) <= '0';
end case;
end process float_comparison;
 
-- latency --
-- -> done in "float_comparator"
 
-- exceptions --
fu_compare.flags <= (others => '0'); -- does not generate exceptions here, but normalizer can generate exceptions
 
 
-- Min/Max Select (FMIN/FMAX) -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
min_max_select: process(fpu_operands, comp_less_ff, fpu_operands, fu_compare, ctrl_i)
variable cond_v : std_ulogic_vector(2 downto 0);
begin
-- comparison restul - check for special cases: -0 is less than +0
if ((fpu_operands.rs1_class(fp_class_neg_zero_c) = '1') and (fpu_operands.rs2_class(fp_class_pos_zero_c) = '1')) then
cond_v(0) := ctrl_i(ctrl_ir_funct3_0_c);
elsif ((fpu_operands.rs1_class(fp_class_pos_zero_c) = '1') and (fpu_operands.rs2_class(fp_class_neg_zero_c) = '1')) then
cond_v(0) := not ctrl_i(ctrl_ir_funct3_0_c);
else -- "normal= comparison
cond_v(0) := comp_less_ff xnor ctrl_i(ctrl_ir_funct3_0_c); -- min/max select
end if;
 
-- nmumber NaN check --
cond_v(2) := fpu_operands.rs1_class(fp_class_snan_c) or fpu_operands.rs1_class(fp_class_qnan_c);
cond_v(1) := fpu_operands.rs2_class(fp_class_snan_c) or fpu_operands.rs2_class(fp_class_qnan_c);
 
-- data output --
case cond_v is
when "000" => fu_min_max.result <= fpu_operands.rs1;
when "001" => fu_min_max.result <= fpu_operands.rs2;
when "010" | "011" => fu_min_max.result <= fpu_operands.rs1; -- if one input is NaN output the non-NaN one
when "100" | "101" => fu_min_max.result <= fpu_operands.rs2; -- if one input is NaN output the non-NaN one
when others => fu_min_max.result <= fp_single_qnan_c; -- output quiet NaN if both inputs are NaN
end case;
end process min_max_select;
 
-- latency --
-- -> done in "float_comparator"
 
-- exceptions --
fu_min_max.flags <= (others => '0'); -- does not generate exceptions here, but normalizer can generate exceptions
 
 
-- Convert: Float to [unsigned] Integer (FCVT.S.W) ----------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_cp_fpu_f2i_inst: neorv32_cpu_cp_fpu_f2i
port map (
-- control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
start_i => fu_conv_f2i.start, -- trigger operation
rmode_i => fpu_operands.frm, -- rounding mode
funct_i => ctrl_i(ctrl_ir_funct12_0_c), -- 0=signed, 1=unsigned
-- input --
sign_i => fpu_operands.rs1(31), -- sign
exponent_i => fpu_operands.rs1(30 downto 23), -- exponent
mantissa_i => fpu_operands.rs1(22 downto 00), -- mantissa
class_i => fpu_operands.rs1_class, -- operand class
-- output --
result_o => fu_conv_f2i.result, -- integer result
flags_o => fu_conv_f2i.flags, -- exception flags
done_o => fu_conv_f2i.done -- operation done
);
 
 
-- Sign-Injection (FSGNJ) -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
sign_injector: process(ctrl_i, fpu_operands)
begin
case ctrl_i(ctrl_ir_funct3_1_c downto ctrl_ir_funct3_0_c) is
when "00" => fu_sign_inject.result(31) <= fpu_operands.rs2(31); -- FSGNJ
when "01" => fu_sign_inject.result(31) <= not fpu_operands.rs2(31); -- FSGNJN
when "10" => fu_sign_inject.result(31) <= fpu_operands.rs1(31) xor fpu_operands.rs2(31); -- FSGNJX
when others => fu_sign_inject.result(31) <= fpu_operands.rs2(31); -- undefined
end case;
fu_sign_inject.result(30 downto 0) <= fpu_operands.rs1(30 downto 0);
fu_sign_inject.flags <= (others => '0'); -- does not generate flags
end process sign_injector;
 
-- latency --
fu_sign_inject.done <= fu_sign_inject.start;
 
 
-- Convert: [unsigned] Integer to Float (FCVT.W.S) ----------------------------------------
-- -------------------------------------------------------------------------------------------
convert_i2f: process(clk_i)
begin
-- this process only computes the absolute input value
-- the actual conversion is done by the normalizer
if rising_edge(clk_i) then
if (ctrl_i(ctrl_ir_funct12_0_c) = '0') and (rs1_i(31) = '1') then -- convert signed integer
fu_conv_i2f.result <= std_ulogic_vector(0 - unsigned(rs1_i));
fu_conv_i2f.sign <= rs1_i(31); -- original sign
else -- convert unsigned integer
fu_conv_i2f.result <= rs1_i;
fu_conv_i2f.sign <= '0';
end if;
fu_conv_i2f.done <= fu_conv_i2f.start; -- actual conversion is done by the normalizer unit
end if;
end process convert_i2f;
 
 
-- Multiplier Core (FMUL) -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
multiplier_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- multiplier core --
if (multiplier.start = '1') then -- FIXME / TODO remove buffer?
multiplier.opa <= unsigned('1' & fpu_operands.rs1(22 downto 0)); -- append hidden one
multiplier.opb <= unsigned('1' & fpu_operands.rs2(22 downto 0));
end if;
multiplier.buf_ff <= multiplier.opa * multiplier.opb;
multiplier.product <= std_ulogic_vector(multiplier.buf_ff(47 downto 0)); -- let the register balancing do the magic here
multiplier.sign <= fpu_operands.rs1(31) xor fpu_operands.rs2(31); -- resulting sign
 
-- exponent computation --
multiplier.exp_res <= std_ulogic_vector(unsigned('0' & multiplier.exp_sum) - 127);
if (multiplier.exp_res(multiplier.exp_res'left) = '1') then -- underflow (exp_res is "negative")
multiplier.flags(fp_exc_of_c) <= '0';
multiplier.flags(fp_exc_uf_c) <= '1';
elsif (multiplier.exp_res(multiplier.exp_res'left-1) = '1') then -- overflow
multiplier.flags(fp_exc_of_c) <= '1';
multiplier.flags(fp_exc_uf_c) <= '0';
else
multiplier.flags(fp_exc_of_c) <= '0';
multiplier.flags(fp_exc_uf_c) <= '0';
end if;
 
-- invalid operation --
multiplier.flags(fp_exc_nv_c) <=
((fpu_operands.rs1_class(fp_class_pos_zero_c) or fpu_operands.rs1_class(fp_class_neg_zero_c)) and
(fpu_operands.rs2_class(fp_class_pos_inf_c) or fpu_operands.rs2_class(fp_class_neg_inf_c))) or -- mul(+/-zero, +/-inf)
((fpu_operands.rs1_class(fp_class_pos_inf_c) or fpu_operands.rs1_class(fp_class_neg_inf_c)) and
(fpu_operands.rs2_class(fp_class_pos_zero_c) or fpu_operands.rs2_class(fp_class_neg_zero_c))); -- mul(+/-inf, +/-zero)
 
-- latency shift register --
multiplier.latency <= multiplier.latency(multiplier.latency'left-1 downto 0) & multiplier.start;
end if;
end process multiplier_core;
 
-- exponent sum --
multiplier.exp_sum <= std_ulogic_vector(unsigned('0' & fpu_operands.rs1(30 downto 23)) + unsigned('0' & fpu_operands.rs2(30 downto 23)));
 
-- latency --
multiplier.start <= fu_mul.start;
multiplier.done <= multiplier.latency(multiplier.latency'left);
fu_mul.done <= multiplier.done;
 
-- unused exception flags --
multiplier.flags(fp_exc_dz_c) <= '0'; -- division by zero: not possible here
multiplier.flags(fp_exc_nx_c) <= '0'; -- inexcat: not possible here
 
 
-- result class --
multiplier_class_core: process(clk_i)
variable a_pos_norm_v, a_neg_norm_v, b_pos_norm_v, b_neg_norm_v : std_ulogic;
variable a_pos_subn_v, a_neg_subn_v, b_pos_subn_v, b_neg_subn_v : std_ulogic;
variable a_pos_zero_v, a_neg_zero_v, b_pos_zero_v, b_neg_zero_v : std_ulogic;
variable a_pos_inf_v, a_neg_inf_v, b_pos_inf_v, b_neg_inf_v : std_ulogic;
variable a_snan_v, a_qnan_v, b_snan_v, b_qnan_v : std_ulogic;
begin
if rising_edge(clk_i) then
-- minions --
a_pos_norm_v := fpu_operands.rs1_class(fp_class_pos_norm_c); b_pos_norm_v := fpu_operands.rs2_class(fp_class_pos_norm_c);
a_neg_norm_v := fpu_operands.rs1_class(fp_class_neg_norm_c); b_neg_norm_v := fpu_operands.rs2_class(fp_class_neg_norm_c);
a_pos_subn_v := fpu_operands.rs1_class(fp_class_pos_denorm_c); b_pos_subn_v := fpu_operands.rs2_class(fp_class_pos_denorm_c);
a_neg_subn_v := fpu_operands.rs1_class(fp_class_neg_denorm_c); b_neg_subn_v := fpu_operands.rs2_class(fp_class_neg_denorm_c);
a_pos_zero_v := fpu_operands.rs1_class(fp_class_pos_zero_c); b_pos_zero_v := fpu_operands.rs2_class(fp_class_pos_zero_c);
a_neg_zero_v := fpu_operands.rs1_class(fp_class_neg_zero_c); b_neg_zero_v := fpu_operands.rs2_class(fp_class_neg_zero_c);
a_pos_inf_v := fpu_operands.rs1_class(fp_class_pos_inf_c); b_pos_inf_v := fpu_operands.rs2_class(fp_class_pos_inf_c);
a_neg_inf_v := fpu_operands.rs1_class(fp_class_neg_inf_c); b_neg_inf_v := fpu_operands.rs2_class(fp_class_neg_inf_c);
a_snan_v := fpu_operands.rs1_class(fp_class_snan_c); b_snan_v := fpu_operands.rs2_class(fp_class_snan_c);
a_qnan_v := fpu_operands.rs1_class(fp_class_qnan_c); b_qnan_v := fpu_operands.rs2_class(fp_class_qnan_c);
 
-- +normal --
multiplier.res_class(fp_class_pos_norm_c) <=
(a_pos_norm_v and b_pos_norm_v) or -- +norm * +norm
(a_neg_norm_v and b_neg_norm_v); -- -norm * -norm
-- -normal --
multiplier.res_class(fp_class_neg_norm_c) <=
(a_pos_norm_v and b_neg_norm_v) or -- +norm * -norm
(a_neg_norm_v and b_pos_norm_v); -- -norm * +norm
 
-- +infinity --
multiplier.res_class(fp_class_pos_inf_c) <=
(a_pos_inf_v and b_pos_inf_v) or -- +inf * +inf
(a_neg_inf_v and b_neg_inf_v) or -- -inf * -inf
(a_pos_norm_v and b_pos_inf_v) or -- +norm * +inf
(a_pos_inf_v and b_pos_norm_v) or -- +inf * +norm
(a_neg_norm_v and b_neg_inf_v) or -- -norm * -inf
(a_neg_inf_v and b_neg_norm_v) or -- -inf * -norm
(a_neg_subn_v and b_neg_inf_v) or -- -denorm * -inf
(a_neg_inf_v and b_neg_subn_v); -- -inf * -denorm
-- -infinity --
multiplier.res_class(fp_class_neg_inf_c) <=
(a_pos_inf_v and b_neg_inf_v) or -- +inf * -inf
(a_neg_inf_v and b_pos_inf_v) or -- -inf * +inf
(a_pos_norm_v and b_neg_inf_v) or -- +norm * -inf
(a_neg_inf_v and b_pos_norm_v) or -- -inf * +norm
(a_neg_norm_v and b_pos_inf_v) or -- -norm * +inf
(a_pos_inf_v and b_neg_norm_v) or -- +inf * -norm
(a_pos_subn_v and b_neg_inf_v) or -- +denorm * -inf
(a_neg_inf_v and b_pos_subn_v) or -- -inf * +de-norm
(a_neg_subn_v and b_pos_inf_v) or -- -denorm * +inf
(a_pos_inf_v and b_neg_subn_v); -- +inf * -de-norm
 
-- +zero --
multiplier.res_class(fp_class_pos_zero_c) <=
(a_pos_zero_v and b_pos_zero_v) or -- +zero * +zero
(a_pos_zero_v and b_pos_norm_v) or -- +zero * +norm
(a_pos_zero_v and b_pos_subn_v) or -- +zero * +denorm
(a_neg_zero_v and b_neg_zero_v) or -- -zero * -zero
(a_neg_zero_v and b_neg_norm_v) or -- -zero * -norm
(a_neg_zero_v and b_neg_subn_v) or -- -zero * -denorm
(a_pos_norm_v and b_pos_zero_v) or -- +norm * +zero
(a_pos_subn_v and b_pos_zero_v) or -- +denorm * +zero
(a_neg_norm_v and b_neg_zero_v) or -- -norm * -zero
(a_neg_subn_v and b_neg_zero_v); -- -denorm * -zero
-- -zero --
multiplier.res_class(fp_class_neg_zero_c) <=
(a_pos_zero_v and b_neg_zero_v) or -- +zero * -zero
(a_pos_zero_v and b_neg_norm_v) or -- +zero * -norm
(a_pos_zero_v and b_neg_subn_v) or -- +zero * -denorm
(a_neg_zero_v and b_pos_zero_v) or -- -zero * +zero
(a_neg_zero_v and b_pos_norm_v) or -- -zero * +norm
(a_neg_zero_v and b_pos_subn_v) or -- -zero * +denorm
(a_neg_norm_v and b_pos_zero_v) or -- -norm * +zero
(a_neg_subn_v and b_pos_zero_v) or -- -denorm * +zero
(a_pos_norm_v and b_neg_zero_v) or -- +norm * -zero
(a_pos_subn_v and b_neg_zero_v); -- +denorm * -zero
 
-- sNaN --
multiplier.res_class(fp_class_snan_c) <= (a_snan_v or b_snan_v); -- any input is sNaN
-- qNaN --
multiplier.res_class(fp_class_qnan_c) <=
(a_snan_v or b_snan_v) or -- any input is sNaN
(a_qnan_v or b_qnan_v) or -- nay input is qNaN
((a_pos_inf_v or a_neg_inf_v) and (b_pos_zero_v or b_neg_zero_v)) or -- +/-inf * +/-zero
((a_pos_zero_v or a_neg_zero_v) and (b_pos_inf_v or b_neg_inf_v)); -- +/-zero * +/-inf
end if;
end process multiplier_class_core;
 
-- subnormal result --
multiplier.res_class(fp_class_pos_denorm_c) <= '0'; -- is evaluated by the normalizer
multiplier.res_class(fp_class_neg_denorm_c) <= '0'; -- is evaluated by the normalizer
 
-- unused --
fu_mul.result <= (others => '0');
fu_mul.flags <= (others => '0');
 
 
-- Adder/Subtractor Core (FADD, FSUB) -----------------------------------------------------
-- -------------------------------------------------------------------------------------------
adder_subtractor_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- arbitration / latency --
if (ctrl_engine.state = S_IDLE) then -- hacky "reset"
addsub.latency <= (others => '0');
else
addsub.latency(0) <= addsub.start; -- input comparator delay
if (addsub.latency(0) = '1') then
addsub.latency(1) <= '1';
addsub.latency(2) <= '0';
elsif (addsub.exp_cnt(7 downto 0) = addsub.large_exp) then -- radix point not yet aligned
addsub.latency(1) <= '0';
addsub.latency(2) <= addsub.latency(1) and (not addsub.latency(0)); -- "shift done"
end if;
addsub.latency(3) <= addsub.latency(2); -- adder stage
addsub.latency(4) <= addsub.latency(3); -- final stage
end if;
 
-- exponent check: find smaller number (radix-offset-only) --
if (unsigned(fpu_operands.rs1(30 downto 23)) < unsigned(fpu_operands.rs2(30 downto 23))) then
addsub.exp_comp(0) <= '1'; -- rs1 < rs2
else
addsub.exp_comp(0) <= '0'; -- rs1 >= rs2
end if;
if (unsigned(fpu_operands.rs1(30 downto 23)) = unsigned(fpu_operands.rs2(30 downto 23))) then
addsub.exp_comp(1) <= '1'; -- rs1 == rs2
else -- rs1 != rs2
addsub.exp_comp(1) <= '0';
end if;
 
-- shift right small mantissa to align radix point --
if (addsub.latency(0) = '1') then
if ((fpu_operands.rs1_class(fp_class_pos_zero_c) or fpu_operands.rs2_class(fp_class_pos_zero_c) or
fpu_operands.rs1_class(fp_class_neg_zero_c) or fpu_operands.rs2_class(fp_class_neg_zero_c)) = '0') then -- no input is zero
addsub.man_sreg <= addsub.small_man;
else
addsub.man_sreg <= (others => '0');
end if;
addsub.exp_cnt <= '0' & addsub.small_exp;
addsub.man_g_ext <= '0';
addsub.man_r_ext <= '0';
addsub.man_s_ext <= '0';
elsif (addsub.exp_cnt(7 downto 0) /= addsub.large_exp) then -- shift right until same magnitude
addsub.man_sreg <= '0' & addsub.man_sreg(addsub.man_sreg'left downto 1);
addsub.man_g_ext <= addsub.man_sreg(0);
addsub.man_r_ext <= addsub.man_g_ext;
addsub.man_s_ext <= addsub.man_s_ext or addsub.man_r_ext; -- sticky bit
addsub.exp_cnt <= std_ulogic_vector(unsigned(addsub.exp_cnt) + 1);
end if;
 
-- mantissa check: find smaller number (magnitude-only) --
if (unsigned(addsub.man_sreg) <= unsigned(addsub.large_man)) then
addsub.man_comp <= '1';
else
addsub.man_comp <= '0';
end if;
 
-- actual addition/subtraction (incl. overflow) --
if ((ctrl_i(ctrl_ir_funct12_7_c) xor (fpu_operands.rs1(31) xor fpu_operands.rs2(31))) = '0') then -- add
addsub.add_stage <= std_ulogic_vector(unsigned('0' & addsub.man_l) + unsigned('0' & addsub.man_s));
else -- sub
addsub.add_stage <= std_ulogic_vector(unsigned('0' & addsub.man_l) - unsigned('0' & addsub.man_s));
end if;
 
-- result sign --
if (ctrl_i(ctrl_ir_funct12_7_c) = '0') then -- add
if (fpu_operands.rs1(31) = fpu_operands.rs2(31)) then -- identical signs
addsub.res_sign <= fpu_operands.rs1(31);
else -- different signs
if (addsub.exp_comp(1) = '1') then -- exp are equal (also check relation of mantissas)
addsub.res_sign <= fpu_operands.rs1(31) xor (not addsub.man_comp);
else
addsub.res_sign <= fpu_operands.rs1(31) xor addsub.exp_comp(0);
end if;
end if;
else -- sub
if (fpu_operands.rs1(31) = fpu_operands.rs2(31)) then -- identical signs
if (addsub.exp_comp(1) = '1') then -- exp are equal (also check relation of mantissas)
addsub.res_sign <= fpu_operands.rs1(31) xor (not addsub.man_comp);
else
addsub.res_sign <= fpu_operands.rs1(31) xor addsub.exp_comp(0);
end if;
else -- different signs
addsub.res_sign <= fpu_operands.rs1(31);
end if;
end if;
 
-- exception flags --
addsub.flags(fp_exc_nv_c) <= ((fpu_operands.rs1_class(fp_class_pos_inf_c) or fpu_operands.rs1_class(fp_class_neg_inf_c)) and
(fpu_operands.rs2_class(fp_class_pos_inf_c) or fpu_operands.rs2_class(fp_class_neg_inf_c))); -- +/-inf +/- +/-inf
end if;
end process adder_subtractor_core;
 
-- exceptions - unused --
addsub.flags(fp_exc_dz_c) <= '0'; -- division by zero -> not possible
addsub.flags(fp_exc_of_c) <= '0'; -- not possible here (but may occur in normalizer)
addsub.flags(fp_exc_uf_c) <= '0'; -- not possible here (but may occur in normalizer)
addsub.flags(fp_exc_nx_c) <= '0'; -- not possible here (but may occur in normalizer)
 
-- exponent check: find smaller number (magnitude-only) --
addsub.small_exp <= fpu_operands.rs1(30 downto 23) when (addsub.exp_comp(0) = '1') else fpu_operands.rs2(30 downto 23);
addsub.large_exp <= fpu_operands.rs2(30 downto 23) when (addsub.exp_comp(0) = '1') else fpu_operands.rs1(30 downto 23);
addsub.small_man <= ('1' & fpu_operands.rs1(22 downto 00)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs2(22 downto 00));
addsub.large_man <= ('1' & fpu_operands.rs2(22 downto 00)) when (addsub.exp_comp(0) = '1') else ('1' & fpu_operands.rs1(22 downto 00));
 
-- mantissa check: find smaller number (magnitude-only) --
addsub.man_s <= (addsub.man_sreg & addsub.man_g_ext & addsub.man_r_ext & addsub.man_s_ext) when (addsub.man_comp = '1') else (addsub.large_man & "000");
addsub.man_l <= (addsub.large_man & "000") when (addsub.man_comp = '1') else (addsub.man_sreg & addsub.man_g_ext & addsub.man_r_ext & addsub.man_s_ext);
 
-- latency --
addsub.start <= fu_addsub.start;
addsub.done <= addsub.latency(addsub.latency'left);
fu_addsub.done <= addsub.done;
 
-- mantissa result --
addsub.res_sum <= addsub.add_stage(27 downto 0);
 
 
-- result class --
adder_subtractor_class_core: process(clk_i)
variable a_pos_norm_v, a_neg_norm_v, b_pos_norm_v, b_neg_norm_v : std_ulogic;
variable a_pos_subn_v, a_neg_subn_v, b_pos_subn_v, b_neg_subn_v : std_ulogic;
variable a_pos_zero_v, a_neg_zero_v, b_pos_zero_v, b_neg_zero_v : std_ulogic;
variable a_pos_inf_v, a_neg_inf_v, b_pos_inf_v, b_neg_inf_v : std_ulogic;
variable a_snan_v, a_qnan_v, b_snan_v, b_qnan_v : std_ulogic;
begin
if rising_edge(clk_i) then
-- minions --
a_pos_norm_v := fpu_operands.rs1_class(fp_class_pos_norm_c); b_pos_norm_v := fpu_operands.rs2_class(fp_class_pos_norm_c);
a_neg_norm_v := fpu_operands.rs1_class(fp_class_neg_norm_c); b_neg_norm_v := fpu_operands.rs2_class(fp_class_neg_norm_c);
a_pos_subn_v := fpu_operands.rs1_class(fp_class_pos_denorm_c); b_pos_subn_v := fpu_operands.rs2_class(fp_class_pos_denorm_c);
a_neg_subn_v := fpu_operands.rs1_class(fp_class_neg_denorm_c); b_neg_subn_v := fpu_operands.rs2_class(fp_class_neg_denorm_c);
a_pos_zero_v := fpu_operands.rs1_class(fp_class_pos_zero_c); b_pos_zero_v := fpu_operands.rs2_class(fp_class_pos_zero_c);
a_neg_zero_v := fpu_operands.rs1_class(fp_class_neg_zero_c); b_neg_zero_v := fpu_operands.rs2_class(fp_class_neg_zero_c);
a_pos_inf_v := fpu_operands.rs1_class(fp_class_pos_inf_c); b_pos_inf_v := fpu_operands.rs2_class(fp_class_pos_inf_c);
a_neg_inf_v := fpu_operands.rs1_class(fp_class_neg_inf_c); b_neg_inf_v := fpu_operands.rs2_class(fp_class_neg_inf_c);
a_snan_v := fpu_operands.rs1_class(fp_class_snan_c); b_snan_v := fpu_operands.rs2_class(fp_class_snan_c);
a_qnan_v := fpu_operands.rs1_class(fp_class_qnan_c); b_qnan_v := fpu_operands.rs2_class(fp_class_qnan_c);
 
if (ctrl_i(ctrl_ir_funct12_7_c) = '0') then -- addition
-- +infinity --
addsub.res_class(fp_class_pos_inf_c) <=
(a_pos_inf_v and b_pos_inf_v) or -- +inf + +inf
(a_pos_inf_v and b_pos_zero_v) or -- +inf + +zero
(a_pos_zero_v and b_pos_inf_v) or -- +zero + +inf
(a_pos_inf_v and b_neg_zero_v) or -- +inf + -zero
(a_neg_zero_v and b_pos_inf_v) or -- -zero + +inf
--
(a_pos_inf_v and b_pos_norm_v) or -- +inf + +norm
(a_pos_norm_v and b_pos_inf_v) or -- +norm + +inf
(a_pos_inf_v and b_pos_subn_v) or -- +inf + +denorm
(a_pos_subn_v and b_pos_inf_v) or -- +denorm + +inf
--
(a_pos_inf_v and b_neg_norm_v) or -- +inf + -norm
(a_neg_norm_v and b_pos_inf_v) or -- -norm + +inf
(a_pos_inf_v and b_neg_subn_v) or -- +inf + -denorm
(a_neg_subn_v and b_pos_inf_v); -- -denorm + +inf
-- -infinity --
addsub.res_class(fp_class_neg_inf_c) <=
(a_neg_inf_v and b_neg_inf_v) or -- -inf + -inf
(a_neg_inf_v and b_pos_zero_v) or -- -inf + +zero
(a_pos_zero_v and b_neg_inf_v) or -- +zero + -inf
(a_neg_inf_v and b_neg_zero_v) or -- -inf + -zero
(a_neg_zero_v and b_neg_inf_v) or -- -zero + -inf
--
(a_neg_inf_v and b_pos_norm_v) or -- -inf + +norm
(a_pos_norm_v and b_neg_inf_v) or -- +norm + -inf
(a_neg_inf_v and b_neg_norm_v) or -- -inf + -norm
(a_neg_norm_v and b_neg_inf_v) or -- -norm + -inf
--
(a_neg_inf_v and b_pos_subn_v) or -- -inf + +denorm
(a_pos_subn_v and b_neg_inf_v) or -- +denorm + -inf
(a_neg_inf_v and b_neg_subn_v) or -- -inf + -denorm
(a_neg_subn_v and b_neg_inf_v); -- -denorm + -inf
 
-- +zero --
addsub.res_class(fp_class_pos_zero_c) <=
(a_pos_zero_v and b_pos_zero_v) or -- +zero + +zero
(a_pos_zero_v and b_neg_zero_v) or -- +zero + -zero
(a_neg_zero_v and b_pos_zero_v); -- -zero + +zero
-- -zero --
addsub.res_class(fp_class_neg_zero_c) <=
(a_neg_zero_v and b_neg_zero_v); -- -zero + -zero
 
-- qNaN --
addsub.res_class(fp_class_qnan_c) <=
(a_snan_v or b_snan_v) or -- any input is sNaN
(a_qnan_v or b_qnan_v) or -- any input is qNaN
(a_pos_inf_v and b_neg_inf_v) or -- +inf + -inf
(a_neg_inf_v and b_pos_inf_v); -- -inf + +inf
 
else -- subtraction
-- +infinity --
addsub.res_class(fp_class_pos_inf_c) <=
(a_pos_inf_v and b_neg_inf_v) or -- +inf - -inf
(a_pos_inf_v and b_pos_zero_v) or -- +inf - +zero
(a_pos_inf_v and b_neg_zero_v) or -- +inf - -zero
(a_pos_inf_v and b_pos_norm_v) or -- +inf - +norm
(a_pos_inf_v and b_pos_subn_v) or -- +inf - +denorm
(a_pos_inf_v and b_neg_norm_v) or -- +inf - -norm
(a_pos_inf_v and b_neg_subn_v) or -- +inf - -denorm
--
(a_pos_zero_v and b_neg_inf_v) or -- +zero - -inf
(a_neg_zero_v and b_neg_inf_v) or -- -zero - -inf
--
(a_pos_norm_v and b_neg_inf_v) or -- +norm - -inf
(a_pos_subn_v and b_neg_inf_v) or -- +denorm - -inf
(a_neg_norm_v and b_neg_inf_v) or -- -norm - -inf
(a_neg_subn_v and b_neg_inf_v); -- -denorm - -inf
-- -infinity --
addsub.res_class(fp_class_neg_inf_c) <=
(a_neg_inf_v and b_pos_inf_v) or -- -inf - +inf
(a_neg_inf_v and b_pos_zero_v) or -- -inf - +zero
(a_neg_inf_v and b_neg_zero_v) or -- -inf - -zero
(a_neg_inf_v and b_pos_norm_v) or -- -inf - +norm
(a_neg_inf_v and b_pos_subn_v) or -- -inf - +denorm
(a_neg_inf_v and b_neg_norm_v) or -- -inf - -norm
(a_neg_inf_v and b_neg_subn_v) or -- -inf - -denorm
--
(a_pos_zero_v and b_pos_inf_v) or -- +zero - +inf
(a_neg_zero_v and b_pos_inf_v) or -- -zero - +inf
--
(a_pos_norm_v and b_pos_inf_v) or -- +norm - +inf
(a_pos_subn_v and b_pos_inf_v) or -- +denorm - +inf
(a_neg_norm_v and b_pos_inf_v) or -- -norm - +inf
(a_neg_subn_v and b_pos_inf_v); -- -denorm - +inf
 
-- +zero --
addsub.res_class(fp_class_pos_zero_c) <=
(a_pos_zero_v and b_pos_zero_v) or -- +zero - +zero
(a_pos_zero_v and b_neg_zero_v) or -- +zero - -zero
(a_neg_zero_v and b_neg_zero_v); -- -zero - -zero
-- -zero --
addsub.res_class(fp_class_neg_zero_c) <=
(a_neg_zero_v and b_pos_zero_v); -- -zero - +zero
 
-- qNaN --
addsub.res_class(fp_class_qnan_c) <=
(a_snan_v or b_snan_v) or -- any input is sNaN
(a_qnan_v or b_qnan_v) or -- any input is qNaN
(a_pos_inf_v and b_pos_inf_v) or -- +inf - +inf
(a_neg_inf_v and b_neg_inf_v); -- -inf - -inf
end if;
 
-- normal --
addsub.res_class(fp_class_pos_norm_c) <= (a_pos_norm_v or a_neg_norm_v) and (b_pos_norm_v or b_neg_norm_v); -- +/-norm +/- +-/norm [sign is irrelevant here]
addsub.res_class(fp_class_neg_norm_c) <= (a_pos_norm_v or a_neg_norm_v) and (b_pos_norm_v or b_neg_norm_v); -- +/-norm +/- +-/norm [sign is irrelevant here]
 
-- sNaN --
addsub.res_class(fp_class_snan_c) <= (a_snan_v or b_snan_v); -- any input is sNaN
end if;
end process adder_subtractor_class_core;
 
-- subnormal result --
addsub.res_class(fp_class_pos_denorm_c) <= '0'; -- is evaluated by the normalizer
addsub.res_class(fp_class_neg_denorm_c) <= '0'; -- is evaluated by the normalizer
 
-- unused --
fu_addsub.result <= (others => '0');
fu_addsub.flags <= (others => '0');
 
 
-- ****************************************************************************************************************************
-- FPU Core - Normalize & Round
-- ****************************************************************************************************************************
 
-- Normalizer Input -----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
normalizer_input_select: process(funct_ff, addsub, multiplier, fu_conv_i2f)
begin
case funct_ff is
when op_addsub_c => -- addition/subtraction
normalizer.mode <= '0'; -- normalization
normalizer.sign <= addsub.res_sign;
normalizer.xexp <= addsub.exp_cnt;
normalizer.xmantissa(47 downto 23) <= addsub.res_sum(27 downto 3);
normalizer.xmantissa(22) <= addsub.res_sum(2);
normalizer.xmantissa(21) <= addsub.res_sum(1);
normalizer.xmantissa(20 downto 01) <= (others => '0');
normalizer.xmantissa(00) <= addsub.res_sum(0);
normalizer.class <= addsub.res_class;
normalizer.flags_in <= addsub.flags;
normalizer.start <= addsub.done;
when op_mul_c => -- multiplication
normalizer.mode <= '0'; -- normalization
normalizer.sign <= multiplier.sign;
normalizer.xexp <= '0' & multiplier.exp_res(7 downto 0);
normalizer.xmantissa <= multiplier.product;
normalizer.class <= multiplier.res_class;
normalizer.flags_in <= multiplier.flags;
normalizer.start <= multiplier.done;
when others => -- op_i2f_c
normalizer.mode <= '1'; -- int_to_float
normalizer.sign <= fu_conv_i2f.sign;
normalizer.xexp <= "001111111"; -- bias = 127
normalizer.xmantissa <= (others => '0'); -- don't care
normalizer.class <= (others => '0'); -- don't care
normalizer.flags_in <= (others => '0'); -- no flags yet
normalizer.start <= fu_conv_i2f.done;
end case;
end process normalizer_input_select;
 
 
-- Normalizer & Rounding Unit -------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cpu_cp_fpu_normalizer_inst: neorv32_cpu_cp_fpu_normalizer
port map (
-- control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
start_i => normalizer.start, -- trigger operation
rmode_i => fpu_operands.frm, -- rounding mode
funct_i => normalizer.mode, -- operation mode
-- input --
sign_i => normalizer.sign, -- sign
exponent_i => normalizer.xexp, -- extended exponent
mantissa_i => normalizer.xmantissa, -- extended mantissa
integer_i => fu_conv_i2f.result, -- integer input
class_i => normalizer.class, -- input number class
flags_i => normalizer.flags_in, -- exception flags input
-- output --
result_o => normalizer.result, -- result (float or int)
flags_o => normalizer.flags_out, -- exception flags
done_o => normalizer.done -- operation done
);
 
 
-- ****************************************************************************************************************************
-- FPU Core - Result
-- ****************************************************************************************************************************
 
-- Result Output to CPU Pipeline ----------------------------------------------------------
-- -------------------------------------------------------------------------------------------
output_gate: process(clk_i)
begin
if rising_edge(clk_i) then
if (ctrl_engine.valid = '1') then
case funct_ff is
when op_class_c =>
res_o <= fu_classify.result;
fflags_o <= fu_classify.flags;
when op_comp_c =>
res_o <= fu_compare.result;
fflags_o <= fu_compare.flags;
when op_f2i_c =>
res_o <= fu_conv_f2i.result;
fflags_o <= fu_conv_f2i.flags;
when op_sgnj_c =>
res_o <= fu_sign_inject.result;
fflags_o <= fu_sign_inject.flags;
when op_minmax_c =>
res_o <= fu_min_max.result;
fflags_o <= fu_min_max.flags;
when others => -- op_mul_c, op_addsub_c, op_i2f_c, ...
res_o <= normalizer.result;
fflags_o <= normalizer.flags_out;
end case;
else
res_o <= (others => '0');
fflags_o <= (others => '0');
end if;
end if;
end process output_gate;
 
-- operation done --
fu_core_done <= fu_compare.done or fu_classify.done or fu_sign_inject.done or fu_min_max.done or normalizer.done or fu_conv_f2i.done;
 
 
end neorv32_cpu_cp_fpu_rtl;
 
-- ###########################################################################################################################################
-- ###########################################################################################################################################
 
-- #################################################################################################
-- # << NEORV32 - Single-Precision Floating-Point Unit: Normalizer and Rounding Unit >> #
-- # ********************************************************************************************* #
-- # This unit also performs integer-to-float conversions. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_cpu_cp_fpu_normalizer is
port (
-- control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
start_i : in std_ulogic; -- trigger operation
rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode
funct_i : in std_ulogic; -- operating mode (0=norm&round, 1=int-to-float)
-- input --
sign_i : in std_ulogic; -- sign
exponent_i : in std_ulogic_vector(08 downto 0); -- extended exponent
mantissa_i : in std_ulogic_vector(47 downto 0); -- extended mantissa
integer_i : in std_ulogic_vector(31 downto 0); -- integer input
class_i : in std_ulogic_vector(09 downto 0); -- input number class
flags_i : in std_ulogic_vector(04 downto 0); -- exception flags input
-- output --
result_o : out std_ulogic_vector(31 downto 0); -- float result
flags_o : out std_ulogic_vector(04 downto 0); -- exception flags output
done_o : out std_ulogic -- operation done
);
end neorv32_cpu_cp_fpu_normalizer;
 
architecture neorv32_cpu_cp_fpu_normalizer_rtl of neorv32_cpu_cp_fpu_normalizer is
 
-- controller --
type ctrl_engine_state_t is (S_IDLE, S_PREPARE_I2F, S_CHECK_I2F, S_PREPARE_NORM, S_PREPARE_SHIFT, S_NORMALIZE_BUSY, S_ROUND, S_CHECK, S_FINALIZE);
type ctrl_t is record
state : ctrl_engine_state_t; -- current state
norm_r : std_ulogic; -- normalization round 0 or 1
cnt : std_ulogic_vector(08 downto 0); -- interation counter/exponent (incl. overflow)
cnt_pre : std_ulogic_vector(08 downto 0);
cnt_of : std_ulogic; -- counter overflow
cnt_uf : std_ulogic; -- counter underflow
rounded : std_ulogic; -- output is rounded
res_sgn : std_ulogic;
res_exp : std_ulogic_vector(07 downto 0);
res_man : std_ulogic_vector(22 downto 0);
class : std_ulogic_vector(09 downto 0);
flags : std_ulogic_vector(04 downto 0);
end record;
signal ctrl : ctrl_t;
 
-- normalization shift register --
type sreg_t is record
done : std_ulogic;
dir : std_ulogic; -- shift direction: 0=right, 1=left
zero : std_ulogic;
upper : std_ulogic_vector(31 downto 0);
lower : std_ulogic_vector(22 downto 0);
ext_g : std_ulogic; -- guard bit
ext_r : std_ulogic; -- round bit
ext_s : std_ulogic; -- sticky bit
end record;
signal sreg : sreg_t;
 
-- rounding unit --
type round_t is record
en : std_ulogic; -- enable rounding
sub : std_ulogic; -- 0=decrement, 1=increment
output : std_ulogic_vector(24 downto 0); -- mantissa size + hidden one + 1
end record;
signal round : round_t;
 
begin
 
-- Control Engine -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
ctrl_engine: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl.state <= S_IDLE;
ctrl.norm_r <= '0';
ctrl.cnt <= (others => '0');
ctrl.cnt_pre <= (others => '0');
ctrl.cnt_of <= '0';
ctrl.cnt_uf <= '0';
ctrl.rounded <= '0';
ctrl.res_exp <= (others => '0');
ctrl.res_man <= (others => '0');
ctrl.res_sgn <= '0';
ctrl.class <= (others => '0');
ctrl.flags <= (others => '0');
--
sreg.upper <= (others => '0');
sreg.lower <= (others => '0');
sreg.dir <= '0';
sreg.ext_g <= '0';
sreg.ext_r <= '0';
sreg.ext_s <= '0';
--
done_o <= '0';
elsif rising_edge(clk_i) then
-- defaults --
ctrl.cnt_pre <= ctrl.cnt;
done_o <= '0';
 
-- exponent counter underflow/overflow --
if ((ctrl.cnt_pre(8 downto 7) = "01") and (ctrl.cnt(8 downto 7) = "10")) then -- overflow
ctrl.cnt_of <= '1';
elsif (ctrl.cnt_pre(8 downto 7) = "00") and (ctrl.cnt(8 downto 7) = "11") then -- underflow
ctrl.cnt_uf <= '1';
end if;
 
-- fsm --
case ctrl.state is
 
when S_IDLE => -- wait for operation trigger
-- ------------------------------------------------------------
ctrl.norm_r <= '0'; -- start with first normalization
ctrl.rounded <= '0'; -- not rounded yet
ctrl.cnt_of <= '0';
ctrl.cnt_uf <= '0';
--
if (start_i = '1') then
ctrl.cnt <= exponent_i;
ctrl.res_sgn <= sign_i;
ctrl.class <= class_i;
ctrl.flags <= flags_i;
if (funct_i = '0') then -- float -> float
ctrl.state <= S_PREPARE_NORM;
else -- integer -> float
ctrl.state <= S_PREPARE_I2F;
end if;
end if;
 
when S_PREPARE_I2F => -- prepare integer-to-float conversion
-- ------------------------------------------------------------
sreg.upper <= integer_i;
sreg.lower <= (others => '0');
sreg.ext_g <= '0';
sreg.ext_r <= '0';
sreg.ext_s <= '0';
sreg.dir <= '0'; -- shift right
ctrl.state <= S_CHECK_I2F;
 
when S_CHECK_I2F => -- check if converting zero
-- ------------------------------------------------------------
if (sreg.zero = '1') then -- all zero
ctrl.class(fp_class_pos_zero_c) <= '1';
ctrl.state <= S_FINALIZE;
else
ctrl.state <= S_NORMALIZE_BUSY;
end if;
 
when S_PREPARE_NORM => -- prepare "normal" normalization & rounding
-- ------------------------------------------------------------
sreg.upper(31 downto 02) <= (others => '0');
sreg.upper(01 downto 00) <= mantissa_i(47 downto 46);
sreg.lower <= mantissa_i(45 downto 23);
sreg.ext_g <= mantissa_i(22);
sreg.ext_r <= mantissa_i(21);
sreg.ext_s <= or_all_f(mantissa_i(20 downto 0));
-- check for special cases --
if ((ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c) or -- NaN
ctrl.class(fp_class_neg_zero_c) or ctrl.class(fp_class_pos_zero_c) or -- zero
ctrl.class(fp_class_neg_denorm_c) or ctrl.class(fp_class_pos_denorm_c) or -- subnormal
ctrl.class(fp_class_neg_inf_c) or ctrl.class(fp_class_pos_inf_c) or -- infinity
ctrl.flags(fp_exc_uf_c) or -- underflow
ctrl.flags(fp_exc_of_c) or -- overflow
ctrl.flags(fp_exc_nv_c)) = '1') then -- invalid
ctrl.state <= S_FINALIZE;
else
ctrl.state <= S_PREPARE_SHIFT;
end if;
 
when S_PREPARE_SHIFT => -- prepare shift direction (for "normal" normalization only)
-- ------------------------------------------------------------
if (sreg.zero = '0') then -- number < 1.0
sreg.dir <= '0'; -- shift right
else -- number >= 1.0
sreg.dir <= '1'; -- shift left
end if;
ctrl.state <= S_NORMALIZE_BUSY;
 
when S_NORMALIZE_BUSY => -- running normalization cycle
-- ------------------------------------------------------------
-- shift until normalized or exception --
if (sreg.done = '1') or (ctrl.cnt_uf = '1') or (ctrl.cnt_of = '1') then
-- normalization control --
ctrl.norm_r <= '1';
if (ctrl.norm_r = '0') then -- first normalization cycle done
ctrl.state <= S_ROUND;
else -- second normalization cycle done
ctrl.state <= S_CHECK;
end if;
else
if (sreg.dir = '0') then -- shift right
ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) + 1);
sreg.upper <= '0' & sreg.upper(sreg.upper'left downto 1);
sreg.lower <= sreg.upper(0) & sreg.lower(sreg.lower'left downto 1);
sreg.ext_g <= sreg.lower(0);
sreg.ext_r <= sreg.ext_g;
sreg.ext_s <= sreg.ext_r or sreg.ext_s; -- sticky bit
else -- shift left
ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 1);
sreg.upper <= sreg.upper(sreg.upper'left-1 downto 0) & sreg.lower(sreg.lower'left);
sreg.lower <= sreg.lower(sreg.lower'left-1 downto 0) & sreg.ext_g;
sreg.ext_g <= sreg.ext_r;
sreg.ext_r <= sreg.ext_s;
sreg.ext_s <= sreg.ext_s; -- sticky bit
end if;
end if;
 
when S_ROUND => -- rounding cycle (after first normalization)
-- ------------------------------------------------------------
ctrl.rounded <= ctrl.rounded or round.en;
sreg.upper(31 downto 02) <= (others => '0');
sreg.upper(01 downto 00) <= round.output(24 downto 23);
sreg.lower <= round.output(22 downto 00);
sreg.ext_g <= '0';
sreg.ext_r <= '0';
sreg.ext_s <= '0';
ctrl.state <= S_PREPARE_SHIFT;
 
when S_CHECK => -- check for overflow/underflow
-- ------------------------------------------------------------
if (ctrl.cnt_uf = '1') then -- underflow
ctrl.flags(fp_exc_uf_c) <= '1';
elsif (ctrl.cnt_of = '1') then -- overflow
ctrl.flags(fp_exc_of_c) <= '1';
elsif (ctrl.cnt(7 downto 0) = x"00") then -- subnormal
ctrl.flags(fp_exc_uf_c) <= '1';
elsif (ctrl.cnt(7 downto 0) = x"FF") then -- infinity
ctrl.flags(fp_exc_of_c) <= '1';
end if;
ctrl.state <= S_FINALIZE;
 
when S_FINALIZE => -- result finalization
-- ------------------------------------------------------------
-- generate result word (the ORDER of checks is imporatant here!) --
if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') then -- sNaN / qNaN
ctrl.res_sgn <= fp_single_qnan_c(31);
ctrl.res_exp <= fp_single_qnan_c(30 downto 23);
ctrl.res_man <= fp_single_qnan_c(22 downto 00);
elsif (ctrl.class(fp_class_neg_inf_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- infinity
(ctrl.flags(fp_exc_of_c) = '1') then -- overflow
ctrl.res_exp <= fp_single_pos_inf_c(30 downto 23); -- keep original sign
ctrl.res_man <= fp_single_pos_inf_c(22 downto 00);
elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') then -- zero
ctrl.res_sgn <= ctrl.class(fp_class_neg_zero_c);
ctrl.res_exp <= fp_single_pos_zero_c(30 downto 23);
ctrl.res_man <= fp_single_pos_zero_c(22 downto 00);
elsif (ctrl.flags(fp_exc_uf_c) = '1') or -- underflow
(sreg.zero = '1') or (ctrl.class(fp_class_neg_denorm_c) = '1') or (ctrl.class(fp_class_pos_denorm_c) = '1') then -- denormalized (flush-to-zero)
ctrl.res_exp <= fp_single_pos_zero_c(30 downto 23); -- keep original sign
ctrl.res_man <= fp_single_pos_zero_c(22 downto 00);
else -- result is ok
ctrl.res_exp <= ctrl.cnt(7 downto 0);
ctrl.res_man <= sreg.lower;
end if;
-- generate exception flags --
ctrl.flags(fp_exc_nv_c) <= ctrl.flags(fp_exc_nv_c) or ctrl.class(fp_class_snan_c); -- invalid if input is SIGNALING NaN
ctrl.flags(fp_exc_nx_c) <= ctrl.flags(fp_exc_nx_c) or ctrl.rounded; -- inexcat if result is rounded
--
done_o <= '1';
ctrl.state <= S_IDLE;
 
when others => -- undefined
-- ------------------------------------------------------------
ctrl.state <= S_IDLE;
 
end case;
end if;
end process ctrl_engine;
 
-- stop shifting when normalized --
sreg.done <= (not or_all_f(sreg.upper(sreg.upper'left downto 1))) and sreg.upper(0); -- input is zero, hidden one is set
 
-- all-zero including hidden bit --
sreg.zero <= not or_all_f(sreg.upper);
 
-- result --
result_o(31) <= ctrl.res_sgn;
result_o(30 downto 23) <= ctrl.res_exp;
result_o(22 downto 0) <= ctrl.res_man;
 
-- exception flags --
flags_o(fp_exc_nv_c) <= ctrl.flags(fp_exc_nv_c); -- invalid operation
flags_o(fp_exc_dz_c) <= ctrl.flags(fp_exc_dz_c); -- divide by zero
flags_o(fp_exc_of_c) <= ctrl.flags(fp_exc_of_c); -- overflow
flags_o(fp_exc_uf_c) <= ctrl.flags(fp_exc_uf_c); -- underflow
flags_o(fp_exc_nx_c) <= ctrl.flags(fp_exc_nx_c); -- inexact
 
 
-- Rounding -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
rounding_unit_ctrl: process(rmode_i, sreg)
begin
-- defaults --
round.en <= '0';
round.sub <= '0';
-- rounding mode --
case rmode_i(2 downto 0) is
when "000" => -- round to nearest, ties to even
if (sreg.ext_g = '0') then
round.en <= '0'; -- round down (do nothing)
else
if (sreg.ext_r = '0') and (sreg.ext_s = '0') then -- tie!
round.en <= sreg.lower(0); -- round up if LSB of mantissa is set
else
round.en <= '1'; -- round up
end if;
end if;
round.sub <= '0'; -- increment
when "001" => -- round towards zero
round.en <= '0'; -- no rounding -> just truncate
when "010" => -- round down (towards -infinity)
round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s;
round.sub <= '1'; -- decrement
when "011" => -- round up (towards +infinity)
round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s;
round.sub <= '0'; -- increment
when "100" => -- round to nearest, ties to max magnitude
round.en <= '0'; -- FIXME / TODO
when others => -- undefined
round.en <= '0';
end case;
end process rounding_unit_ctrl;
 
 
-- incrementer/decrementer --
rounding_unit_add: process(round, sreg)
variable tmp_v : std_ulogic_vector(24 downto 0);
begin
tmp_v := '0' & sreg.upper(0) & sreg.lower;
if (round.en = '1') then
if (round.sub = '0') then -- increment
round.output <= std_ulogic_vector(unsigned(tmp_v) + 1);
else -- decrement
round.output <= std_ulogic_vector(unsigned(tmp_v) - 1);
end if;
else -- do nothing
round.output <= tmp_v;
end if;
end process rounding_unit_add;
 
 
end neorv32_cpu_cp_fpu_normalizer_rtl;
 
-- ###########################################################################################################################################
-- ###########################################################################################################################################
 
-- #################################################################################################
-- # << NEORV32 - Single-Precision Floating-Point Unit: Float-To-Int Converter >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library neorv32;
use neorv32.neorv32_package.all;
 
entity neorv32_cpu_cp_fpu_f2i is
port (
-- control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
start_i : in std_ulogic; -- trigger operation
rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode
funct_i : in std_ulogic; -- 0=signed, 1=unsigned
-- input --
sign_i : in std_ulogic; -- sign
exponent_i : in std_ulogic_vector(07 downto 0); -- exponent
mantissa_i : in std_ulogic_vector(22 downto 0); -- mantissa
class_i : in std_ulogic_vector(09 downto 0); -- operand class
-- output --
result_o : out std_ulogic_vector(31 downto 0); -- integer result
flags_o : out std_ulogic_vector(04 downto 0); -- exception flags
done_o : out std_ulogic -- operation done
);
end neorv32_cpu_cp_fpu_f2i;
 
architecture neorv32_cpu_cp_fpu_f2i_rtl of neorv32_cpu_cp_fpu_f2i is
 
-- controller --
type ctrl_engine_state_t is (S_IDLE, S_PREPARE_F2I, S_NORMALIZE_BUSY, S_ROUND, S_FINALIZE);
type ctrl_t is record
state : ctrl_engine_state_t; -- current state
unsign : std_ulogic;
cnt : std_ulogic_vector(07 downto 0); -- interation counter/exponent
sign : std_ulogic;
class : std_ulogic_vector(09 downto 0);
rounded : std_ulogic; -- output is rounded
over : std_ulogic; -- output is overflowing
under : std_ulogic; -- output in underflowing
result_tmp : std_ulogic_vector(31 downto 0);
result : std_ulogic_vector(31 downto 0);
end record;
signal ctrl : ctrl_t;
 
-- conversion shift register --
type sreg_t is record
int : std_ulogic_vector(31 downto 0); -- including hidden-zero
mant : std_ulogic_vector(22 downto 0);
ext_g : std_ulogic; -- guard bit
ext_r : std_ulogic; -- round bit
ext_s : std_ulogic; -- sticky bit
end record;
signal sreg : sreg_t;
 
-- rounding unit --
type round_t is record
en : std_ulogic; -- enable rounding
sub : std_ulogic; -- 0=decrement, 1=increment
output : std_ulogic_vector(32 downto 0); -- result + overflow
end record;
signal round : round_t;
 
begin
 
-- Control Engine -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
ctrl_engine: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
ctrl.state <= S_IDLE;
ctrl.cnt <= (others => '0');
ctrl.sign <= '0';
ctrl.class <= (others => '0');
ctrl.rounded <= '0';
ctrl.over <= '0';
ctrl.under <= '0';
ctrl.unsign <= '0';
ctrl.result <= (others => '0');
ctrl.result_tmp <= (others => '0');
sreg.int <= (others => '0');
sreg.mant <= (others => '0');
sreg.ext_s <= '0';
done_o <= '0';
elsif rising_edge(clk_i) then
-- defaults --
done_o <= '0';
 
-- fsm --
case ctrl.state is
 
when S_IDLE => -- wait for operation trigger
-- ------------------------------------------------------------
ctrl.rounded <= '0'; -- not rounded yet
ctrl.over <= '0'; -- not overflowing yet
ctrl.under <= '0'; -- not underflowing yet
ctrl.unsign <= funct_i;
sreg.ext_s <= '0'; -- init
if (start_i = '1') then
ctrl.cnt <= exponent_i;
ctrl.sign <= sign_i;
ctrl.class <= class_i;
sreg.mant <= mantissa_i;
ctrl.state <= S_PREPARE_F2I;
end if;
 
when S_PREPARE_F2I => -- prepare float-to-integer conversion
-- ------------------------------------------------------------
if (unsigned(ctrl.cnt) < 126) then -- less than 0.5
sreg.int <= (others => '0');
ctrl.under <= '1'; -- this is an underflow!
ctrl.cnt <= (others => '0');
elsif (unsigned(ctrl.cnt) = 126) then -- num < 1.0 but num >= 0.5
sreg.int <= (others => '0');
sreg.mant <= '1' & sreg.mant(sreg.mant'left downto 1);
ctrl.cnt <= (others => '0');
else
sreg.int <= (others => '0');
sreg.int(0) <= '1'; -- hidden one
ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 127); -- remove bias to get raw number of left shifts
end if;
-- check terminal cases --
if ((ctrl.class(fp_class_neg_inf_c) or ctrl.class(fp_class_pos_inf_c) or
ctrl.class(fp_class_neg_zero_c) or ctrl.class(fp_class_pos_zero_c) or
ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c)) = '1') then
ctrl.state <= S_FINALIZE;
else
ctrl.state <= S_NORMALIZE_BUSY;
end if;
 
when S_NORMALIZE_BUSY => -- running normalization cycle
-- ------------------------------------------------------------
sreg.ext_s <= sreg.ext_s or or_all_f(sreg.mant(sreg.mant'left-2 downto 0)); -- sticky bit
if (or_all_f(ctrl.cnt(ctrl.cnt'left-1 downto 0)) = '0') then
if (ctrl.unsign = '0') then -- signed conversion
ctrl.over <= ctrl.over or sreg.int(sreg.int'left); -- update overrun flag again to check for numerical overflow into sign bit
end if;
ctrl.state <= S_ROUND;
else -- shift left
ctrl.cnt <= std_ulogic_vector(unsigned(ctrl.cnt) - 1);
sreg.int <= sreg.int(sreg.int'left-1 downto 0) & sreg.mant(sreg.mant'left);
sreg.mant <= sreg.mant(sreg.mant'left-1 downto 0) & '0';
ctrl.over <= ctrl.over or sreg.int(sreg.int'left);
end if;
 
when S_ROUND => -- rounding cycle
-- ------------------------------------------------------------
ctrl.rounded <= ctrl.rounded or round.en;
ctrl.over <= ctrl.over or round.output(round.output'left); -- overflow after rounding
ctrl.result_tmp <= round.output(round.output'left-1 downto 0);
ctrl.state <= S_FINALIZE;
 
when S_FINALIZE => -- check for corner cases and finalize result
-- ------------------------------------------------------------
if (ctrl.unsign = '1') then -- unsigned conversion
if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- NaN or +inf
((ctrl.sign = '0') and (ctrl.over = '1')) then -- positive out-of-range
ctrl.result <= x"ffffffff";
elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') or (ctrl.class(fp_class_neg_inf_c) = '1') or -- subnormal zero or -inf
(ctrl.sign = '1') or (ctrl.under = '1') then -- negative out-of-range or underflow
ctrl.result <= x"00000000";
else
ctrl.result <= ctrl.result_tmp;
end if;
 
else -- signed conversion
if (ctrl.class(fp_class_snan_c) = '1') or (ctrl.class(fp_class_qnan_c) = '1') or (ctrl.class(fp_class_pos_inf_c) = '1') or -- NaN or +inf
((ctrl.sign = '0') and (ctrl.over = '1')) then -- positive out-of-range
ctrl.result <= x"7fffffff";
elsif (ctrl.class(fp_class_neg_zero_c) = '1') or (ctrl.class(fp_class_pos_zero_c) = '1') or (ctrl.under = '1') then -- subnormal zero or underflow
ctrl.result <= x"00000000";
elsif (ctrl.class(fp_class_neg_inf_c) = '1') or ((ctrl.sign = '1') and (ctrl.over = '1')) then -- -inf or negative out-of-range
ctrl.result <= x"80000000";
else -- result is ok, make sign adaption
if (ctrl.sign = '1') then
ctrl.result <= std_ulogic_vector(0 - unsigned(ctrl.result_tmp)); -- abs()
else
ctrl.result <= ctrl.result_tmp;
end if;
end if;
end if;
done_o <= '1';
ctrl.state <= S_IDLE;
 
when others => -- undefined
-- ------------------------------------------------------------
ctrl.state <= S_IDLE;
 
end case;
end if;
end process ctrl_engine;
 
-- result --
result_o <= ctrl.result;
 
-- exception flags --
flags_o(fp_exc_nv_c) <= ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c); -- invalid operation
flags_o(fp_exc_dz_c) <= '0'; -- divide by zero - not possible here
flags_o(fp_exc_of_c) <= ctrl.over or ctrl.class(fp_class_pos_inf_c) or ctrl.class(fp_class_neg_inf_c); -- overflow
flags_o(fp_exc_uf_c) <= ctrl.under; -- underflow
flags_o(fp_exc_nx_c) <= ctrl.rounded; -- inexact if result was rounded
 
 
-- Rounding -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
rounding_unit_ctrl: process(rmode_i, sreg)
begin
-- defaults --
round.en <= '0';
round.sub <= '0';
-- rounding mode --
case rmode_i(2 downto 0) is
when "000" => -- round to nearest, ties to even
if (sreg.ext_g = '0') then
round.en <= '0'; -- round down (do nothing)
else
if (sreg.ext_r = '0') and (sreg.ext_s = '0') then -- tie!
round.en <= sreg.int(0); -- round up if LSB of integer is set
else
round.en <= '1'; -- round up
end if;
end if;
round.sub <= '0'; -- increment
when "001" => -- round towards zero
round.en <= '0'; -- no rounding -> just truncate
when "010" => -- round down (towards -infinity)
round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s;
round.sub <= '1'; -- decrement
when "011" => -- round up (towards +infinity)
round.en <= sreg.ext_g or sreg.ext_r or sreg.ext_s;
round.sub <= '0'; -- increment
when "100" => -- round to nearest, ties to max magnitude
round.en <= '0'; -- FIXME / TODO
when others => -- undefined
round.en <= '0';
end case;
end process rounding_unit_ctrl;
 
-- rounding: guard and round bits --
sreg.ext_g <= sreg.mant(sreg.mant'left);
sreg.ext_r <= sreg.mant(sreg.mant'left-1);
 
 
-- incrementer/decrementer --
rounding_unit_add: process(round, sreg)
variable tmp_v : std_ulogic_vector(32 downto 0); -- including overflow
begin
tmp_v := '0' & sreg.int;
if (round.en = '1') then
if (round.sub = '0') then -- increment
round.output <= std_ulogic_vector(unsigned(tmp_v) + 1);
else -- decrement
round.output <= std_ulogic_vector(unsigned(tmp_v) - 1);
end if;
else -- do nothing
round.output <= tmp_v;
end if;
end process rounding_unit_add;
 
 
end neorv32_cpu_cp_fpu_f2i_rtl;
/rtl/core/neorv32_package.vhd
50,7 → 50,8
constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
 
-- CPU core --
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
constant ipb_entries_c : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
constant cp_timeout_en_c : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
 
-- "critical" number of implemented PMP regions --
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
60,7 → 61,7
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050208"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01050302"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions - FIXED!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
constant rf_r0_is_reg_c : boolean := true; -- reg_file.r0 is a *physical register* that has to be initialized to zero by the CPU HW
870,6 → 871,7
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
-- Extension Options --
/rtl/core/neorv32_top.vhd
5,7 → 5,7
-- # and define all the configuration generics according to your needs. Alternatively, you can use #
-- # one of the alternative top entities provided in the "rtl/top_templates" folder. #
-- # #
-- # Check the processor's data sheet for more information: docs/NEORV32.pdf #
-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
60,6 → 60,7
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
 
415,7 → 416,7
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Extension Options --
/rtl/top_templates/neorv32_test_setup.vhd
80,6 → 80,7
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => false, -- implement instruction stream sync.?
-- Extension Options --
/rtl/top_templates/neorv32_top_axi4lite.vhd
2,6 → 2,7
-- # << NEORV32 - Processor Top Entity with AXI4-Lite Compatible Master Interface >> #
-- # ********************************************************************************************* #
-- # (c) "AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc. #
-- # Note: External MTIME is not supported. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
58,6 → 59,7
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
-- Extension Options --
163,7 → 165,6
neoled_o : out std_logic; -- async serial data line
-- Interrupts --
soc_firq_i : in std_logic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_logic := '0'; -- machine software interrupt
mext_irq_i : in std_logic := '0' -- machine external interrupt
);
206,7 → 207,6
signal neoled_o_int : std_ulogic;
--
signal soc_firq_i_int : std_ulogic_vector(05 downto 0);
signal mtime_irq_i_int : std_ulogic;
signal msw_irq_i_int : std_ulogic;
signal mext_irq_i_int : std_ulogic;
 
260,6 → 260,7
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Extension Options --
354,7 → 355,7
mtime_i => (others => '0'), -- current system time
-- Interrupts --
soc_firq_i => soc_firq_i_int, -- fast interrupt channels
mtime_irq_i => mtime_irq_i_int, -- machine timer interrupt, available if IO_MTIME_EN = false
mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i => msw_irq_i_int, -- machine software interrupt
mext_irq_i => mext_irq_i_int -- machine external interrupt
);
/rtl/top_templates/neorv32_top_stdlogic.vhd
53,6 → 53,7
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
-- Extension Options --
229,6 → 230,7
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
-- Extension Options --
318,7 → 320,7
-- NCO output (available if IO_NCO_EN = true) --
nco_o => nco_o_int, -- numerically-controlled oscillator channels
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
neoled_o =>neoled_o_int, -- async serial data line
neoled_o => neoled_o_int, -- async serial data line
-- system time input from external MTIME (available if IO_MTIME_EN = false) --
mtime_i => mtime_i_int, -- current system time
-- Interrupts --
371,6 → 373,7
mtime_i_int <= std_ulogic_vector(mtime_i);
 
soc_firq_i_int <= std_ulogic_vector(soc_firq_i);
mtime_irq_i_int <= std_ulogic(mtime_irq_i);
msw_irq_i_int <= std_ulogic(msw_irq_i);
mext_irq_i_int <= std_ulogic(mext_irq_i);
 
/sim/neorv32_tb.vhd
200,6 → 200,7
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
-- Extension Options --
/sw/bootloader/bootloader.c
1,7 → 1,7
// #################################################################################################
// # << NEORV32 - Bootloader >> #
// # ********************************************************************************************* #
// # In order to run the bootloader on any CPU configuration, the bootloader should be compiled #
// # In order to run the bootloader on *any* CPU configuration, the bootloader should be compiled #
// # unsing the base ISA (rv32i/rv32e) only. #
// # ********************************************************************************************* #
// # Boot from (internal) instruction memory, UART or SPI Flash. #
18,7 → 18,7
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
261,10 → 261,12
print_hex_word(neorv32_cpu_csr_read(CSR_MIMPID));
neorv32_uart_print("\nCLK: ");
print_hex_word(SYSINFO_CLK);
neorv32_uart_print(" Hz\nUSER: ");
neorv32_uart_print("\nUSER: ");
print_hex_word(SYSINFO_USER_CODE);
neorv32_uart_print("\nMISA: ");
print_hex_word(neorv32_cpu_csr_read(CSR_MISA));
neorv32_uart_print("\nZEXT: ");
print_hex_word(neorv32_cpu_csr_read(CSR_MZEXT));
neorv32_uart_print("\nPROC: ");
print_hex_word(SYSINFO_FEATURES);
neorv32_uart_print("\nIMEM: ");
/sw/bootloader/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/bit_manipulation/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/bit_manipulation/neorv32_b_extension_intrinsics.h
1,6 → 1,9
// #################################################################################################
// # << NEORV32 - Intrinsics + Emulation Functions for the B.Zbb CPU extensions >> #
// # << NEORV32 - Intrinsics + Emulation Functions for the B CPU extensions >> #
// # ********************************************************************************************* #
// # The intrinsics provided by this library allow to use the hardware bit manipulation unit of #
// # the RISC-V B CPU extension without the need for B support by the compiler. #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
36,9 → 39,9
/**********************************************************************//**
* @file bit_manipulation/neorv32_b_extension_intrinsics.h
* @author Stephan Nolting
* @brief "Intrinsic" library for the NEORV32 bit manipulation (B.Zbb) extension. Also provides emulation functions for all intrinsics (functionality re-built in pure software).
* @brief "Intrinsic" library for the NEORV32 bit manipulation B extension. Also provides emulation functions for all intrinsics (functionality re-built in pure software).
*
* @warning This library is just a temporary fall-back until the B/Zbb extensions are supported by the upstream RISC-V GCC port.
* @warning This library is just a temporary fall-back until the B extensions are supported by the upstream RISC-V GCC port.
**************************************************************************/
#ifndef neorv32_b_extension_intrinsics_h
65,7 → 68,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_clz(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// clz a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00000, a0, 0b001, a0, 0b0010011);
 
84,7 → 91,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_ctz(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// ctz a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00001, a0, 0b001, a0, 0b0010011);
 
103,7 → 114,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_cpop(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// cpop a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00010, a0, 0b001, a0, 0b0010011);
 
122,7 → 137,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sextb(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// sext.b a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00100, a0, 0b001, a0, 0b0010011);
 
141,7 → 160,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sexth(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// sext.h a0, a0
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b00101, a0, 0b001, a0, 0b0010011);
 
161,9 → 184,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_min(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// min a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0000101, a1, a0, 0b100, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b100, a0, 0b0110011);
 
return result;
}
181,9 → 209,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_minu(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// minu a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0000101, a1, a0, 0b101, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b101, a0, 0b0110011);
 
return result;
}
201,9 → 234,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_max(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// max a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0000101, a1, a0, 0b110, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b110, a0, 0b0110011);
 
return result;
}
221,9 → 259,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_maxu(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// maxu a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0000101, a1, a0, 0b111, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0000101, a1, a0, 0b111, a0, 0b0110011);
 
return result;
}
241,9 → 284,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_pack(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// maxu a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0000100, a1, a0, 0b100, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0000100, a1, a0, 0b100, a0, 0b0110011);
 
return result;
}
261,9 → 309,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_andn(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// andn a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0100000, a1, a0, 0b111, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0100000, a1, a0, 0b111, a0, 0b0110011);
 
return result;
}
281,9 → 334,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_orn(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// orn a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0100000, a1, a0, 0b110, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0100000, a1, a0, 0b110, a0, 0b0110011);
 
return result;
}
301,9 → 359,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_xnor(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// xnor a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0100000, a1, a0, 0b100, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0100000, a1, a0, 0b100, a0, 0b0110011);
 
return result;
}
321,9 → 384,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_rol(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// rol a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0110000, a1, a0, 0b001, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0110000, a1, a0, 0b001, a0, 0b0110011);
 
return result;
}
341,9 → 409,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_ror(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// ror a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0110000, a1, a0, 0b101, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0110000, a1, a0, 0b101, a0, 0b0110011);
 
return result;
}
361,7 → 434,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_rori20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// rori a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0110000, 0b10100, a0, 0b101, a0, 0b0010011);
 
380,7 → 457,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_orcb(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// gorci a0, a0, 7 (pseudo-instruction: orc.b a0, a0)
CUSTOM_INSTR_R1_TYPE(0b0010100, 0b00111, a0, 0b101, a0, 0b0010011);
 
399,7 → 480,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_rev8(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// grevi a0, a0, -8 (pseudo-instruction: rev8 a0, a0)
CUSTOM_INSTR_R1_TYPE(0b0110100, 0b11000, a0, 0b101, a0, 0b0010011);
 
424,9 → 509,15
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbclr(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
 
// sbclr a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0100100, a1, a0, 0b001, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0100100, a1, a0, 0b001, a0, 0b0110011);
 
return result;
}
444,9 → 535,15
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbset(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
 
// sbset a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0010100, a1, a0, 0b001, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0010100, a1, a0, 0b001, a0, 0b0110011);
 
return result;
}
464,9 → 561,15
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbinv(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
 
// sbinv a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0110100, a1, a0, 0b001, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0110100, a1, a0, 0b001, a0, 0b0110011);
 
return result;
}
484,9 → 587,15
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbext(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
 
// sbext a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0100100, a1, a0, 0b101, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0100100, a1, a0, 0b101, a0, 0b0110011);
 
return result;
}
504,7 → 613,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbclri20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// sbclri a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0100100, 0b10100, a0, 0b001, a0, 0b0010011);
 
524,7 → 637,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbseti20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// sbseti a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0010100, 0b10100, a0, 0b001, a0, 0b0010011);
 
544,7 → 661,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbinvi20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// sbinvi a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0110100, 0b10100, a0, 0b001, a0, 0b0010011);
 
564,7 → 685,11
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sbexti20(uint32_t rs1) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// sbexti a0, a0, 20
CUSTOM_INSTR_R1_TYPE(0b0100100, 0b10100, a0, 0b101, a0, 0b0010011);
 
573,7 → 698,7
 
 
// ---------------------------------------------
// Zba - Single-bit instructions
// Zba - Shifted-add instructions
// ---------------------------------------------
 
 
589,9 → 714,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sh1add(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// sh1add a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0010000, a1, a0, 0b010, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b010, a0, 0b0110011);
 
return result;
}
609,9 → 739,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sh2add(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// sh2add a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0010000, a1, a0, 0b100, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b100, a0, 0b0110011);
 
return result;
}
629,9 → 764,14
uint32_t __attribute__ ((noinline)) riscv_intrinsic_sh3add(uint32_t rs1, uint32_t rs2) {
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
register uint32_t tmp_b __asm__ ("a1") = rs2;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// sh3add a0, a0, a1
CUSTOM_INSTR_R_TYPE(0b0010000, a1, a0, 0b110, a0, 0b0110011);
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b110, a0, 0b0110011);
 
return result;
}
1036,7 → 1176,7
 
 
// ---------------------------------------------
// Zba - Single-bit instructions
// Zba - Shifted-add instructions
// ---------------------------------------------
 
 
/sw/example/blink_led/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/coremark/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/cpu_test/main.c
206,7 → 206,7
// Test standard RISC-V performance counter [m]cycle[h]
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] [m]instret[h] counter test: ", cnt_test);
neorv32_uart_printf("[%i] [m]instret[h] counter: ", cnt_test);
 
cnt_test++;
 
230,7 → 230,7
// Test standard RISC-V performance counter [m]instret[h]
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] [m]cycle[h] counter test: ", cnt_test);
neorv32_uart_printf("[%i] [m]cycle[h] counter: ", cnt_test);
 
cnt_test++;
 
255,7 → 255,7
// Test mcountinhibt: inhibit auto-inc of [m]cycle
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] mcountinhibt.cy CSR test: ", cnt_test);
neorv32_uart_printf("[%i] mcountinhibt.cy CSR: ", cnt_test);
 
cnt_test++;
 
291,7 → 291,7
// Test mcounteren: do not allow cycle[h] access from user-mode
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] mcounteren.cy CSR test: ", cnt_test);
neorv32_uart_printf("[%i] mcounteren.cy CSR: ", cnt_test);
 
cnt_test++;
 
393,7 → 393,7
// External memory interface test
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] External memory access (@ 0x%x) test: ", cnt_test, (uint32_t)EXT_MEM_BASE);
neorv32_uart_printf("[%i] External memory access (@ 0x%x): ", cnt_test, (uint32_t)EXT_MEM_BASE);
 
if (is_simulation) { // check if this is a simulation
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT)) {
441,7 → 441,7
//// Test FENCE.I instruction (instruction buffer / i-cache clear & reload)
//// ----------------------------------------------------------
//neorv32_cpu_csr_write(CSR_MCAUSE, 0);
//neorv32_uart_printf("[%i] FENCE.I test: ", cnt_test);
//neorv32_uart_printf("[%i] FENCE.I: ", cnt_test);
//
//// check if implemented
//if (neorv32_cpu_csr_read(CSR_MZEXT) & (1 << CSR_MZEXT_ZIFENCEI)) {
466,7 → 466,7
// Illegal CSR access (CSR not implemented)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Illegal CSR (0xfff) access test: ", cnt_test);
neorv32_uart_printf("[%i] Illegal CSR (0xfff) access: ", cnt_test);
 
cnt_test++;
 
484,7 → 484,7
// Write-access to read-only CSR
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Read-only CSR (time) write access test: ", cnt_test);
neorv32_uart_printf("[%i] Read-only CSR (time) write access: ", cnt_test);
 
cnt_test++;
 
502,7 → 502,7
// No "real" CSR write access (because rs1 = r0)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Read-only CSR (time) no-write (rs1=0) access test: ", cnt_test);
neorv32_uart_printf("[%i] Read-only CSR (time) no-write (rs1=0) access: ", cnt_test);
 
cnt_test++;
 
608,7 → 608,7
// Unaligned instruction address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] I_ALIGN (instr. alignment) EXC test: ", cnt_test);
neorv32_uart_printf("[%i] I_ALIGN (instr. alignment) EXC: ", cnt_test);
 
// skip if C-mode is implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) == 0) {
636,7 → 636,7
// Instruction access fault
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] I_ACC (instr. bus access) EXC test: ", cnt_test);
neorv32_uart_printf("[%i] I_ACC (instr. bus access) EXC: ", cnt_test);
cnt_test++;
 
// call unreachable aligned address
654,7 → 654,7
// Illegal instruction
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] I_ILLEG (illegal instr.) EXC test: ", cnt_test);
neorv32_uart_printf("[%i] I_ILLEG (illegal instr.) EXC: ", cnt_test);
 
cnt_test++;
 
680,7 → 680,7
// Illegal compressed instruction
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] CI_ILLEG (illegal compr. instr.) EXC test: ", cnt_test);
neorv32_uart_printf("[%i] CI_ILLEG (illegal compr. instr.) EXC: ", cnt_test);
 
// skip if C-mode is not implemented
if ((neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_C_EXT)) != 0) {
712,7 → 712,7
// Breakpoint instruction
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] BREAK (break instr.) EXC test: ", cnt_test);
neorv32_uart_printf("[%i] BREAK (break instr.) EXC: ", cnt_test);
cnt_test++;
 
asm volatile("EBREAK");
729,7 → 729,7
// Unaligned load address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] L_ALIGN (load addr alignment) EXC test: ", cnt_test);
neorv32_uart_printf("[%i] L_ALIGN (load addr alignment) EXC: ", cnt_test);
cnt_test++;
 
// load from unaligned address
747,7 → 747,7
// Load access fault
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] L_ACC (load bus access) EXC test: ", cnt_test);
neorv32_uart_printf("[%i] L_ACC (load bus access) EXC: ", cnt_test);
cnt_test++;
 
// load from unreachable aligned address
765,7 → 765,7
// Unaligned store address
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] S_ALIGN (store addr alignment) EXC test: ", cnt_test);
neorv32_uart_printf("[%i] S_ALIGN (store addr alignment) EXC: ", cnt_test);
cnt_test++;
 
// store to unaligned address
783,7 → 783,7
// Store access fault
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] S_ACC (store bus access) EXC test: ", cnt_test);
neorv32_uart_printf("[%i] S_ACC (store bus access) EXC: ", cnt_test);
cnt_test++;
 
// store to unreachable aligned address
801,7 → 801,7
// Environment call from M-mode
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] ENVCALL (ecall instr.) from M-mode EXC test: ", cnt_test);
neorv32_uart_printf("[%i] ENVCALL (ecall instr.) from M-mode EXC: ", cnt_test);
cnt_test++;
 
asm volatile("ECALL");
818,7 → 818,7
// Environment call from U-mode
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] ENVCALL (ecall instr.) from U-mode EXC test: ", cnt_test);
neorv32_uart_printf("[%i] ENVCALL (ecall instr.) from U-mode EXC: ", cnt_test);
 
// skip if U-mode is not implemented
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U_EXT)) {
848,7 → 848,7
// Machine timer interrupt (MTIME)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MTI (machine timer) IRQ test: ", cnt_test);
neorv32_uart_printf("[%i] MTI (machine timer) IRQ: ", cnt_test);
 
if (neorv32_mtime_available()) {
cnt_test++;
879,7 → 879,7
// Machine software interrupt (MSI) via testbench
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MSI (via testbench) IRQ test: ", cnt_test);
neorv32_uart_printf("[%i] MSI (via testbench) IRQ: ", cnt_test);
 
if (is_simulation) { // check if this is a simulation
cnt_test++;
907,7 → 907,7
// Machine external interrupt (MEI) via testbench
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] MEI (via testbench) IRQ test: ", cnt_test);
neorv32_uart_printf("[%i] MEI (via testbench) IRQ: ", cnt_test);
 
if (is_simulation) { // check if this is a simulation
cnt_test++;
1294,7 → 1294,7
// ----------------------------------------------------------
// Fast interrupt channel 9 (reserved)
// ----------------------------------------------------------
neorv32_uart_printf("[%i] FIRQ9 test: ", cnt_test);
neorv32_uart_printf("[%i] FIRQ9: ", cnt_test);
neorv32_uart_printf("skipped (not implemented)\n");
 
 
1302,7 → 1302,7
// Fast interrupt channel 10..15 (SoC fast IRQ 0..5)
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] FIRQ10..15 (SoC fast IRQ 0..5; via testbench) test: ", cnt_test);
neorv32_uart_printf("[%i] FIRQ10..15 (SoC fast IRQ 0..5; via testbench): ", cnt_test);
 
if (is_simulation) { // check if this is a simulation
 
1384,7 → 1384,7
// Test invalid CSR access in user mode
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] Invalid CSR access (mstatus) from user mode test: ", cnt_test);
neorv32_uart_printf("[%i] Invalid CSR access (mstatus) from user mode: ", cnt_test);
 
// skip if U-mode is not implemented
if (neorv32_cpu_csr_read(CSR_MISA) & (1<<CSR_MISA_U_EXT)) {
1420,7 → 1420,7
// Test RTE debug trap handler
// ----------------------------------------------------------
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
neorv32_uart_printf("[%i] RTE (runtime env.) debug trap handler test: ", cnt_test);
neorv32_uart_printf("[%i] RTE (runtime env.) debug trap handler: ", cnt_test);
 
cnt_test++;
 
1474,7 → 1474,7
 
 
// ------ EXECUTE: should fail ------
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] execute test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] execute: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1499,7 → 1499,7
 
 
// ------ LOAD: should work ------
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] read test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] read: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1524,7 → 1524,7
 
 
// ------ STORE: should fail ------
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] write test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: U-mode [!X,!W,R] write: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1549,7 → 1549,7
 
 
// ------ Lock test - pmpcfg0.0 / pmpaddr0 ------
neorv32_uart_printf("[%i] PMP: Entry [mode=off] lock test: ", cnt_test);
neorv32_uart_printf("[%i] PMP: Entry [mode=off] lock: ", cnt_test);
cnt_test++;
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
 
1666,7 → 1666,7
neorv32_uart_printf("#08 - Store operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER8));
neorv32_uart_printf("#09 - Load/store wait cycles: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER9));
neorv32_uart_printf("#10 - Unconditional jumps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER10));
neorv32_uart_printf("#11 - Cond. branches (all): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
neorv32_uart_printf("#11 - Cond. branches (total): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER11));
neorv32_uart_printf("#12 - Cond. branches (taken): %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER12));
neorv32_uart_printf("#13 - Entered traps: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER13));
neorv32_uart_printf("#14 - Illegal operations: %u\n", (uint32_t)neorv32_cpu_csr_read(CSR_MHPMCOUNTER14));
/sw/example/cpu_test/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/demo_freeRTOS/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
57,7 → 57,7
MABI ?= -mabi=ilp32
 
# User flags for additional configuration (will be added to compiler flags)
USER_FLAGS ?=
USER_FLAGS ?=
 
# Serial port for executable upload via bootloer
COM_PORT ?= /dev/ttyUSB0
69,79 → 69,6
 
 
# -----------------------------------------------------------------------------
# FreeRTOS
# -----------------------------------------------------------------------------
ifneq (,$(findstring RUN_FREERTOS_DEMO,$(USER_FLAGS)))
# FreeRTOS home folder (adapt this!)
FREERTOS_HOME ?= /mnt/n/Projects/FreeRTOSv10.4.1
 
# FreeRTOS RISC-V specific
APP_SRC += $(wildcard $(FREERTOS_HOME)/FreeRTOS/Source/portable/GCC/RISC-V/*.c)
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
 
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS/Source/portable/GCC/RISC-V
 
# FreeRTOS core
APP_SRC += $(wildcard $(FREERTOS_HOME)/FreeRTOS/Source/*.c)
APP_SRC += $(wildcard $(FREERTOS_HOME)/FreeRTOS/Source/portable/MemMang/heap_4.c)
 
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS/Source/include
 
# FreeRTOS sources for the full_demo
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/blocktim.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/dynamic.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/GenQTest.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/recmutex.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/TaskNotify.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/TaskNotifyArray.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS/Demo/Common/Minimal/TimerDemo.c
 
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS/Demo/Common/include
 
# NEORV32 specific
ASM_INC += -DportasmHANDLE_INTERRUPT=SystemIrqHandler
 
APP_INC += -I chip_specific_extensions/neorv32
 
ASM_INC += -I chip_specific_extensions/neorv32
 
# Demo application
APP_SRC += blinky_demo/main_blinky.c
APP_SRC += full_demo/main_full.c
APP_SRC += full_demo/RegTest.s
endif
 
# -----------------
# FreeRTOS-Plus-CLI
# -----------------
ifneq (,$(findstring FREERTOS_PLUS_CLI,$(USER_FLAGS)))
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI/FreeRTOS_CLI.c
 
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI
endif
 
# -----------------
# FreeRTOS-Plus-TCP
# -----------------
ifneq (,$(findstring FREERTOS_PLUS_TCP,$(USER_FLAGS)))
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_ARP.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DHCP.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_DNS.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_IP.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Sockets.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_Stream_Buffer.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_IP.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_TCP_WIN.c
APP_SRC += $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/FreeRTOS_UDP_IP.c
 
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/include
APP_INC += -I $(FREERTOS_HOME)/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP/portable/Compiler/GCC
endif
 
 
 
# -----------------------------------------------------------------------------
# NEORV32 framework
# -----------------------------------------------------------------------------
# Path to NEORV32 linker script and startup file
199,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/demo_gpio_irq/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/demo_nco/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/demo_neopixel/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/demo_pwm/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/demo_trng/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/demo_twi/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/demo_wdt/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/floating_point_test/README.md
0,0 → 1,38
# NEORV32 `Zfinx` Floating-Point Extension
 
The RISC-V `Zfinx` single-precision floating-point extensions uses the integer register file `x` instead of the dedicated floating-point `f` register file (which is
defined by the RISC-V `F` single-precision floating-point extension). Hence, the standard data transfer instructions from the `F` extension are **not** available in `Zfinx`:
 
* floating-point load/store operations (`FLW`, `FSW`) and their compressed versions
* integer register file `x` <-> floating point register file `f` move operations (`FMV.W.X`, `FMV.X.W`)
 
 
:information_source: More information regarding the RISC-V `Zfinx` single-precision floating-point extension can be found in the officail GitHub repo:
[`github.com/riscv/riscv-zfinx`](https://github.com/riscv/riscv-zfinx).
 
:warning: The RISC-V `Zfinx` extension is not officially ratified yet, but it is assumed to remain unchanged. Hence, it is not supported by the upstream RISC-V GCC port.
Make sure you **do not** use the `f` ISA attribute when compiling applications that use floating-point arithmetic (`-march=rv32i*f*` is **NOT ALLOWED!**).
 
 
## Intrinsic Library
 
The NEORV32 `Zfinx` floating-point extension can still be used using the provided **intrinsic library**. This library uses "custom" inline assmbly instructions
wrapped within normal C-language functions. Each original instruction of the extension can be utilized using an according intrinsic function.
 
For example, the floating-point addition instruction `FADD.S` can be invoked using the according intrinsic function:
 
```c
float riscv_intrinsic_fadds(float rs1, float rs2)
```
 
The pure-software emulation instruction, which uses the standard builtin functions to execute all floating-point operations, is available via wrapper function. The
emulation function for the `FADD.S` instruction is:
 
```c
float riscv_emulate_fadds(float rs1, float rs2)
```
 
The emulation functions as well as the available intrinsics for the `Zfinx` extension are located in `neorv32_zfinx_extension_intrinsics.h`.
 
The provided test program `main.c` verifies all currently implemented `Zfinx` instructions by checking the functionality against the pure software-based emulation model
(GCC soft-float library).
/sw/example/floating_point_test/main.c
0,0 → 1,604
// #################################################################################################
// # << NEORV32 - RISC-V Single-Precision Floating-Point 'Zfinx' Extension Verification Program >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file floating_point_test/main.c
* @author Stephan Nolting
* @brief Verification program for the NEORV32 'Zfinx' extension (floating-point in x registers) using pseudo-random data as input; compares results from hardware against pure-sw reference functions.
**************************************************************************/
 
#include <neorv32.h>
#include <float.h>
#include <math.h>
#include "neorv32_zfinx_extension_intrinsics.h"
 
#ifdef NAN
/* NAN is supported */
#else
#warning NAN macro not supported!
#endif
#ifdef INFINITY
/* INFINITY is supported */
#else
#warning INFINITY macro not supported!
#endif
 
 
/**********************************************************************//**
* @name User configuration
**************************************************************************/
/**@{*/
/** UART BAUD rate */
#define BAUD_RATE (19200)
//** Number of test cases for each instruction */
#define NUM_TEST_CASES (1000000)
//** Silent mode (only show actual errors when != 0) */
#define SILENT_MODE (1)
//** Run conversion tests when != 0 */
#define RUN_CONV_TESTS (1)
//** Run add/sub tests when != 0 */
#define RUN_ADDSUB_TESTS (1)
//** Run multiplication tests when != 0 */
#define RUN_MUL_TESTS (1)
//** Run min/max tests when != 0 */
#define RUN_MINMAX_TESTS (1)
//** Run comparison tests when != 0 */
#define RUN_COMPARE_TESTS (1)
//** Run sign-injection tests when != 0 */
#define RUN_SGNINJ_TESTS (1)
//** Run classify tests when != 0 */
#define RUN_CLASSIFY_TESTS (1)
//** Run unsupported instructions tests when != 0 */
#define RUN_UNAVAIL_TESTS (1)
/**@}*/
 
 
// Prototypes
uint32_t get_test_vector(void);
uint32_t xorshift32(void);
uint32_t verify_result(uint32_t num, uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res);
void print_report(uint32_t num_err);
 
 
/**********************************************************************//**
* Main function; test all available operations of the NEORV32 'Zfinx' extensions using bit floating-point hardware intrinsics and software-only reference functions (emulation).
*
* @note This program requires the Zfinx CPU extension.
*
* @return Irrelevant.
**************************************************************************/
int main() {
 
uint32_t err_cnt = 0;
uint32_t err_cnt_total = 0;
uint32_t test_cnt = 0;
uint32_t i = 0;
float_conv_t opa;
float_conv_t opb;
float_conv_t res_hw;
float_conv_t res_sw;
 
 
// init primary UART
neorv32_uart_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
 
// capture all exceptions and give debug info via UART
neorv32_rte_setup();
 
// check available hardware extensions and compare with compiler flags
neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
 
// check if Zfinx extension is implemented at all
if (neorv32_check_zextension(CSR_MZEXT_ZFINX) == 0) {
neorv32_uart_print("Error! <Zfinx> extension not synthesized!\n");
return 0;
}
 
 
// Disable compilation by default
#ifndef RUN_TEST
#warning Program HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_TEST clean_all exe<< to compile it.
 
// inform the user if you are actually executing this
neorv32_uart_printf("ERROR! Program has not been compiled. Use >>make USER_FLAGS+=-DRUN_TEST clean_all exe<< to compile it.\n");
 
return 0;
#endif
 
 
// intro
neorv32_uart_printf("<<< Zfinx extension test >>>\n");
#if (SILENT_MODE != 0)
neorv32_uart_printf("SILENT_MODE enabled (only showing actual errors)\n");
#endif
neorv32_uart_printf("Test cases per instruction: %u\n\n", (uint32_t)NUM_TEST_CASES);
 
 
// clear exception status word
neorv32_cpu_csr_write(CSR_FFLAGS, 0);; // real hardware
feclearexcept(FE_ALL_EXCEPT); // software runtime (GCC floating-point emulation)
 
 
// ----------------------------------------------------------------------------
// Conversion Tests
// ----------------------------------------------------------------------------
 
#if (RUN_CONV_TESTS != 0)
neorv32_uart_printf("\n#%u: FCVT.S.WU (unsigned integer to float)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fcvt_swu(opa.binary_value);
res_sw.float_value = riscv_emulate_fcvt_swu(opa.binary_value);
err_cnt += verify_result(i, opa.binary_value, 0, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
 
neorv32_uart_printf("\n#%u: FCVT.S.W (signed integer to float)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fcvt_sw((int32_t)opa.binary_value);
res_sw.float_value = riscv_emulate_fcvt_sw((int32_t)opa.binary_value);
err_cnt += verify_result(i, opa.binary_value, 0, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
 
neorv32_uart_printf("\n#%u: FCVT.WU.S (float to unsigned integer)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
res_hw.binary_value = riscv_intrinsic_fcvt_wus(opa.float_value);
res_sw.binary_value = riscv_emulate_fcvt_wus(opa.float_value);
err_cnt += verify_result(i, opa.binary_value, 0, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
 
neorv32_uart_printf("\n#%u: FCVT.W.S (float to signed integer)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
res_hw.binary_value = (uint32_t)riscv_intrinsic_fcvt_ws(opa.float_value);
res_sw.binary_value = (uint32_t)riscv_emulate_fcvt_ws(opa.float_value);
err_cnt += verify_result(i, opa.binary_value, 0, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
#endif
 
 
// ----------------------------------------------------------------------------
// Add/Sub Tests
// ----------------------------------------------------------------------------
 
#if (RUN_ADDSUB_TESTS != 0)
neorv32_uart_printf("\n#%u: FADD.S (addition)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fadds(opa.float_value, opb.float_value);
res_sw.float_value = riscv_emulate_fadds(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
 
neorv32_uart_printf("\n#%u: FSUB.S (subtraction)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fsubs(opa.float_value, opb.float_value);
res_sw.float_value = riscv_emulate_fsubs(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
#endif
 
 
// ----------------------------------------------------------------------------
// Multiplication Tests
// ----------------------------------------------------------------------------
 
#if (RUN_MUL_TESTS != 0)
neorv32_uart_printf("\n#%u: FMUL.S (multiplication)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fmuls(opa.float_value, opb.float_value);
res_sw.float_value = riscv_emulate_fmuls(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
#endif
 
 
// ----------------------------------------------------------------------------
// Min/Max Tests
// ----------------------------------------------------------------------------
 
#if (RUN_MINMAX_TESTS != 0)
neorv32_uart_printf("\n#%u: FMIN.S (select minimum)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fmins(opa.float_value, opb.float_value);
res_sw.float_value = riscv_emulate_fmins(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
 
neorv32_uart_printf("\n#%u: FMAX.S (select maximum)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fmaxs(opa.float_value, opb.float_value);
res_sw.float_value = riscv_emulate_fmaxs(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
#endif
 
 
// ----------------------------------------------------------------------------
// Comparison Tests
// ----------------------------------------------------------------------------
 
#if (RUN_COMPARE_TESTS != 0)
neorv32_uart_printf("\n#%u: FEQ.S (compare if equal)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.binary_value = riscv_intrinsic_feqs(opa.float_value, opb.float_value);
res_sw.binary_value = riscv_emulate_feqs(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
 
neorv32_uart_printf("\n#%u: FLT.S (compare if less-than)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.binary_value = riscv_intrinsic_flts(opa.float_value, opb.float_value);
res_sw.binary_value = riscv_emulate_flts(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
 
neorv32_uart_printf("\n#%u: FLE.S (compare if less-than-or-equal)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.binary_value = riscv_intrinsic_fles(opa.float_value, opb.float_value);
res_sw.binary_value = riscv_emulate_fles(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
#endif
 
 
// ----------------------------------------------------------------------------
// Sign-Injection Tests
// ----------------------------------------------------------------------------
 
#if (RUN_SGNINJ_TESTS != 0)
neorv32_uart_printf("\n#%u: FSGNJ.S (sign-injection)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fsgnjs(opa.float_value, opb.float_value);
res_sw.float_value = riscv_emulate_fsgnjs(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
 
neorv32_uart_printf("\n#%u: FSGNJN.S (sign-injection NOT)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fsgnjns(opa.float_value, opb.float_value);
res_sw.float_value = riscv_emulate_fsgnjns(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
 
neorv32_uart_printf("\n#%u: FSGNJX.S (sign-injection XOR)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
res_hw.float_value = riscv_intrinsic_fsgnjxs(opa.float_value, opb.float_value);
res_sw.float_value = riscv_emulate_fsgnjxs(opa.float_value, opb.float_value);
err_cnt += verify_result(i, opa.binary_value, opb.binary_value, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
#endif
 
 
// ----------------------------------------------------------------------------
// Classify Tests
// ----------------------------------------------------------------------------
 
#if (RUN_CLASSIFY_TESTS != 0)
neorv32_uart_printf("\n#%u: FCLASS.S (classify)...\n", test_cnt);
err_cnt = 0;
for (i=0;i<(uint32_t)NUM_TEST_CASES; i++) {
opa.binary_value = get_test_vector();
res_hw.binary_value = riscv_intrinsic_fclasss(opa.float_value);
res_sw.binary_value = riscv_emulate_fclasss(opa.float_value);
err_cnt += verify_result(i, opa.binary_value, 0, res_sw.binary_value, res_hw.binary_value);
}
print_report(err_cnt);
err_cnt_total += err_cnt;
test_cnt++;
#endif
 
// ----------------------------------------------------------------------------
// UNSUPPORTED Instructions Tests - Execution should raise illegal instruction exception
// ----------------------------------------------------------------------------
 
#if (RUN_UNAVAIL_TESTS != 0)
neorv32_uart_printf("\n# unsupported FDIV.S (division) [illegal instruction]...\n");
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
riscv_intrinsic_fdivs(opa.float_value, opb.float_value);
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
err_cnt_total++;
}
else {
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
}
 
neorv32_uart_printf("\n# unsupported FSQRT.S (square root) [illegal instruction]...\n");
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
riscv_intrinsic_fsqrts(opa.float_value);
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
err_cnt_total++;
}
else {
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
}
 
neorv32_uart_printf("\n# unsupported FMADD.S (fused multiply-add) [illegal instruction]...\n");
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
riscv_intrinsic_fmadds(opa.float_value, opb.float_value, -opa.float_value);
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
err_cnt_total++;
}
else {
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
}
 
neorv32_uart_printf("\n# unsupported FMSUB.S (fused multiply-sub) [illegal instruction]...\n");
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
riscv_intrinsic_fmsubs(opa.float_value, opb.float_value, -opa.float_value);
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
err_cnt_total++;
}
else {
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
}
 
neorv32_uart_printf("\n# unsupported FNMSUB.S (fused negated multiply-sub) [illegal instruction]...\n");
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
riscv_intrinsic_fnmadds(opa.float_value, opb.float_value, -opa.float_value);
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
err_cnt_total++;
}
else {
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
}
 
neorv32_uart_printf("\n# unsupported FNMADD.S (fused negated multiply-add) [illegal instruction]...\n");
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
opa.binary_value = get_test_vector();
opb.binary_value = get_test_vector();
riscv_intrinsic_fnmadds(opa.float_value, opb.float_value, -opa.float_value);
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
err_cnt_total++;
}
else {
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
}
#endif
 
 
// final report
if (err_cnt_total != 0) {
neorv32_uart_printf("\n%c[1m[ZFINX EXTENSION VERIFICATION FAILED!]%c[0m\n", 27, 27);
neorv32_uart_printf("%u errors in %u test cases\n", err_cnt_total, test_cnt*(uint32_t)NUM_TEST_CASES);
}
else {
neorv32_uart_printf("\n%c[1m[Zfinx extension verification successful!]%c[0m\n", 27, 27);
}
 
return 0;
}
 
 
/**********************************************************************//**
* Generate 32-bit test data (including special values like INFINITY every now and then).
*
* @return Test data (32-bit).
**************************************************************************/
uint32_t get_test_vector(void) {
 
float_conv_t tmp;
 
// generate special value "every" ~256th time this function is called
if ((xorshift32() & 0xff) == 0xff) {
 
switch((xorshift32() >> 10) & 0x3) { // random decision which special value we are taking
case 0: tmp.float_value = +INFINITY; break;
case 1: tmp.float_value = -INFINITY; break;
case 2: tmp.float_value = +0.0f; break;
case 3: tmp.float_value = -0.0f; break;
case 4: tmp.binary_value = 0x7fffffff; break;
case 5: tmp.binary_value = 0xffffffff; break;
case 6: tmp.float_value = NAN; break;
case 7: tmp.float_value = NAN; break; // FIXME signaling_NAN?
default: tmp.float_value = NAN; break;
}
}
else {
tmp.binary_value = xorshift32();
}
 
// subnormal numbers are not supported yet!
// flush them to zero
//tmp.float_value = subnormal_flush(tmp.float_value);
 
return tmp.binary_value;
}
 
 
/**********************************************************************//**
* PSEUDO-RANDOM number generator.
*
* @return Random data (32-bit).
**************************************************************************/
uint32_t xorshift32(void) {
 
static uint32_t x32 = 314159265;
 
x32 ^= x32 << 13;
x32 ^= x32 >> 17;
x32 ^= x32 << 5;
 
return x32;
}
 
 
/**********************************************************************//**
* Verify results (software reference vs. actual hardware).
*
* @param[in] num Test case number
* @param[in] opa Operand 1
* @param[in] opb Operand 2
* @param[in] ref Software reference
* @param[in] res Actual results from hardware
* @return zero if results are equal.
**************************************************************************/
uint32_t verify_result(uint32_t num, uint32_t opa, uint32_t opb, uint32_t ref, uint32_t res) {
 
#if (SILENT_MODE == 0)
neorv32_uart_printf("%u: opa = 0x%x, opb = 0x%x : ref[SW] = 0x%x vs. res[HW] = 0x%x ", num, opa, opb, ref, res);
#endif
 
if (ref != res) {
#if (SILENT_MODE != 0)
neorv32_uart_printf("%u: opa = 0x%x, opb = 0x%x : ref[SW] = 0x%x vs. res[HW] = 0x%x ", num, opa, opb, ref, res);
#endif
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
return 1;
}
else {
#if (SILENT_MODE == 0)
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
#endif
return 0;
}
}
 
 
/**********************************************************************//**
* Print test report.
*
* @param[in] num_err Number or errors in this test.
**************************************************************************/
void print_report(uint32_t num_err) {
 
neorv32_uart_printf("Errors: %u/%u ", num_err, (uint32_t)NUM_TEST_CASES);
 
if (num_err == 0) {
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
}
else {
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
}
}
/sw/example/floating_point_test/makefile
0,0 → 1,338
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
# #
# 1. Redistributions of source code must retain the above copyright notice, this list of #
# conditions and the following disclaimer. #
# #
# 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
# conditions and the following disclaimer in the documentation and/or other materials #
# provided with the distribution. #
# #
# 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
# endorse or promote products derived from this software without specific prior written #
# permission. #
# #
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
# OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
# GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
# OF THE POSSIBILITY OF SUCH DAMAGE. #
# ********************************************************************************************* #
# The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
#################################################################################################
 
 
# *****************************************************************************
# USER CONFIGURATION
# *****************************************************************************
# User's application sources (*.c, *.cpp, *.s, *.S); add additional files here
APP_SRC ?= $(wildcard ./*.c) $(wildcard ./*.s) $(wildcard ./*.cpp) $(wildcard ./*.S)
 
# User's application include folders (don't forget the '-I' before each entry)
APP_INC ?= -I .
# User's application include folders - for assembly files only (don't forget the '-I' before each entry)
ASM_INC ?= -I .
 
# Optimization
EFFORT ?= -Os
 
# Compiler toolchain
RISCV_TOOLCHAIN ?= riscv32-unknown-elf
 
# CPU architecture and ABI
MARCH ?= -march=rv32i
MABI ?= -mabi=ilp32
 
# User flags for additional configuration (will be added to compiler flags)
USER_FLAGS ?=
 
# Serial port for executable upload via bootloer
COM_PORT ?= /dev/ttyUSB0
 
# Relative or absolute path to the NEORV32 home folder
NEORV32_HOME ?= ../../..
# *****************************************************************************
 
 
 
# -----------------------------------------------------------------------------
# NEORV32 framework
# -----------------------------------------------------------------------------
# Path to NEORV32 linker script and startup file
NEORV32_COM_PATH = $(NEORV32_HOME)/sw/common
# Path to main NEORV32 library include files
NEORV32_INC_PATH = $(NEORV32_HOME)/sw/lib/include
# Path to main NEORV32 library source files
NEORV32_SRC_PATH = $(NEORV32_HOME)/sw/lib/source
# Path to NEORV32 executable generator
NEORV32_EXG_PATH = $(NEORV32_HOME)/sw/image_gen
# Path to NEORV32 core rtl folder
NEORV32_RTL_PATH = $(NEORV32_HOME)/rtl/core
# Marker file to check for NEORV32 home folder
NEORV32_HOME_MARKER = $(NEORV32_INC_PATH)/neorv32.h
 
# Core libraries (peripheral and CPU drivers)
CORE_SRC = $(wildcard $(NEORV32_SRC_PATH)/*.c)
# Application start-up code
CORE_SRC += $(NEORV32_COM_PATH)/crt0.S
 
# Linker script
LD_SCRIPT = $(NEORV32_COM_PATH)/neorv32.ld
 
# Main output files
APP_EXE = neorv32_exe.bin
APP_ASM = main.asm
APP_IMG = neorv32_application_image.vhd
BOOT_IMG = neorv32_bootloader_image.vhd
 
 
# -----------------------------------------------------------------------------
# Sources and objects
# -----------------------------------------------------------------------------
# Define all sources
SRC = $(APP_SRC)
SRC += $(CORE_SRC)
 
# Define all object files
OBJ = $(SRC:%=%.o)
 
 
# -----------------------------------------------------------------------------
# Tools and flags
# -----------------------------------------------------------------------------
# Compiler tools
CC = $(RISCV_TOOLCHAIN)-gcc
OBJDUMP = $(RISCV_TOOLCHAIN)-objdump
OBJCOPY = $(RISCV_TOOLCHAIN)-objcopy
SIZE = $(RISCV_TOOLCHAIN)-size
 
# Host native compiler
CC_X86 = g++ -Wall -O -g
 
# NEORV32 executable image generator
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
CC_OPTS += $(USER_FLAGS)
 
 
# -----------------------------------------------------------------------------
# Application output definitions
# -----------------------------------------------------------------------------
.PHONY: check info help elf_info clean clean_all bootloader
.DEFAULT_GOAL := help
 
# 'compile' is still here for compatibility
exe: $(APP_ASM) $(APP_EXE)
compile: $(APP_ASM) $(APP_EXE)
install: $(APP_ASM) $(APP_IMG)
all: $(APP_ASM) $(APP_EXE) $(APP_IMG)
 
# Check if making bootloader
# Use different base address and legth for instruction memory/"rom" (BOOTMEM instead of IMEM)
# Also define "make_bootloader" for crt0.S
target bootloader: CC_OPTS += -Wl,--defsym=make_bootloader=1 -Dmake_bootloader
 
 
# -----------------------------------------------------------------------------
# Image generator targets
# -----------------------------------------------------------------------------
# install/compile tools
$(IMAGE_GEN): $(NEORV32_EXG_PATH)/image_gen.cpp
@echo Compiling $(IMAGE_GEN)
@$(CC_X86) $< -o $(IMAGE_GEN)
 
 
# -----------------------------------------------------------------------------
# General targets: Assemble, compile, link, dump
# -----------------------------------------------------------------------------
# Compile app *.s sources (assembly)
%.s.o: %.s
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@
 
# Compile app *.S sources (assembly + C pre-processor)
%.S.o: %.S
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(ASM_INC) $< -o $@
 
# Compile app *.c sources
%.c.o: %.c
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@
 
# Compile app *.cpp sources
%.cpp.o: %.cpp
@$(CC) -c $(CC_OPTS) -I $(NEORV32_INC_PATH) $(APP_INC) $< -o $@
 
# Link object files and show memory utilization
main.elf: $(OBJ)
@$(CC) $(CC_OPTS) -T $(LD_SCRIPT) $(OBJ) -o $@ -lm
@echo "Memory utilization:"
@$(SIZE) main.elf
 
# Assembly listing file (for debugging)
$(APP_ASM): main.elf
@$(OBJDUMP) -d -S -z $< > $@
 
# Generate final executable from .text + .rodata + .data (in THIS order!)
main.bin: main.elf $(APP_ASM)
@$(OBJCOPY) -I elf32-little $< -j .text -O binary text.bin
@$(OBJCOPY) -I elf32-little $< -j .rodata -O binary rodata.bin
@$(OBJCOPY) -I elf32-little $< -j .data -O binary data.bin
@cat text.bin rodata.bin data.bin > $@
@rm -f text.bin rodata.bin data.bin
 
 
# -----------------------------------------------------------------------------
# Application targets: Generate binary executable, install (as VHDL file)
# -----------------------------------------------------------------------------
# Generate NEORV32 executable image for upload via bootloader
$(APP_EXE): main.bin $(IMAGE_GEN)
@set -e
@$(IMAGE_GEN) -app_bin $< $@ $(shell basename $(CURDIR))
@echo "Executable ($(APP_EXE)) size in bytes:"
@wc -c < $(APP_EXE)
 
# Generate NEORV32 executable VHDL boot image
$(APP_IMG): main.bin $(IMAGE_GEN)
@set -e
@$(IMAGE_GEN) -app_img $< $@ $(shell basename $(CURDIR))
@echo "Installing application image to $(NEORV32_RTL_PATH)/$(APP_IMG)"
@cp $(APP_IMG) $(NEORV32_RTL_PATH)/.
 
 
# -----------------------------------------------------------------------------
# Bootloader targets
# -----------------------------------------------------------------------------
# Create and install bootloader VHDL init image
$(BOOT_IMG): main.bin $(IMAGE_GEN)
@set -e
@$(IMAGE_GEN) -bld_img $< $(BOOT_IMG) $(shell basename $(CURDIR))
@echo "Installing bootloader image to $(NEORV32_RTL_PATH)/$(BOOT_IMG)"
@cp $(BOOT_IMG) $(NEORV32_RTL_PATH)/.
 
# Just an alias that
bootloader: $(BOOT_IMG)
 
 
# -----------------------------------------------------------------------------
# Check toolchain
# -----------------------------------------------------------------------------
check: $(IMAGE_GEN)
@echo "---------------- Check: NEORV32_HOME folder ----------------"
ifneq ($(shell [ -e $(NEORV32_HOME_MARKER) ] && echo 1 || echo 0 ), 1)
$(error NEORV32_HOME folder not found!)
endif
@echo "NEORV32_HOME: $(NEORV32_HOME)"
@echo "---------------- Check: $(CC) ----------------"
@$(CC) -v
@echo "---------------- Check: $(OBJDUMP) ----------------"
@$(OBJDUMP) -V
@echo "---------------- Check: $(OBJCOPY) ----------------"
@$(OBJCOPY) -V
@echo "---------------- Check: $(SIZE) ----------------"
@$(SIZE) -V
@echo "---------------- Check: NEORV32 image_gen ----------------"
@$(IMAGE_GEN) -help
@echo "---------------- Check: Native GCC ----------------"
@$(CC_X86) -v
@echo
@echo "Toolchain check OK"
 
 
# -----------------------------------------------------------------------------
# Upload executable via serial port to bootloader
# -----------------------------------------------------------------------------
upload: $(APP_EXE)
@sh $(NEORV32_EXG_PATH)/uart_upload.sh $(COM_PORT) $(APP_EXE)
 
 
# -----------------------------------------------------------------------------
# Show configuration
# -----------------------------------------------------------------------------
info:
@echo "---------------- Info: Project ----------------"
@echo "Project folder: $(shell basename $(CURDIR))"
@echo "Source files: $(APP_SRC)"
@echo "Include folder(s): $(APP_INC)"
@echo "ASM include folder(s): $(ASM_INC)"
@echo "---------------- Info: NEORV32 ----------------"
@echo "NEORV32 home folder (NEORV32_HOME): $(NEORV32_HOME)"
@echo "IMAGE_GEN: $(IMAGE_GEN)"
@echo "Core source files:"
@echo "$(CORE_SRC)"
@echo "Core include folder:"
@echo "$(NEORV32_INC_PATH)"
@echo "---------------- Info: Objects ----------------"
@echo "Project object files:"
@echo "$(OBJ)"
@echo "---------------- Info: RISC-V CPU ----------------"
@echo "MARCH: $(MARCH)"
@echo "MABI: $(MABI)"
@echo "---------------- Info: Toolchain ----------------"
@echo "Toolchain: $(RISCV_TOLLCHAIN)"
@echo "CC: $(CC)"
@echo "OBJDUMP: $(OBJDUMP)"
@echo "OBJCOPY: $(OBJCOPY)"
@echo "SIZE: $(SIZE)"
@echo "---------------- Info: Compiler Libraries ----------------"
@echo "LIBGCC:"
@$(CC) -print-libgcc-file-name
@echo "SEARCH-DIRS:"
@$(CC) -print-search-dirs
@echo "---------------- Info: Flags ----------------"
@echo "USER_FLAGS: $(USER_FLAGS)"
@echo "CC_OPTS: $(CC_OPTS)"
@echo "---------------- Info: Host Native GCC Flags ----------------"
@echo "CC_X86: $(CC_X86)"
 
 
# -----------------------------------------------------------------------------
# Show final ELF details (just for debugging)
# -----------------------------------------------------------------------------
elf_info: main.elf
@$(OBJDUMP) -x main.elf
 
 
# -----------------------------------------------------------------------------
# Help
# -----------------------------------------------------------------------------
help:
@echo "<<< NEORV32 Application Makefile >>>"
@echo "Make sure to add the bin folder of RISC-V GCC to your PATH variable."
@echo "Targets:"
@echo " help - show this text"
@echo " check - check toolchain"
@echo " info - show makefile/toolchain configuration"
@echo " exe - compile and generate <neorv32_exe.bin> executable for upload via bootloader"
@echo " install - compile, generate and install VHDL IMEM boot image (for application)"
@echo " all - compile and generate <neorv32_exe.bin> executable for upload via bootloader and generate and install VHDL IMEM boot image (for application)"
@echo " clean - clean up project"
@echo " clean_all - clean up project, core libraries and image generator"
@echo " bootloader - compile, generate and install VHDL BOOTROM boot image (for bootloader only!)"
@echo " upload - upload <neorv32_exe.bin> executable via serial port <COM_PORT> to bootloader"
 
 
# -----------------------------------------------------------------------------
# Clean up
# -----------------------------------------------------------------------------
clean:
@rm -f *.elf *.o *.bin *.out *.asm *.vhd
 
clean_all: clean
@rm -f $(OBJ) $(IMAGE_GEN)
/sw/example/floating_point_test/neorv32_zfinx_extension_intrinsics.h
0,0 → 1,1396
// #################################################################################################
// # << NEORV32 - Intrinsics + Emulation Functions for the RISC-V "Zfinx" CPU extension >> #
// # ********************************************************************************************* #
// # The intrinsics provided by this library allow to use the hardware floating-point unit of the #
// # RISC-V Zfinx CPU extension without the need for Zfinx support by the compiler / toolchain. #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
// # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
// # #
// # Redistribution and use in source and binary forms, with or without modification, are #
// # permitted provided that the following conditions are met: #
// # #
// # 1. Redistributions of source code must retain the above copyright notice, this list of #
// # conditions and the following disclaimer. #
// # #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
// # conditions and the following disclaimer in the documentation and/or other materials #
// # provided with the distribution. #
// # #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
// # endorse or promote products derived from this software without specific prior written #
// # permission. #
// # #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
// # OF THE POSSIBILITY OF SUCH DAMAGE. #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
* @file floating_point_test/neorv32_zfinx_extension_intrinsics.h
* @author Stephan Nolting
*
* @brief "Intrinsic" library for the NEORV32 single-precision floating-point in x registers (Zfinx) extension
* @brief Also provides emulation functions for all intrinsics (functionality re-built in pure software). The functionality of the emulation
* @brief functions is based on the RISC-V floating-point spec.
*
* @note All operations from this library use the default GCC "round to nearest, ties to even" rounding mode.
*
* @warning This library is just a temporary fall-back until the Zfinx extensions are supported by the upstream RISC-V GCC port.
**************************************************************************/
#ifndef neorv32_zfinx_extension_intrinsics_h
#define neorv32_zfinx_extension_intrinsics_h
 
#define __USE_GNU
 
#include <fenv.h>
//#pragma STDC FENV_ACCESS ON
 
#define _GNU_SOURCE
 
#include <float.h>
#include <math.h>
 
 
/**********************************************************************//**
* Sanity check
**************************************************************************/
#if defined __riscv_f || (__riscv_flen == 32)
#error Application programs using the Zfinx intrinsic library have to be compiled WITHOUT the <F> MARCH ISA attribute!
#endif
 
 
/**********************************************************************//**
* Custom data type to access floating-point values as native floats and in binary representation
**************************************************************************/
typedef union
{
uint32_t binary_value; /**< Access as native float */
float float_value; /**< Access in binary representation */
} float_conv_t;
 
 
// ################################################################################################
// Helper functions
// ################################################################################################
 
/**********************************************************************//**
* Flush to zero if denormal number.
*
* @warning Subnormal numbers are not supported yet! Flush them to zero.
*
* @param[in] tmp Source operand 1.
* @return Result.
**************************************************************************/
float subnormal_flush(float tmp) {
 
float res = tmp;
 
if (fpclassify(tmp) == FP_SUBNORMAL) {
if (signbit(tmp) != 0) {
res = -0.0f;
}
else {
res = +0.0f;
}
}
 
return res;
}
 
 
// ################################################################################################
// Exception access
// ################################################################################################
 
/**********************************************************************//**
* Get exception flags from fflags CSR (floating-point hardware).
*
* @return Floating point exception status word.
**************************************************************************/
uint32_t get_hw_exceptions(void) {
 
uint32_t res = neorv32_cpu_csr_read(CSR_FFLAGS);
 
neorv32_cpu_csr_write(CSR_FFLAGS, 0); // clear status word
 
return res;
}
 
 
/**********************************************************************//**
* Get exception flags from C runtime (floating-point emulation).
*
* @warning WORK-IN-PROGRESS!
*
* @return Floating point exception status word.
**************************************************************************/
uint32_t get_sw_exceptions(void) {
 
const uint32_t FP_EXC_NV_C = 1 << 0; // invalid operation
const uint32_t FP_EXC_DZ_C = 1 << 1; // divide by zero
const uint32_t FP_EXC_OF_C = 1 << 2; // overflow
const uint32_t FP_EXC_UF_C = 1 << 3; // underflow
const uint32_t FP_EXC_NX_C = 1 << 4; // inexact
 
int fpeRaised = fetestexcept(FE_ALL_EXCEPT);
 
uint32_t res = 0;
 
if (fpeRaised & FE_INVALID) { res |= FP_EXC_NV_C; }
if (fpeRaised & FE_DIVBYZERO) { res |= FP_EXC_DZ_C; }
if (fpeRaised & FE_OVERFLOW) { res |= FP_EXC_OF_C; }
if (fpeRaised & FE_UNDERFLOW) { res |= FP_EXC_UF_C; }
if (fpeRaised & FE_INEXACT) { res |= FP_EXC_NX_C; }
 
feclearexcept(FE_ALL_EXCEPT);
 
return res;
}
 
 
// ################################################################################################
// "Intrinsics"
// ################################################################################################
 
/**********************************************************************//**
* Single-precision floating-point addition
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fadds(float rs1, float rs2) {
 
float_conv_t opa, opb, res;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fadd.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000000, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point subtraction
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fsubs(float rs1, float rs2) {
 
float_conv_t opa, opb, res;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsub.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0000100, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point multiplication
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fmuls(float rs1, float rs2) {
 
float_conv_t opa, opb, res;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fmul.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0001000, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point minimum
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fmins(float rs1, float rs2) {
 
float_conv_t opa, opb, res;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fmin.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010100, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point maximum
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fmaxs(float rs1, float rs2) {
 
float_conv_t opa, opb, res;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fmax.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010100, a1, a0, 0b001, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point convert float to unsigned integer
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Result.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_fcvt_wus(float rs1) {
 
float_conv_t opa;
opa.float_value = rs1;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// fcvt.wu.s a0, a0
CUSTOM_INSTR_R2_TYPE(0b1100000, x1, a0, 0b000, a0, 0b1010011);
 
return result;
}
 
 
/**********************************************************************//**
* Single-precision floating-point convert float to signed integer
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Result.
**************************************************************************/
int32_t __attribute__ ((noinline)) riscv_intrinsic_fcvt_ws(float rs1) {
 
float_conv_t opa;
opa.float_value = rs1;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// fcvt.w.s a0, a0
CUSTOM_INSTR_R2_TYPE(0b1100000, x0, a0, 0b000, a0, 0b1010011);
 
return (int32_t)result;
}
 
 
/**********************************************************************//**
* Single-precision floating-point convert unsigned integer to float
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fcvt_swu(uint32_t rs1) {
 
float_conv_t res;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// fcvt.s.wu a0, a0
CUSTOM_INSTR_R2_TYPE(0b1101000, x1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point convert signed integer to float
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fcvt_sw(int32_t rs1) {
 
float_conv_t res;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = (uint32_t)rs1;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// fcvt.s.w a0, a0
CUSTOM_INSTR_R2_TYPE(0b1101000, x0, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point equal comparison
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_feqs(float rs1, float rs2) {
 
float_conv_t opa, opb;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// feq.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b010, a0, 0b1010011);
 
return result;
}
 
 
/**********************************************************************//**
* Single-precision floating-point less-than comparison
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_flts(float rs1, float rs2) {
 
float_conv_t opa, opb;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// flt.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b001, a0, 0b1010011);
 
return result;
}
 
 
/**********************************************************************//**
* Single-precision floating-point less-than-or-equal comparison
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_fles(float rs1, float rs2) {
 
float_conv_t opa, opb;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fle.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b1010000, a1, a0, 0b000, a0, 0b1010011);
 
return result;
}
 
 
/**********************************************************************//**
* Single-precision floating-point sign-injection
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fsgnjs(float rs1, float rs2) {
 
float_conv_t opa, opb, res;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsgnj.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point sign-injection NOT
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fsgnjns(float rs1, float rs2) {
 
float_conv_t opa, opb, res;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsgnjn.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b001, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point sign-injection XOR
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fsgnjxs(float rs1, float rs2) {
 
float_conv_t opa, opb, res;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fsgnjx.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0010000, a1, a0, 0b010, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point number classification
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Result.
**************************************************************************/
uint32_t __attribute__ ((noinline)) riscv_intrinsic_fclasss(float rs1) {
 
float_conv_t opa;
opa.float_value = rs1;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// fclass.s a0, a0
CUSTOM_INSTR_R2_TYPE(0b1110000, x0, a0, 0b001, a0, 0b1010011);
 
return result;
}
 
 
// ################################################################################################
// !!! UNSUPPORTED instructions !!!
// ################################################################################################
 
/**********************************************************************//**
* Single-precision floating-point division
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0).
* @param[in] rs2 Source operand 2 (a1).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fdivs(float rs1, float rs2) {
 
float_conv_t opa, opb, res;
opa.float_value = rs1;
opb.float_value = rs2;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
 
// fdiv.s a0, a0, x1
CUSTOM_INSTR_R2_TYPE(0b0001100, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point square root
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0).
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fsqrts(float rs1) {
 
float_conv_t opa, res;
opa.float_value = rs1;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], x0" : : [input_i] "r" (tmp_a));
 
// fsqrt.s a0, a0, a1
CUSTOM_INSTR_R2_TYPE(0b0101100, a1, a0, 0b000, a0, 0b1010011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point fused multiply-add
*
* @note "noinline" attributed to make sure arguments/return values are in a0, a1 and a2.
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0)
* @param[in] rs2 Source operand 2 (a1)
* @param[in] rs3 Source operand 3 (a2)
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fmadds(float rs1, float rs2, float rs3) {
 
float_conv_t opa, opb, opc, res;
opa.float_value = rs1;
opb.float_value = rs2;
opc.float_value = rs3;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
register uint32_t tmp_c __asm__ ("a2") = opc.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c));
 
// fmadd.s a0, a0, a1, a2
CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1000011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point fused multiply-sub
*
* @note "noinline" attributed to make sure arguments/return values are in a0, a1 and a2.
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0)
* @param[in] rs2 Source operand 2 (a1)
* @param[in] rs3 Source operand 3 (a2)
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fmsubs(float rs1, float rs2, float rs3) {
 
float_conv_t opa, opb, opc, res;
opa.float_value = rs1;
opb.float_value = rs2;
opc.float_value = rs3;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
register uint32_t tmp_c __asm__ ("a2") = opc.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c));
 
// fmsub.s a0, a0, a1, a2
CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1000111);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point fused negated multiply-sub
*
* @note "noinline" attributed to make sure arguments/return values are in a0, a1 and a2.
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0)
* @param[in] rs2 Source operand 2 (a1)
* @param[in] rs3 Source operand 3 (a2)
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fnmsubs(float rs1, float rs2, float rs3) {
 
float_conv_t opa, opb, opc, res;
opa.float_value = rs1;
opb.float_value = rs2;
opc.float_value = rs3;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
register uint32_t tmp_c __asm__ ("a2") = opc.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c));
 
// fnmsub.s a0, a0, a1, a2
CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1001011);
 
res.binary_value = result;
return res.float_value;
}
 
 
/**********************************************************************//**
* Single-precision floating-point fused negated multiply-add
*
* @note "noinline" attributed to make sure arguments/return values are in a0, a1 and a2.
*
* @warning This instruction is not supported and should raise an illegal instruction exception when executed.
*
* @param[in] rs1 Source operand 1 (a0)
* @param[in] rs2 Source operand 2 (a1)
* @param[in] rs3 Source operand 3 (a2)
* @return Result.
**************************************************************************/
float __attribute__ ((noinline)) riscv_intrinsic_fnmadds(float rs1, float rs2, float rs3) {
 
float_conv_t opa, opb, opc, res;
opa.float_value = rs1;
opb.float_value = rs2;
opc.float_value = rs3;
 
register uint32_t result __asm__ ("a0");
register uint32_t tmp_a __asm__ ("a0") = opa.binary_value;
register uint32_t tmp_b __asm__ ("a1") = opb.binary_value;
register uint32_t tmp_c __asm__ ("a2") = opc.binary_value;
 
// dummy instruction to prevent GCC "constprop" optimization
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_a), [input_j] "r" (tmp_b));
asm volatile ("add x0, %[input_i], %[input_j]" : : [input_i] "r" (tmp_b), [input_j] "r" (tmp_c));
 
// fnmadd.s a0, a0, a1, a2
CUSTOM_INSTR_R3_TYPE(a2, a1, a0, 0b000, a0, 0b1001111);
 
res.binary_value = result;
return res.float_value;
}
 
 
// ################################################################################################
// Emulation functions
// ################################################################################################
 
/**********************************************************************//**
* Single-precision floating-point addition
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
float riscv_emulate_fadds(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
float res = opa + opb;
return subnormal_flush(res);
}
 
 
/**********************************************************************//**
* Single-precision floating-point subtraction
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
float riscv_emulate_fsubs(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
float res = opa - opb;
return subnormal_flush(res);
}
 
 
/**********************************************************************//**
* Single-precision floating-point multiplication
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
float riscv_emulate_fmuls(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
float res = opa * opb;
return subnormal_flush(res);
}
 
 
/**********************************************************************//**
* Single-precision floating-point minimum
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
float riscv_emulate_fmins(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
union {
uint32_t binary_value; /**< Access as native float */
float float_value; /**< Access in binary representation */
} tmp_a, tmp_b;
 
if ((fpclassify(opa) == FP_NAN) && (fpclassify(opb) == FP_NAN)) {
return nanf("");
}
 
if (fpclassify(opa) == FP_NAN) {
return opb;
}
 
if (fpclassify(opb) == FP_NAN) {
return opa;
}
 
// RISC-V spec: -0 < +0
tmp_a.float_value = opa;
tmp_b.float_value = opb;
if (((tmp_a.binary_value == 0x80000000) && (tmp_b.binary_value == 0x00000000)) ||
((tmp_a.binary_value == 0x00000000) && (tmp_b.binary_value == 0x80000000))) {
return -0.0f;
}
 
return fmin(opa, opb);
}
 
 
/**********************************************************************//**
* Single-precision floating-point maximum
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
float riscv_emulate_fmaxs(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
union {
uint32_t binary_value; /**< Access as native float */
float float_value; /**< Access in binary representation */
} tmp_a, tmp_b;
 
 
if ((fpclassify(opa) == FP_NAN) && (fpclassify(opb) == FP_NAN)) {
return nanf("");
}
 
if (fpclassify(opa) == FP_NAN) {
return opb;
}
 
if (fpclassify(opb) == FP_NAN) {
return opa;
}
 
// RISC-V spec: -0 < +0
tmp_a.float_value = opa;
tmp_b.float_value = opb;
if (((tmp_a.binary_value == 0x80000000) && (tmp_b.binary_value == 0x00000000)) ||
((tmp_a.binary_value == 0x00000000) && (tmp_b.binary_value == 0x80000000))) {
return +0.0f;
}
 
return fmax(opa, opb);
}
 
 
/**********************************************************************//**
* Single-precision floating-point float to unsigned integer
*
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
uint32_t riscv_emulate_fcvt_wus(float rs1) {
 
float opa = subnormal_flush(rs1);
 
return (uint32_t)roundf(opa);
}
 
 
/**********************************************************************//**
* Single-precision floating-point float to signed integer
*
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
int32_t riscv_emulate_fcvt_ws(float rs1) {
 
float opa = subnormal_flush(rs1);
 
return (int32_t)roundf(opa);
}
 
 
/**********************************************************************//**
* Single-precision floating-point unsigned integer to float
*
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
float riscv_emulate_fcvt_swu(uint32_t rs1) {
 
return (float)rs1;
}
 
 
/**********************************************************************//**
* Single-precision floating-point signed integer to float
*
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
float riscv_emulate_fcvt_sw(int32_t rs1) {
 
return (float)rs1;
}
 
 
/**********************************************************************//**
* Single-precision floating-point equal comparison
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
uint32_t riscv_emulate_feqs(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
if ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) {
return 0;
}
 
if isless(opa, opb) {
return 0;
}
else if isgreater(opa, opb) {
return 0;
}
else {
return 1;
}
}
 
 
/**********************************************************************//**
* Single-precision floating-point less-than comparison
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
uint32_t riscv_emulate_flts(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
if ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) {
return 0;
}
 
if isless(opa, opb) {
return 1;
}
else {
return 0;
}
}
 
 
/**********************************************************************//**
* Single-precision floating-point less-than-or-equal comparison
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
uint32_t riscv_emulate_fles(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
if ((fpclassify(opa) == FP_NAN) || (fpclassify(opb) == FP_NAN)) {
return 0;
}
 
if islessequal(opa, opb) {
return 1;
}
else {
return 0;
}
}
 
 
/**********************************************************************//**
* Single-precision floating-point sign-injection
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
float riscv_emulate_fsgnjs(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
int sign_1 = (int)signbit(opa);
int sign_2 = (int)signbit(opb);
float res = 0;
 
if (sign_2 != 0) { // opb is negative
if (sign_1 == 0) {
res = -opa;
}
else {
res = opa;
}
}
else { // opb is positive
if (sign_1 == 0) {
res = opa;
}
else {
res = -opa;
}
}
 
return res;
}
 
 
/**********************************************************************//**
* Single-precision floating-point sign-injection NOT
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
float riscv_emulate_fsgnjns(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
int sign_1 = (int)signbit(opa);
int sign_2 = (int)signbit(opb);
float res = 0;
 
if (sign_2 != 0) { // opb is negative
if (sign_1 == 0) {
res = opa;
}
else {
res = -opa;
}
}
else { // opb is positive
if (sign_1 == 0) {
res = -opa;
}
else {
res = opa;
}
}
 
return res;
}
 
 
/**********************************************************************//**
* Single-precision floating-point sign-injection XOR
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
float riscv_emulate_fsgnjxs(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
int sign_1 = (int)signbit(opa);
int sign_2 = (int)signbit(opb);
float res = 0;
 
if (((sign_1 == 0) && (sign_2 != 0)) || ((sign_1 != 0) && (sign_2 == 0))) {
if (sign_1 == 0) {
res = -opa;
}
else {
res = opa;
}
}
else {
if (sign_1 == 0) {
res = opa;
}
else {
res = -opa;
}
}
 
return res;
}
 
 
/**********************************************************************//**
* Single-precision floating-point number classification
*
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
uint32_t riscv_emulate_fclasss(float rs1) {
 
float opa = subnormal_flush(rs1);
 
union {
uint32_t binary_value; /**< Access as native float */
float float_value; /**< Access in binary representation */
} aux;
 
// RISC-V classify result layout
const uint32_t CLASS_NEG_INF = 1 << 0; // negative infinity
const uint32_t CLASS_NEG_NORM = 1 << 1; // negative normal number
const uint32_t CLASS_NEG_DENORM = 1 << 2; // negative subnormal number
const uint32_t CLASS_NEG_ZERO = 1 << 3; // negative zero
const uint32_t CLASS_POS_ZERO = 1 << 4; // positive zero
const uint32_t CLASS_POS_DENORM = 1 << 5; // positive subnormal number
const uint32_t CLASS_POS_NORM = 1 << 6; // positive normal number
const uint32_t CLASS_POS_INF = 1 << 7; // positive infinity
const uint32_t CLASS_SNAN = 1 << 8; // signaling NaN (sNaN)
const uint32_t CLASS_QNAN = 1 << 9; // quiet NaN (qNaN)
 
int tmp = fpclassify(opa);
int sgn = (int)signbit(opa);
 
uint32_t res = 0;
 
// infinity
if (tmp == FP_INFINITE) {
if (sgn) { res |= CLASS_NEG_INF; }
else { res |= CLASS_POS_INF; }
}
 
// zero
if (tmp == FP_ZERO) {
if (sgn) { res |= CLASS_NEG_ZERO; }
else { res |= CLASS_POS_ZERO; }
}
 
// normal
if (tmp == FP_NORMAL) {
if (sgn) { res |= CLASS_NEG_NORM; }
else { res |= CLASS_POS_NORM; }
}
 
// subnormal
if (tmp == FP_SUBNORMAL) {
if (sgn) { res |= CLASS_NEG_DENORM; }
else { res |= CLASS_POS_DENORM; }
}
 
// NaN
if (tmp == FP_NAN) {
aux.float_value = opa;
if ((aux.binary_value >> 22) & 0b1) { // bit 22 (mantissa's MSB) is set -> canonical (quiet) NAN
res |= CLASS_QNAN;
}
else {
res |= CLASS_SNAN;
}
}
 
return res;
}
 
 
/**********************************************************************//**
* Single-precision floating-point division
*
* @param[in] rs1 Source operand 1.
* @param[in] rs2 Source operand 2.
* @return Result.
**************************************************************************/
float riscv_emulate_fdivs(float rs1, float rs2) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
 
float res = opa / opb;
return subnormal_flush(res);
}
 
 
/**********************************************************************//**
* Single-precision floating-point square root
*
* @param[in] rs1 Source operand 1.
* @return Result.
**************************************************************************/
float riscv_emulate_fsqrts(float rs1) {
 
float opa = subnormal_flush(rs1);
 
float res = sqrtf(opa);
return subnormal_flush(res);
}
 
 
/**********************************************************************//**
* Single-precision floating-point fused multiply-add
*
* @note "noinline" attributed to make sure arguments/return values are in a0 and a1.
*
* @warning This instruction is not supported!
*
* @param[in] rs1 Source operand 1
* @param[in] rs2 Source operand 2
* @param[in] rs3 Source operand 3
* @return Result.
**************************************************************************/
float riscv_emulate_fmadds(float rs1, float rs2, float rs3) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
float opc = subnormal_flush(rs3);
 
float res = (opa * opb) + opc;
return subnormal_flush(res);
}
 
 
/**********************************************************************//**
* Single-precision floating-point fused multiply-sub
*
* @param[in] rs1 Source operand 1
* @param[in] rs2 Source operand 2
* @param[in] rs3 Source operand 3
* @return Result.
**************************************************************************/
float riscv_emulate_fmsubs(float rs1, float rs2, float rs3) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
float opc = subnormal_flush(rs3);
 
float res = (opa * opb) - opc;
return subnormal_flush(res);
}
 
 
/**********************************************************************//**
* Single-precision floating-point fused negated multiply-sub
*
* @param[in] rs1 Source operand 1
* @param[in] rs2 Source operand 2
* @param[in] rs3 Source operand 3
* @return Result.
**************************************************************************/
float riscv_emulate_fnmsubs(float rs1, float rs2, float rs3) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
float opc = subnormal_flush(rs3);
 
float res = -(opa * opb) + opc;
return subnormal_flush(res);
}
 
 
/**********************************************************************//**
* Single-precision floating-point fused negated multiply-add
*
* @param[in] rs1 Source operand 1
* @param[in] rs2 Source operand 2
* @param[in] rs3 Source operand 3
* @return Result.
**************************************************************************/
float riscv_emulate_fnmadds(float rs1, float rs2, float rs3) {
 
float opa = subnormal_flush(rs1);
float opb = subnormal_flush(rs2);
float opc = subnormal_flush(rs3);
 
float res = -(opa * opb) - opc;
return subnormal_flush(res);
}
 
 
#endif // neorv32_zfinx_extension_intrinsics_h
/sw/example/game_of_life/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/hello_world/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/example/hex_viewer/makefile
1,11 → 1,11
#################################################################################################
# << NEORV32 - Application Makefile >> #
# ********************************************************************************************* #
# Make sure to add the riscv GCC compiler's bin folder to your PATH environment variable. #
# Make sure to add the RISC-V GCC compiler's bin folder to your PATH environment variable. #
# ********************************************************************************************* #
# BSD 3-Clause License #
# #
# Copyright (c) 2020, Stephan Nolting. All rights reserved. #
# Copyright (c) 2021, Stephan Nolting. All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without modification, are #
# permitted provided that the following conditions are met: #
126,7 → 126,7
IMAGE_GEN = $(NEORV32_EXG_PATH)/image_gen
 
# Compiler & linker flags
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles
CC_OPTS = $(MARCH) $(MABI) $(EFFORT) -Wall -ffunction-sections -fdata-sections -nostartfiles -mno-fdiv
CC_OPTS += -Wl,--gc-sections -lm -lc -lgcc -lc
# This accelerates instruction fetch after branches when C extension is enabled (irrelevant when C extension is disabled)
CC_OPTS += -falign-functions=4 -falign-labels=4 -falign-loops=4 -falign-jumps=4
/sw/lib/include/neorv32_cpu.h
57,6 → 57,7
uint32_t neorv32_cpu_pmp_get_granularity(void);
int neorv32_cpu_pmp_configure_region(uint32_t index, uint32_t base, uint32_t size, uint8_t config);
uint32_t neorv32_cpu_hpm_get_counters(void);
int neorv32_check_zextension(uint32_t);
 
 
/**********************************************************************//**
/sw/lib/include/neorv32_intrinsics.h
1,5 → 1,5
// #################################################################################################
// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >> #
// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >> #
// # ********************************************************************************************* #
// # BSD 3-Clause License #
// # #
120,32 → 120,45
#define REG_ADDR_t5 30 /**< register 30 - according to calling convention */
#define REG_ADDR_t6 31 /**< register 31 - according to calling convention */
 
//** Construct instruction word (32-bit) for R-type instruction */
#define CMD_WORD_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
//** Construct instruction word (32-bit) for R2-type instruction */
#define CMD_WORD_R2_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
( (opcode & 0x7f) << 0 ) + \
( (rd & 0x1f) << 7 ) + \
( (funct3 & 0x1f) << 12 ) + \
( (rs1 & 0x1f) << 15 ) + \
( (rs2 & 0x1f) << 20 ) + \
( (funct7 & 0x7f) << 25 ) + \
( (funct3 & 0x1f) << 12 )
( (funct7 & 0x7f) << 25 )
 
//** Construct instruction word (32-bit) for R3-type instruction */
#define CMD_WORD_R3_TYPE(rs3, rs2, rs1, funct3, rd, opcode) \
( (opcode & 0x7f) << 0 ) + \
( (rd & 0x1f) << 7 ) + \
( (funct3 & 0x1f) << 12 ) + \
( (rs1 & 0x1f) << 15 ) + \
( (rs2 & 0x1f) << 20 ) + \
( (rs3 & 0x1f) << 27 )
 
//** Construct instruction word (32-bit) for I-type instruction */
#define CMD_WORD_I_TYPE(imm12, rs1_f5, funct3, rd, opcode) \
( (opcode & 0x7f) << 0 ) + \
( (rd & 0x1f) << 7 ) + \
( (funct3 & 0x1f) << 12 ) + \
( (rs1_f5 & 0x1f) << 15 ) + \
( (imm12 & 0xfff) << 20 ) + \
( (funct3 & 0x1f) << 12 )
( (imm12 & 0xfff) << 20 )
 
//** Construct custom instruction for R-type instruction */
#define CUSTOM_INSTR_R_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
//** Construct custom R3-type instruction (4 registers, funct3, opcode) */
#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, rd, opcode) \
asm volatile (".word "STR(CMD_WORD_R3_TYPE(GET_REG_ADDR(rs3), GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
 
//** Construct custom instruction for R1-type instruction (register + 5-bit immediate/function_select) */
//** Construct custom R2-type instruction (3 registers, funct3, funct7, opcode) */
#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, rd, opcode) \
asm volatile (".word "STR(CMD_WORD_R2_TYPE(funct7, GET_REG_ADDR(rs2), GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
 
//** Construct custom R1-type instruction (2 registers, funct3, funct7, funct5, opcode) */
#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, rd, opcode) \
asm volatile (".word "STR(CMD_WORD_R_TYPE(funct7, funct5, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
asm volatile (".word "STR(CMD_WORD_R2_TYPE(funct7, funct5, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
//** Construct custom instruction for I-type instruction */
//** Construct custom I-type instruction (2 registers, funct3, imm12, opcode) */
#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, rd, opcode) \
asm volatile (".word "STR(CMD_WORD_I_TYPE(imm12, GET_REG_ADDR(rs1), funct3, GET_REG_ADDR(rd), opcode))"\n");
/**@}*/
/sw/lib/source/neorv32_cpu.c
683,3 → 683,26
 
return num_hpm_cnts;
}
 
 
/**********************************************************************//**
* Check if certain Z* extension is available
*
* @param[in] flag Index of the Z-extension to check from #NEORV32_CSR_MZEXT_enum
* @return 0 if extension is NOT available, != 0 if extension is available.
**************************************************************************/
int neorv32_check_zextension(uint32_t flag) {
 
// check if out of range
if (flag > 31) {
return 0;
}
 
uint32_t tmp = neorv32_cpu_csr_read(CSR_MZEXT);
if ((tmp & (1 << flag)) == 0) {
return 0;
}
else {
return 1;
}
}
/sw/lib/source/neorv32_uart.c
505,8 → 505,10
__neorv32_uart_tohex(va_arg(a, uint32_t), string_buf);
neorv32_uart0_print(string_buf);
break;
default:
return;
default: // unsupported format
neorv32_uart0_putc('%');
neorv32_uart0_putc(c);
break;
}
}
else {
858,8 → 860,10
__neorv32_uart_tohex(va_arg(a, uint32_t), string_buf);
neorv32_uart1_print(string_buf);
break;
default:
return;
default: // unsupported format
neorv32_uart1_putc('%');
neorv32_uart1_putc(c);
break;
}
}
else {
964,7 → 968,7
* Private function for 'neorv32_printf' to convert into hexadecimal.
*
* @param[in] x Unsigned input number.
* @param[in,out] res Pointer for storing the reuslting number string (9 chars).
* @param[in,out] res Pointer for storing the resulting number string (9 chars).
**************************************************************************/
static void __neorv32_uart_tohex(uint32_t x, char *res) {
 
971,7 → 975,7
static const char symbols[] = "0123456789abcdef";
 
int i;
for (i=0; i<8; i++) { // nibble by bibble
for (i=0; i<8; i++) { // nibble by nibble
uint32_t num_tmp = x >> (4*i);
res[7-i] = (char)symbols[num_tmp & 0x0f];
}
/CHANGELOG.md
17,7 → 17,7
 
* :bug: = bug-fix
* :sparkles: = new feature
* :warning: = major change
* :warning: = major change / important note
* :lock: = security issue
* :rocket: = release
 
24,9 → 24,13
 
| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 26.03.2021 | 1.5.3.2 | :sparkles: **added single-precision floating-point unit (FPU)** `rtl/core/neorv32_cpu_cp_fpu.vhd` implementing the `Zfinx` CPU extension; added/updated `Zfinx` **intrinsic library** and verification framework: [`sw/example/floating_point_test`](https://github.com/stnolting/neorv32/tree/master/sw/example/floating_point_test); added co-processor timeout counter to CPU to auto-terminate co-processor operations (for debugging only; defaullt=deactivated) |
| 25.03.2021 | 1.5.3.1 | :bug: fixed bug in invalid floating-point instruction detection (caused CPU to stall if executing an invalid floating-point operation); intrinsic core library (mainly used for not-yet-supported CPU extensions like `B` and `Zfinx`): clean-up, added R3 instruction type |
| 24.03.2021 | [**:rocket:1.5.3.0**](https://github.com/stnolting/neorv32/releases/tag/v1.5.3.0) | **New release** |
| 23.03.2021 | 1.5.2.9 | :sparkles: added new top generic to enable single-precision floating-point extensions `Zfinx`: `CPU_EXTENSION_RISCV_Zfinx` - type `boolean`, default = `false`, :warning: **extension is not yet operational!**; bootloader now shows available `Z*` extensions (from `mzext` CSR) like `Zifencei` |
| 21.03.2021 | 1.5.2.8 | :bug: fixed problem with linking `math.h` library in makefile; added floating-point-related global definitions to main VHDL package; added intrinsic core library file `sw/lib/include/neorv32_intrinsics.h` - intrinsic library support for CPU extensions, which are not yet supported by the upstream GCC, are based on this |
| 18.03.2021 | 1.5.2.7 | :bug: fixed bug in `sw/common/crt0.S` dummy exception handler (wrong order of register push/pop); changed upcoming floating-point extension (orignally `F` extension) to `Zfinx` extension (-> [RISC-V `Zfinx` spec](https://github.com/riscv/riscv-zfinx)) - updated CPU infrastructure |
| 16.03.2021 | 1.5.2.6 | reworked atomic/exclusive memory access interface: removed CPU's `i_bus_lock_o` and `i_bus_lock_o` signal (was always zero anyway); removed top's `wb_lock_o` signal; added *exclusive access request* to Wishbone tag signal `wb_tag_o` (is not one bit wider); added more details to NEORV32.pdf regarding excluisve/atomic memory accesses (interface/protocol) |
| 16.03.2021 | 1.5.2.6 | reworked atomic/exclusive memory access interface: removed CPU's `d_bus_lock_o` and `i_bus_lock_o` signal (was always zero anyway); removed top's `wb_lock_o` signal; added *exclusive access request* to Wishbone tag signal `wb_tag_o` (is now one bit wider); added more details to NEORV32.pdf regarding excluisve/atomic memory accesses (interface/protocol) |
| 09.03.2021 | 1.5.2.5 | added bit-manipulation `Zba` sub-extension (shifted-adds: `SH1ADD` `SH2ADD` `SH3ADD`) |
| 07.03.2021 | 1.5.2.4 | :sparkles: added new IO/peripheral module: **Smart LED Interface (NEOLED)** to interface intelligent LEDs (WS2812/WS2811/NeoPixel(c) compatible; supports RGB and RGBW LEDs in *parallel*) with internal TX buffer; new top generics: `IO_NEOLED_EN`: implement NEOLED interface when *true*; new top signals: `neoled_o`: single-wire async. serial data interface; FIFO re-fill interrupt via *fast interrupt request channel 9* `FIRQ9`; added new "NEOLED" section to data sheet; added SW driver library and simple NEOLED example program (`sw/example/demo_neopixel`) |
| 06.03.2021 | 1.5.2.3 | clean-up of CPU control code: fixed minor bug in F-exension's instruction decoding; changed coding style for CSR write access (old version might have caused "inferring latch..." warning in Intel Quartus); fixed default values for CSRs when according extensions are disabled |
/README.md
24,8 → 24,8
![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
 
The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
on the RISC-V NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
designs or as stand-alone custom microcontroller.
on the RISC-V NEORV32 CPU. The processor is intended as auxiliary processor within a larger SoC
designs or as *ready-to-go* stand-alone custom microcontroller.
 
:books: For detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
The doxygen-based documentation of the *software framework* is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
55,6 → 55,7
* [`M`](#M---Integer-multiplication-and-division-hardware-extension) - integer multiplication and division hardware (optional)
* [`U`](#U---Privileged-architecture---User-mode-extension) - less-privileged *user mode* (optional)
* [`X`](#X---NEORV32-specific-CPU-extensions) - NEORV32-specific extensions (always enabled)
* [`Zfinx`](#Zfinx---Single-precision-floating-point-extension) - Single-precision floating-point extensions (optional)
* [`Zicsr`](#Zicsr---Privileged-architecture---CSR-access-extension) - control and status register access instructions (+ exception/irq system) (optional)
* [`Zifencei`](#Zifencei---Privileged-architecture---Instruction-stream-synchronization-extension) - instruction stream synchronization (optional)
* [`PMP`](#PMP---Privileged-architecture---Physical-memory-protection) - physical memory protection (optional)
75,7 → 76,7
* bootloader with UART interface console
* runtime environment
* several example programs
* [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) software documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
* [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/Doxyfile) software documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
174,7 → 175,7
* :warning: this extension has not been officially ratified yet!
* :books: more information can be found here: [RISC-V `B` spec.](https://github.com/riscv/riscv-bitmanip)
* Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
* Support via intrinsic library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
* Software support via intrinsic library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
* `Zbb` base instruction set: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR[I]` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
* `Zbs` single-bit instructions: `SBSET[I]` `SBCLR[I]` `SBINV[I]` `SBEXT[I]`
* `Zba` shifted-add instructions: `SH1ADD` `SH2ADD` `SH3ADD`
224,14 → 225,18
* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
 
 
#### `Zfinx` - Single-precision floating-point extension (using integer `x` registers)
#### `Zfinx` - Single-precision floating-point extension
 
* :construction: **work-in-progress** :construction:
* :warning: this extension has not been officially ratified yet!
* :books: more information can be found here: [RISC-V `Zfinx` spec.](https://github.com/riscv/riscv-zfinx)
* :information_source: check out the [floating-point extension project board](https://github.com/stnolting/neorv32/projects/4) for the current implementation state
* Software support via intrinsic library (see [`sw/example/floating_point_test`](https://github.com/stnolting/neorv32/tree/master/sw/example/floating_point_test))
* Fused multiply-add instructions (`F[N]MADD.S` & `F[N)MSUB.S`) are **not** supported!
* Computational instructions: `FADD.S` `FSUB.S` `FMUL.S` `FSGNJ[N/X].S` `FCLASS.S` ~~`FDIV.S`~~ ~~`FSQRT.S`~~
* Comparison instructions: `FMIN.S` `FMAX.S` `FEQ.S` `FLT.S` `FLE.S`
* Conversion instructions: `FCVT.W.S` `FCVT.WU.S` `FCVT.S.W` `FCVT.S.WU`
* Additional CSRs: `fcsr` `frm` `fflags`
 
 
#### `Zicsr` - Privileged architecture - CSR access extension
 
* Privilege levels: `M-mode` (Machine mode)
251,11 → 256,11
* Store access fault (via unacknowledged bus access after timeout)
* Environment call from U-mode (via `ecall` instruction in user mode)
* Environment call from M-mode (via `ecall` instruction in machine mode)
* Supported (async.) exceptions / interrupts:
* Machine timer interrupt `mti` (via processor's MTIME unit / external signal)
* Machine software interrupt `msi` (via external signal)
* Machine external interrupt `mei` (via external signal)
* 16 fast interrupt requests (custom extension), 6+1 available for custom usage
* Supported interrupts:
* RISC-V machine timer interrupt `mti` (via processor-internal MTIME unit *or* external signal)
* RISC-V machine software interrupt `msi` (via external signal)
* RISC-V machine external interrupt `mei` (via external signal)
* 16 fast interrupt requests, 6+1 available for custom usage
 
 
#### `Zifencei` - Privileged architecture - Instruction stream synchronization extension
284,7 → 289,6
* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt")
* The bit manipulation extension is not yet officially ratified, but is expected to stay unchanged. There is no software support in the upstream GCC RISC-V port yet. However, an intrinsic library is provided to utilize the provided bit manipulation extension from C-language code (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)). NEORV32's `B` extension is compatible to spec. version "0.94-draft".
 
 
 
298,47 → 302,47
of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
No constraints were used at all.
 
Results generated for hardware version [`1.5.1.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|:-----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
| `rv32i` | 979 | 409 | 1024 | 0 | 123 MHz |
| `rv32i` + `Zicsr` | 1789 | 847 | 1024 | 0 | 122 MHz |
| `rv32im` + `Zicsr` | 2381 | 1125 | 1024 | 0 | 122 MHz |
| `rv32imc` + `Zicsr` | 2608 | 1140 | 1024 | 0 | 122 MHz |
| `rv32imac` + `Zicsr` | 2621 | 1144 | 1024 | 0 | 122 MHz |
| `rv32imacb` + `Zicsr` | 3013 | 1310 | 1024 | 0 | 122 MHz |
| `rv32imacb` + `Zicsr` + `u` | 3031 | 1313 | 1024 | 0 | 122 MHz |
| `rv32imacb` + `Zicsr` + `u` + `Zifencei` | 3050 | 1313 | 1024 | 0 | 116 MHz |
| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
|:--------------------------------------------------|:----:|:----:|:-----------:|:------------:|:-------:|
| `rv32i` | 980 | 409 | 1024 | 0 | 123 MHz |
| `rv32i` + `Zicsr` | 1835 | 856 | 1024 | 0 | 124 MHz |
| `rv32im` + `Zicsr` | 2443 | 1134 | 1024 | 0 | 124 MHz |
| `rv32imc` + `Zicsr` | 2669 | 1149 | 1024 | 0 | 125 MHz |
| `rv32imac` + `Zicsr` | 2685 | 1156 | 1024 | 0 | 124 MHz |
| `rv32imac` + `Zicsr` + `u` | 2698 | 1162 | 1024 | 0 | 124 MHz |
| `rv32imac` + `Zicsr` + `u` + `Zifencei` | 2715 | 1162 | 1024 | 0 | 122 MHz |
| `rv32imac` + `Zicsr` + `u` + `Zifencei` + `Zfinx` | 4004 | 1812 | 1024 | 0 | 121 MHz |
 
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max as the according `I` configuration.
However, the size of the register file is cut in half.
However, the size of the register file is cut in half.
 
 
### NEORV32 Processor-Internal Peripherals and Memories
 
Results generated for hardware version [`1.5.2.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
Results generated for hardware version [`1.5.3.2`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
| Module | Description | LEs | FFs | Memory bits | DSPs |
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
| BUSSWITCH | Bus mux for CPU instr. & data interfaces | 65 | 8 | 0 | 0 |
| i-CACHE | Proc.-int. nstruction cache (default 1x4x64 bytes) | 234 | 156 | 8 192 | 0 |
| CFS | Custom functions subsystem | - | - | - | - |
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
| MTIME | Machine system timer | 274 | 166 | 0 | 0 |
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0 |
| NEOLED | Smart LED Interface (NeoPixel-compatibile) [4x FIFO] | 347 | 309 | 0 | 0 |
| PWM | Pulse-width modulation controller | 71 | 69 | 0 | 0 |
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
| SYSINFO | System configuration information memory | 11 | 10 | 0 | 0 |
| TRNG | True random number generator | 132 | 105 | 0 | 0 |
| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
| Module | Description | LEs | FFs | Memory bits | DSPs (9-bit) |
|:----------|:-----------------------------------------------------|----:|----:|------------:|-------------:|
| BOOT ROM | Bootloader ROM (default 4kB) | 3 | 1 | 32 768 | 0 |
| BUSSWITCH | Bus mux for CPU instr. & data interfaces | 65 | 8 | 0 | 0 |
| i-CACHE | Proc.-int. nstruction cache (default 1x4x64 bytes) | 234 | 156 | 8 192 | 0 |
| CFS | Custom functions subsystem | - | - | - | - |
| DMEM | Processor-internal data memory (default 8kB) | 6 | 2 | 65 536 | 0 |
| GPIO | General purpose input/output ports | 67 | 65 | 0 | 0 |
| IMEM | Processor-internal instruction memory (default 16kb) | 6 | 2 | 131 072 | 0 |
| MTIME | Machine system timer | 274 | 166 | 0 | 0 |
| NCO | Numerically-controlled oscillator | 254 | 226 | 0 | 0 |
| NEOLED | Smart LED Interface (NeoPixel-compatibile) [4x FIFO] | 347 | 309 | 0 | 0 |
| PWM | Pulse-width modulation controller | 71 | 69 | 0 | 0 |
| SPI | Serial peripheral interface | 138 | 124 | 0 | 0 |
| SYSINFO | System configuration information memory | 11 | 10 | 0 | 0 |
| TRNG | True random number generator | 132 | 105 | 0 | 0 |
| TWI | Two-wire interface | 77 | 46 | 0 | 0 |
| UART0/1 | Universal asynchronous receiver/transmitter 0/1 | 176 | 132 | 0 | 0 |
| WDT | Watchdog timer | 60 | 45 | 0 | 0 |
| WISHBONE | External memory interface | 129 | 104 | 0 | 0 |
 
 
### NEORV32 Processor - Exemplary FPGA Setups
350,11 → 354,11
 
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
 
| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|:--------|:----------------------------------|:-----------------|:---------------------------|:-----------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|--------------:|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imc` + `u` + `Zicsr` + `Zifencei` | 3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4397 (83%) | 1679 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.15 MHz |
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP (9-bit) | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|:--------|:----------------------------------|:-----------------|:---------------------------|:-----------------------------------------------|:-----------|:-----------|:------------|:-------------|:-----------|:---------|--------------:|
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 20.1 | `rv32imc` + `u` + `Zicsr` + `Zifencei` | 3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4397 (83%) | 1679 (31%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.15 MHz |
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
 
**_Notes_**
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
549,7 → 553,7
 
The NEORV32 project includes several [example program project](https://github.com/stnolting/neorv32/tree/master/sw/example) from
which you can start your own application. There are example programs to check out the processor's peripheral like I2C or the true-random number generator.
And yes, there is also a port of [Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life) available! :wink:
And of course there is also a port of [Conway's Game of Life](https://github.com/stnolting/neorv32/tree/master/sw/example/game_of_life) available.
 
Simply compile one of these projects using
 
575,14 → 579,15
```
<< NEORV32 Bootloader >>
 
BLDV: Nov 7 2020
HWV: 0x01040606
CLK: 0x0134FD90 Hz
USER: 0x0001CE40
MISA: 0x42801104
PROC: 0x03FF0035
IMEM: 0x00010000 bytes @ 0x00000000
DMEM: 0x00010000 bytes @ 0x80000000
BLDV: Mar 23 2021
HWV: 0x01050208
CLK: 0x05F5E100
USER: 0x10000DE0
MISA: 0x40901105
ZEXT: 0x00000023
PROC: 0x0EFF0037
IMEM: 0x00004000 bytes @ 0x00000000
DMEM: 0x00002000 bytes @ 0x80000000
 
Autoboot in 8s. Press key to abort.
Aborted.

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