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/trunk/Next186_features.doc
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/trunk/Next186_CPU.v
1,60 → 1,62
////////////////////////////////////////////////////////////////////////////////// |
// |
// This file is part of the Next186 project |
// http://opencores.org/project,next186 |
// |
// Filename: Next186_CPU.v |
// Description: Implementation of 80186 instruction compatible CPU |
// Version 1.0 |
// Creation date: 24Mar2011 - 07Jun2011 |
// |
// Author: Nicolae Dumitrache |
// e-mail: ndumitrache@opencores.org |
// |
///////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2011 Nicolae Dumitrache |
// |
// This source file may be used and distributed without |
// restriction provided that this copyright statement is not |
// removed from the file and that any derivative work contains |
// the original copyright notice and the associated disclaimer. |
// |
// This source file is free software; you can redistribute it |
// and/or modify it under the terms of the GNU Lesser General |
// Public License as published by the Free Software Foundation; |
// either version 2.1 of the License, or (at your option) any |
// later version. |
// |
// This source is distributed in the hope that it will be |
// useful, but WITHOUT ANY WARRANTY; without even the implied |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
// PURPOSE. See the GNU Lesser General Public License for more |
// details. |
// |
// You should have received a copy of the GNU Lesser General |
// Public License along with this source; if not, download it |
// from http://www.opencores.org/lgpl.shtml |
// |
/////////////////////////////////////////////////////////////////////////////////// |
// |
// Comments: |
// This project was developed and tested on a XILINX Spartan3AN board. |
// |
// Next186 processor features: |
////////////////////////////////////////////////////////////////////////////////// |
// |
// This file is part of the Next186 project |
// http://opencores.org/project,next186 |
// |
// Filename: Next186_CPU.v |
// Description: Implementation of 80186 instruction compatible CPU |
// Version 1.0 |
// Creation date: 24Mar2011 - 07Jun2011 |
// |
// Author: Nicolae Dumitrache |
// e-mail: ndumitrache@opencores.org |
// |
///////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2011 Nicolae Dumitrache |
// |
// This source file may be used and distributed without |
// restriction provided that this copyright statement is not |
// removed from the file and that any derivative work contains |
// the original copyright notice and the associated disclaimer. |
// |
// This source file is free software; you can redistribute it |
// and/or modify it under the terms of the GNU Lesser General |
// Public License as published by the Free Software Foundation; |
// either version 2.1 of the License, or (at your option) any |
// later version. |
// |
// This source is distributed in the hope that it will be |
// useful, but WITHOUT ANY WARRANTY; without even the implied |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
// PURPOSE. See the GNU Lesser General Public License for more |
// details. |
// |
// You should have received a copy of the GNU Lesser General |
// Public License along with this source; if not, download it |
// from http://www.opencores.org/lgpl.shtml |
// |
/////////////////////////////////////////////////////////////////////////////////// |
// |
// Comments: |
// This project was developed and tested on a XILINX Spartan3AN board. |
// |
// Next186 processor features: |
// All 80186 intstructions are implemented according with the 80186 specifications (excepting ENTER instruction, |
// which uses always 0 as the second parameter - level). |
// which uses always 0 as the second parameter - level). |
// Designed with 2 buses: 16bit/20bit data/data_address and 48bit/20bit instruction/instruction_address. |
// This allows most instructions to be executed in one clock cycle. |
// In order to couple the CPU unit with a single bus, these sepparate data/instruction buses must be multiplexed by |
// a dedicated bus interface unit (BIU). |
// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU. |
// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN |
// It is able to execute up to 40Mips on Spartan XC3S700AN speed grade -4, performances comparable with a 486 CPU. |
// Small size, the CPU + BIU requires ~25% or 1500 slices - on Spartan XC3S700AN |
// |
// 16May2012 - fixed REP CMPS/SCAS bug when interrupted on the <equal> item |
// 23Dec2012 - fixed DIV bug (exception on sign bit) |
// 27Feb2013 - fixed MUL/IMUL 8bit flags bug |
/////////////////////////////////////////////////////////////////////////////////// |
// 27Feb2013 - fixed MUL/IMUL 8bit flags bug |
// 03Apr2013 - fix RET n alignment bug |
// 04Apr2013 - fix TRAP interrupt acknowledge |
/////////////////////////////////////////////////////////////////////////////////// |
`timescale 1ns / 1ps |
|
module Next186_CPU( |
180,7 → 182,7
wire SAMPLEINT = ~(WE[2] & RASEL[1:0] == 2'b10) & ~status[2] & ~status[4] & ~status[5]; // not load SS, no prefix |
wire NMIACK = SNMI & ~FNMI; // NMI acknowledged |
wire INTRACK = FLAGS[9] & (~WE[4] | FIN[9]) & SINTR; // INTR acknowledged (IF and not CLI in progress) |
wire IACK = IRQ | (SAMPLEINT & (NMIACK | INTRACK)) | (~WE[2] & ~HALT & FLAGS[8]); // interrupt acknowledged |
wire IACK = IRQ | (SAMPLEINT & (NMIACK | INTRACK | (~HALT & FLAGS[8]))); // interrupt acknowledged (fixed 04Apr2013) |
reg CMPS; // early EQ test for CMPS |
reg SCAS; // early EQ test for SCAS |
|
341,7 → 343,7
end |
|
always @(FETCH[0], FETCH[1], FETCH[2], FETCH[3], FETCH[4], FETCH[5], MOD, REG, RM, CPUStatus, USEBP, NOBP, RASEL, ISIZEI, TLF, EAC, COUT, DIVEND, DIVC, QSGN, CMPS, SCAS, |
WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, SOUT) begin |
WBIT, ISIZES, ISELS, WRBIT, ISIZEW, STAGE, NULLSHIFT, ALUCONT, FLAGS, CXZ, RCXZ, NRORCXLE1, TZF, JMPC, LOOPC, ICODE1, DIVQSGN, DIVSGN, DIVRSGN, SOUT, IDIV) begin |
WORD = FETCH[0][0]; |
BASEL = FETCH[0][1] | &MOD; |
RASEL = FETCH[0][1] ? REG : RM; // destination |
1287,6 → 1289,7
end |
// -------------------------------- ret near -------------------------------- |
41: begin |
WORD = 1'b1; // fix RET n alignment bug - 03Apr2013 |
ISIZE = FETCH[0][0] ? 1 : 3; |
IFETCH = STAGE[0]; |
ALUOP = 31; // PASS B |
1306,6 → 1309,7
end |
// -------------------------------- ret far -------------------------------- |
42: begin |
WORD = 1'b1; // fix RET n alignment bug - 03Apr2013 |
ALUOP = 31; // PASS B |
RSSEL = 2'b10; // SS |
IFETCH = STAGE[1]; |