URL
https://opencores.org/ocsvn/nextz80/nextz80/trunk
Subversion Repositories nextz80
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- This comparison shows the changes necessary to convert path
/nextz80
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/trunk/Next8080CPU.v
84,7 → 84,7
); |
|
// connections and registers |
reg [2:0] CPUStatus = 0; // 0=HL-DE, 1=EI, 2-indexed mode |
reg [2:0] CPUStatus = 0; // 0=HL-DE, 1=EI, 2-indexed mode |
wire [7:0] ALU8FLAGS; |
wire [7:0] FLAGS; |
wire [7:0] ALU80; |
117,7 → 117,7
reg SRESET = 0; |
reg SINT = 0; |
|
Z80Reg CPU_REGS ( |
N8080_Reg CPU_REGS ( |
.rstatus(CPUStatus[0]), |
.M1(M1), |
.WE(WE), |
142,7 → 142,7
.WAIT(WAIT) |
); |
|
ALU8 CPU_ALU8 ( |
N8080_ALU8 CPU_ALU8 ( |
.D0(ALU80), |
.D1(ALU81), |
.FIN(FLAGS), |
151,7 → 151,7
.OP(ALU8OP) |
); |
|
ALU16 CPU_ALU16 ( |
N8080_ALU16 CPU_ALU16 ( |
.D0(ALU160), |
.D1(ALU161), |
.DOUT(ADDR), |
983,7 → 983,7
// 11101 - IN, pass D1 |
// 11110 - FLAGS <- D0 |
/////////////////////////////////////////////////////////////////////////////////// |
module ALU8( |
module N8080_ALU8( |
input [7:0]D0, |
input [7:0]D1, |
input [7:0]FIN, |
1006,7 → 1006,7
wire [7:0]shift = OP[0] ? {csin, D0[7:1]} : {D0[6:0], csin}; |
wire [15:0]inc16 = OP[0] ? {D0, D1} - 1'b1 : {D0, D1} + 1'b1; |
|
LOG8 log8_unit |
N8080_LOG8 log8_unit |
( |
.A(D0), |
.B(D1), |
1082,7 → 1082,7
end |
endmodule |
|
module LOG8( |
module N8080_LOG8( |
input [7:0]A, |
input [7:0]B, |
input [3:0]op, // 0=0, 1=~(A|B), 2=~A&B, 3=~A, 4=A&~B, 5=~B, 6=A^B, 7=~(A&B), 8=A&B, 9=~(A^B), 10=B, 11=~A|B, 12=A, 13=A|~B, 14=A|B, 15=-1 |
1100,7 → 1100,7
assign O[7] = op[{A[7], B[7]}]; |
endmodule |
|
module ALU16( |
module N8080_ALU16( |
input [15:0]D0, |
input [7:0]D1, |
input [2:0]OP, // 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2 |
1124,7 → 1124,7
assign DOUT = D0 + {{8{mux[7]}}, mux}; |
endmodule |
|
module Z80Reg( |
module N8080_Reg( |
input rstatus, // hl-de |
input M1, |
input [5:0]WE, // 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo |
1166,7 → 1166,7
|
//------------------------------------ RAM block registers ---------------------------------- |
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:BC', 5:DE', 6:HL', 7:A'-x, 8:tmp |
RAM16X8D_regs regs_lo ( |
N8080_RAM16X8D_regs regs_lo ( |
.DPO(rdor[7:0]), // Read-only data output |
.SPO(rdow[7:0]), // R/W data output |
.A(SELW), // R/W address |
1176,7 → 1176,7
.WE(WE[0] & !WAIT) // Write enable input |
); |
|
RAM16X8D_regs regs_hi ( |
N8080_RAM16X8D_regs regs_hi ( |
.DPO(rdor[15:8]), // Read-only data output |
.SPO(rdow[15:8]), // R/W data output |
.A(SELW), // R/W address |
1221,13 → 1221,13
endcase |
end |
|
RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus(rstatus)); |
RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus)); |
N8080_RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus(rstatus)); |
N8080_RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus)); |
|
endmodule |
|
|
module RegSelect( |
module N8080_RegSelect( |
input [2:0]SEL, |
input rstatus, // 2=hl-de |
|
1245,7 → 1245,7
end |
endmodule |
|
module RAM16X8D_regs( |
module N8080_RAM16X8D_regs( |
input [2:0]A, // R/W address |
input [7:0]D, // Write data input |
input [2:0]DPRA, // Read-only address |