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URL https://opencores.org/ocsvn/oc_axi_bfm/oc_axi_bfm/trunk

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/trunk/example/avalon_dma.qsys
0,0 → 1,293
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element dma_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element dma_0.control_port_slave
{
datum baseAddress
{
value = "8192";
type = "String";
}
}
element oc_axi_lite_bfm_0
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element onchip_memory2_0
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element onchip_memory2_1
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element onchip_memory2_1.s1
{
datum baseAddress
{
value = "4096";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="5CSEMA5F31C6" />
<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceSpeedGrade" value="6" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface
name="oc_axi_lite_bfm_0_driver"
internal="oc_axi_lite_bfm_0.driver"
type="conduit"
dir="end" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<module name="clk_0" kind="clock_source" version="19.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module name="dma_0" kind="altera_avalon_dma" version="19.1" enabled="1">
<parameter name="allowByteTransactions" value="true" />
<parameter name="allowDoubleWordTransactions" value="true" />
<parameter name="allowHalfWordTransactions" value="true" />
<parameter name="allowQuadWordTransactions" value="true" />
<parameter name="allowWordTransactions" value="true" />
<parameter name="avalonSpec" value="2.0" />
<parameter name="bigEndian" value="false" />
<parameter name="burstEnable" value="false" />
<parameter name="fifoDepth" value="32" />
<parameter name="maxBurstSize" value="128" />
<parameter name="minimumDmaTransactionRegisterWidth" value="13" />
<parameter name="readAddressMap"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x0' end='0x1000' /><slave name='onchip_memory2_1.s1' start='0x1000' end='0x2000' /></address-map>]]></parameter>
<parameter name="readSlaveAddressWidthMax" value="13" />
<parameter name="readSlaveDataWidthMax" value="32" />
<parameter name="softresetEnable" value="true" />
<parameter name="useRegistersForFIFO" value="false" />
<parameter name="writeAddressMap"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x0' end='0x1000' /><slave name='onchip_memory2_1.s1' start='0x1000' end='0x2000' /></address-map>]]></parameter>
<parameter name="writeSlaveAddressWidthMax" value="13" />
<parameter name="writeSlaveDataWidthMax" value="32" />
</module>
<module
name="oc_axi_lite_bfm_0"
kind="oc_axi_lite_bfm"
version="1.0"
enabled="1">
<parameter name="AW_NW" value="1" />
<parameter name="B_WAIT" value="3" />
<parameter name="IDLE" value="0" />
<parameter name="NAW_W" value="2" />
<parameter name="N_AW_W" value="0" />
<parameter name="READ" value="1" />
<parameter name="R_AR" value="0" />
<parameter name="R_R" value="1" />
<parameter name="R_RSP" value="2" />
<parameter name="WRITE" value="2" />
</module>
<module
name="onchip_memory2_0"
kind="altera_avalon_onchip_memory2"
version="19.1"
enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
<parameter name="blockType" value="AUTO" />
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
<parameter name="dataWidth2" value="32" />
<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
<parameter name="dualPort" value="false" />
<parameter name="ecc_enabled" value="false" />
<parameter name="enPRInitMode" value="false" />
<parameter name="enableDiffWidth" value="false" />
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="4096" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
<module
name="onchip_memory2_1"
kind="altera_avalon_onchip_memory2"
version="19.1"
enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_1</parameter>
<parameter name="blockType" value="AUTO" />
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
<parameter name="dataWidth2" value="32" />
<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
<parameter name="dualPort" value="false" />
<parameter name="ecc_enabled" value="false" />
<parameter name="enPRInitMode" value="false" />
<parameter name="enableDiffWidth" value="false" />
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="4096" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
<connection
kind="avalon"
version="19.1"
start="oc_axi_lite_bfm_0.axm_m0"
end="dma_0.control_port_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x2000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="19.1"
start="oc_axi_lite_bfm_0.axm_m0"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="19.1"
start="dma_0.read_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="19.1"
start="dma_0.read_master"
end="onchip_memory2_1.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x1000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="19.1"
start="dma_0.write_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="19.1"
start="dma_0.write_master"
end="onchip_memory2_1.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x1000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="clock" version="19.1" start="clk_0.clk" end="dma_0.clk" />
<connection
kind="clock"
version="19.1"
start="clk_0.clk"
end="onchip_memory2_0.clk1" />
<connection
kind="clock"
version="19.1"
start="clk_0.clk"
end="onchip_memory2_1.clk1" />
<connection
kind="clock"
version="19.1"
start="clk_0.clk"
end="oc_axi_lite_bfm_0.clock" />
<connection kind="reset" version="19.1" start="clk_0.clk_reset" end="dma_0.reset" />
<connection
kind="reset"
version="19.1"
start="clk_0.clk_reset"
end="onchip_memory2_0.reset1" />
<connection
kind="reset"
version="19.1"
start="clk_0.clk_reset"
end="onchip_memory2_1.reset1" />
<connection
kind="reset"
version="19.1"
start="clk_0.clk_reset"
end="oc_axi_lite_bfm_0.reset_1" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
/trunk/example/avalon_dma_tb.v
0,0 → 1,116
// avalon_dma_tb.v
 
// Generated using ACDS version 19.1 670
 
`timescale 1 ps / 1 ps
module avalon_dma_tb (
);
 
integer i;
reg [31:0] i_r;
 
 
reg [0:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5_r;
reg [0:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2_r;
reg [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3_r;
reg [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_r;
 
wire avalon_dma_inst_clk_bfm_clk_clk; // avalon_dma_inst_clk_bfm:clk -> [avalon_dma_inst:clk_clk, avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:clk, avalon_dma_inst_reset_bfm:clk]
wire avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4; // avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_4 -> avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_4
wire [0:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5; // avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_5 -> avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_5
wire [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_1; // avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_1 -> avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_1
wire [0:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2; // avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_2 -> avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_2
wire [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3; // avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal_3 -> avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal_3
wire [31:0] avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal; // avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm:sig_new_signal -> avalon_dma_inst:oc_axi_lite_bfm_0_driver_new_signal
wire avalon_dma_inst_reset_bfm_reset_reset; // avalon_dma_inst_reset_bfm:reset -> avalon_dma_inst:reset_reset_n
 
assign avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5 = avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5_r;
assign avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2 = avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2_r;
assign avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3 = avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3_r;
assign avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal = avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_r;
 
avalon_dma avalon_dma_inst (
.clk_clk (avalon_dma_inst_clk_bfm_clk_clk), // clk.clk
.oc_axi_lite_bfm_0_driver_new_signal (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal), // oc_axi_lite_bfm_0_driver.new_signal
.oc_axi_lite_bfm_0_driver_new_signal_1 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_1), // .new_signal_1
.oc_axi_lite_bfm_0_driver_new_signal_2 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2), // .new_signal_2
.oc_axi_lite_bfm_0_driver_new_signal_3 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3), // .new_signal_3
.oc_axi_lite_bfm_0_driver_new_signal_4 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4), // .new_signal_4
.oc_axi_lite_bfm_0_driver_new_signal_5 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5), // .new_signal_5
.reset_reset_n (avalon_dma_inst_reset_bfm_reset_reset) // reset.reset_n
);
 
altera_avalon_clock_source #(
.CLOCK_RATE (50000000),
.CLOCK_UNIT (1)
) avalon_dma_inst_clk_bfm (
.clk (avalon_dma_inst_clk_bfm_clk_clk) // clk.clk
);
 
/*
altera_conduit_bfm avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm (
.clk (avalon_dma_inst_clk_bfm_clk_clk), // clk.clk
.sig_new_signal (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal), // conduit.new_signal
.sig_new_signal_1 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_1), // .new_signal_1
.sig_new_signal_2 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2), // .new_signal_2
.sig_new_signal_3 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3), // .new_signal_3
.sig_new_signal_4 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4), // .new_signal_4
.sig_new_signal_5 (avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5), // .new_signal_5
.reset (1'b0) // (terminated)
);
*/
altera_avalon_reset_source #(
.ASSERT_HIGH_RESET (0),
.INITIAL_RESET_CYCLES (50)
) avalon_dma_inst_reset_bfm (
.reset (avalon_dma_inst_reset_bfm_reset_reset), // reset.reset_n
.clk (avalon_dma_inst_clk_bfm_clk_clk) // clk.clk
);
 
/*
.addr (oc_axi_lite_bfm_0_driver_new_signal), // driver.new_signal
.r_data (oc_axi_lite_bfm_0_driver_new_signal_1), // .new_signal_1
.transaction_type (oc_axi_lite_bfm_0_driver_new_signal_2), // .new_signal_2
.w_data (oc_axi_lite_bfm_0_driver_new_signal_3), // .new_signal_3
.done (oc_axi_lite_bfm_0_driver_new_signal_4), // .new_signal_4
.start (oc_axi_lite_bfm_0_driver_new_signal_5), // .new_signal_5
*/
 
initial begin
#2000000
 
i_r = 32'h00000000;
 
for(i = 0; i < 4096; i=i+4)
begin
write(i_r, 32'hdeadbeef);
i_r = i_r + 4;
end
 
write(32'h00002004, 32'h00000000); // read address
write(32'h00002008, 32'h00001000); // write address
write(32'h0000200C, 32'h00001000); // length
write(32'h00002018, 32'h0000000a); // GO and WORD
 
 
end
 
 
task write;
input [31:0] addr;
input [31:0] data;
begin
$display("In task\n");
avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_r = addr; //addr
avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_3_r = data; // data
avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_2_r = 1'b0; // write - transaction type
avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5_r = 1'b1; // start
 
wait(avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4); // done
avalon_dma_inst_oc_axi_lite_bfm_0_driver_bfm_conduit_new_signal_5_r = 1'b0; // start
 
wait(~avalon_dma_inst_oc_axi_lite_bfm_0_driver_new_signal_4); // done
end
endtask
 
endmodule
/trunk/new_component.v
0,0 → 1,219
// new_component.v
 
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
 
`timescale 1 ps / 1 ps
module new_component (
input wire clock_clk, // clock.clk
output wire [31:0] axm_m0_awaddr, // axm_m0.awaddr
output wire [2:0] axm_m0_awprot, // .awprot
output wire axm_m0_awvalid, // .awvalid
input wire axm_m0_awready, // .awready
output wire [31:0] axm_m0_wdata, // .wdata
output wire axm_m0_wlast, // .wlast
output wire axm_m0_wvalid, // .wvalid
input wire axm_m0_wready, // .wready
input wire axm_m0_bvalid, // .bvalid
output wire axm_m0_bready, // .bready
output wire [31:0] axm_m0_araddr, // .araddr
output wire [2:0] axm_m0_arprot, // .arprot
output wire axm_m0_arvalid, // .arvalid
input wire axm_m0_arready, // .arready
input wire [31:0] axm_m0_rdata, // .rdata
input wire axm_m0_rvalid, // .rvalid
output wire axm_m0_rready, // .rready
input wire [31:0] addr, // driver.new_signal
output wire [31:0] r_data, // .new_signal_1
input wire transaction_type, // .new_signal_2
input wire [31:0] w_data, // .new_signal_3
output wire done, // .new_signal_4
input wire start, // .new_signal_5
input wire reset_reset // reset_1.reset
);
 
parameter IDLE=0, READ=1, WRITE=2;
parameter N_AW_W=0, AW_NW=1, NAW_W=2, B_WAIT=3 ;
parameter R_AR=0, R_R=1, R_RSP=2;
 
reg [1:0] state;
reg [1:0] write_state;
reg [1:0] read_state;
 
reg done_r;
reg [31:0] r_data_r;
 
reg [31:0] axm_m0_awaddr_r ;
reg axm_m0_awvalid_r ;
reg [31:0] axm_m0_wdata_r ;
reg axm_m0_wvalid_r ;
reg axm_m0_bready_r ;
reg [31:0] axm_m0_araddr_r ;
reg axm_m0_arvalid_r ;
reg axm_m0_rready_r ;
reg axm_m0_wlast_r ;
reg [2:0] axm_m0_awprot_r ;
 
assign done = done_r ;
assign axm_m0_awaddr = axm_m0_awaddr_r ;
assign axm_m0_awvalid = axm_m0_awvalid_r;
assign axm_m0_wdata = axm_m0_wdata_r ;
assign axm_m0_wvalid = axm_m0_wvalid_r ;
assign axm_m0_bready = axm_m0_bready_r ;
assign axm_m0_arvalid = axm_m0_arvalid_r;
assign axm_m0_araddr = axm_m0_araddr_r ;
assign axm_m0_rready = axm_m0_rready_r ;
assign axm_m0_wlast = axm_m0_wlast_r ;
assign axm_m0_awprot = axm_m0_awprot_r ;
assign r_data = r_data_r ;
 
initial
begin
state = IDLE;
done_r = 0;
write_state = 0;
done_r = '0;
axm_m0_awaddr_r = '0;
axm_m0_awvalid_r = '0;
axm_m0_wdata_r = '0;
axm_m0_wvalid_r = '0;
axm_m0_bready_r = '0;
axm_m0_arvalid_r = '0;
axm_m0_araddr_r = '0;
axm_m0_rready_r = '0;
axm_m0_wlast_r = '0;
axm_m0_awprot_r = '0;
 
end
 
always @(posedge clock_clk)
begin
if(reset_reset)
begin
done_r <= 0;
end
else
begin
case(state)
IDLE:
begin
if(done_r)
begin
done_r <= 1'b0;
end
 
if(start)
begin
done_r <= 1'b0;
if(transaction_type)
begin
axm_m0_arvalid_r <= 1'b1;
axm_m0_araddr_r <= addr;
state <= READ;
read_state <= R_AR;
end
else
begin
axm_m0_awaddr_r <= addr;
axm_m0_awvalid_r <= 1'b1;
axm_m0_wdata_r <= w_data;
axm_m0_wvalid_r <= 1'b1;
axm_m0_wlast_r <= 1'b1;
axm_m0_awprot_r <= 3'b000;
state <= WRITE;
write_state <= N_AW_W;
end
end
end
READ:
begin
case(read_state)
R_AR:
begin
if(axm_m0_arvalid & axm_m0_arready)
begin
read_state <= R_R;
axm_m0_arvalid_r <= 1'b0;
axm_m0_rready_r <= 1'b1;
end
end
R_R:
begin
if(axm_m0_rready & axm_m0_rvalid)
begin
read_state <= R_RSP;
r_data_r <= axm_m0_rdata;
axm_m0_rready_r <= 1'b0;
end
end
R_RSP:
begin
done_r <= 1'b1;
state <= IDLE;
end
endcase
end
WRITE:
begin
case(write_state)
N_AW_W:
begin
if(axm_m0_awvalid & axm_m0_awready & axm_m0_wvalid & axm_m0_wready)
begin
axm_m0_awvalid_r <= 1'b0;
axm_m0_wvalid_r <= 1'b0;
axm_m0_bready_r <= 1'b1;
write_state <= B_WAIT;
end
else if(axm_m0_awvalid & axm_m0_awready)
begin
axm_m0_awvalid_r <= 1'b0;
write_state <= AW_NW;
end
else if(axm_m0_wvalid & axm_m0_wready) //Not sure if this can actually happen
begin
axm_m0_wvalid_r <= 1'b0;
write_state <= NAW_W;
end
end
AW_NW:
begin
if(axm_m0_wvalid & axm_m0_wready)
begin
axm_m0_wvalid_r <= 1'b0;
axm_m0_bready_r <= 1'b1;
write_state <= B_WAIT;
end
end
NAW_W:
begin
if(axm_m0_awvalid & axm_m0_awready)
begin
axm_m0_awvalid_r <= 1'b0;
axm_m0_bready_r <= 1'b1;
write_state <= B_WAIT;
end
end
B_WAIT:
begin
if(axm_m0_bvalid & axm_m0_bready)
begin
state <= IDLE;
done_r <= 1'b1;
axm_m0_bready_r <= 1'b0;
end
end
endcase
end
endcase
end
end
 
 
 
endmodule
/trunk/oc_axi_lite_bfm_hw.tcl
0,0 → 1,203
# TCL File Generated by Component Editor 19.1
# Sat Jun 06 22:05:16 EDT 2020
# DO NOT MODIFY
 
 
#
# oc_axi_lite_bfm "oc_axi_lite_bfm" v1.0
# Jack Frye 2020.06.06.22:05:16
# Bus Functional Model AXI4-Lite for Platform Designer
#
 
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
 
 
#
# module oc_axi_lite_bfm
#
set_module_property DESCRIPTION "Bus Functional Model AXI4-Lite for Platform Designer"
set_module_property NAME oc_axi_lite_bfm
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Open Cores"
set_module_property AUTHOR "Jack Frye"
set_module_property DISPLAY_NAME oc_axi_lite_bfm
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
 
 
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL new_component
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file new_component.v VERILOG PATH new_component.v TOP_LEVEL_FILE
 
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL new_component
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file new_component.v VERILOG PATH new_component.v
 
 
#
# parameters
#
add_parameter IDLE INTEGER 0
set_parameter_property IDLE DEFAULT_VALUE 0
set_parameter_property IDLE DISPLAY_NAME IDLE
set_parameter_property IDLE TYPE INTEGER
set_parameter_property IDLE UNITS None
set_parameter_property IDLE HDL_PARAMETER true
add_parameter READ INTEGER 1
set_parameter_property READ DEFAULT_VALUE 1
set_parameter_property READ DISPLAY_NAME READ
set_parameter_property READ TYPE INTEGER
set_parameter_property READ UNITS None
set_parameter_property READ HDL_PARAMETER true
add_parameter WRITE INTEGER 2
set_parameter_property WRITE DEFAULT_VALUE 2
set_parameter_property WRITE DISPLAY_NAME WRITE
set_parameter_property WRITE TYPE INTEGER
set_parameter_property WRITE UNITS None
set_parameter_property WRITE HDL_PARAMETER true
add_parameter N_AW_W INTEGER 0
set_parameter_property N_AW_W DEFAULT_VALUE 0
set_parameter_property N_AW_W DISPLAY_NAME N_AW_W
set_parameter_property N_AW_W TYPE INTEGER
set_parameter_property N_AW_W UNITS None
set_parameter_property N_AW_W HDL_PARAMETER true
add_parameter AW_NW INTEGER 1
set_parameter_property AW_NW DEFAULT_VALUE 1
set_parameter_property AW_NW DISPLAY_NAME AW_NW
set_parameter_property AW_NW TYPE INTEGER
set_parameter_property AW_NW UNITS None
set_parameter_property AW_NW HDL_PARAMETER true
add_parameter NAW_W INTEGER 2
set_parameter_property NAW_W DEFAULT_VALUE 2
set_parameter_property NAW_W DISPLAY_NAME NAW_W
set_parameter_property NAW_W TYPE INTEGER
set_parameter_property NAW_W UNITS None
set_parameter_property NAW_W HDL_PARAMETER true
add_parameter B_WAIT INTEGER 3
set_parameter_property B_WAIT DEFAULT_VALUE 3
set_parameter_property B_WAIT DISPLAY_NAME B_WAIT
set_parameter_property B_WAIT TYPE INTEGER
set_parameter_property B_WAIT UNITS None
set_parameter_property B_WAIT HDL_PARAMETER true
add_parameter R_AR INTEGER 0
set_parameter_property R_AR DEFAULT_VALUE 0
set_parameter_property R_AR DISPLAY_NAME R_AR
set_parameter_property R_AR TYPE INTEGER
set_parameter_property R_AR UNITS None
set_parameter_property R_AR HDL_PARAMETER true
add_parameter R_R INTEGER 1
set_parameter_property R_R DEFAULT_VALUE 1
set_parameter_property R_R DISPLAY_NAME R_R
set_parameter_property R_R TYPE INTEGER
set_parameter_property R_R UNITS None
set_parameter_property R_R HDL_PARAMETER true
add_parameter R_RSP INTEGER 2
set_parameter_property R_RSP DEFAULT_VALUE 2
set_parameter_property R_RSP DISPLAY_NAME R_RSP
set_parameter_property R_RSP TYPE INTEGER
set_parameter_property R_RSP UNITS None
set_parameter_property R_RSP HDL_PARAMETER true
 
 
#
# display items
#
 
 
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
 
add_interface_port clock clock_clk clk Input 1
 
 
#
# connection point axm_m0
#
add_interface axm_m0 axi4 start
set_interface_property axm_m0 associatedClock clock
set_interface_property axm_m0 associatedReset reset_1
set_interface_property axm_m0 readIssuingCapability 1
set_interface_property axm_m0 writeIssuingCapability 1
set_interface_property axm_m0 combinedIssuingCapability 1
set_interface_property axm_m0 ENABLED true
set_interface_property axm_m0 EXPORT_OF ""
set_interface_property axm_m0 PORT_NAME_MAP ""
set_interface_property axm_m0 CMSIS_SVD_VARIABLES ""
set_interface_property axm_m0 SVD_ADDRESS_GROUP ""
 
add_interface_port axm_m0 axm_m0_awaddr awaddr Output 32
add_interface_port axm_m0 axm_m0_awprot awprot Output 3
add_interface_port axm_m0 axm_m0_awvalid awvalid Output 1
add_interface_port axm_m0 axm_m0_awready awready Input 1
add_interface_port axm_m0 axm_m0_wdata wdata Output 32
add_interface_port axm_m0 axm_m0_wlast wlast Output 1
add_interface_port axm_m0 axm_m0_wvalid wvalid Output 1
add_interface_port axm_m0 axm_m0_wready wready Input 1
add_interface_port axm_m0 axm_m0_bvalid bvalid Input 1
add_interface_port axm_m0 axm_m0_bready bready Output 1
add_interface_port axm_m0 axm_m0_araddr araddr Output 32
add_interface_port axm_m0 axm_m0_arprot arprot Output 3
add_interface_port axm_m0 axm_m0_arvalid arvalid Output 1
add_interface_port axm_m0 axm_m0_arready arready Input 1
add_interface_port axm_m0 axm_m0_rdata rdata Input 32
add_interface_port axm_m0 axm_m0_rvalid rvalid Input 1
add_interface_port axm_m0 axm_m0_rready rready Output 1
 
 
#
# connection point driver
#
add_interface driver conduit end
set_interface_property driver associatedClock clock
set_interface_property driver associatedReset ""
set_interface_property driver ENABLED true
set_interface_property driver EXPORT_OF ""
set_interface_property driver PORT_NAME_MAP ""
set_interface_property driver CMSIS_SVD_VARIABLES ""
set_interface_property driver SVD_ADDRESS_GROUP ""
 
add_interface_port driver addr new_signal Input 32
add_interface_port driver r_data new_signal_1 Output 32
add_interface_port driver transaction_type new_signal_2 Input 1
add_interface_port driver w_data new_signal_3 Input 32
add_interface_port driver done new_signal_4 Output 1
add_interface_port driver start new_signal_5 Input 1
 
 
#
# connection point reset_1
#
add_interface reset_1 reset end
set_interface_property reset_1 associatedClock clock
set_interface_property reset_1 synchronousEdges DEASSERT
set_interface_property reset_1 ENABLED true
set_interface_property reset_1 EXPORT_OF ""
set_interface_property reset_1 PORT_NAME_MAP ""
set_interface_property reset_1 CMSIS_SVD_VARIABLES ""
set_interface_property reset_1 SVD_ADDRESS_GROUP ""
 
add_interface_port reset_1 reset_reset reset Input 1
 

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