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Subversion Repositories open8_urisc

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Rev 298 → Rev 299

/open8_urisc/trunk/VHDL/status_led.vhd
35,6 → 35,8
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/24/20 Created as a separate sub-component
-- Seth Henry 07/13/22 Modified to allow for chaining of toggle signal as
-- well as slowing down the DIM50PCT signal to 1/32
 
library ieee;
use ieee.std_logic_1164.all;
44,11 → 46,16
 
entity status_led is
generic(
Source : boolean := TRUE;
Reset_Level : std_logic
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Toggle_In : in std_logic := '0';
Toggle_Out : out std_logic;
--
LED_Mode : in std_logic_vector(2 downto 0);
LED_Out : out std_logic
);
67,7 → 74,8
return retval;
end function;
 
signal Dim50Pct_Out : std_logic := '0';
signal Dim50Pct_Ctr : std_logic_vector(4 downto 0) := "00000";
alias Dim50Pct_Out is Dim50Pct_Ctr(4);
 
constant TAP1 : integer := 16;
constant TAP2 : integer := 21;
114,23 → 122,51
d0 <= LFSR_poly(TAP4) xnor LFSR_poly(TAP3) xnor
LFSR_poly(TAP2) xnor LFSR_poly(TAP1);
 
Timer_proc: process( Clock, Reset )
Source_Mode : if( Source )generate
 
Toggle_Out <= Cycle_Toggle;
 
Toggle_Gen: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Dim50Pct_Out <= '0';
LFSR_poly <= Init_Seed;
Cycle_Toggle <= '0';
Fade_Timer1 <= (others => '0');
Fade_Timer2 <= (others => '0');
Fade_out <= '0';
elsif( rising_edge(Clock) )then
Dim50Pct_Out <= not Dim50Pct_Out;
 
LFSR_poly <= LFSR_poly(22 downto 0) & d0;
if( LFSR_poly = Init_Seed )then
Cycle_Toggle <= not Cycle_Toggle;
end if;
end if;
end process;
 
end generate;
 
Sink_Mode : if( not Source )generate
 
Toggle_Out <= '0';
 
Toggle_Gen: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Cycle_Toggle <= '0';
elsif( rising_edge(Clock) )then
Cycle_Toggle <= Toggle_In;
end if;
end process;
 
end generate;
 
 
Timer_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Dim50Pct_Ctr <= (others => '0');
Fade_Timer1 <= (others => '0');
Fade_Timer2 <= (others => '0');
Fade_out <= '0';
elsif( rising_edge(Clock) )then
Dim50Pct_Ctr <= Dim50Pct_Ctr - 1;
 
Fade_Timer1 <= Fade_Timer1 - 1;
Fade_Timer2 <= Fade_Timer2 - 1;
if( or_reduce(Fade_Timer2) = '0' )then

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