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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/Documents/CPU Instruction Set_files
    from Rev 241 to Rev 272
    ↔ Reverse comparison
  •

Rev 241 → Rev 272

/sheet001.htm
57,11 → 57,11
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<td class=xl107 colspan=2 width=734 style='mso-ignore:colspan;width:551pt'>Open8
<td class=xl106 colspan=2 width=734 style='mso-ignore:colspan;width:551pt'>Open8
Instruction Set</td>
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<td width=97 style='width:73pt'></td>
/sheet002.htm
52,10 → 52,10
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<td class=xl106 colspan=2 width=954 style='mso-ignore:colspan;width:716pt'>Open8
<td class=xl107 colspan=2 width=954 style='mso-ignore:colspan;width:716pt'>Open8
CPU Core Generics</td>
</tr>
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98,26 → 98,13
false, the RSP instruction will reset the stack pointer to
&quot;Stack_Start_Addr&quot; by default. If true, the RSP instruction will
either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0
depending on the status of the specified ALU flag bit.</td>
depending on the status of the PSR_GP4 flag.</td>
</tr>
<tr height=80 style='height:60.0pt'>
<td height=80 class=xl76 style='height:60.0pt;border-top:none'>Stack_Xfer_Flag</td>
<td class=xl76 style='border-top:none;border-left:none'>Integer 0-7</td>
<td class=xl103 style='border-top:none;border-left:none'>PSR_GP4</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Specifies
which processor flag controls the behavior of RSP when
'Allow_Stack_Address_move' is true. If the specified bit is clear ('0'), the
RSP instruction will transfer the stack pointer to R1:R0 (SP -&gt; R1:R0),
otherwise, if it is true ('1'), the RSP instruction will set the stack
pointer from R1:R0 ( R1:R0 -&gt; SP ). Any of the 8 CPU flags may be
specified, but the intent was to use FL_GP[1-4], as these are purely under
software control and are not otherwise modified by the ALU.</td>
</tr>
<tr height=80 style='height:60.0pt'>
<td height=80 class=xl73 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
<td height=80 class=xl108 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
true, indexed instructions such as LDX, LDO, STX, STO will automatically
increment if an odd register is specified. The effect is similar to a normal
indexed instruction followed by an UPP instruction on the same register pair.
127,10 → 114,10
will result in normal behavior.</td>
</tr>
<tr height=40 style='height:30.0pt'>
<td height=40 class=xl76 style='height:30.0pt;border-top:none'>BRK_Implements_WAI</td>
<td class=xl76 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl103 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>If
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>BRK_Implements_WAI</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
true, the BRK instruction will cause the processor to halt as if an INT
instruction was executed, but without triggering an interrupt. This is useful
for pausing the CPU until an interrupt occurs. If false, the BRK instruction
137,17 → 124,17
simply causes the CPU to execute 5 NOP cycles.</td>
</tr>
<tr height=20 style='height:15.0pt'>
<td height=20 class=xl73 style='height:15.0pt;border-top:none'>Enable_NMI</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>TRUE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Forces
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Enable_NMI</td>
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl109 style='border-top:none;border-left:none'>TRUE</td>
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Forces
bit 0 of the Interrupt Mask to 1, causing Interrupt 0 to be non-maskable.</td>
</tr>
<tr height=40 style='height:30.0pt'>
<td height=40 class=xl76 style='height:30.0pt;border-top:none'>Sequential_Interrupts</td>
<td class=xl76 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl103 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Prohibits
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Sequential_Interrupts</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Prohibits
interrupts from initiating an ISR if the I-bit is set, making ISRs
sequential. This potentially blocks interrupt priority by allowing a lower
level interrupt to block a higher level interrupt. This can be fixed by
154,26 → 141,44
clearing the I-bit in interruptable ISRs.</td>
</tr>
<tr height=40 style='height:30.0pt'>
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
<td height=40 class=xl108 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
set, preserves the general purpose flags GP_PSR4 to GP_PSR7 on ISR exit,
allowing them to be persistently set by interrupts. The lower four flag bits
are always restored.</td>
</tr>
<tr height=40 style='height:30.0pt'>
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Supervisor_Mode</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
set to true, enables restrictions on RSP, CLP/STP, and SMSK where they only
can alter internal registers if the I bit is set. Also initializes the CPU to
start with the I-bit set. If set to false, there are no restrictions on these
instructions.</td>
</tr>
<tr height=20 style='height:15.0pt'>
<td height=20 class=xl76 style='height:15.0pt;border-top:none'>Default_Interrupt_Mask</td>
<td class=xl76 style='border-top:none;border-left:none'>8-bit Data</td>
<td class=xl103 style='border-top:none;border-left:none'>x&quot;FF&quot;</td>
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Unsigned_Index_Offsets</td>
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Determines
whether the offset calculation for LDO/STO is signed or unsigned. Default
behavior is signed.</td>
</tr>
<tr height=20 style='height:15.0pt'>
<td height=20 class=xl73 style='height:15.0pt;border-top:none'>Default_Interrupt_Mask</td>
<td class=xl73 style='border-top:none;border-left:none'>8-bit Data</td>
<td class=xl74 style='border-top:none;border-left:none'>x&quot;FF&quot;</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
the initial interrupt mask (note that bit 0 is ignored, as this is the NMI)</td>
</tr>
<tr height=20 style='height:15.0pt'>
<td height=20 class=xl73 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
<td class=xl73 style='border-top:none;border-left:none'>Real</td>
<td class=xl74 style='border-top:none;border-left:none'>-</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Clock
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
<td class=xl108 style='border-top:none;border-left:none'>Real</td>
<td class=xl109 style='border-top:none;border-left:none'>-</td>
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Clock
frequency in Hz of the CPU clock. Used to configure the 1Mhz/1uSec tick pulse</td>
</tr>
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/stylesheet.css
287,8 → 287,32
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