URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/Documents/CPU Instruction Set_files
- from Rev 311 to Rev 312
- ↔ Reverse comparison
Rev 311 → Rev 312
/sheet001.htm
1,5 → 1,4
<html xmlns:v="urn:schemas-microsoft-com:vml" |
xmlns:o="urn:schemas-microsoft-com:office:office" |
<html xmlns:o="urn:schemas-microsoft-com:office:office" |
xmlns:x="urn:schemas-microsoft-com:office:excel" |
xmlns="http://www.w3.org/TR/REC-html40"> |
|
/sheet002.htm
98,7 → 98,7
false, the RSP instruction will reset the stack pointer to |
"Stack_Start_Addr" by default. If true, the RSP instruction will |
either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0 |
depending on the status of the PSR_GP4 flag.</td> |
depending on the status of the PSR_GP4 (PSR_S) flag.</td> |
</tr> |
<tr height=80 style='height:60.0pt'> |
<td height=80 class=xl108 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td> |
113,8 → 113,8
be incremented by 1. If false, specifying either register in a register pair |
will result in normal behavior.</td> |
</tr> |
<tr height=40 style='height:30.0pt'> |
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>BRK_Implements_WAI</td> |
<tr height=60 style='height:45.0pt'> |
<td height=60 class=xl73 style='height:45.0pt;border-top:none'>BRK_Implements_WAI</td> |
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td> |
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td> |
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If |
121,7 → 121,7
true, the BRK instruction will cause the processor to halt as if an INT |
instruction was executed, but without triggering an interrupt. This is useful |
for pausing the CPU until an interrupt occurs. If false, the BRK instruction |
simply causes the CPU to execute 5 NOP cycles.</td> |
flushes the pipeline and executes an extended (5-clock) NOP cycle.</td> |
</tr> |
<tr height=20 style='height:15.0pt'> |
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Enable_NMI</td> |
137,8 → 137,8
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Prohibits |
interrupts from initiating an ISR if the I-bit is set, making ISRs |
sequential. This potentially blocks interrupt priority by allowing a lower |
level interrupt to block a higher level interrupt. This can be fixed by |
clearing the I-bit in interruptable ISRs.</td> |
level interrupt to block a higher level interrupt. This can be worked around |
by clearing the I-bit in known interruptable ISRs.</td> |
</tr> |
<tr height=40 style='height:30.0pt'> |
<td height=40 class=xl108 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td> |
145,9 → 145,9
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td> |
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td> |
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If |
set, preserves the general purpose flags GP_PSR4 to GP_PSR7 on ISR exit, |
allowing them to be persistently set by interrupts. The lower four flag bits |
are always restored.</td> |
set, preserves the general purpose flags GP_PSR4 (PSR_S) to GP_PSR7 on ISR |
exit, allowing them to be persistently set by interrupts. The lower four flag |
bits are always restored.</td> |
</tr> |
<tr height=40 style='height:30.0pt'> |
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Supervisor_Mode</td> |
182,7 → 182,8
<td class=xl73 style='border-top:none;border-left:none'>8-bit Data</td> |
<td class=xl74 style='border-top:none;border-left:none'>x"FF"</td> |
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets |
the initial interrupt mask (note that bit 0 is ignored, as this is the NMI)</td> |
the initial interrupt mask (note that bit 0 is ignored if Enable_NMI is set |
TRUE)</td> |
</tr> |
<tr height=20 style='height:15.0pt'> |
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Clock_Frequency</td> |