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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 315 to Rev 316
    ↔ Reverse comparison
  •

Rev 315 → Rev 316

/o8_cpu.vhd
279,6 → 279,10
-- Seth Henry 07/12/22 Fixed a long-standing bug in the SBC instruction
-- where the 2's complement inversion wasn't adding
-- the additional 1, causing off by 1 errors
-- Seth Henry 05/18/23 Removed reset signal from address offset pipeline
-- registers and cleaned up comments. Also removed
-- superfluous constant definitions, as they can't
-- be realistically altered.
 
library ieee;
use ieee.std_logic_1164.all;
321,9 → 325,13
 
architecture behave of o8_cpu is
 
-- The CPU uses the PLL_Locked signal to create an internal reset pulse
signal Reset_q : std_logic := Reset_Level;
signal Reset : std_logic := Reset_Level;
 
-- Utility 1uS counter signals & constants. Note that the correct clock
-- frequency is required in Hz. Note that some clock frequencies will not
-- divide cleanly, producing a slightly fast/slow uSec tick signal
constant USEC_VAL : integer := integer(Clock_Frequency / 1000000.0);
constant USEC_WDT : integer := ceil_log2(USEC_VAL - 1);
constant USEC_DLY : std_logic_vector :=
540,15 → 548,6
alias ISR_Addr_Base is ISR_Start_Addr(15 downto 4);
signal ISR_Addr_Offset : std_logic_vector(3 downto 0) := x"0";
 
constant INT_VECTOR_0 : std_logic_vector(3 downto 0) := x"0";
constant INT_VECTOR_1 : std_logic_vector(3 downto 0) := x"2";
constant INT_VECTOR_2 : std_logic_vector(3 downto 0) := x"4";
constant INT_VECTOR_3 : std_logic_vector(3 downto 0) := x"6";
constant INT_VECTOR_4 : std_logic_vector(3 downto 0) := x"8";
constant INT_VECTOR_5 : std_logic_vector(3 downto 0) := x"A";
constant INT_VECTOR_6 : std_logic_vector(3 downto 0) := x"C";
constant INT_VECTOR_7 : std_logic_vector(3 downto 0) := x"E";
 
signal IDX_Offset_SX : std_logic := '0';
 
signal IDX_Offset : ADDRESS_TYPE := x"0000";
1262,7 → 1261,7
else
Int_Mask <= Default_Interrupt_Mask;
end if;
ISR_Addr_Offset <= INT_VECTOR_0;
ISR_Addr_Offset <= x"0";
 
for i in 0 to 7 loop
Regfile(i) <= x"00";
1278,7 → 1277,9
 
CPU_State <= CPU_Next_State;
 
-------------------------------------------------------------------------------
-- Register the halt request and acknowledge lines
-------------------------------------------------------------------------------
 
CPU_Halt_Req <= Halt_Req;
Halt_Ack <= CPU_Halt_Ack;
1459,28 → 1460,28
 
if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
if( Pending(0) = '1' )then
ISR_Addr_Offset <= INT_VECTOR_0;
ISR_Addr_Offset <= x"0";
Pending(0) <= '0';
elsif( Pending(1) = '1' )then
ISR_Addr_Offset <= INT_VECTOR_1;
ISR_Addr_Offset <= x"2";
Pending(1) <= '0';
elsif( Pending(2) = '1' )then
ISR_Addr_Offset <= INT_VECTOR_2;
ISR_Addr_Offset <= x"4";
Pending(2) <= '0';
elsif( Pending(3) = '1' )then
ISR_Addr_Offset <= INT_VECTOR_3;
ISR_Addr_Offset <= x"6";
Pending(3) <= '0';
elsif( Pending(4) = '1' )then
ISR_Addr_Offset <= INT_VECTOR_4;
ISR_Addr_Offset <= x"8";
Pending(4) <= '0';
elsif( Pending(5) = '1' )then
ISR_Addr_Offset <= INT_VECTOR_5;
ISR_Addr_Offset <= x"A";
Pending(5) <= '0';
elsif( Pending(6) = '1' )then
ISR_Addr_Offset <= INT_VECTOR_6;
ISR_Addr_Offset <= x"C";
Pending(6) <= '0';
elsif( Pending(7) = '1' )then
ISR_Addr_Offset <= INT_VECTOR_7;
ISR_Addr_Offset <= x"E";
Pending(7) <= '0';
end if;
Wait_for_FSM <= or_reduce(Pending);

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