URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 320 to Rev 321
- ↔ Reverse comparison
Rev 320 → Rev 321
/async_ser_rx.vhd
35,6 → 35,7
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
-- Seth Henry 04/14/20 Code cleanup and revision section added |
-- Seth Henry 06/08/23 Fixed issue where parity flag could get stuck high |
|
library ieee; |
use ieee.std_logic_1164.all; |
118,8 → 119,6
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begin |
|
Rx_Perr <= Rx_PErr_int; |
|
UART_Regs: process( Clock, Reset ) |
begin |
if( Reset = Reset_Level )then |
130,11 → 129,13
Rx_Parity <= '0'; |
Rx_Data <= (others => '0'); |
Rx_Valid <= '0'; |
Rx_Perr <= '0'; |
Rx_PErr_int <= '0'; |
elsif( rising_edge(Clock) )then |
Rx_In_SR <= Rx_In_SR(2 downto 0) & Rx_In; |
|
Rx_Valid <= '0'; |
Rx_Perr <= '0'; |
case( Rx_State )is |
when IO_STRT => |
if( Rx_In_Q = '1' )then |
190,6 → 191,7
when IO_DONE => |
Rx_Data <= Rx_Buffer; |
Rx_Valid <= not Rx_PErr_int; |
Rx_Perr <= Rx_PErr_int; |
Rx_State <= Rx_State + 1; |
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when others => |