URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 329 to Rev 330
- ↔ Reverse comparison
Rev 329 → Rev 330
/o8_ts_ioctl.vhd
57,7 → 57,6
|
entity o8_ts_ioctl is |
generic( |
Default_Int_Mask : ADDRESS_TYPE := x"0000"; |
Address : ADDRESS_TYPE |
); |
port( |
64,11 → 63,11
Open8_Bus : in OPEN8_BUS_TYPE; |
Rd_Data : out DATA_TYPE; |
-- |
PIT_Interrupt : out std_logic; |
CPU_Interrupts : out DATA_TYPE; |
-- |
RAM_Write_Fault : in std_logic; |
IO_Interrupts_In : in ADDRESS_TYPE := x"0000"; |
IO_Interrupt : out std_logic; |
IO_Write_Qual : out ADDRESS_TYPE |
IO_Write_Qual_Out : out ADDRESS_TYPE |
); |
end entity; |
|
88,7 → 87,7
|
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0); |
signal Reg_Sel_q : std_logic_vector(2 downto 0); |
signal Wr_En_d : std_logic; |
signal Wr_En_d : std_logic := '0'; |
signal Wr_En_q : std_logic := '0'; |
alias Wr_Data_d is Open8_Bus.Wr_Data; |
signal Wr_Data_q : DATA_TYPE := x"00"; |
99,6 → 98,8
signal Update_Interval : std_logic; |
signal Timer_Cnt : DATA_TYPE := x"00"; |
|
signal PIT_Interrupt : std_logic := '0'; |
|
signal Int_Mask : ADDRESS_TYPE := x"0000"; |
alias Int_Mask_l is Int_Mask(7 downto 0); |
alias Int_Mask_h is Int_Mask(15 downto 8); |
107,7 → 108,7
alias Clear_Pending_l is Clear_Pending(7 downto 0); |
alias Clear_Pending_h is Clear_Pending(15 downto 8); |
|
signal Ack_IO_Ints : std_logic; |
signal Ack_IO_Ints : std_logic := '0'; |
|
signal Pending : ADDRESS_TYPE := x"0000"; |
alias Pending_l is Pending(7 downto 0); |
115,8 → 116,10
signal Pending_q : ADDRESS_TYPE := x"0000"; |
signal Pending_RE : ADDRESS_TYPE := x"0000"; |
|
signal IO_Int_Pending : std_logic; |
signal IO_Int_Pending : std_logic := '0'; |
|
signal IO_Interrupt : std_logic := '0'; |
|
signal IO_Qual_Reg : ADDRESS_TYPE := x"0000"; |
alias IO_Qual_l is IO_Qual_Reg(7 downto 0); |
alias IO_Qual_h is IO_Qual_Reg(15 downto 8); |
123,8 → 126,14
|
begin |
|
IO_Write_Qual <= IO_Qual_Reg; |
-- The task switcher assumes the following CPU interrupt configuration |
CPU_Interrupts(0) <= RAM_Write_Fault; -- WPR fault interrupt |
CPU_Interrupts(1) <= PIT_Interrupt; -- Pre-emption timer interrupt |
CPU_Interrupts(2) <= IO_Interrupt; -- Cascaded I/O interrupt |
CPU_Interrupts(7 downto 3) <= (others => '0'); -- Supervisor functions |
|
IO_Write_Qual_Out <= IO_Qual_Reg; |
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0'; |
Wr_En_d <= Addr_Match and CPU_Wr_En and CPU_ISR_En; |
Rd_En_d <= Addr_Match and CPU_Rd_En; |
139,7 → 148,7
Rd_Data <= OPEN8_NULLBUS; |
Interval <= x"00"; |
Update_Interval <= '0'; |
Int_Mask <= Default_Int_Mask; |
Int_Mask <= x"0000"; |
Clear_Pending <= x"0000"; |
Ack_IO_Ints <= '0'; |
elsif( rising_edge( Clock ) )then |