URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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/open8_urisc/trunk
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Rev 300 → Rev 301

/taskmgr/APP.HEX

0,0 → 1,1026

/taskmgr/app.out Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/taskmgr/app.out

taskmgr/app.out Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: taskmgr/app.s =================================================================== --- taskmgr/app.s (nonexistent) +++ taskmgr/app.s (revision 301) @@ -0,0 +1,89 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; Sample Task Manager application +; +; Revision History +; Author Date Change +;---------------- -------- --------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;----------------------------------------------------------------------------- + +;------------------------------------------------------------------------------ +; This application requires the following build parameters in the Open8 CPU +; core to function correctly: +; +; Allow_Stack_Address_Move => true RSP may relocate/retrieve the SP->R1:R0 +; Enable_Auto_Increment => true Indexed load/store instructions can use +; auto-increment feature when Rn is odd +; (or Rn++ is specified). +; BRK_Implements_WAI => true BRK is interpreted as a WAI +; Enable_NMI => true Interrupt 0 is not maskable +; Sequential_Interrupts => true ISRs are NOT interruptable +; RTI_Ignores_GP_Flags => true RTI restores only lower 4 ALU flags +; Supervisor_Mode => true I-bit is restrictive +; Unsigned_Index_Offsets => true LDO/SDO treat offset as UNSIGNED +; Rotate_Ignores_Carry => true Rotate instrs do not use the carry +; Default_Int_Mask => x"00" CPU starts with only the NMI active +; +; Further note - NOP is mapped to BRK in the assembler. Do NOT use NOP with +; the BRK_Implements_WAI enabled, as the NOP will instead trigger WAI. +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; BNI is used as a BRA (branch always) in user-mode code, since the I-bit +; should never be set. There are checks in each task's main loop that verify +; that this bit is cleared, and will panic the system otherwise. +; Similarily, in code running in the supervisor context, the I bit should +; always be set, potentially allowing BRI to be used as a BRA. Note that this +; isn't inherently safe, as ISR's are allowed to clear the I bit themselves +; while user-mode code can't affect the I-bit. +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Include block - add all of the other source files here +; +; Note that the order of included files is important due to the way the +; assembler works. Any constant which is used to derive another constant must +; be defined first. The exception is creating pointer tables, which occurs on +; a later pass. +;------------------------------------------------------------------------------ + +.INCLUDE "sys_hw_map.s" ; System Memory Map (HDL <> ASSY) +.INCLUDE "sys_const.s" ; System-Wide Constants +.INCLUDE "sys_version.s" ; System software version + +.INCLUDE "taskmgr_config.s" ; Task manager cconfiguration constants + +.INCLUDE "taskmgr_const.s" ; Main task scheduler constants + +.INCLUDE "task_0_const.s" ; Task 0 Constants & Macros +.INCLUDE "task_1_const.s" ; Task 1 Constants & Macros + +.INCLUDE "taskmgr_func.s" ; Main task scheduler & ISR code + +.INCLUDE "task_0_func.s" ; Task 0 Executable +.INCLUDE "task_1_func.s" ; Task 1 Executable + +;------------------------------------------------------------------------------ \ No newline at end of file Index: taskmgr/make.bat =================================================================== --- taskmgr/make.bat (nonexistent) +++ taskmgr/make.bat (revision 301) @@ -0,0 +1,9 @@ +echo off +cls +cd software +echo Making Application ROM +open8_as -o app.s app.obj +open8_link -vb mk_app app.out +srec_cat app.out -binary -o APP.HEX -i +del *.obj +echo Done! Index: taskmgr/mk_app =================================================================== --- taskmgr/mk_app (nonexistent) +++ taskmgr/mk_app (revision 301) @@ -0,0 +1,2 @@ +[objects] +app.obj \ No newline at end of file Index: taskmgr/open8_as.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: taskmgr/open8_as.exe =================================================================== --- taskmgr/open8_as.exe (nonexistent) +++ taskmgr/open8_as.exe (revision 301)

taskmgr/open8_as.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: taskmgr/open8_link.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: taskmgr/open8_link.exe =================================================================== --- taskmgr/open8_link.exe (nonexistent) +++ taskmgr/open8_link.exe (revision 301)

taskmgr/open8_link.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: taskmgr/srec_cat.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: taskmgr/srec_cat.exe =================================================================== --- taskmgr/srec_cat.exe (nonexistent) +++ taskmgr/srec_cat.exe (revision 301)

taskmgr/srec_cat.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: taskmgr/sys_const.s =================================================================== --- taskmgr/sys_const.s (nonexistent) +++ taskmgr/sys_const.s (revision 301) @@ -0,0 +1,323 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; sys_const.s +; +; Common constants & macros for generic hardware or structures used by several +; tasks +; +; Revision History +; Author Date Change +;---------------- -------- --------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +;-- Serial Port Constants & Macros +;------------------------------------------------------------------------------ +.DEFINE UART_DATA 0 +.DEFINE UART_STATUS 1 + +.DEFINE UART_RX_PERR 3 +.DEFINE UART_RX_EMPTY 4 +.DEFINE UART_RX_FULL 5 +.DEFINE UART_TX_EMPTY 6 +.DEFINE UART_TX_FULL 7 + +.DEFINE UART_RX_PERR_BIT 2^UART_RX_PERR +.DEFINE UART_RX_PERR_MASK UART_RX_PERR_BIT ~ $FF + +.DEFINE UART_RX_EMPTY_BIT 2^UART_RX_EMPTY +.DEFINE UART_RX_EMPTY_MASK UART_RX_EMPTY_BIT ~ $FF + +.DEFINE UART_RX_FULL_BIT 2^UART_RX_FULL +.DEFINE UART_RX_FULL_MASK UART_RX_FULL_BIT ~ $FF + +.DEFINE UART_TX_EMPTY_BIT 2^UART_TX_EMPTY +.DEFINE UART_TX_EMPTY_MASK UART_TX_EMPTY_BIT ~ $FF + +.DEFINE UART_TX_FULL_BIT 2^UART_TX_FULL +.DEFINE UART_TX_FULL_MASK UART_TX_FULL_BIT ~ $FF + +; Checking the UART flags involves testing bits in the status register +; The assembler isn't bright enough to use the defined constant, so this macro +; does the test on the correct bit + +.MACRO CHECK_UART_RX_PERR + BTT 3 +.ENDM + +.MACRO CHECK_UART_RX_EMPTY + BTT 4 +.ENDM + +.MACRO CHECK_UART_RX_FULL + BTT 5 +.ENDM + +.MACRO CHECK_UART_TX_EMPTY + BTT 6 +.ENDM + +.MACRO CHECK_UART_TX_FULL + BTT 7 +.ENDM + +; Register Map: +; Offset Bitfield Description Read/Write +; 0x00 AAAAAAAA TX Data (WR) RX Data (RD) (RW) +; 0x01 EDCBA--- FIFO Status (RO*) +; A: RX Parity Error (write to clear) +; B: RX FIFO Empty +; C: RX FIFO almost full (922/1024) +; D: TX FIFO Empty +; E: TX FIFO almost full (922/1024) +; +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Macros for setting the return value in Cmd_Error +;------------------------------------------------------------------------------ +.DEFINE RX_CERR $FB +.DEFINE RX_TERR $FC +.DEFINE RX_LERR $FD +.DEFINE RX_PERR $FE +.DEFINE RX_OKAY $FF + +.MACRO RETURN_RX_CMD_OKAY + LDI R0, #RX_OKAY +.ENDM + +.MACRO RETURN_RX_CMD_ERROR + LDI R0, #RX_CERR +.ENDM + +.MACRO RETURN_RX_TIMEOUT_ERROR + LDI R0, #RX_TERR +.ENDM + +.MACRO RETURN_RX_LENGTH_ERROR + LDI R0, #RX_LERR +.ENDM + +.MACRO RETURN_RX_PARITY_ERROR + LDI R0, #RX_PERR +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Common buffer/memory copy +; Uses R3:R2 as source, R5:R4 as destination, and R1 as the counter variable +;------------------------------------------------------------------------------ +.MACRO MEM_COPY +__MEM_CP_LP\@:LDX R2++ + STX R4++ + DBNZ R1, __MEM_CP_LP\@ +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Common buffer/memory fill/flush +; Uses R5:R4 as destination, and R1 as the counter variable +;------------------------------------------------------------------------------ +.MACRO MEM_FILL +__MEM_FL_LP\@:STX R4++ + DBNZ R1, __MEM_FL_LP\@ +.ENDM + +.MACRO MEM_FLUSH + CLR R0 + MEM_FILL +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Compute 16-bit Checksum +; +; Uses R3:R2 as source, R5:R4 as destination, and R1 as the counter variable +; Adds all of the memory locations specified to a 16-bit accumulator, returning +; the result in R5:R4 (destination) +;------------------------------------------------------------------------------ +.MACRO CALC_CHECKSUM16 + CLR R0 + T0X R4 ; Initialize accumulator R5:R0 to 0 + T0X R5 + T0X R7 ; Initialize R7 to 0 + +__CHK_SM_LP\@:LDX R2++ + ADD R4 + T0X R4 + + TX0 R5 + ADC R7 + T0X R5 + + DBNZ R1, __CHK_SM_LP\@ +.ENDM + +; These macros assume that the pointer in R3:R2 has been left pointing to the +; end of the receive buffer by the CALC_CHECKSUM16 macro. Do NOT repoint +; R3:R2, and be sure to use these macros in the order that the checksum bytes +; appear in the packet. (THESE ARE ORDER DEPENDENT) + +.MACRO CHECK_SUM_LB + LDX R2++ + XOR R4 +.ENDM + +.MACRO CHECK_SUM_UB + LDX R2++ + XOR R5 +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Convert ASCII to HEX +; +; Converts an ASCII value into an integer value from 0x0 to 0xF +; Assumes incoming data is in R0. Returns a value in R0 +; Returns a value of 0x00 to 0x0F for valid characters, or +; 0xFF (-1) for invalid characters +;------------------------------------------------------------------------------ +.MACRO CONVERT_ASC2HEX + PSH R1 ; Preserve R1 and R2 + PSH R2 + + T0X R2 ; Make a copy of R0 to R2 for backup + LDI R1, #$F0 ; Mask off the lower bits to figure out the range + AND R1 + T0X R1 ; Copy the upper 4-bits to R1 for branching tests + + LDI R0, #$30 ; Is it a decimal char 0-9? + XOR R1 + BRZ _CNV_AH_09_\@ + + LDI R0, #$40 ; Is it a hex char A-F? + XOR R1 + BRZ _CNV_AH_AF_\@ + + LDI R0, #$60 ; Is it a hex char a-f? + XOR R1 + BRZ _CNV_AH_AF_\@ + + BNI _CNV_AH_NV_\@ + +; Valid HEX characters 0-9 are ASCII codes 0x30 to 0x39. Codes 0x3A to 0x3F are +; invalid, so check that the value in R0 is LESS than $3A. +_CNV_AH_09_\@:TX0 R2 ; Restore R0 from backup + LDI R1, #$0F ; Mask off the upper bits to check validity + AND R1 + T0X R2 ; Backup the lower 4-bits to R2 + +; Check for 0x0A to 0x0F + LDI R1, #$0A ; Load R1 with 0x0A (:) + CMP R1 ; Compare R0 to R1 + BNN _CNV_AH_NV_\@ ; Branch if not negative (R0 > 9) + + TX0 R2 ; Restore the lower 4-bits to R0 + BNI _CNV_AH_EX_\@ + +; Valid HEX characters A-F are 0x41 to 0x46 OR 0x61 to $66. The upper 4-bits +; have already been checked, so just verify that the lower 4-bits are between +; 0x01 and 0x06. 0x00 and 0x07 to 0x0F are invalid, +; so check that the value in R0 is LESS than $3A +_CNV_AH_AF_\@:TX0 R2 ; Restore R0 from backup + LDI R1, #$0F ; Mask off the upper bits to check validity + AND R1 + T0X R2 ; Backup the lower 4-bits to R2 + +; Check for 0x00 + BRZ _CNV_AH_NV_\@ ; 0x0 is an invalid code + +; Check for 0x07 to 0x0F + LDI R1, #$07 ; Load R1 with 0x7 (G or g) + CMP R1 ; Compare R0 to R1 + BNN _CNV_AH_NV_\@ ; Branch of not negative (R0 > 6) + +; If this is a valid character, add 9 to the lower 4-bits for the result +; (0x01 to 0x06 -> 0x0A to 0x0F) + TX0 R2 ; Restore lower 4-bits to R0 + LDI R1, #$09 ; Load R1 with 0x9 + ADD R1 ; Added 9 to R0 to convert to A-F + BNI _CNV_AH_EX_\@ + +_CNV_AH_NV_\@:LDI R0, #$FF ; Return 0xFF on an invalid character + +_CNV_AH_EX_\@:POP R2 ; Restore R1 and R2 + POP R1 +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Convert the lower nibble of R0 into a valid ASCII character +; Accepts data in R0 and returns the ASCII code in R0 +;------------------------------------------------------------------------------ +.MACRO CONVERT_NIB2ASC + PSH R1 ; Preserve R1 + + LDI R1, #$0F ; Mask away the upper 4-bits + AND R1 + + T0X R1 ; Copy to R1 + LDI R0, #$09 ; Load R0 with 0x09 + CMP R1 ; Compare R0 to R1 + BNN _CNV_NA_09_\@ + ; Fall into _MC_FM_CHA_AF + +_CNV_NA_AF_\@:LDI R0, #$37 ; Add 0x37 to the nibble to get the ASCII value + ADD R1 + BNI _CNV_NA_EX_\@ + +_CNV_NA_09_\@:LDI R0, #$30 ; Add 0x30 to the nibble to get the ASCII value + OR R1 + ; Fall into _MC_FM_CHA_EX + +_CNV_NA_EX_\@:POP R1 +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Convert the packed BCD value in R0 to its ASCII equivalent in R3:R2 +; $59 -> $35, $39 +;------------------------------------------------------------------------------ +.MACRO CONV_PBCD_TO_ASCII + T0X R2 ; Copy R0 -> R2 for re-use + LDI R0, #$F0 ; Set the upper nibble mask. BCD is only 3-bit + AND R2 ; Mask off the upper 3-bits of value -> R0 + CLP PSR_C ; Clear the carry (in case CPU options not set) + ROR R0 ; Shift the upper nibble down + ROR R0 + ROR R0 + ROR R0 + LDI R1, #$30 ; Set the ASCII upper nibble mask of $30 + OR R1 ; Create an ASCII character + T0X R3 ; Transfer the upper character to R3 + + LDI R0, #$0F ; Set the lower nibble mask + AND R2 ; Mask off the lower bits + OR R1 ; Create an ASCII character + T0X R2 ; Store the lower character to R1 + RTS +.ENDM +;------------------------------------------------------------------------------ Index: taskmgr/sys_hw_map.s =================================================================== --- taskmgr/sys_hw_map.s (nonexistent) +++ taskmgr/sys_hw_map.s (revision 301) @@ -0,0 +1,73 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; sys_hw_map.s +; +; Defines the interface between HDL and assembly, and should be derived from +; Open8_cfg.vhd (this is a minimal configuration) +; +; Revision History +; Author Date Change +;---------------- -------- --------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; System Memory Map from Open8_cfg +;------------------------------------------------------------------------------ +.DEFINE RAM_Address $0000 ; System RAM +.DEFINE WPR_Address $1000 ; RAM Write Protect Mask +.DEFINE WQL_Address $1020 ; I/O Write Qual Register +.DEFINE INT_Address $1040 ; Cascaded Interrupt Manager +;... +.DEFINE ROM_Address $8000 ; Application ROM +.DEFINE ISR_Start_Addr $FFF0 ; ISR vector table +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Interrupt Manager Selection +; +; Uncomment the INTMGR16 define if using the 16-bit "complex" interrupt manager +; firmware. Otherwise, the 8-bit "simple" external interrupt manager is +; assumed. Note that the interfaces are NOT register compatible, so this will +; break the system if the wrong manager is selected! +; +;.DEFINE INTMGR16 +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; RAM Configuration +;------------------------------------------------------------------------------ +; Define the size of the memory and number of partitions in order to configure +; the region size constant - which will be used by tasks to assign their +; write-protection requirements +.DEFINE RAM_Size 4096 +.DEFINE RAM_Partitions 32 +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Write Qualification Groups from Open8_cfg +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ \ No newline at end of file Index: taskmgr/sys_version.s =================================================================== --- taskmgr/sys_version.s (nonexistent) +++ taskmgr/sys_version.s (revision 301) @@ -0,0 +1,35 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; sys_version.s +; +; Defines a software version num for use in telemetry +; +; Revision History +; Author Date Change +;---------------- -------- --------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ +.DEFINE SW_VERSION 0 +;------------------------------------------------------------------------------ \ No newline at end of file Index: taskmgr/task_0_const.s =================================================================== --- taskmgr/task_0_const.s (nonexistent) +++ taskmgr/task_0_const.s (revision 301) @@ -0,0 +1,92 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; task_0_consts.s +; +; Revision History +; Author Date Change +;---------------- -------- --------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Manager Macros & Defines +;------------------------------------------------------------------------------ + +; Task supervisory functions (optional, but must be defined) + +.MACRO TASK0_PANIC +.ENDM + +.MACRO TASK0_SUPV_FN0 +.ENDM + +.MACRO TASK0_SUPV_FN1 +.ENDM + +.MACRO TASK0_SUPV_FN2 +.ENDM + +.MACRO TASK0_SUPV_FN3 +.ENDM + +.MACRO TASK0_SUPV_FN4 +.ENDM + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; I/O Mapping (HDL -> ASSY) +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Pointer Defines and Memory Management +;------------------------------------------------------------------------------ + +.MACRO INSTANCE_TASK0_POINTERS +.ENDM + +; Memory Structures and Variable Organization + +; Variable Size Description +; -------- ---- ------------------------------------------------------- + +; Allocate the variable structures in memory +.ENUM TASK0_VARMEM +TSK0_TL INSTANCEOF str_task_label +.ENDE + +.MACRO SET_TASK0_LABEL + LDI R0, #$54 ; T + STA R0, TSK0_TL.Label+0 + LDI R0, #$30 ; 0 + STA R0, TSK0_TL.Label+1 +.ENDM + +.MACRO INITIALIZE_TASK0_VARS + SET_TASK0_LABEL +.ENDM +;------------------------------------------------------------------------------ \ No newline at end of file Index: taskmgr/task_0_func.s =================================================================== --- taskmgr/task_0_func.s (nonexistent) +++ taskmgr/task_0_func.s (revision 301) @@ -0,0 +1,51 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; task_0_func.s +; +; Revision History +; Author Date Change +;---------------- -------- --------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ +.ORG TASK0_BLOCK + +;------------------------------------------------------------------------------ +; Pointer table +;------------------------------------------------------------------------------ + INSTANCE_TASK0_POINTERS +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Initialization +;------------------------------------------------------------------------------ +TASK0_INIT: INITIALIZE_TASK0_VARS + RTS +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Executive +;------------------------------------------------------------------------------ +TASK0_EXEC: RTS +;------------------------------------------------------------------------------ \ No newline at end of file Index: taskmgr/task_1_const.s =================================================================== --- taskmgr/task_1_const.s (nonexistent) +++ taskmgr/task_1_const.s (revision 301) @@ -0,0 +1,93 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; task_1_const.s +; +; Revision History +; Author Date Change +;---------------- -------- --------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Manager Macros & Defines +;------------------------------------------------------------------------------ + +; Task supervisory functions (optional, but must be defined) + +.MACRO TASK1_PANIC +.ENDM + +.MACRO TASK1_SUPV_FN0 +.ENDM + +.MACRO TASK1_SUPV_FN1 +.ENDM + +.MACRO TASK1_SUPV_FN2 +.ENDM + +.MACRO TASK1_SUPV_FN3 +.ENDM + +.MACRO TASK1_SUPV_FN4 +.ENDM + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; I/O Mapping (HDL -> ASSY) +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Pointer Defines and Memory Management +;------------------------------------------------------------------------------ + +.MACRO INSTANCE_TASK1_POINTERS +.ENDM + +; Memory Structures and Variable Organization + +; Variable Size Description +; -------- ---- ------------------------------------------------------- + +; Allocate the variable structures in memory +.ENUM TASK1_VARMEM +TSK1_TL INSTANCEOF str_task_label +.ENDE + +.MACRO SET_TASK1_LABEL + LDI R0, #$54 ; T + STA R0, TSK1_TL.Label+0 + LDI R0, #$31 ; 1 + STA R0, TSK1_TL.Label+1 +.ENDM + +.MACRO INITIALIZE_TASK1_VARS + SET_TASK1_LABEL +.ENDM + +;------------------------------------------------------------------------------ \ No newline at end of file Index: taskmgr/task_1_func.s =================================================================== --- taskmgr/task_1_func.s (nonexistent) +++ taskmgr/task_1_func.s (revision 301) @@ -0,0 +1,51 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; task_1_func.s +; +; Revision History +; Author Date Change +;---------------- -------- --------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ +.ORG TASK1_BLOCK + +;------------------------------------------------------------------------------ +; Pointer table +;------------------------------------------------------------------------------ + INSTANCE_TASK1_POINTERS +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Initialization +;------------------------------------------------------------------------------ +TASK1_INIT: INITIALIZE_TASK1_VARS + RTS +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Executive +;------------------------------------------------------------------------------ +TASK1_EXEC: RTS +;------------------------------------------------------------------------------ \ No newline at end of file Index: taskmgr/taskmgr_config.s =================================================================== --- taskmgr/taskmgr_config.s (nonexistent) +++ taskmgr/taskmgr_config.s (revision 301) @@ -0,0 +1,207 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; taskmgr_config.s +; +; Main Manager task specific constants (this must precede taskmgr_const.s) +; +; Revision History +; Author Date Change +;---------------- -------- ---------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Management Constants +;------------------------------------------------------------------------------ +.DEFINE MAX_TASK_TIMESLICE $FA ; Preemption Time slice is 250uS +.DEFINE TASK_COUNT 2 ; Number of defined tasks +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task RAM Placement Constants +;------------------------------------------------------------------------------ +; Low memory regions (15:0) +; 0 - System Memory +; 1 - Task 0 Private Memory +; 2 - Task 1 Private Memory +; 3-15 - (Unused) + +; High memory regions (31:16) +; 16-20 - (Unused) +; 30 - Task 0 Stack Memory +; 31 - Task 1 Stack Memory + +; Assign each memory region within the 32 write protect blocks using 31 to 0 +; Note that regions from 15 to 0 are "low" memory (don't need to be adjusted +; for the mask calculation) while regions from 31 to 16 are "high" memory, and +; should have 16 subtracted to avoid overflowing a 16-bit value. +; +; Note that this implies a maximum task count of 15, as at least one region is +; required for the task manager itself, unless an additional BRAM is allocated +; for the task manager. + +; Variable Memory regions (15:0) +.DEFINE SYSTEM_VAR_RGN 0 +.DEFINE TASK0_VAR_RGN 1 +.DEFINE TASK1_VAR_RGN 2 + +; Stack Memory regions (31:16) +.DEFINE TASK0_STACK_RGN 30 +.DEFINE TASK1_STACK_RGN 31 + +; Note that the WPR masks are handled here in order to add flexibility, such as +; adding a data buffer region in "high" memory or otherwise configuring a +; task's WPR for its memory needs +; +; Note that, because of the nature of the WPR, additional memory regions, such +; as a while region to handle block transfers, can be added by by logically +; OR'ing the region masks together. Note that the resultant line does need to +; be on one line or the assembler won't process it correctly. +; ie .DEFINE TASK_VAR_MASK (2^TASK2_VAR_RGN) | (2^BUF_RGN0) | (2^BUF_RGN1) + +; Note that the assembler can't generate a 32-bit value for the mask, so for values +; greater than 15, an offset of 16 is subtracted and the mask value. Thus, there +; is a "low mask" for regions 0-15 and a "high mask" for regions 16-31. +.DEFINE HIGH_MEM_OFFSET 16 + +.DEFINE TASK0_WPR_LOW 2^TASK0_VAR_RGN +.DEFINE TASK1_WPR_LOW 2^TASK1_VAR_RGN + +.DEFINE TASK0_WPR_HIGH 2^( TASK0_STACK_RGN - HIGH_MEM_OFFSET ) +.DEFINE TASK1_WPR_HIGH 2^( TASK1_STACK_RGN - HIGH_MEM_OFFSET ) + +; Allocate the variable structures in memory. Note that WP_Rgn_Size is also +; used in taskmgr_const.s to compute the address of each task's stack start +; and end +.DEFINE WP_Rgn_Size RAM_Size / RAM_Partitions ; From sys_hw_map.s + +.DEFINE SYSTEM_VARMEM RAM_Address + ( SYSTEM_VAR_RGN * WP_Rgn_Size ) +.DEFINE TASK0_VARMEM RAM_Address + ( TASK0_VAR_RGN * WP_Rgn_Size ) +.DEFINE TASK1_VARMEM RAM_Address + ( TASK1_VAR_RGN * WP_Rgn_Size ) + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task ROM Placement Constants +; Note that the task blocks define the initial location for each task's code +; and data. If a region overflows, these constants will need to be adjusted. +;------------------------------------------------------------------------------ +.DEFINE BOOT_BLOCK $8000 ; Start of ROM +.DEFINE DATA_BLOCK $8800 ; ROM Data +.DEFINE TASK0_BLOCK $9000 ; Task 0 +.DEFINE TASK1_BLOCK $A000 ; Task 1 +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task I/O Write Qualification Constants +;------------------------------------------------------------------------------ +.DEFINE TASK0_WQL $00 +.DEFINE TASK1_WQL $00 +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; External I/O Interrupt Flag Macros - processed from within +; CHECK_EXTERNAL_IO_INTS +; +; Note that the relevant tasks should define macros allowing access to their +; ISR flag variables and/or other code that should run in supervisor context +; when the relevant interrupt is triggered. +; +; Note also that only R1 and R0 are safe to use when setting flags. Avoid R7-R2 +; as R3 and R2 are keeping track of flags and R4 through R7 aren't backed up +;------------------------------------------------------------------------------ + +; 0 = (unused) +; 1 = (unused) +; 2 = (unused) +; 3 = (unused) +; 4 = (unused) +; 5 = (unused) +; 6 = (unused) +; 7 = (unused) +; 8 = (unused) +; 9 = (unused) +; 10 = (unused) +; 11 = (unused) +; 12 = (unused) +; 13 = (unused) +; 14 = (unused) +; 15 = (unused) + +; For 8-bit external interrupt manager, only use the _L constant +.DEFINE EXT_INTERRUPT_EN_L $00 +.DEFINE EXT_INTERRUPT_EN_H $00 + +; These macros are valid for both the 8 and 16-bit interrupt managers +.MACRO SET_INT0_FLAGS +.ENDM + +.MACRO SET_INT1_FLAGS +.ENDM + +.MACRO SET_INT2_FLAGS +.ENDM + +.MACRO SET_INT3_FLAGS +.ENDM + +.MACRO SET_INT4_FLAGS +.ENDM + +.MACRO SET_INT5_FLAGS +.ENDM + +.MACRO SET_INT6_FLAGS +.ENDM + +.MACRO SET_INT7_FLAGS +.ENDM + +; These macros are only valid for the 16-bit interrupt manager +.MACRO SET_INT8_FLAGS +.ENDM + +.MACRO SET_INT9_FLAGS +.ENDM + +.MACRO SET_INT10_FLAGS +.ENDM + +.MACRO SET_INT11_FLAGS +.ENDM + +.MACRO SET_INT12_FLAGS +.ENDM + +.MACRO SET_INT13_FLAGS +.ENDM + +.MACRO SET_INT14_FLAGS +.ENDM + +.MACRO SET_INT15_FLAGS +.ENDM + +;------------------------------------------------------------------------------ \ No newline at end of file Index: taskmgr/taskmgr_const.s =================================================================== --- taskmgr/taskmgr_const.s (nonexistent) +++ taskmgr/taskmgr_const.s (revision 301) @@ -0,0 +1,1019 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; taskmgr_const.s +; +; Task Manager constants, tables, and macros +; +; Revision History +; Author Date Change +;---------------- -------- ---------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Semaphore Value - should always be non-zero +.DEFINE SEMAPHORE_VAL $FF ; Standard value used to set semaphores +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; I/O Mapping (HDL -> ASSY) +;------------------------------------------------------------------------------ + +; System RAM Write-Protect Register +.DEFINE WPR_MASK_REG WPR_Address + +; Write Protect Mask +.DEFINE WPR_MASK_0 WPR_MASK_REG + 0 +.DEFINE WPR_MASK_1 WPR_MASK_REG + 1 +.DEFINE WPR_MASK_2 WPR_MASK_REG + 2 +.DEFINE WPR_MASK_3 WPR_MASK_REG + 3 + +; WP Register Map: +; Offset Bitfield Description Read/Write +; 0x00 AAAAAAAA Region Enables 7:0 (RW) +; 0x01 AAAAAAAA Region Enables 15:8 (RW) +; 0x02 AAAAAAAA Region Enables 23:16 (RW) +; 0x03 AAAAAAAA Region Enables 31:24 (RW) + +; I/O Write Qualification Register +.DEFINE IO_WRITE_QUAL WQL_Address + +; External Interrupt Manager / Task Timer +.DEFINE INT_MGR_IF INT_Address ; Shared with the main +.DEFINE TASK_TIMER_PRD INT_MGR_IF + 0 + +; Defines for the 8-bit interrupt manager +.DEFINE EXT_INT_MASK INT_MGR_IF + 1 +.DEFINE EXT_INT_PEND INT_MGR_IF + 2 +.DEFINE EXT_INT_ACK INT_MGR_IF + 3 + +; Defines for the 16-bit interrupt manager +.DEFINE EXT_INT16_MASK_L INT_MGR_IF + 2 +.DEFINE EXT_INT16_MASK_H INT_MGR_IF + 3 +.DEFINE EXT_INT16_PEND_L INT_MGR_IF + 4 +.DEFINE EXT_INT16_PEND_H INT_MGR_IF + 5 +.DEFINE EXT_INT16_ACK INT_MGR_IF + 7 + +; Register Map: +; Offset Bitfield Description Read/Write +; 0x00 AAAAAAAA PIT Timer Interval (0 = disabled) (RW) +; 0x01 AAAAAAAA External Interrupt Mask (RW) +; 0x02 AAAAAAAA Pending External Ints* (RW) +; 0x02 A------- Interrupt Requested (write to clear) (RW) + +; External Interrupt bit & mask definitions +.DEFINE EXT_INT0_BIT 2^0 +.DEFINE EXT_INT1_BIT 2^1 +.DEFINE EXT_INT2_BIT 2^2 +.DEFINE EXT_INT3_BIT 2^3 +.DEFINE EXT_INT4_BIT 2^4 +.DEFINE EXT_INT5_BIT 2^5 +.DEFINE EXT_INT6_BIT 2^6 +.DEFINE EXT_INT7_BIT 2^7 + +.DEFINE EXT_INT8_BIT 2^0 +.DEFINE EXT_INT9_BIT 2^1 +.DEFINE EXT_INT10_BIT 2^2 +.DEFINE EXT_INT11_BIT 2^3 +.DEFINE EXT_INT12_BIT 2^4 +.DEFINE EXT_INT13_BIT 2^5 +.DEFINE EXT_INT14_BIT 2^6 +.DEFINE EXT_INT15_BIT 2^7 +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Register the interrupt service routines and form the vector address table at +; the end of the ROM +;------------------------------------------------------------------------------ +.ORG ISR_Start_Addr +.DW RAM_FAULT ; (0xFFF1:0xFFF0) ISR 0 +.DW TASK_SW_INT ; (0xFFF3:0xFFF2) ISR 1 +.DW EXT_INT_MGR ; (0xFFF5:0xFFF4) ISR 2 +.DW EXEC_SUPV0 ; (0xFFF7:0xFFF6) ISR 3 +.DW EXEC_SUPV1 ; (0xFFF9:0xFFF8) ISR 4 +.DW EXEC_SUPV2 ; (0xFFFB:0xFFFA) ISR 5 +.DW EXEC_SUPV3 ; (0xFFFD:0xFFFC) ISR 6 +.DW EXEC_SUPV4 ; (0xFFFF:0xFFFE) ISR 7 + +.DEFINE CPU_INT_ENABLES $FF +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Pointer Defines and Table Organization +;------------------------------------------------------------------------------ + +; Create defined constants to pointer table +; Note that these are offset by 4 to account for the bootstrap JMP and NOP +.DEFINE STACK_MEMORY_PTR BOOT_BLOCK + 4 +.DEFINE FREE_SYSMEM_PTR BOOT_BLOCK + 6 +.DEFINE TASK_PARAMS_PTR BOOT_BLOCK + 8 +.DEFINE TASK_PARAM_TABLE BOOT_BLOCK + 10 + +.MACRO INSTANCE_TASK_POINTERS + +.DW TaskMgr.Task_Stacks ; ( + 4) First available RAM location for stack data +.DW TaskMgr.Free_Mem ; ( + 6) First available free RAM location in sysmem +.DW TASK_PARAM_TABLE ; ( + 8) Start of task parameter table +.ENDM + +;------------------------------------------------------------------------------ +; INSTANCE_TASK_EXPORTS / CREATE_TASK_EXPORTS setup a ROM table for the task +; switcher with critical entry points and memory & I/O write access +; permissions. The entry points are created automatically by +; INSTANCE_MAIN_LOOPS, while the other constants are setup in taskmgr_config.s +; based on its task configuration and memory needs +;------------------------------------------------------------------------------ + +.DEFINE STACK_TABLE_OFFSET 2 +.DEFINE PARAM_TABLE_OFFSET 20 + +; Define table offsets to allow quick use of LDO to access individual records +; for each task + +.DEFINE PARAM_MAIN_ADDR_LOW 0 +.DEFINE PARAM_MAIN_ADDR_HIGH 1 + +.DEFINE PARAM_STACK_ADDR_LOW 2 +.DEFINE PARAM_STACK_ADDR_HIGH 3 + +.DEFINE PARAM_WPR_BYTE0 4 +.DEFINE PARAM_WPR_BYTE1 5 +.DEFINE PARAM_WPR_BYTE2 6 +.DEFINE PARAM_WPR_BYTE3 7 + +.DEFINE PARAM_WQL_LOW 8 +.DEFINE PARAM_WQL_HIGH 9 + +.DEFINE SUPV_FN0_ENTRY_LOW 10 +.DEFINE SUPV_FN0_ENTRY_HIGH 11 + +.DEFINE SUPV_FN1_ENTRY_LOW 12 +.DEFINE SUPV_FN1_ENTRY_HIGH 13 + +.DEFINE SUPV_FN2_ENTRY_LOW 14 +.DEFINE SUPV_FN2_ENTRY_HIGH 15 + +.DEFINE SUPV_FN3_ENTRY_LOW 16 +.DEFINE SUPV_FN3_ENTRY_HIGH 17 + +.DEFINE SUPV_FN4_ENTRY_LOW 18 +.DEFINE SUPV_FN4_ENTRY_HIGH 19 + +; CREATE_TASK_EXPORTS creates an entry in the TASK_PARAM_TABLE with critical +; task information. Note that the WPR_LOW, WPR_HIGH, and WQL must be defined +; in taskmgr_config.s. Everything else is automatically created here, or by +; the assembler/linker. + +.MACRO CREATE_TASK_EXPORTS +.DEFINE TASK\@_STACK_END RAM_Address + (TASK\@_STACK_RGN * WP_Rgn_Size) +.DEFINE TASK\@_STACK_START TASK\@_STACK_END + WP_Rgn_Size - 1 + +.DW TASK\@_MAIN ; 1:0 Entry point created by INSTANCE_MAIN_LOOPS +.DW TASK\@_STACK_START ; 3:2 Pointer to top of the task stack +.DW TASK\@_WPR_LOW ; 5:4 Mask for enabling task mem writes for vars +.DW TASK\@_WPR_HIGH ; 7:6 Mask for enabling task mem writes for stack +.DW TASK\@_WQL ; 9:8 Mask for enabling task I/O write access +.DW _F0_EXE_S\@ ; 11:10 Entry point for supervisory function 0 +.DW _F1_EXE_S\@ ; 13:12 Entry point for supervisory function 1 +.DW _F2_EXE_S\@ ; 15:14 Entry point for supervisory function 2 +.DW _F3_EXE_S\@ ; 17:16 Entry point for supervisory function 3 +.DW _F4_EXE_S\@ ; 19:18 Entry point for supervisory function 4 +.ENDM + +.MACRO INSTANCE_TASK_EXPORTS + .REPEAT TASK_COUNT + CREATE_TASK_EXPORTS + .ENDR +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Memory Structures and Variable Organization +;------------------------------------------------------------------------------ + +; Variable Size Description +; -------- ---- ------------------------------------------------------- +.STRUCT str_task_label +Label DW ; 2-byte "header" to allow task RAM to be easily found +.ENDST + +.STRUCT str_isr_flag +Flag DB ; Single-byte flag variable for returning semaphores +.ENDST + +.DEFINE TSB_SIZE 2 * TASK_COUNT +.DEFINE FREE_SYS 124 - TSB_SIZE + +.STRUCT str_taskman +This_Task DB ; Holds the task number of the current task +Next_Task DB ; Specifieds which task to be executed next +Fault_Flag DB ; Memory write fault flag +Fault_Task DB ; Task active/responsible for write fault +Task_Stacks DSB TSB_SIZE ; First location for stack data* +Free_Mem DSB FREE_SYS ; Unused memory in system region +.ENDST + +; * Note that this location is used to setup a pointer, which the task manager +; will use to assign each task a backup location for its current stack pointer +; Thus, this area grows up to 2x the number tasks. The type is intentionally +; set as DB as a reminder. If attempting to reuse memory in this region, this +; should be noted + +.ENUM SYSTEM_VARMEM +TaskMgr INSTANCEOF str_taskman +.ENDE +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Utility macros for booting the system and providing access to internal vars +;------------------------------------------------------------------------------ + +; The Open8 supports an optional mode for the RSP instruction that +; converts it from Reset Stack Pointer to Relocate Stack Pointer. +; The new form of the instruction takes one of the CPU flags as a +; direction/mode bit. Setting PSR_S will cause the instruction +; to write R1:R0 -> SP, while clearing it will cause the instruction +; to copy the SP -> R1:R0. + +.MACRO RETRIEVE_SP + CLP PSR_S ; Affirmatively clear PSR_S flag first + RSP ; Then execute the RSP instruction +.ENDM + +.MACRO RELOCATE_SP + STP PSR_S ; Affirmatively set PSR_S flag first + RSP ; Execute the RSP instruction + CLP PSR_S ; Reset PSR_GP4 afterward +.ENDM + +; Task initialization, switching time, and init/exec macros +.MACRO DISABLE_PREEMPTION_TIMER + CLR R0 ; Make sure the PIT is disabled + STA R0, TASK_TIMER_PRD ; by writing 0 to the PIT period +.ENDM + +.MACRO RESET_PREEMPTION_TIMER + LDI R0, #MAX_TASK_TIMESLICE; Turn on the PIT timer at this point + STA R0, TASK_TIMER_PRD ; to kick off the task switcher +.ENDM + +; Fault flag macros +.MACRO INITIALIZE_FAULT_FLAGS + CLR R0 + STA R0, TaskMgr.Fault_Flag + STA R0, TaskMgr.Fault_Task +.ENDM + +.MACRO SET_FAULT_FLAGS + LDI R0, #SEMAPHORE_VAL + STA R0, TaskMgr.Fault_Flag + LDA R0, TaskMgr.This_Task + STA R0, TaskMgr.Fault_Task; +.ENDM + +; TASK_SETUP is a template used to generate code that sets up a single task's +; stack and stack pointer for each a task. This macros will temporarily +; relocate the stack pointer, push the task's initial state to the task's +; stack. Note that it is important to also ensure that the stack has data to +; not only restore the return address, but also R7:R0, as well as the flag +; state. +.MACRO TASK_SETUP + + ; Setup a pointer in R3:R2 to the beginning of the parameter + ; table to load task information from. + LDI R0, #\@ + LDI R1, #PARAM_TABLE_OFFSET + MUL R1 + + LDA R2, TASK_PARAMS_PTR + 0 ; Load R3:R2 with the start of the + LDA R3, TASK_PARAMS_PTR + 1 ; task paramenter region + + ADD R2 + T0X R2 + TX0 R1 + ADC R3 + T0X R3 + + ; Get the task's starting stack address from the table and load + ; it into the CPU SP + LDO R2, PARAM_STACK_ADDR_HIGH + T0X R1 + LDO R2, PARAM_STACK_ADDR_LOW + RELOCATE_SP ; R1:R0 -> CPU SP + + ; From here on out, the CPU SP is pointing to the target task's + ; stack region, so we can initialize its stack memory + + ; Write initial flag value + CLR R0 + PSH R0 + + ; Initialize the return address to point to the "initialize" + ; portion of the task, so that the task can do its one-time + ; startup code. + + LDO R2, PARAM_MAIN_ADDR_HIGH ; Write return PC MSB + PSH R0 + + LDO R2, PARAM_MAIN_ADDR_LOW ; Write return PC LSB + PSH R0 + + ; Setup the initial reg values + CLR R0 ; Initialize all registers to 0 + PSH R0 ; R0 + PSH R0 ; R1 + PSH R0 ; R2 + PSH R0 ; R3 + PSH R0 ; R4 + PSH R0 ; R5 + PSH R0 ; R6 + PSH R0 ; R7 + + ; Once the task's stack has been initialized, retrieve the new + ; stack pointer from the SP and store it in the task's backup + ; variable. + + LDI R0, #\@ + LDI R1, #STACK_TABLE_OFFSET + MUL R1 + + LDA R2, STACK_MEMORY_PTR + 0 + LDA R3, STACK_MEMORY_PTR + 1 + + ADD R2 + T0X R2 + TX0 R1 + ADC R3 + T0X R3 + + RETRIEVE_SP + STX R2 + TX0 R1 + STO R2,1 +.ENDM + +; INSTANCE_TASK_SETUP expands to create setup code for all of the tasks based +; on the template above. There should be one setup per task, hence the repeat +; based on TASK_COUNT +.MACRO INSTANCE_TASK_SETUP + .REPT TASK_COUNT + TASK_SETUP + .ENDR +.ENDM + +; REINIT_STACK_BUFFER_PTR uses the This_Task variable to configure R3:R2 as a +; pointer into the system memory where stack pointer backups are stored. +.MACRO REINIT_STACK_BUFFER_PTR + LDA R0, TaskMgr.This_Task ; Get the task number + LDI R1, #STACK_TABLE_OFFSET ; Multiply it by 2 + MUL R1 + + LDA R2, STACK_MEMORY_PTR + 0 ; Load R3:R2 with the start of the + LDA R3, STACK_MEMORY_PTR + 1 ; stack memory region + + ADD R2 ; Add [R3:R2] + [R1:R0] -> [R3:R2] + T0X R2 + TX0 R1 + ADC R3 + T0X R3 +.ENDM + + +; REINIT_TASK_TABLE_PTR uses the This_Task variable to configure R3:R2 as a +; pointer into the TASK_PARAMS table. +.MACRO REINIT_TASK_TABLE_PTR + + LDA R0, TaskMgr.This_Task + LDI R1, #PARAM_TABLE_OFFSET + MUL R1 + + LDA R2, TASK_PARAMS_PTR + 0 ; Load R3:R2 with the start of the + LDA R3, TASK_PARAMS_PTR + 1 ; task parameter region + + ADD R2 ; Add [R3:R2] + [R1:R0] -> [R3:R2] + T0X R2 + TX0 R1 + ADC R3 + T0X R3 +.ENDM + +; BACKUP_FULL_CONTEXT pushes all 8 registers to the stack +.MACRO BACKUP_FULL_CONTEXT + PSH R0 + PSH R1 + PSH R2 + PSH R3 + PSH R4 + PSH R5 + PSH R6 + PSH R7 +.ENDM + +; RESTORE_FULL_CONTEXT pops all 8 registers off of the stack +.MACRO RESTORE_FULL_CONTEXT + POP R7 + POP R6 + POP R5 + POP R4 + POP R3 + POP R2 + POP R1 + POP R0 +.ENDM + +; SUSPEND_CURRENT_TASK pushes all of the registers to a task's stack, then +; backups up the stack pointer to the system memory backup location for that +; task. +.MACRO SUSPEND_CURRENT_TASK + BACKUP_FULL_CONTEXT + + REINIT_STACK_BUFFER_PTR + + RETRIEVE_SP ; Copy CPU SP -> R1:R0 + STX R2 ; Push R1:R0 -> [R3:R2]* + TX0 R1 + STO R2,1 +.ENDM + +; AWAKEN_NEXT_TASK is responsible for updating the Next_Task variable, then +; using it to restore the stack pointer from the system memory copy. It then +; updates the memory write protection parameters and I/O write qualification +; register for the new task. Finally, it resets the pre-emption timer and +; restores the register state from the task's stack. +.MACRO AWAKEN_NEXT_TASK + LDA R1, TaskMgr.Next_Task ; Copy Next_Task -> This_Task + STA R1, TaskMgr.This_Task + +; This is a simple round-robin scheduler, unless an ISR alters the Next_Task +; variable, so increment the task count, check it against the total task +; count, and reset it to task 0 if necessary. + + INC R1 ; Increment the task count + LDI R0, #TASK_COUNT ; Compare it with the task count + XOR R1 + BNZ _TS_ADV_TN_\@ ; If it matches the task count + LDI R1, #$00 ; reset the counter to zero +_TS_ADV_TN_\@:STA R1, TaskMgr.Next_Task ; Store the new value into Next_Task + + REINIT_STACK_BUFFER_PTR ; Lookup the new task's table pointer + + LDO R2, PARAM_MAIN_ADDR_HIGH ; Push [R3:R2]* -> R1:R0 + T0X R1 + LDO R2, PARAM_MAIN_ADDR_LOW + RELOCATE_SP ; Update R1:R0 -> CPU SP + + REINIT_TASK_TABLE_PTR ; Setup R3:R2 to point to the task table + + ; Rewrite the RAM WPR register for this task. Note that the WPR + ; is a 32-bit register. + LDO R2, PARAM_WPR_BYTE0 + STA R0, WPR_MASK_0 + + LDO R2, PARAM_WPR_BYTE1 + STA R0, WPR_MASK_1 + + LDO R2, PARAM_WPR_BYTE2 + STA R0, WPR_MASK_2 + + LDO R2, PARAM_WPR_BYTE3 + STA R0, WPR_MASK_3 + + LDO R2, PARAM_WQL_LOW ; Update the new task's WQL + STA R0, IO_WRITE_QUAL + + RESET_PREEMPTION_TIMER ; Reset the PIT timer + + RESTORE_FULL_CONTEXT ; Restore the new task's register state + RTI +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; System Start +; +; System initialization requires that the CPU start in supervisor mode, as it +; writes to every active region in memory. Thus, if the CPU is NOT in +; in supervisor mode, something has gone horribly wrong. This branch locks the +; main loop if the I bit is not set. This is probably unnecessary now that the +; panic ISR is in place. +;------------------------------------------------------------------------------ + +; INIT_NEXT_TASK forces the Next_Task variable to 0 (Task 0) +.MACRO INIT_NEXT_TASK + CLR R0 + STA R0, TaskMgr.Next_Task +.ENDM + +.MACRO BOOT_SYSTEM +; Before beginning, turn off all of the CPU interrupts (The NMI will still be +; active, but memory write protection is effectively disabled with the I-bit +; set) Note that this code is running in interrupt context (I-bit is set) +; so it is "uninterruptible" due to the HDL generic being set. However, this +; doesn't prevent pending interrupts from being latched by the CPU. +; Note that this macro is defined in "isr_const.s" + DISABLE_CPU_INTS + +; Even though interrupts are off, disable the task timer so that there isn't +; a pending task timer interrupt waiting when interrupts are re-enabled. This +; avoids the first task missing out on initialization. + DISABLE_PREEMPTION_TIMER + +; Initialize the system fault flags + INITIALIZE_FAULT_FLAGS + +; Setup the stack and stack pointer for each of the tasks. (see above) + INSTANCE_TASK_SETUP + +; Before starting, make sure the external interrupt controller has been +; initialized. Initialization of the external interrupt controller involves +; clearing any pending interrupts and setting up the interrupt mask. Finally, +; the CPU interrupts should be enabled at this point, as the interrupt core is +; ready. +.IFDEF INTMGR16 + INITIALIZE_IO_INTMGR16 ; Setup the 16-bit IF +.ELSE + INITIALIZE_IO_INTMGR ; Setup the 8-bit IF +.ENDIF +; Once the external interrupt manager is configured, enable the CPU interrupts + ENABLE_CPU_INTS ; Enable the CPU interrupt inputs + +; Like the task switcher ISR, restore the full CPU state for the first task + INIT_NEXT_TASK + AWAKEN_NEXT_TASK + +; Create all of the task loops here. + INSTANCE_TASK_LOOPS +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Loops +;------------------------------------------------------------------------------ + +; INSTANCE_MAIN_LOOP: +; These loops represent each task's "main()", and should never "exit". +; Each task's func.s file should declare two required functions, TASKn_INIT and +; TASKn_EXEC +; +; Note that the call to the task switch ISR occurs prior to the task's exec +; function to allow every task to finish its setup BEFORE any task begins +; processing. +; +; Last, the final branch is only taken if the I bit is still NOT set. If it +; somehow gets set, the task will trigger a system panic (which never returns) + +; There should be one loop per task. Note that the labels are used in to create +; the table of entry points + +.MACRO INSTANCE_TASK_LOOP +TASK\@_MAIN: JSR TASK\@_INIT +_TASK\@_LOOP: CALL_TASK_SW + JSR TASK\@_EXEC + BNI _TASK\@_LOOP + CALL_PANIC +.ENDM + +; INSTANCE_MAIN_LOOPS expands to create the stub main loops for all of the +; tasks based on the template above. There should be one setup per task, hence +; the repeat based on TASK_COUNT. Note that the output labels will be used to +; populate fields in the task parameter table. +.MACRO INSTANCE_TASK_LOOPS + .REPEAT TASK_COUNT + INSTANCE_TASK_LOOP + .ENDR +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Software-callable Interrupts +;------------------------------------------------------------------------------ + +; CALL_PANIC executes the same ISR as a memory fault and triggers the shutdown +; sequence. This requires a hard-reset to recover +.MACRO CALL_PANIC + INT 0 +.ENDM + +; CALL_TASK_SW executes the same ISR as the pre-emption timer, and allows tasks +; to give up any remaining time +.MACRO CALL_TASK_SW + INT 1 +.ENDM + +; Interrupt 2 is reserved for the external interrupt manager. Calling it would +; likely be harmless, but do no real work. + +; CALL_SUPV_FNn allow tasks to execute code in an interrupt/supervisor context +; and should be used with caution. +.MACRO CALL_SUPV_FN0 + INT 3 +.ENDM + +.MACRO CALL_SUPV_FN1 + INT 4 +.ENDM + +.MACRO CALL_SUPV_FN2 + INT 5 +.ENDM + +.MACRO CALL_SUPV_FN3 + INT 6 +.ENDM + +.MACRO CALL_SUPV_FN4 + INT 7 +.ENDM + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; CPU Interrupt Control Macros +;------------------------------------------------------------------------------ +.MACRO DISABLE_CPU_INTS + CLR R0 + SMSK +.ENDM + +.MACRO ENABLE_CPU_INTS + LDI R0, #CPU_INT_ENABLES + SMSK +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; RAM Access Fault Shutdown (CALL_PANIC) +; If a task manages to cause a memory fault, sets default conditions and +; then soft-halts the CPU. +; Note that DISABLE_PREEMPTION_TIMER, SET_FAULT_FLAGS are defined in +; "main_const.s", while PANIC_HALT macro calls each task's PANICn_HALT macro +;------------------------------------------------------------------------------ + +.MACRO PROCESS_RAM_FAULT + DISABLE_CPU_INTS ; Disable interrupts + DISABLE_PREEMPTION_TIMER ; Disable the task timer + SET_FAULT_FLAGS ; Copy the faulting task info + EXEC_PANIC_HALT ; Run any necessary shutdown code +_RFLT_HALT: WAI ; Soft-Halt the CPU + JMP _RFLT_HALT ; This shouldn't happen, but if it does +.ENDM + +.MACRO CREATE_PANIC_TASK_BLOCK + LDI R0, #\@ + LDI R1, #PARAM_TABLE_OFFSET + MUL R1 + + LDA R2, TASK_PARAMS_PTR + 0 ; Load R3:R2 with the start of the + LDA R3, TASK_PARAMS_PTR + 1 ; task parameter region + + ADD R2 ; Add [R3:R2] + [R1:R0] -> [R3:R2] + T0X R2 + TX0 R1 + ADC R3 + T0X R3 + + ; Update the WQL for the task's panic code so each task isn't + ; doing this on its own + + LDO R2, PARAM_WQL_LOW + STA R0, IO_WRITE_QUAL + + TASK\@_PANIC +.ENDM + +.MACRO EXEC_PANIC_HALT + .REPEAT TASK_COUNT + CREATE_PANIC_TASK_BLOCK + .ENDR +.ENDM + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Switcher ISR (CALL_TASK_SW) +; +; Handles switching context between tasks when called. +;------------------------------------------------------------------------------ + +.MACRO SWITCH_TASKS + SUSPEND_CURRENT_TASK + AWAKEN_NEXT_TASK +.ENDM + +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; External System Interrupt Map & ISR Macros +; This code configures the external I/O interrupt manager at startup +;------------------------------------------------------------------------------ + +; Setup the external I/O Interrupt manager by writing the mask registers and +; clearing any pending interrupts. Note that the interrupt enable constants +; are defined in ext_isr_config.s + +.MACRO INITIALIZE_IO_INTMGR + CLR R0 ; Disable all external interrupts + STA R0, EXT_INT_MASK + + LDI R0, #SEMAPHORE_VAL ; Clear any pending interrupts + STA R0, EXT_INT_PEND ; and do a master acknowledge + STA R0, EXT_INT_ACK + + LDI R0, #EXT_INTERRUPT_EN_L; Re-enable the external interrupts + STA R0, EXT_INT_MASK +.ENDM + +.MACRO INITIALIZE_IO_INTMGR16 + CLR R0 ; Disable all external interrupts + STA R0, EXT_INT16_MASK_L + STA R0, EXT_INT16_MASK_H + + LDI R0, #SEMAPHORE_VAL ; Clear any pending interrupts + STA R0, EXT_INT16_PEND_L ; and do a master acknowledge + STA R0, EXT_INT16_PEND_H + STA R0, EXT_INT16_ACK + + LDI R0, #EXT_INTERRUPT_EN_L; Re-enable the external interrupts + STA R0, EXT_INT16_MASK_L + + LDI R0, #EXT_INTERRUPT_EN_H; Re-enable the external interrupts + STA R0, EXT_INT16_MASK_H +.ENDM + +; Sets up an individual external interrupt macro. Note that these refer to +; macros defined in ext_isr_config.s + +.MACRO PROCESS_EXT_ISR + SET_INT\@_FLAGS + + TX0 R3 ; When done with the flags, update the + LDI R1, #EXT_INT\@_BIT ; mask clear register with the ext bit + OR R1 ; and restore it to R3. Then, before + T0X R3 ; falling into the next check, make + TX0 R2 ; sure to restore the current ints +.ENDM + +; This code checks the external I/O interrupt manager status and processes the +; flag code for each interrupt source. + +.MACRO CHECK_EXTERNAL_IO_INTS +_EXT_INT_STRT:PSH R0 + PSH R1 + PSH R2 + PSH R3 + +_EXT_INT_LO: CLR R0 ; R3 will be our pending mask clear reg, + T0X R3 ; so clear it here + + LDA R0, EXT_INT_PEND ; R2 will be our current pending reg, so + T0X R2 ; load it from the hardware here + +_EXT_INT_0: BTT 0 + BRZ _EXT_INT_1 + PROCESS_EXT_ISR + +_EXT_INT_1: BTT 1 + BRZ _EXT_INT_2 + PROCESS_EXT_ISR + +_EXT_INT_2: BTT 2 + BRZ _EXT_INT_3 + PROCESS_EXT_ISR + +_EXT_INT_3: BTT 3 + BRZ _EXT_INT_4 + PROCESS_EXT_ISR + +_EXT_INT_4: BTT 4 + BRZ _EXT_INT_5 + PROCESS_EXT_ISR + +_EXT_INT_5: BTT 5 + BRZ _EXT_INT_6 + PROCESS_EXT_ISR + +_EXT_INT_6: BTT 6 + BRZ _EXT_INT_7 + PROCESS_EXT_ISR + +_EXT_INT_7: BTT 7 + BRZ _EXT_INT_CLR + PROCESS_EXT_ISR + +_EXT_INT_CLR: STA R3, EXT_INT_PEND + + STA R3, EXT_INT_ACK ; pending ints and ack the HW + + POP R3 + POP R2 + POP R1 + POP R0 + RTI +.ENDM + +.MACRO CHECK_EXTERNAL_IO_INTS16 +_EXT_INT_STRT:PSH R0 + PSH R1 + PSH R2 + PSH R3 + +_EXT_INT_LO: CLR R0 ; R3 will be our pending mask clear reg, + T0X R3 ; so clear it here + + LDA R0, EXT_INT16_PEND_L; R2 will be our current pending reg, so + T0X R2 ; load it from the hardware here + +_EXT_INT_0: BTT 0 + BRZ _EXT_INT_1 + PROCESS_EXT_ISR + +_EXT_INT_1: BTT 1 + BRZ _EXT_INT_2 + PROCESS_EXT_ISR + +_EXT_INT_2: BTT 2 + BRZ _EXT_INT_3 + PROCESS_EXT_ISR + +_EXT_INT_3: BTT 3 + BRZ _EXT_INT_4 + PROCESS_EXT_ISR + +_EXT_INT_4: BTT 4 + BRZ _EXT_INT_5 + PROCESS_EXT_ISR + +_EXT_INT_5: BTT 5 + BRZ _EXT_INT_6 + PROCESS_EXT_ISR + +_EXT_INT_6: BTT 6 + BRZ _EXT_INT_7 + PROCESS_EXT_ISR + +_EXT_INT_7: BTT 7 + BRZ _EXT_INT_CLRL + PROCESS_EXT_ISR + +_EXT_INT_CLRL:STA R3, EXT_INT16_PEND_L + +_EXT_INT_HI: CLR R0 + T0X R3 + + LDA R0, EXT_INT16_PEND_H + T0X R2 + +_EXT_INT_8: BTT 0 + BRZ _EXT_INT_9 + PROCESS_EXT_ISR + +_EXT_INT_9: BTT 1 + BRZ _EXT_INT_10 + PROCESS_EXT_ISR + +_EXT_INT_10: BTT 2 + BRZ _EXT_INT_11 + PROCESS_EXT_ISR + +_EXT_INT_11: BTT 3 + BRZ _EXT_INT_12 + PROCESS_EXT_ISR + +_EXT_INT_12: BTT 4 + BRZ _EXT_INT_13 + PROCESS_EXT_ISR + +_EXT_INT_13: BTT 5 + BRZ _EXT_INT_14 + PROCESS_EXT_ISR + +_EXT_INT_14: BTT 6 + BRZ _EXT_INT_15 + PROCESS_EXT_ISR + +_EXT_INT_15: BTT 7 + BRZ _EXT_INT_CLRH + PROCESS_EXT_ISR + +_EXT_INT_CLRH:STA R3, EXT_INT16_PEND_H + +_EXT_ACK_HW: STA R3, EXT_INT16_ACK ; pending ints and ack the HW + + POP R3 + POP R2 + POP R1 + POP R0 + RTI +.ENDM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; ISR/Supervisory Mode Functions - Allows tasks to define up to 5 functions +; that will operate in supervisor mode by calling a soft-int. +; +; Note 1: Due to assembler limitations, it is actually necessary for each task +; to define all 5 sets of these macros, even if not used. These are defined +; in the pattern of TASKx_SPV_FUNCy, where x is the task number and +; y is the function 0-4. +; +; Note 2: Task code for these functions should NOT use RTS or RTI, as this WILL +; corrupt their stacks and likely crash the whole system. These are intended +; for operations that are atomic in nature, or that require supervisor perms +; due to write access (writing flags/messages to other tasks) +; +; Note 3: These functions will run to completion (or hang) regardless of the +; task timer, as interrupts can't pre-empt each other, so caution should be +; used with them. However, both the internal and external interrupt managers +; will latch incoming interrupts while these are running. +;------------------------------------------------------------------------------ + +; CREATE_SUPV_FUNC creates an individual supervisory task function, which is +; referenced in the ISR table. (EXEC_SUPVn is used in the interrupt table) + +.MACRO CREATE_SUPV_FUNC +EXEC_SUPV\@: BACKUP_FULL_CONTEXT + + REINIT_TASK_TABLE_PTR ; Setup R3:R2 to point to the task table + + LDO R2, SUPV_FN\@_ENTRY_HIGH + PSH R0 + + LDO R2, SUPV_FN\@_ENTRY_LOW + PSH R0 + + RTS ; Use RTS to "return" to our jump addr + +_F\@_EXIT: RESTORE_FULL_CONTEXT + RTI +.ENDM + +; CREATE_Fn_FUNCTION_STUB creates an entry point that is referenced in the +; TASK_PARAM_TABLE, and is "RTS JMP'ed" to by the code from CREATE_SUPV_FUNC. +; Because RTS was used to reach the code generated in these blocks, a final +; JMP instruction will return to the calling supervisory function without +; disrupting the stack. (These aren't technically subroutines) + +.MACRO CREATE_F0_FUNCTION_STUB +_F0_EXE_S\@: TASK\@_SUPV_FN0 + JMP _F0_EXIT +.ENDM + +.MACRO CREATE_F1_FUNCTION_STUB +_F1_EXE_S\@: TASK\@_SUPV_FN1 + JMP _F1_EXIT +.ENDM + +.MACRO CREATE_F2_FUNCTION_STUB +_F2_EXE_S\@: TASK\@_SUPV_FN2 + JMP _F2_EXIT +.ENDM + +.MACRO CREATE_F3_FUNCTION_STUB +_F3_EXE_S\@: TASK\@_SUPV_FN3 + JMP _F3_EXIT +.ENDM + +.MACRO CREATE_F4_FUNCTION_STUB +_F4_EXE_S\@: TASK\@_SUPV_FN4 + JMP _F4_EXIT +.ENDM + +; INSTANCE_SUPV_FUNCS creates all 5 supervisory function entry points and a set +; of stub functions for each task and is used to place everything in ROM +.MACRO INSTANCE_SUPV_FUNCS + .REPEAT 5 + CREATE_SUPV_FUNC + .ENDR + + .REPEAT TASK_COUNT + CREATE_F0_FUNCTION_STUB + CREATE_F1_FUNCTION_STUB + CREATE_F2_FUNCTION_STUB + CREATE_F3_FUNCTION_STUB + CREATE_F4_FUNCTION_STUB + .ENDR +.ENDM + +;------------------------------------------------------------------------------ \ No newline at end of file Index: taskmgr/taskmgr_func.s =================================================================== --- taskmgr/taskmgr_func.s (nonexistent) +++ taskmgr/taskmgr_func.s (revision 301) @@ -0,0 +1,93 @@ +; Copyright (c)2022 Jeremy Seth Henry +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution, +; where applicable (as part of a user interface, debugging port, etc.) +; +; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY +; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;------------------------------------------------------------------------------ +; taskmgr_func.s +; +; Program Start, Task Setup, and Core Interrupt Service +; +; Note that the CPU must be in supervisory mode for this code to execute +; properly, which means the I bit MUST be set at startup. This is controlled +; by HDL generics - specifically the supervisor mode enable. +; +; Revision History +; Author Date Change +;---------------- -------- --------------------------------------------------- +; Seth Henry 7/15/22 Initial Release +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; System Bootstrap / Start of ROM +;------------------------------------------------------------------------------ +.ORG BOOT_BLOCK +BOOTSTRAP: JMP INIT_MAIN ; Jump past the pointer block + NOP ; Aligns the data block, but not executed +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Pointer table +;------------------------------------------------------------------------------ + INSTANCE_TASK_POINTERS +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Parameter table +;------------------------------------------------------------------------------ + INSTANCE_TASK_EXPORTS +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; System start +;------------------------------------------------------------------------------ +INIT_MAIN: BNI INIT_MAIN ; Trap in a loop if supervisor mode isn't set + BOOT_SYSTEM +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; RAM Access Fault Shutdown (CALL_PANIC) +;------------------------------------------------------------------------------ +RAM_FAULT: PROCESS_RAM_FAULT +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; Task Switch ISR (CALL_TASK_SW) +;------------------------------------------------------------------------------ +TASK_SW_INT: SWITCH_TASKS +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; External Interrupt Handler ISR +;------------------------------------------------------------------------------ +EXT_INT_MGR: +.IFDEF INTMGR16 + CHECK_EXTERNAL_IO_INTS16 +.ELSE + CHECK_EXTERNAL_IO_INTS +.ENDIF +;------------------------------------------------------------------------------ + +;------------------------------------------------------------------------------ +; ISR Context Function Calls (CALL_SUPV_FN) +;------------------------------------------------------------------------------ + INSTANCE_SUPV_FUNCS +;------------------------------------------------------------------------------

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