URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/open8_urisc/trunk
- from Rev 307 to Rev 308
- ↔ Reverse comparison
Rev 307 → Rev 308
/VHDL/o8_sys_timer_ii.vhd
22,7 → 22,7
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
-- |
-- VHDL Units : o8_sys_timer |
-- Description: Provides an 8-bit microsecond resolution timer for generating |
-- Description: Provides an 24-bit microsecond resolution timer for generating |
-- : periodic interrupts for the Open8 CPU. |
-- |
-- Register Map: |
47,7 → 47,9
-- Seth Henry 04/16/20 Modified to use Open8 bus record |
-- Seth Henry 04/17/20 Altered interval to be a 24-bit counter |
-- Seth Henry 05/18/20 Added write qualification input |
-- Seth Henry 01/18/23 Added microsecond/millisecond generic |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
59,6 → 61,7
|
entity o8_sys_timer_ii is |
generic( |
mSec_Resolution : boolean := FALSE; |
Address : ADDRESS_TYPE |
); |
port( |
101,6 → 104,13
signal Output_Enable : std_logic := '0'; |
signal Timer_Cnt : std_logic_vector(23 downto 0) := x"000000"; |
|
constant MSEC_DELAY : std_logic_vector(9 downto 0) := |
conv_std_logic_vector(1000,10); |
|
signal mSec_Timer : std_logic_vector(9 downto 0) := (others => '0'); |
|
signal Timer_Tick : std_logic := '0'; |
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begin |
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0'; |
107,6 → 117,31
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En; |
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En; |
|
mSec_Resolution_enabled : if( mSec_Resolution )generate |
|
mSec_Tick_proc: process( Clock, Reset ) |
begin |
if( Reset = Reset_Level )then |
mSec_Timer <= (others => '0'); |
Timer_Tick <= '0'; |
elsif( rising_edge(Clock) )then |
mSec_Timer <= mSec_Timer - uSec_Tick; |
Timer_Tick <= '0'; |
if( mSec_Timer = 0 )then |
mSec_Timer <= MSEC_DELAY; |
Timer_Tick <= '1'; |
end if; |
end if; |
end process; |
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end generate; |
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uSec_Resolution_enabled : if( not mSec_Resolution )generate |
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Timer_Tick <= uSec_Tick; |
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end generate; |
|
io_reg: process( Clock, Reset ) |
begin |
if( Reset = Reset_Level )then |
173,7 → 208,7
Interrupt <= '0'; |
elsif( rising_edge(Clock) )then |
Interrupt <= '0'; |
Timer_Cnt <= Timer_Cnt - uSec_Tick; |
Timer_Cnt <= Timer_Cnt - Timer_Tick; |
if( Update_Interval = '1' )then |
Int_Interval <= Req_Interval; |
Timer_Cnt <= Req_Interval; |