URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/open8_urisc
- from Rev 309 to Rev 310
- ↔ Reverse comparison
Rev 309 → Rev 310
/trunk/VHDL/vdsm8.vhd
46,6 → 46,7
Clock : in std_logic; |
Reset : in std_logic; |
DACin : in std_logic_vector(DAC_Width-1 downto 0); |
DACadv : in std_logic := '1'; |
DACout : out std_logic |
); |
end entity; |
153,7 → 154,7
q <= (others => '0'); |
count <= (others => '1'); |
Divisor <= (others => '0'); |
DACin_q <= (others => '0'); |
DACin_q <= (others => '0'); |
PWM_Width <= (others => '0'); |
PWM_Period <= (others => '0'); |
Period_Ctr <= (others => '0'); |
170,7 → 171,7
if( count = DIV_WIDTH )then |
PWM_Width <= Next_Width; |
PWM_Period <= Next_Period; |
DACin_q <= DACin; |
DACin_q <= DACin; |
Divisor <= (others => '0'); |
Divisor(DAC_Width-1 downto 0) <= DACin_q; |
q <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend; |
177,8 → 178,8
count <= (others => '0'); |
end if; |
|
Period_Ctr <= Period_Ctr - 1; |
Width_Ctr <= Width_Ctr - 1; |
Period_Ctr <= Period_Ctr - DACadv; |
Width_Ctr <= Width_Ctr - DACadv; |
|
DACout <= '1'; |
if( Width_Ctr = 0 )then |
194,4 → 195,4
end if; |
end process; |
|
end architecture; |
end architecture; |