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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc
    from Rev 311 to Rev 312
    ↔ Reverse comparison
  •

Rev 311 → Rev 312

/trunk/Documents/CPU Instruction Set.htm
51,7 → 51,7
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312,6 → 312,7
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<x:ActiveSheet>1</x:ActiveSheet>
<x:ProtectStructure>False</x:ProtectStructure>
<x:ProtectWindows>False</x:ProtectWindows>
</x:ExcelWorkbook>
319,7 → 320,7
</head>
 
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<body>
/trunk/Documents/CPU Instruction Set_files/sheet001.htm
1,5 → 1,4
<html xmlns:v="urn:schemas-microsoft-com:vml"
xmlns:o="urn:schemas-microsoft-com:office:office"
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xmlns:x="urn:schemas-microsoft-com:office:excel"
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/trunk/Documents/CPU Instruction Set_files/sheet002.htm
98,7 → 98,7
false, the RSP instruction will reset the stack pointer to
&quot;Stack_Start_Addr&quot; by default. If true, the RSP instruction will
either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0
depending on the status of the PSR_GP4 flag.</td>
depending on the status of the PSR_GP4 (PSR_S) flag.</td>
</tr>
<tr height=80 style='height:60.0pt'>
<td height=80 class=xl108 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
113,8 → 113,8
be incremented by 1. If false, specifying either register in a register pair
will result in normal behavior.</td>
</tr>
<tr height=40 style='height:30.0pt'>
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>BRK_Implements_WAI</td>
<tr height=60 style='height:45.0pt'>
<td height=60 class=xl73 style='height:45.0pt;border-top:none'>BRK_Implements_WAI</td>
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
121,7 → 121,7
true, the BRK instruction will cause the processor to halt as if an INT
instruction was executed, but without triggering an interrupt. This is useful
for pausing the CPU until an interrupt occurs. If false, the BRK instruction
simply causes the CPU to execute 5 NOP cycles.</td>
flushes the pipeline and executes an extended (5-clock) NOP cycle.</td>
</tr>
<tr height=20 style='height:15.0pt'>
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Enable_NMI</td>
137,8 → 137,8
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Prohibits
interrupts from initiating an ISR if the I-bit is set, making ISRs
sequential. This potentially blocks interrupt priority by allowing a lower
level interrupt to block a higher level interrupt. This can be fixed by
clearing the I-bit in interruptable ISRs.</td>
level interrupt to block a higher level interrupt. This can be worked around
by clearing the I-bit in known interruptable ISRs.</td>
</tr>
<tr height=40 style='height:30.0pt'>
<td height=40 class=xl108 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
145,9 → 145,9
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
set, preserves the general purpose flags GP_PSR4 to GP_PSR7 on ISR exit,
allowing them to be persistently set by interrupts. The lower four flag bits
are always restored.</td>
set, preserves the general purpose flags GP_PSR4 (PSR_S) to GP_PSR7 on ISR
exit, allowing them to be persistently set by interrupts. The lower four flag
bits are always restored.</td>
</tr>
<tr height=40 style='height:30.0pt'>
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Supervisor_Mode</td>
182,7 → 182,8
<td class=xl73 style='border-top:none;border-left:none'>8-bit Data</td>
<td class=xl74 style='border-top:none;border-left:none'>x&quot;FF&quot;</td>
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
the initial interrupt mask (note that bit 0 is ignored, as this is the NMI)</td>
the initial interrupt mask (note that bit 0 is ignored if Enable_NMI is set
TRUE)</td>
</tr>
<tr height=20 style='height:15.0pt'>
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
/trunk/VHDL/o8_timer24.vhd
0,0 → 1,196
-- VHDL Units : o8_timer24
-- Description: Provides an 24-bit microsecond resolution timer for generating
-- : periodic interrupts for the Open8 CPU. This timer has a
-- : programmable timebase selector that allows the resolution to
-- : be set at run-time.
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA Req Interval Byte 0 (RW)
-- 0x01 AAAAAAAA Req Interval Byte 1 (RW)
-- 0x02 AAAAAAAA Req Interval Byte 2 (RW)
-- 0x03 CBA----- Control/Status Register (RW)
-- A: Update timer (WR) or pending (RD)
-- B: Timebase (0 = uS / 1 = mS)
-- C: Output Enable
--
-- Notes : Setting the output to 0x000000 OR clearing bit C will disable
-- : the timer.
-- : Update pending is true if bit A is 1, otherwise false
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/17/23 Initial upload (based on sys_timer_ii)
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_timer24 is
generic(
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
end entity;
 
architecture behave of o8_timer24 is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 2) :=
Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic := '0';
 
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Wr_En_d : std_logic;
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Req_Interval : std_logic_vector(23 downto 0) := x"000000";
alias Req_Interval_B0 is Req_Interval( 7 downto 0);
alias Req_Interval_B1 is Req_Interval(15 downto 8);
alias Req_Interval_B2 is Req_Interval(23 downto 16);
 
signal Int_Interval : std_logic_vector(23 downto 0) := x"000000";
 
signal Timebase : std_logic := '0';
signal Update_Interval : std_logic := '0';
signal Update_Pending : std_logic := '0';
signal Output_Enable : std_logic := '0';
signal Output_Qual : std_logic := '0';
 
 
signal Timer_Cnt : std_logic_vector(23 downto 0) := x"000000";
 
constant MSEC_DELAY : std_logic_vector(9 downto 0) :=
conv_std_logic_vector(1000,10);
 
signal mSec_Timer : std_logic_vector(9 downto 0) := (others => '0');
signal mSec_Tick : std_logic := '0';
 
signal Timer_Tick : std_logic := '0';
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
mSec_Tick_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
mSec_Timer <= (others => '0');
mSec_Tick <= '0';
elsif( rising_edge(Clock) )then
mSec_Timer <= mSec_Timer - uSec_Tick;
mSec_Tick <= '0';
if( mSec_Timer = 0 )then
mSec_Timer <= MSEC_DELAY;
mSec_Tick <= '1';
end if;
end if;
end process;
 
Timer_Tick <= mSec_Tick when Timebase = '1' else uSec_Tick;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Req_Interval <= x"000000";
Update_Interval <= '0';
Update_Pending <= '0';
Timebase <= '0';
Output_Enable <= '0';
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
Update_Interval <= '0';
if( Wr_En_q = '1' and Write_Qual = '1' )then
case( Reg_Sel_q )is
when "00" =>
Req_Interval_B0 <= Wr_Data_q;
Update_Pending <= '1';
when "01" =>
Req_Interval_B1 <= Wr_Data_q;
Update_Pending <= '1';
when "10" =>
Req_Interval_B2 <= Wr_Data_q;
Update_Pending <= '1';
when "11" =>
Output_Enable <= Wr_Data_q(7);
Timebase <= Wr_Data_q(6);
Update_Interval <= Wr_Data_q(5);
when others => null;
end case;
end if;
 
if( Update_Interval = '1' )then
Update_Pending <= '0';
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= Req_Interval_B0;
when "01" =>
Rd_Data <= Req_Interval_B1;
when "10" =>
Rd_Data <= Req_Interval_B2;
when "11" =>
Rd_Data <= Output_Enable & Timebase &
Update_Pending & "00000";
when others => null;
end case;
end if;
end if;
end process;
 
Interval_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Output_Qual <= '0';
Int_Interval <= x"000000";
Timer_Cnt <= x"000000";
Interrupt <= '0';
elsif( rising_edge(Clock) )then
Output_Qual <= Output_Enable and or_reduce(Int_Interval);
Interrupt <= '0';
Timer_Cnt <= Timer_Cnt - Timer_Tick;
if( Update_Interval = '1' )then
Int_Interval <= Req_Interval;
Timer_Cnt <= Req_Interval;
elsif( or_reduce(Timer_Cnt) = '0' )then
Timer_Cnt <= Int_Interval;
Interrupt <= Output_Qual;
end if;
end if;
end process;
 
end architecture;

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