OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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Rev 314 → Rev 315

/trunk/VHDL/adc128s022.vhd
0,0 → 1,253
-- Copyright (c)2023 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL units : adc12s022
-- Description: Provides higher-level control of a single ADC128S022 12-bit ADC
-- Note that the base part has a maximum Fsclk of 3.2MHz. Note that to simplify
-- downstream logic, the data is expanded to a 16-bit bus.
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/18/23 Initial Upload
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
entity adc12s022 is
generic(
Clock_Frequency : real;
Reset_Level : std_logic := '1'
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Reinit : in std_logic;
--
RAW_Channel : out std_logic_vector(2 downto 0);
RAW_Data : out std_logic_vector(15 downto 0);
RAW_Valid : out std_logic;
--
Busy_In : in std_logic;
--
SDO : in std_logic;
SDI : out std_logic;
SCLK : out std_logic;
CSn : out std_logic
);
end entity;
 
architecture behave of adc12s022 is
 
-- The ceil_log2 function returns the minimum register width required to
-- hold the supplied integer.
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end function;
 
-- Per the datasheet, the _022 part has a Fsmax of 3.2MHz, which results in
-- a maximum single-channel conversion rate of 200ksps, or maximum
-- multiplexed rate of 25ksps.
constant ADS128S022_FSCLK : real := 3200000.0;
 
constant Clock_Ratio : real :=
((Clock_Frequency + (0.5*ADS128S022_FSCLK)) / ADS128S022_FSCLK);
 
constant Half_Period_Clks : integer := integer(Clock_Ratio * 0.5);
 
type ADC_STATES is ( INIT, IDLE, REQ_SP, SP_WAIT, INC_CH );
signal ADC_State : ADC_STATES := INIT;
 
signal Channel : std_logic_vector(2 downto 0) := "000";
signal Conv_Start : std_logic := '0';
 
signal Data_Out : std_logic_vector(11 downto 0) :=
(others => '0');
signal Valid : std_logic := '0';
 
constant Clk_Div_i : integer := Half_Period_Clks - 1;
constant Clk_Div_Bits : integer := ceil_log2(Clk_Div_i);
constant CLK_DIV_VAL : std_logic_vector(Clk_Div_Bits - 1 downto 0) :=
conv_std_logic_vector(Clk_Div_i,Clk_Div_Bits);
signal HT_Cntr : std_logic_vector(Clk_Div_Bits - 1 downto 0);
signal HT_Tick : std_logic := '0';
 
type SPI_STATES is ( IDLE, ALIGN, CSn_START, CLK_SETUP, CLK_HOLD, CSn_END );
signal spi_state : SPI_STATES;
 
signal spi_wr_buffer : std_logic_vector(15 downto 0) := x"0000";
signal spi_rd_buffer : std_logic_vector(15 downto 0) := x"0000";
 
signal bit_cntr : std_logic_vector(3 downto 0) := x"0";
 
begin
 
ADC_Control_FSM_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
ADC_State <= INIT;
Channel <= (others => '0');
Conv_Start <= '0';
 
RAW_Channel <= (others => '0');
RAW_Data <= (others => '0');
RAW_Valid <= '0';
 
elsif( rising_edge(Clock) )then
Conv_Start <= '0';
 
RAW_Channel <= (others => '0');
RAW_Data <= (others => '0');
RAW_Valid <= '0';
 
case ADC_State is
when INIT =>
Channel <= (others => '0');
ADC_State <= IDLE;
 
when IDLE =>
if( Reinit = '1' )then
ADC_State <= INIT;
elsif( Busy_In = '0' )then
ADC_State <= REQ_SP;
end if;
 
when REQ_SP =>
Conv_Start <= '1';
ADC_State <= SP_WAIT;
 
when SP_WAIT =>
if( Valid = '1' )then
RAW_Channel <= Channel;
RAW_Data <= "0000" & Data_Out;
RAW_Valid <= '1';
ADC_State <= INC_CH;
end if;
 
when INC_CH =>
Channel <= Channel + 1;
ADC_State <= IDLE;
 
when others =>
null;
end case;
end if;
end process;
 
 
SPI_IO_FSM: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
spi_state <= IDLE;
spi_wr_buffer <= (others => '0');
spi_rd_buffer <= (others => '0');
bit_cntr <= (others => '0');
 
 
HT_Cntr <= (others => '0');
HT_Tick <= '0';
 
SDI <= '0';
SCLK <= '0';
CSn <= '1';
 
Data_Out <= (others => '0');
Valid <= '0';
elsif( rising_edge(Clock) )then
 
HT_Cntr <= HT_Cntr - 1;
HT_Tick <= '0';
if( HT_Cntr = 0 )then
HT_Cntr <= CLK_DIV_VAL;
HT_Tick <= '1';
end if;
 
SCLK <= '1';
SDI <= '1';
 
Valid <= '0';
 
case( spi_state )is
when IDLE =>
CSn <= '1';
bit_cntr <= x"F";
if( Conv_Start = '1' )then
spi_wr_buffer <= "00" & Channel & "00000000000";
spi_state <= ALIGN;
end if;
 
when ALIGN =>
if( HT_Tick = '1' )then
spi_state <= CSn_START;
end if;
 
when CSn_START =>
CSn <= '0';
if( HT_Tick = '1' )then
spi_state <= CLK_SETUP;
end if;
 
when CLK_SETUP =>
SCLK <= '0';
SDI <= spi_wr_buffer(conv_integer(bit_cntr));
CSn <= '0';
if( HT_Tick = '1' )then
spi_rd_buffer <= spi_rd_buffer(14 downto 0) & SDO;
spi_state <= CLK_HOLD;
end if;
 
when CLK_HOLD =>
SDI <= spi_wr_buffer(conv_integer(bit_cntr));
if( HT_Tick = '1' )then
bit_cntr <= bit_cntr - 1;
spi_state <= CLK_SETUP;
if( bit_cntr = 0 )then
spi_state <= CSn_END;
end if;
end if;
 
when CSn_END =>
if( HT_Tick = '1' )then
Data_Out <= spi_rd_buffer(11 downto 0);
Valid <= '1';
spi_state <= IDLE;
end if;
 
when others =>
null;
end case;
 
end if;
end process;
 
end architecture;
/trunk/VHDL/adc_buffer.vhd
0,0 → 1,197
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: adc_buffer.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 20.1.0 Build 711 06/05/2020 SJ Lite Edition
-- ************************************************************
 
 
--Copyright (C) 2020 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and any partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details, at
--https://fpgasoftware.intel.com/eula.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
 
ENTITY adc_buffer IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END adc_buffer;
 
 
ARCHITECTURE SYN OF adc_buffer IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
 
BEGIN
q <= sub_wire0(7 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 8,
numwords_b => 16,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => 3,
widthad_b => 4,
width_a => 16,
width_b => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
address_b => rdaddress,
clock0 => clock,
data_a => data,
wren_a => wren,
q_b => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "128"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 3 0 INPUT NODEFVAL "wraddress[2..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 3 0 wraddress 0 0 3 0
-- Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_buffer.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_buffer.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_buffer.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_buffer.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_buffer_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/VHDL/adc_monitor.vhd
0,0 → 1,157
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: adc_monitor.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 20.1.0 Build 711 06/05/2020 SJ Lite Edition
-- ************************************************************
 
 
--Copyright (C) 2020 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and any partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details, at
--https://fpgasoftware.intel.com/eula.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
 
ENTITY adc_monitor IS
PORT
(
address : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END adc_monitor;
 
 
ARCHITECTURE SYN OF adc_monitor IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
 
BEGIN
q <= sub_wire0(15 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone IV GX",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ABUF",
lpm_type => "altsyncram",
numwords_a => 8,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 3,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "ABUF"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=ABUF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_monitor.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_monitor.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_monitor.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_monitor.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL adc_monitor_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/VHDL/mavg_8ch_16b_64d.vhd
0,0 → 1,199
-- Copyright (c)2023 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL units : mavg_8ch_16b_64d
-- Description: 8-channel moving average calculation for 16-bit unsigned data
-- Accumulator depth is 64 elements, using 1 block RAM.
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/18/23 Initial Upload
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
 
entity mavg_8ch_16b_64d is
generic(
Reset_Level : std_logic := '1'
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
RAW_Channel : in std_logic_vector(2 downto 0);
RAW_Data : in std_logic_vector(15 downto 0);
RAW_Valid : in std_logic;
--
Busy_Out : out std_logic;
--
AVG_Channel : out std_logic_vector(2 downto 0);
AVG_Out : out std_logic_vector(15 downto 0);
AVG_Valid : out std_logic;
--
Busy_In : in std_logic
);
end entity;
 
architecture behave of mavg_8ch_16b_64d is
 
type AVG_CTL_STATES is (INIT, CLR_BUFF, IDLE, BUSY_WAIT, RD_LAST,
ADV_PTR, CALC_NEXT, WR_NEW);
signal AVG_Ctl : AVG_CTL_STATES := INIT;
 
signal CH_Select : std_logic_vector(2 downto 0);
signal Data_New : std_logic_vector(15 downto 0) := (others => '0');
 
signal RAM_Wr_Addr : std_logic_vector(8 downto 0) := (others => '0');
alias RAM_Wr_Chan is RAM_Wr_Addr(8 downto 6);
alias RAM_Wr_Ptr is RAM_Wr_Addr(5 downto 0);
 
signal RAM_Wr_Data : std_logic_vector(15 downto 0) := (others => '0');
 
signal RAM_Wr_En : std_logic := '0';
 
signal RAM_Rd_Addr : std_logic_vector(8 downto 0) := (others => '0');
alias RAM_Rd_Chan is RAM_Rd_Addr(8 downto 6);
alias RAM_Rd_Ptr is RAM_Rd_Addr(5 downto 0);
 
signal RAM_Rd_Data : std_logic_vector(15 downto 0) := (others => '0');
alias Data_Old is RAM_Rd_Data;
 
type PTR_ARRAY is array (0 to 7) of std_logic_vector(5 downto 0);
signal SP0_Pointers : PTR_ARRAY;
signal SPN_Pointers : PTR_ARRAY;
 
-- Accumulator width is bus_size (16) + log depth (6)
type ACCUM_ARRAY is array (0 to 7) of unsigned(21 downto 0);
signal Accumulators : ACCUM_ARRAY;
 
begin
 
MAVG_Control_proc: process( Clock, Reset )
variable i : integer := 0;
begin
if( Reset = Reset_Level )then
AVG_Ctl <= INIT;
 
CH_Select <= (others => '0');
Data_New <= (others => '0');
 
Busy_Out <= '0';
 
for i in 0 to 7 loop
SP0_Pointers(i) <= (others => '1');
SPN_Pointers(i) <= (others => '0');
Accumulators(i) <= (others => '0');
end loop;
 
RAM_Wr_Addr <= (others => '0');
RAM_Wr_Data <= (others => '0');
RAM_Wr_En <= '0';
RAM_Rd_Addr <= (others => '0');
 
AVG_Channel <= (others => '0');
AVG_Out <= (others => '0');
AVG_Valid <= '0';
 
elsif( rising_edge(Clock) )then
 
RAM_Wr_En <= '0';
 
Busy_Out <= '1';
AVG_Valid <= '0';
 
i := conv_integer(unsigned(CH_Select));
 
case( AVG_Ctl )is
when INIT =>
RAM_Wr_Addr <= (others => '0');
RAM_Wr_Data <= (others => '0');
AVG_Ctl <= CLR_BUFF;
 
when CLR_BUFF =>
RAM_Wr_Addr <= RAM_Wr_Addr + 1;
RAM_Wr_En <= '1';
if( and_reduce(RAM_Wr_Addr) = '1' )then
AVG_Ctl <= IDLE;
end if;
 
when IDLE =>
Busy_Out <= '0';
if( RAW_Valid = '1' )then
Data_New <= RAW_Data;
CH_Select <= RAW_Channel;
AVG_Ctl <= BUSY_WAIT;
end if;
 
when BUSY_WAIT =>
if( Busy_In = '0' )then
AVG_Ctl <= RD_LAST;
end if;
 
when RD_LAST =>
RAM_Rd_Chan <= CH_Select;
RAM_Rd_Ptr <= SPN_Pointers(i);
AVG_Ctl <= ADV_PTR;
 
when ADV_PTR =>
SP0_Pointers(i) <= SP0_Pointers(i) + 1;
AVG_Ctl <= CALC_NEXT;
 
when CALC_NEXT =>
Accumulators(i) <= Accumulators(i) +
unsigned( Data_New ) -
unsigned( Data_Old );
AVG_Ctl <= WR_NEW;
 
when WR_NEW =>
RAM_Wr_Chan <= CH_Select;
RAM_Wr_Ptr <= SP0_Pointers(i);
RAM_Wr_Data <= Data_New;
RAM_Wr_En <= '1';
SPN_Pointers(i) <= SP0_Pointers(i) + 1;
AVG_Channel <= CH_Select;
AVG_Out <= std_logic_vector(Accumulators(i)(21 downto 6));
AVG_Valid <= '1';
AVG_Ctl <= IDLE;
 
when others =>
null;
end case;
 
end if;
end process;
 
U_BUFF : entity work.mavg_buffer_16b
port map(
clock => Clock,
data => RAM_Wr_Data,
rdaddress => RAM_Rd_Addr,
wraddress => RAM_Wr_Addr,
wren => RAM_Wr_En,
q => RAM_Rd_Data
);
 
end architecture;
/trunk/VHDL/mavg_buffer_16b.vhd
0,0 → 1,196
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
 
-- ============================================================
-- File Name: mavg_buffer_16b.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
 
 
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
 
ENTITY mavg_buffer_16b IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END mavg_buffer_16b;
 
 
ARCHITECTURE SYN OF mavg_buffer_16b IS
 
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
 
BEGIN
q <= sub_wire0(15 DOWNTO 0);
 
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 512,
numwords_b => 512,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => 9,
widthad_b => 9,
width_a => 16,
width_b => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => clock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
q_b => sub_wire0
);
 
 
 
END SYN;
 
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "7168"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL "rdaddress[8..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
-- Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL mavg_buffer_16b.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mavg_buffer_16b.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mavg_buffer_16b.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mavg_buffer_16b.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mavg_buffer_16b_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
/trunk/VHDL/o8_de0_nano_adc_if.vhd
0,0 → 1,209
-- Copyright (c)2023 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL units : o8_de0_nano_adc_if
-- Description: Stitches together all of the components needed to supply data
-- from the DE0 nano's on-board ADC. Provides an interrupt output
-- when the 8th (last) input is written to the buffer.
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA AFE 0, Channel 0, Lower Byte RO
-- 0x01 AAAAAAAA AFE 0, Channel 0, Upper Byte RO
-- 0x02 AAAAAAAA AFE 0, Channel 1, Lower Byte RO
-- 0x03 AAAAAAAA AFE 0, Channel 1, Upper Byte RO
-- 0x04 AAAAAAAA AFE 0, Channel 2, Lower Byte RO
-- 0x05 AAAAAAAA AFE 0, Channel 2, Upper Byte RO
-- 0x06 AAAAAAAA AFE 0, Channel 3, Lower Byte RO
-- 0x07 AAAAAAAA AFE 0, Channel 3, Upper Byte RO
-- 0x08 AAAAAAAA AFE 0, Channel 4, Lower Byte RO
-- 0x09 AAAAAAAA AFE 0, Channel 4, Upper Byte RO
-- 0x0A AAAAAAAA AFE 0, Channel 5, Lower Byte RO
-- 0x0B AAAAAAAA AFE 0, Channel 5, Upper Byte RO
-- 0x0C AAAAAAAA AFE 0, Channel 6, Lower Byte RO
-- 0x0D AAAAAAAA AFE 0, Channel 6, Upper Byte RO
-- 0x0E AAAAAAAA AFE 0, Channel 7, Lower Byte RO
-- 0x0F AAAAAAAA AFE 0, Channel 7, Upper Byte RO
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/18/23 Initial Upload
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library work;
use work.open8_pkg.all;
use work.open8_cfg.all;
 
entity o8_de0_nano_adc_if is
generic(
Address : ADDRESS_TYPE
);
port(
-- Bus IF Interface
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
-- ADC IF
ADC_SDO : in std_logic;
ADC_SDI : out std_logic;
ADC_SCLK : out std_logic;
ADC_CSn : out std_logic
);
end entity;
 
architecture behave of o8_de0_nano_adc_if is
 
-- Bus Interface Signals
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
signal Reinit : std_logic := '0';
 
signal RAW_Channel : std_logic_vector(2 downto 0) := (others => '0');
signal RAW_Data : std_logic_vector(15 downto 0) := (others => '0');
signal RAW_Valid : std_logic := '0';
 
signal AVG_Busy : std_logic := '0';
 
signal AVG_Channel : std_logic_vector(2 downto 0) := (others => '0');
signal AVG_Data : std_logic_vector(15 downto 0) := (others => '0');
signal AVG_Valid : std_logic := '0';
 
alias Buf_Wr_Ptr is AVG_Channel;
alias Buf_Wr_Data is AVG_Data;
alias Buf_Wr_Valid is AVG_Valid;
 
alias Buf_Rd_Ptr is Open8_Bus.Address(3 downto 0);
signal Buf_Rd_Data : std_logic_vector(7 downto 0) := (others => '0');
 
constant LAST_ADDR : std_logic_vector(2 downto 0) := (others => '1');
signal Last_Sample : std_logic := '0';
 
constant User_Addr : std_logic_vector(15 downto 4) :=
Address(15 downto 4);
alias Comp_Addr is Open8_Bus.Address(15 downto 4);
 
signal Addr_Match : std_logic := '0';
signal Rd_En : std_logic := '0';
 
begin
 
-------------------------------------------------------------------------------
-- ADC0 - Interface
-------------------------------------------------------------------------------
 
U_ADC0 : entity work.adc12s022
generic map(
Clock_Frequency => Clock_Frequency,
Reset_Level => Reset_Level
)
port map(
Clock => Clock,
Reset => Reset,
--
Reinit => Reinit,
--
RAW_Channel => RAW_Channel,
RAW_Data => RAW_Data,
RAW_Valid => RAW_Valid,
--
Busy_In => AVG_Busy,
--
SDO => ADC_SDO,
SDI => ADC_SDI,
SCLK => ADC_SCLK,
CSn => ADC_CSn
);
 
U_AVG0 : entity work.mavg_8ch_16b_64d
generic map(
Reset_Level => Reset_Level
)
port map(
Clock => Clock,
Reset => Reset,
--
RAW_Channel => RAW_Channel,
RAW_Data => RAW_Data,
RAW_Valid => RAW_Valid,
--
Busy_Out => AVG_Busy,
--
AVG_Channel => AVG_Channel,
AVG_Out => AVG_Data,
AVG_Valid => AVG_Valid,
--
Busy_In => '0'
);
 
-------------------------------------------------------------------------------
-- Buffer Storage
-------------------------------------------------------------------------------
 
U_DBUF : entity work.adc_buffer
port map(
clock => Clock,
data => Buf_Wr_Data,
rdaddress => Buf_Rd_Ptr,
wraddress => Buf_Wr_Ptr,
wren => Buf_Wr_Valid,
q => Buf_Rd_Data
);
 
U_DMON : entity work.adc_monitor
port map(
address => Buf_Wr_Ptr,
clock => Clock,
data => Buf_Wr_Data,
wren => Buf_Wr_Valid,
q => open
);
 
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
'0';
 
Last_Sample <= Buf_Wr_Valid when Buf_Wr_Ptr = LAST_ADDR else '0';
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
Interrupt <= '0';
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
Interrupt <= Last_Sample;
Rd_En <= Addr_Match;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
Rd_Data <= Buf_Rd_Data;
end if;
end if;
end process;
 
end architecture;

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