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Rev 19 → Rev 20

/openarty/trunk/rtl/eqspiflash.v
63,7 → 63,8
// Attempted reads before buffer is full will stall bus until
// buffer is read. Writes act like the asynch-Read-ID command,
// and will cause the controller to read the buffer.
// 13.-14. Unused, mapped to Asynch-read-ID
// 13. Reset Enable
// 14. Reset Memory
// 15. OTP control word
// Write zero to permanently lock OTP
// Read to determine if OTP is permanently locked
178,7 → 179,7
bus_pipewr, bus_endwr, bus_ctreq, bus_idreq,
bus_other_req,
// Live parameters
w_xip, w_quad, w_idloaded;
w_xip, w_quad, w_idloaded, w_leave_xip;
reg bus_wip;
qspibus preproc(i_clk_200mhz, i_rst,
i_wb_cyc, i_wb_data_stb, i_wb_ctrl_stb,
218,7 → 219,7
rd_spi_spd, rd_spi_dir, rd_spi_recycle,
spi_out, spi_valid,
spi_busy, spi_stopped, rd_data_ack, rd_data,
w_quad, w_xip);
w_quad, w_xip, w_leave_xip);
 
//
// Write/Erase flash module
268,12 → 269,12
wire [1:0] ct_spi_len;
//
ctrlspi ctproc(i_clk_200mhz,
bus_ctreq, bus_wr, bus_addr[2:0], bus_data, bus_sector,
bus_ctreq, bus_wr, bus_addr[3:0], bus_data, bus_sector,
ct_qspi_req, ct_grant,
ct_spi_wr, ct_spi_hold, ct_spi_word, ct_spi_len,
ct_spi_spd, ct_spi_dir,
spi_out, spi_valid, spi_busy, spi_stopped,
ct_ack, ct_data_ack, ct_data, w_xip, w_quad);
ct_ack, ct_data_ack, ct_data, w_leave_xip, w_xip, w_quad);
assign ct_spi_hold = 1'b0;
assign ct_spi_spd = 1'b0;
 
529,14 → 530,14
5'h5: lcl_ctreq <= 1'b1;
5'h6: lcl_ctreq <= 1'b1;
5'h7: lcl_ctreq <= 1'b1;
5'h8: o_idreq <= 1'b1; // ID[0]
5'h9: o_idreq <= 1'b1; // ID[1]
5'ha: o_idreq <= 1'b1; // ID[2]
5'hb: o_idreq <= 1'b1; // ID[3]
5'hc: o_idreq <= 1'b1; // ID[4]
5'hd: o_idreq <= 1'b1; //
5'he: o_idreq <= 1'b1;
5'hf: o_idreq <= 1'b1; // Program OTP register
5'h8: o_idreq <= 1'b1; // ID[0]
5'h9: o_idreq <= 1'b1; // ID[1]
5'ha: o_idreq <= 1'b1; // ID[2]
5'hb: o_idreq <= 1'b1; // ID[3]
5'hc: o_idreq <= 1'b1; // ID[4]
5'hd: lcl_ctreq <= 1'b1; //
5'he: lcl_ctreq <= 1'b1;
5'hf: o_idreq <= 1'b1; // Program OTP register
default: begin o_idreq <= 1'b1; end
endcase
end else if (i_ctrl_stb)
581,6 → 582,7
wire new_req;
assign new_req = (pending)&&(~last_pending);
 
initial esector = 15'h00;
initial o_wrreq = 1'b0;
initial o_erreq = 1'b0;
initial wp_err = 1'b0;
612,9 → 614,9
begin
esector[13:0] <= { o_data[23:14], 4'h0 };
wp <= (o_data[30])&&(new_req)||(wp)&&(~new_req);
esector[14] <= o_data[28]; // Subsector
if (o_data[28])
begin
esector[14] <= o_data[28];
esector[3:0] <= o_data[13:10];
end
end
701,7 → 703,7
o_spi_wr, o_spi_hold, o_spi_word, o_spi_len,
o_spi_spd, o_spi_dir, o_spi_recycle,
i_spi_data, i_spi_valid, i_spi_busy, i_spi_stopped,
o_data_ack, o_data, i_quad, i_xip);
o_data_ack, o_data, i_quad, i_xip, o_leave_xip);
input i_clk;
input i_readreq, i_piperd, i_other_req;
input [21:0] i_addr;
717,6 → 719,7
output reg o_data_ack;
output reg [31:0] o_data;
input i_quad, i_xip;
output wire o_leave_xip;
 
reg accepted;
initial accepted = 1'b0;
807,7 → 810,7
o_qspi_req <= 1'b1;
o_spi_wr <= 1'b1;
o_spi_dir <= 1'b0; // Write the address
o_spi_spd <= 1'b1; // High speed
o_spi_spd <= 1'b0;
o_spi_word[31:0] <= { i_addr, 2'b00, 8'h00 };
o_spi_len <= 2'b10; // 24 bits, High speed, 6 clocks
if (accepted)
830,7 → 833,7
o_spi_word <= { i_addr, 2'b00, 8'h00 };
o_spi_wr <= 1'b0;
o_spi_dir <= 1'b0; // Write to SPI
o_spi_spd <= 1'b1; // High speed
o_spi_spd <= 1'b0;
o_spi_len <= 2'b11;
r_leave_xip <= i_other_req;
r_xip <= (~i_other_req);
868,6 → 871,7
end
 
assign o_spi_hold = 1'b0;
assign o_leave_xip = r_leave_xip;
 
endmodule
 
1119,12 → 1123,13
o_spi_spd, o_spi_dir,
i_spi_data, i_spi_valid, i_spi_busy,
i_spi_stopped,
o_bus_ack, o_data_ack, o_data, o_xip, o_quad);
o_bus_ack, o_data_ack, o_data,
i_leave_xip, o_xip, o_quad);
input i_clk;
// From the WB bus controller
input i_req;
input i_wr;
input [2:0] i_addr;
input [3:0] i_addr;
input [31:0] i_data;
input [21:0] i_sector_address;
// To/from the arbiter
1144,6 → 1149,7
output reg o_bus_ack, o_data_ack;
output reg [31:0] o_data;
// Configuration items that we may have configured.
input wire i_leave_xip;
output reg o_xip;
output wire o_quad;
 
1181,13 → 1187,13
ctcmd_len <= 2'b00; // 8bit command (for all but Lock regs)
r_ctdat_len <= 1'b0; // 8bit data (read or write)
ctdat_wr <= i_wr;
casez({ i_addr[2:0], i_wr, i_data[30] })
5'b00010: begin // Write Disable
casez({ i_addr[3:0], i_wr, i_data[30] })
6'b000010: begin // Write Disable
ctcmd_word[31:24] <= 8'h04;
ctdat_skip <= 1'b1;
ctbus_ack <= 1'b0;
end
5'b00011: begin // Write enable
6'b000011: begin // Write enable
ctcmd_word[31:24] <= 8'h06;
ctdat_skip <= 1'b1;
ctbus_ack <= 1'b0;
1194,7 → 1200,7
end
// 4'b0010?: begin // Read Status register
// Moved to defaults section
5'b0011?: begin // Write Status register (Requires WEL)
6'b00011?: begin // Write Status register (Requires WEL)
ctcmd_word[31:24] <= 8'h01;
`ifdef CT_SAFE
ctdat_word <= { 6'h00, i_data[1:0], 24'h00 };
1202,11 → 1208,11
ctdat_word <= { i_data[7:0], 24'h00 };
`endif
end
5'b0100?: begin // Read NV-Config register (two bytes)
6'b00100?: begin // Read NV-Config register (two bytes)
ctcmd_word[31:24] <= 8'hB5;
r_ctdat_len <= 1'b1; // 16-bit data
end
5'b0101?: begin // Write NV-Config reg (2 bytes, Requires WEL)
6'b00101?: begin // Write NV-Config reg (2 bytes, Requires WEL)
ctcmd_word[31:24] <= 8'hB1;
r_ctdat_len <= 1'b1; // 16-bit data
`ifdef CT_SAFE
1215,23 → 1221,23
ctdat_word <= { i_data[15:0], 16'h00 };
`endif
end
5'b0110?: begin // Read V-Config register
6'b00110?: begin // Read V-Config register
ctcmd_word[31:24] <= 8'h85;
end
5'b0111?: begin // Write V-Config register (Requires WEL)
6'b00111?: begin // Write V-Config register (Requires WEL)
ctcmd_word[31:24] <= 8'h81;
r_ctdat_len <= 1'b0; // 8-bit data
`ifdef CT_SAFE
ctdat_word <= { 4'h8, i_data[3:2], 2'b11, 24'h00 };
`else
// `ifdef CT_SAFE
// ctdat_word <= { 4'h8, i_data[3:2], 2'b11, 24'h00 };
// `else
ctdat_word <= { i_data[7:0], 24'h00 };
`endif
o_xip <= i_data[3];
// `endif
o_xip <= ~i_data[3];
end
5'b1000?: begin // Read EV-Config register
6'b01000?: begin // Read EV-Config register
ctcmd_word[31:24] <= 8'h65;
end
5'b1001?: begin // Write EV-Config register (Requires WEL)
6'b01001?: begin // Write EV-Config register (Requires WEL)
ctcmd_word[31:24] <= 8'h61;
// o_quad <= (~i_data[7]);
`ifdef CT_SAFE
1240,24 → 1246,32
ctdat_word <= { i_data[7:0], 24'h00 };
`endif
end
5'b1010?: begin // Read Lock register
6'b01010?: begin // Read Lock register
ctcmd_word[31:0] <= { 8'he8, i_sector_address, 2'b00 };
ctcmd_len <= 2'b11;
ctdat_wr <= 1'b0; // Read, not write
end
5'b1011?: begin // Write Lock register (Requires WEL)
6'b01011?: begin // Write Lock register (Requires WEL)
ctcmd_word[31:0] <= { 8'he5, i_sector_address, 2'b00 };
ctcmd_len <= 2'b11;
ctdat_wr <= 1'b1; // Write
end
5'b1100?: begin // Read Flag Status register
6'b01100?: begin // Read Flag Status register
ctcmd_word[31:24] <= 8'h70;
ctdat_wr <= 1'b0; // Read, not write
end
5'b1101?: begin // Write/Clear Flag Status register (No WEL required)
6'b01101?: begin // Write/Clear Flag Status register (No WEL required)
ctcmd_word[31:24] <= 8'h50;
ctdat_skip <= 1'b1;
end
6'b11011?: begin // RESET_ENABLE (when written to)
ctcmd_word[31:24] <= 8'h66;
ctdat_skip <= 1'b1;
end
6'b11101?: begin // RESET_MEMORY (when written to)
ctcmd_word[31:24] <= 8'h99;
ctdat_skip <= 1'b1;
end
default: begin // Default to reading the status register
ctcmd_word[31:24] <= 8'h05;
ctdat_wr <= 1'b0; // Read, not write
1264,7 → 1278,8
r_ctdat_len <= 1'b0; // 8-bit data
end
endcase
end
end else if (i_leave_xip)
o_xip <= 1'b0;
 
assign o_quad = 1'b1;
 

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