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URL https://opencores.org/ocsvn/openarty/openarty/trunk

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Rev 22 → Rev 23

/openarty/trunk/arty.xdc
9,44 → 9,69
 
## Clock signal
 
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { i_clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { i_clk_100mhz }];
set_property PACKAGE_PIN E3 [get_ports i_clk_100mhz]
set_property IOSTANDARD LVCMOS33 [get_ports i_clk_100mhz]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk_100mhz]
 
##Switches
 
set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
set_property PACKAGE_PIN A8 [get_ports {i_sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i_sw[0]}]
set_property PACKAGE_PIN C11 [get_ports {i_sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i_sw[1]}]
set_property PACKAGE_PIN C10 [get_ports {i_sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i_sw[2]}]
set_property PACKAGE_PIN A10 [get_ports {i_sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i_sw[3]}]
 
##RGB LEDs
 
set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led0[0] }]; #IO_L18N_T2_35 Sch=led0_b
set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led0[1] }]; #IO_L19N_T3_VREF_35 Sch=led0_g
set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led0[2] }]; #IO_L19P_T3_35 Sch=led0_r
set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led1[0] }]; #IO_L20P_T3_35 Sch=led1_b
set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led1[1] }]; #IO_L21P_T3_DQS_35 Sch=led1_g
set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led1[2] }]; #IO_L20N_T3_35 Sch=led1_r
set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led2[0] }]; #IO_L21N_T3_DQS_35 Sch=led2_b
set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led2[1] }]; #IO_L22N_T3_35 Sch=led2_g
set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led2[2] }]; #IO_L22P_T3_35 Sch=led2_r
set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led3[0] }]; #IO_L23P_T3_35 Sch=led3_b
set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led3[1] }]; #IO_L24P_T3_35 Sch=led3_g
set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led3[2] }]; #IO_L23N_T3_35 Sch=led3_r
set_property PACKAGE_PIN E1 [get_ports {o_clr_led0[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led0[0]}]
set_property PACKAGE_PIN F6 [get_ports {o_clr_led0[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led0[1]}]
set_property PACKAGE_PIN G6 [get_ports {o_clr_led0[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led0[2]}]
set_property PACKAGE_PIN G4 [get_ports {o_clr_led1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led1[0]}]
set_property PACKAGE_PIN J4 [get_ports {o_clr_led1[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led1[1]}]
set_property PACKAGE_PIN G3 [get_ports {o_clr_led1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led1[2]}]
set_property PACKAGE_PIN H4 [get_ports {o_clr_led2[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led2[0]}]
set_property PACKAGE_PIN J2 [get_ports {o_clr_led2[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led2[1]}]
set_property PACKAGE_PIN J3 [get_ports {o_clr_led2[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led2[2]}]
set_property PACKAGE_PIN K2 [get_ports {o_clr_led3[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led3[0]}]
set_property PACKAGE_PIN H6 [get_ports {o_clr_led3[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led3[1]}]
set_property PACKAGE_PIN K1 [get_ports {o_clr_led3[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_clr_led3[2]}]
 
##LEDs
 
set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }]; #IO_L24N_T3_35 Sch=led[4]
set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_25_35 Sch=led[5]
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
set_property PACKAGE_PIN H5 [get_ports {o_led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_led[0]}]
set_property PACKAGE_PIN J5 [get_ports {o_led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_led[1]}]
set_property PACKAGE_PIN T9 [get_ports {o_led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_led[2]}]
set_property PACKAGE_PIN T10 [get_ports {o_led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {o_led[3]}]
 
##Buttons
 
set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { i_btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { i_btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { i_btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { i_btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
set_property PACKAGE_PIN D9 [get_ports {i_btn[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i_btn[0]}]
set_property PACKAGE_PIN C9 [get_ports {i_btn[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i_btn[1]}]
set_property PACKAGE_PIN B9 [get_ports {i_btn[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i_btn[2]}]
set_property PACKAGE_PIN B8 [get_ports {i_btn[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {i_btn[3]}]
 
##Pmod Header JA: PModCLS (bottom)
 
61,45 → 86,70
 
##Pmod Header JB: OLEDrgb
 
set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { o_oled_cs_n }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { o_oled_mosi }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
set_property PACKAGE_PIN E15 [get_ports o_oled_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports o_oled_cs_n]
set_property PACKAGE_PIN E16 [get_ports o_oled_mosi]
set_property IOSTANDARD LVCMOS33 [get_ports o_oled_mosi]
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { i_oled_nc }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { o_oled_sck }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { o_oled_dcn }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { o_oled_reset_n }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { o_oled_vccen }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { o_oled_pmoden }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
set_property PACKAGE_PIN C15 [get_ports o_oled_sck]
set_property IOSTANDARD LVCMOS33 [get_ports o_oled_sck]
set_property PACKAGE_PIN J17 [get_ports o_oled_dcn]
set_property IOSTANDARD LVCMOS33 [get_ports o_oled_dcn]
set_property PACKAGE_PIN J18 [get_ports o_oled_reset_n]
set_property IOSTANDARD LVCMOS33 [get_ports o_oled_reset_n]
set_property PACKAGE_PIN K15 [get_ports o_oled_vccen]
set_property IOSTANDARD LVCMOS33 [get_ports o_oled_vccen]
set_property PACKAGE_PIN J15 [get_ports o_oled_pmoden]
set_property IOSTANDARD LVCMOS33 [get_ports o_oled_pmoden]
 
##Pmod Header JC: GPS (top), UART (bottom)
 
set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { i_gps_3df }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { o_gps_tx }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { i_gps_rx }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { i_gps_pps }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { i_aux_rts }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { o_aux_tx }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { i_aux_rx }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { o_aux_cts }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
set_property PACKAGE_PIN U12 [get_ports i_gps_3df]
set_property IOSTANDARD LVCMOS33 [get_ports i_gps_3df]
set_property PACKAGE_PIN V12 [get_ports o_gps_tx]
set_property IOSTANDARD LVCMOS33 [get_ports o_gps_tx]
set_property PACKAGE_PIN V10 [get_ports i_gps_rx]
set_property IOSTANDARD LVCMOS33 [get_ports i_gps_rx]
set_property PACKAGE_PIN V11 [get_ports i_gps_pps]
set_property IOSTANDARD LVCMOS33 [get_ports i_gps_pps]
set_property PACKAGE_PIN U14 [get_ports i_aux_rts]
set_property IOSTANDARD LVCMOS33 [get_ports i_aux_rts]
set_property PACKAGE_PIN V14 [get_ports o_aux_tx]
set_property IOSTANDARD LVCMOS33 [get_ports o_aux_tx]
set_property PACKAGE_PIN T13 [get_ports i_aux_rx]
set_property IOSTANDARD LVCMOS33 [get_ports i_aux_rx]
set_property PACKAGE_PIN U13 [get_ports o_aux_cts]
set_property IOSTANDARD LVCMOS33 [get_ports o_aux_cts]
 
##Pmod Header JD: SD-Card
 
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { io_sd[3] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { io_sd_cmd }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { io_sd[0] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { o_sd_sck }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { io_sd[1] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { io_sd[2] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { i_sd_cs }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { i_sd_wp }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
set_property PACKAGE_PIN D4 [get_ports {io_sd[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_sd[3]}]
set_property PACKAGE_PIN D3 [get_ports io_sd_cmd]
set_property IOSTANDARD LVCMOS33 [get_ports io_sd_cmd]
set_property PACKAGE_PIN F4 [get_ports {io_sd[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_sd[0]}]
set_property PACKAGE_PIN F3 [get_ports o_sd_sck]
set_property IOSTANDARD LVCMOS33 [get_ports o_sd_sck]
set_property PACKAGE_PIN E2 [get_ports {io_sd[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_sd[1]}]
set_property PACKAGE_PIN D2 [get_ports {io_sd[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_sd[2]}]
set_property PACKAGE_PIN H2 [get_ports i_sd_cs]
set_property IOSTANDARD LVCMOS33 [get_ports i_sd_cs]
set_property PACKAGE_PIN G2 [get_ports i_sd_wp]
set_property IOSTANDARD LVCMOS33 [get_ports i_sd_wp]
 
##USB-UART Interface
# THESE ARE CORRECT
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { o_uart_tx }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { i_uart_rx }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
set_property PACKAGE_PIN D10 [get_ports o_uart_tx]
set_property IOSTANDARD LVCMOS33 [get_ports o_uart_tx]
set_property PACKAGE_PIN A9 [get_ports i_uart_rx]
set_property IOSTANDARD LVCMOS33 [get_ports i_uart_rx]
#
 
##ChipKit Single Ended Analog Inputs
##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].
 
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0]
188,14 → 238,17
##Misc. ChipKit signals
 
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { i_reset_btn }]; #IO_L16P_T2_35 Sch=ck_rst
set_property PACKAGE_PIN C2 [get_ports i_reset_btn]
set_property IOSTANDARD LVCMOS33 [get_ports i_reset_btn]
 
##SMSC Ethernet PHY
 
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { o_eth_mdclk }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { io_eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
set_property PACKAGE_PIN F16 [get_ports o_eth_mdclk]
set_property IOSTANDARD LVCMOS33 [get_ports o_eth_mdclk]
set_property PACKAGE_PIN K13 [get_ports io_eth_mdio]
set_property IOSTANDARD LVCMOS33 [get_ports io_eth_mdio]
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
214,14 → 267,20
 
##Quad SPI Flash
 
set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { o_qspi_cs_n }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { o_qspi_sck }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
set_property PACKAGE_PIN L13 [get_ports o_qspi_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports o_qspi_cs_n]
set_property PACKAGE_PIN K17 [get_ports {io_qspi_dat[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_qspi_dat[0]}]
set_property PACKAGE_PIN K18 [get_ports {io_qspi_dat[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_qspi_dat[1]}]
set_property PACKAGE_PIN L14 [get_ports {io_qspi_dat[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_qspi_dat[2]}]
set_property PACKAGE_PIN M14 [get_ports {io_qspi_dat[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {io_qspi_dat[3]}]
set_property PACKAGE_PIN L16 [get_ports o_qspi_sck]
set_property IOSTANDARD LVCMOS33 [get_ports o_qspi_sck]
 
##Power Measurements
##Power Measurements
 
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
235,58 → 294,113
## Memory
 
# Memory address lines
set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[0] }];
set_property -dict { PACKAGE_PIN M6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[1] }];
set_property -dict { PACKAGE_PIN N4 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[2] }];
set_property -dict { PACKAGE_PIN T1 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[3] }];
set_property -dict { PACKAGE_PIN N6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[4] }];
set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[5] }];
set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[6] }];
set_property -dict { PACKAGE_PIN U7 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[7] }];
set_property -dict { PACKAGE_PIN R8 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[8] }];
set_property -dict { PACKAGE_PIN V7 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[9] }];
set_property -dict { PACKAGE_PIN R6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[10] }];
set_property -dict { PACKAGE_PIN U6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[11] }];
set_property -dict { PACKAGE_PIN T6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[12] }];
set_property -dict { PACKAGE_PIN T8 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[13] }];
set_property -dict { PACKAGE_PIN R1 IOSTANDARD SSTL135 } [get_ports { o_ddr_ba[0] }];
set_property -dict { PACKAGE_PIN P4 IOSTANDARD SSTL135 } [get_ports { o_ddr_ba[1] }];
set_property -dict { PACKAGE_PIN P2 IOSTANDARD SSTL135 } [get_ports { o_ddr_ba[2] }];
set_property PACKAGE_PIN R2 [get_ports {o_ddr_addr[0]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[0]}]
set_property PACKAGE_PIN M6 [get_ports {o_ddr_addr[1]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[1]}]
set_property PACKAGE_PIN N4 [get_ports {o_ddr_addr[2]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[2]}]
set_property PACKAGE_PIN T1 [get_ports {o_ddr_addr[3]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[3]}]
set_property PACKAGE_PIN N6 [get_ports {o_ddr_addr[4]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[4]}]
set_property PACKAGE_PIN R7 [get_ports {o_ddr_addr[5]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[5]}]
set_property PACKAGE_PIN V6 [get_ports {o_ddr_addr[6]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[6]}]
set_property PACKAGE_PIN U7 [get_ports {o_ddr_addr[7]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[7]}]
set_property PACKAGE_PIN R8 [get_ports {o_ddr_addr[8]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[8]}]
set_property PACKAGE_PIN V7 [get_ports {o_ddr_addr[9]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[9]}]
set_property PACKAGE_PIN R6 [get_ports {o_ddr_addr[10]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[10]}]
set_property PACKAGE_PIN U6 [get_ports {o_ddr_addr[11]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[11]}]
set_property PACKAGE_PIN T6 [get_ports {o_ddr_addr[12]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[12]}]
set_property PACKAGE_PIN T8 [get_ports {o_ddr_addr[13]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_addr[13]}]
set_property PACKAGE_PIN R1 [get_ports {o_ddr_ba[0]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_ba[0]}]
set_property PACKAGE_PIN P4 [get_ports {o_ddr_ba[1]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_ba[1]}]
set_property PACKAGE_PIN P2 [get_ports {o_ddr_ba[2]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_ba[2]}]
#
set_property -dict { PACKAGE_PIN M4 IOSTANDARD SSTL135 } [get_ports { o_ddr_cas_n }];
set_property PACKAGE_PIN M4 [get_ports o_ddr_cas_n]
set_property IOSTANDARD SSTL135 [get_ports o_ddr_cas_n]
# Clock lines
set_property -dict { PACKAGE_PIN V9 IOSTANDARD DIFF_SSTL135 } [get_ports { o_ddr_ck_n }];
set_property -dict { PACKAGE_PIN U9 IOSTANDARD DIFF_SSTL135 } [get_ports { o_ddr_ck_p }];
set_property IOSTANDARD DIFF_SSTL135 [get_ports o_ddr_ck_n]
set_property PACKAGE_PIN U9 [get_ports o_ddr_ck_p]
set_property IOSTANDARD DIFF_SSTL135 [get_ports o_ddr_ck_p]
#
set_property -dict { PACKAGE_PIN N5 IOSTANDARD SSTL135 } [get_ports { o_ddr_cke }];
set_property -dict { PACKAGE_PIN U8 IOSTANDARD SSTL135 } [get_ports { o_ddr_cs_n }];
set_property -dict { PACKAGE_PIN L1 IOSTANDARD SSTL135 } [get_ports { o_ddr_dm[0] }];
set_property -dict { PACKAGE_PIN U1 IOSTANDARD SSTL135 } [get_ports { o_ddr_dm[1] }];
set_property PACKAGE_PIN N5 [get_ports o_ddr_cke]
set_property IOSTANDARD SSTL135 [get_ports o_ddr_cke]
set_property PACKAGE_PIN U8 [get_ports o_ddr_cs_n]
set_property IOSTANDARD SSTL135 [get_ports o_ddr_cs_n]
set_property PACKAGE_PIN L1 [get_ports {o_ddr_dm[0]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_dm[0]}]
set_property PACKAGE_PIN U1 [get_ports {o_ddr_dm[1]}]
set_property IOSTANDARD SSTL135 [get_ports {o_ddr_dm[1]}]
# Data (DQ) lines
set_property -dict { PACKAGE_PIN K5 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[0] }];
set_property -dict { PACKAGE_PIN L3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[1] }];
set_property -dict { PACKAGE_PIN K3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[2] }];
set_property -dict { PACKAGE_PIN L6 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[3] }];
set_property -dict { PACKAGE_PIN M3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[4] }];
set_property -dict { PACKAGE_PIN M1 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[5] }];
set_property -dict { PACKAGE_PIN L4 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[6] }];
set_property -dict { PACKAGE_PIN M2 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[7] }];
set_property -dict { PACKAGE_PIN V4 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[8] }];
set_property -dict { PACKAGE_PIN T5 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[9] }];
set_property -dict { PACKAGE_PIN U4 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[10] }];
set_property -dict { PACKAGE_PIN V5 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[11] }];
set_property -dict { PACKAGE_PIN V1 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[12] }];
set_property -dict { PACKAGE_PIN T3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[13] }];
set_property -dict { PACKAGE_PIN U3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[14] }];
set_property -dict { PACKAGE_PIN R3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[15] }];
set_property PACKAGE_PIN K5 [get_ports {io_ddr_data[0]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[0]}]
set_property PACKAGE_PIN L3 [get_ports {io_ddr_data[1]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[1]}]
set_property PACKAGE_PIN K3 [get_ports {io_ddr_data[2]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[2]}]
set_property PACKAGE_PIN L6 [get_ports {io_ddr_data[3]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[3]}]
set_property PACKAGE_PIN M3 [get_ports {io_ddr_data[4]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[4]}]
set_property PACKAGE_PIN M1 [get_ports {io_ddr_data[5]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[5]}]
set_property PACKAGE_PIN L4 [get_ports {io_ddr_data[6]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[6]}]
set_property PACKAGE_PIN M2 [get_ports {io_ddr_data[7]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[7]}]
set_property PACKAGE_PIN V4 [get_ports {io_ddr_data[8]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[8]}]
set_property PACKAGE_PIN T5 [get_ports {io_ddr_data[9]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[9]}]
set_property PACKAGE_PIN U4 [get_ports {io_ddr_data[10]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[10]}]
set_property PACKAGE_PIN V5 [get_ports {io_ddr_data[11]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[11]}]
set_property PACKAGE_PIN V1 [get_ports {io_ddr_data[12]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[12]}]
set_property PACKAGE_PIN T3 [get_ports {io_ddr_data[13]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[13]}]
set_property PACKAGE_PIN U3 [get_ports {io_ddr_data[14]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[14]}]
set_property PACKAGE_PIN R3 [get_ports {io_ddr_data[15]}]
set_property IOSTANDARD SSTL135 [get_ports {io_ddr_data[15]}]
# DQS
set_property -dict { PACKAGE_PIN N1 IOSTANDARD DIFF_SSTL135 } [get_ports { io_ddr_dqs_n[0] }];
set_property -dict { PACKAGE_PIN V2 IOSTANDARD DIFF_SSTL135 } [get_ports { io_ddr_dqs_n[1] }];
set_property -dict { PACKAGE_PIN N2 IOSTANDARD DIFF_SSTL135 } [get_ports { io_ddr_dqs_p[0] }];
set_property -dict { PACKAGE_PIN U2 IOSTANDARD DIFF_SSTL135 } [get_ports { io_ddr_dqs_p[1] }];
set_property -dict { PACKAGE_PIN R5 IOSTANDARD SSTL135 } [get_ports { o_ddr_odt }];
set_property -dict { PACKAGE_PIN P3 IOSTANDARD SSTL135 } [get_ports { o_ddr_ras_n }];
set_property -dict { PACKAGE_PIN K6 IOSTANDARD SSTL135 } [get_ports { o_ddr_reset_n }];
set_property -dict { PACKAGE_PIN P5 IOSTANDARD SSTL135 } [get_ports { o_ddr_we_n }];
set_property IOSTANDARD DIFF_SSTL135 [get_ports {io_ddr_dqs_n[0]}]
set_property IOSTANDARD DIFF_SSTL135 [get_ports {io_ddr_dqs_n[1]}]
set_property IOSTANDARD DIFF_SSTL135 [get_ports {io_ddr_dqs_p[0]}]
set_property PACKAGE_PIN N2 [get_ports {io_ddr_dqs_p[0]}]
set_property IOSTANDARD DIFF_SSTL135 [get_ports {io_ddr_dqs_p[1]}]
set_property PACKAGE_PIN U2 [get_ports {io_ddr_dqs_p[1]}]
set_property PACKAGE_PIN R5 [get_ports o_ddr_odt]
set_property IOSTANDARD SSTL135 [get_ports o_ddr_odt]
set_property PACKAGE_PIN P3 [get_ports o_ddr_ras_n]
set_property IOSTANDARD SSTL135 [get_ports o_ddr_ras_n]
set_property PACKAGE_PIN K6 [get_ports o_ddr_reset_n]
set_property IOSTANDARD SSTL135 [get_ports o_ddr_reset_n]
set_property PACKAGE_PIN P5 [get_ports o_ddr_we_n]
set_property IOSTANDARD SSTL135 [get_ports o_ddr_we_n]
#Internal VREF
set_property INTERNAL_VREF 0.675 [ get_iobanks 34 ];
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
 
 
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property BITSTREAM.CONFIG.CCLKPIN PULLNONE [current_design]
set_property CONFIG_MODE SPIx1 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR NO [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]
 
 

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