URL
https://opencores.org/ocsvn/openarty/openarty/trunk
Subversion Repositories openarty
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- This comparison shows the changes necessary to convert path
/openarty/trunk/rtl
- from Rev 20 to Rev 21
- ↔ Reverse comparison
Rev 20 → Rev 21
/wboled.v
58,16 → 58,42
lwlvl(i_clk, dev_wr, dev_dbit, dev_word, dev_len, dev_busy, |
o_sck, o_cs_n, o_mosi, o_dbit); |
|
`define EXTRA_WB_DELAY |
`ifdef EXTRA_WB_DELAY |
reg r_wb_stb, r_wb_we; |
reg [31:0] r_wb_data; |
reg [1:0] r_wb_addr; |
always @(posedge i_clk) |
r_wb_stb <= i_stb; |
always @(posedge i_clk) |
r_wb_we <= i_we; |
always @(posedge i_clk) |
r_wb_data <= i_data; |
always @(posedge i_clk) |
r_wb_addr <= i_addr; |
`else |
wire r_wb_stb, r_wb_we; |
wire r_wb_data; |
wire [1:0] r_wb_addr; |
|
assign r_wb_stb = i_stb; |
assign r_wb_we = i_we; |
assign r_wb_data = i_data; |
assign r_wb_addr = i_addr; |
`endif |
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|
|
reg r_busy; |
reg [3:0] r_len; |
reg [31:0] r_a, r_b; |
always @(posedge i_clk) |
if ((i_stb)&&(i_we)) |
if ((r_wb_stb)&&(r_wb_we)) |
begin |
if (i_addr[1:0]==2'b01) |
r_a <= i_data; |
if (i_addr[1:0]==2'b10) |
r_b <= i_data; |
if (r_wb_addr[1:0]==2'b01) |
r_a <= r_wb_data; |
if (r_wb_addr[1:0]==2'b10) |
r_b <= r_wb_data; |
end else if (r_cstb) |
begin |
r_a <= 32'h00; |
76,7 → 102,7
|
always @(posedge i_clk) |
begin |
case (i_addr) |
case (r_wb_addr) |
2'b00: o_data <= { 13'h00, o_pwr, 8'h00, r_len, 3'h0, r_busy }; |
2'b01: o_data <= r_a; |
2'b10: o_data <= r_b; |
86,7 → 112,7
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initial o_ack = 1'b0; |
always @(posedge i_clk) |
o_ack <= i_stb; |
o_ack <= r_wb_stb; |
assign o_stall = 1'b0; |
|
reg r_cstb, r_dstb, r_pstb; |
95,24 → 121,24
initial r_dstb = 1'b0; |
initial r_pstb = 1'b0; |
always @(posedge i_clk) |
r_cstb <= (i_stb)&&(i_addr[1:0]==2'b00); |
r_cstb <= (r_wb_stb)&&(r_wb_addr[1:0]==2'b00); |
always @(posedge i_clk) |
r_dstb <= (i_stb)&&(i_addr[1:0]==2'b11)&&(i_data[22:20]==3'h0); |
r_dstb <= (r_wb_stb)&&(r_wb_addr[1:0]==2'b11)&&(r_wb_data[22:20]==3'h0); |
always @(posedge i_clk) |
r_pstb <= (i_stb)&&(i_addr[1:0]==2'b11)&&(i_data[22:20]!=3'h0); |
r_pstb <= (r_wb_stb)&&(r_wb_addr[1:0]==2'b11)&&(r_wb_data[22:20]!=3'h0); |
always @(posedge i_clk) |
r_data <= i_data[23:0]; |
r_data <= r_wb_data[23:0]; |
|
initial o_pwr = 3'h0; |
always @(posedge i_clk) |
if (r_pstb) |
o_pwr <= ((o_pwr)&(~r_data[22:20])) |
|((i_data[18:16])&(r_data[22:20])); |
|((r_wb_data[18:16])&(r_data[22:20])); |
|
reg [3:0] b_len; |
always @(posedge i_clk) |
casez(i_data[31:28]) |
4'b000?: b_len <= (i_data[16])? 4'h1:4'h2; |
casez(r_wb_data[31:28]) |
4'b000?: b_len <= (r_wb_data[16])? 4'h1:4'h2; |
4'b0010: b_len <= 4'h3; |
4'b0011: b_len <= 4'h4; |
4'b0100: b_len <= 4'h5; |