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    /openarty/trunk/rtl
    from Rev 32 to Rev 33
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Rev 32 → Rev 33

/Makefile
60,7 → 60,8
rxuart.v txuart.v eqspiflash.v lleqspi.v flash_config.v \
wbicapetwo.v sdspi.v gpsclock_tb.v gpsclock.v wboled.v lloled.v \
wbscopc.v wbscope.v memdev.v addepreamble.v addemac.v addecrc.v \
addepad.v rxecrc.v rxepreambl.v rxehwmac.v rxewrite.v
addepad.v rxecrc.v rxepreambl.v rxehwmac.v rxewrite.v \
rxemin.v rxeipchk.v
BIGMATH:= bigadd.v bigsmpy.v bigsub.v
SOURCES := fastmaster.v builddate.v \
$(CPUSOURCES) $(JTAGBUS) $(PERIPHERALS) $(BIGMATH)
/addepad.v
40,6 → 40,9
//
//
module addepad(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_v, o_d);
parameter MINNIBBLES=120;
localparam LGNCOUNT=(MINNIBBLES<63)? 6
:((MINNIBBLES<127)? 7:((MINNIBBLES<255)? 8:9));
input i_clk, i_ce, i_en, i_cancel;
input i_v; // Valid
input [3:0] i_d; // Data nibble
46,11 → 49,7
output reg o_v;
output reg [3:0] o_d;
 
// 60 bytes translates to 120 nibbles, so let's keep track of our
// minimum number of nibbles to transmit
reg [119:0] r_v;
 
initial r_v = 120'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
reg [(LGNCOUNT-1):0] r_ncnt;
initial o_v = 1'b0;
always @(posedge i_clk)
if (i_ce)
57,15 → 56,15
begin
if (((!i_v)&&(!o_v))||(i_cancel))
begin
r_v <= 120'hff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
r_ncnt <= 0;
o_v <= 1'b0;
end else if (i_v)
begin
o_v <= i_v;
r_v <= { r_v[118:0], 1'b0 };
r_ncnt <= (r_ncnt<MINNIBBLES) ? r_ncnt+1'b1 : r_ncnt;
end else begin
o_v <= r_v[119];
r_v <= { r_v[118:0], 1'b0 };
o_v <= (r_ncnt<MINNIBBLES);
r_ncnt <= (r_ncnt<MINNIBBLES) ? r_ncnt+1'b1 : r_ncnt;
end
 
if (i_v)
/builddate.v
38,4 → 38,4
////////////////////////////////////////////////////////////////////////////////
//
//
`define DATESTAMP 32'h20161015
`define DATESTAMP 32'h20161018
/busmaster.v
813,7 → 813,7
wire [1:0] gps_dbg_tick;
 
gpsclock_tb ppscktb(i_clk, ck_pps, tb_pps,
(wb_stb)&&(gps_sel)&&(wb_addr[3]),
(wb_stb)&&(gps_sel)&&(!wb_addr[4]),
wb_we, wb_addr[2:0],
wb_data, gtb_ack, gtb_stall, gtb_data,
gps_err, gps_now, gps_step);
830,7 → 830,7
gpsclock #(
.DEFAULT_STEP(32'h834d_c736)
) ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
(wb_stb)&&(gps_sel)&&(~wb_addr[3]),
(wb_stb)&&(gps_sel)&&(wb_addr[4]),
wb_we, wb_addr[1:0],
wb_data, gck_ack, gck_stall, gck_data,
gps_tracking, gps_now, gps_step, gps_err, gps_locked,
/enetpackets.v
211,7 → 211,7
`else
reg tx_busy, tx_complete;
`endif
reg config_hw_crc, config_hw_mac;
reg config_hw_crc, config_hw_mac, config_hw_ip_check;
reg rx_crcerr, rx_err, rx_miss, rx_clear;
`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
wire rx_valid, rx_busy;
229,6 → 229,7
 
initial config_hw_crc = 0;
initial config_hw_mac = 0;
initial config_hw_ip_check = 0;
initial o_net_reset_n = 1'b0;
initial tx_cmd = 1'b0;
initial tx_cancel = 1'b0;
274,6 → 275,7
begin // TX command register
 
// Reset bit must be held down to be valid
config_hw_ip_check <= (!wr_data[18]);
o_net_reset_n <= (!wr_data[17]);
config_hw_mac <= (!wr_data[16]);
config_hw_crc <= (!wr_data[15]);
305,7 → 307,8
rx_miss, rx_busy, (rx_valid)&&(!rx_clear),
{(14-MAW-2){1'b0}}, rx_len };
 
assign w_tx_ctrl = { 4'h0, w_maw, {(24-18){1'b0}},
assign w_tx_ctrl = { 4'h0, w_maw, {(24-19){1'b0}},
!config_hw_ip_check,
!o_net_reset_n,!config_hw_mac,
!config_hw_crc, tx_busy,
{(14-MAW-2){1'b0}}, tx_len };
545,10 → 548,11
 
`ifdef RX_SYNCHRONOUS_WITH_WB_CLK
wire n_rx_clear;
reg n_rx_config_hw_mac, n_rx_config_hw_crc;
reg n_rx_config_hw_mac, n_rx_config_hw_crc, n_rx_config_ip_check;
assign n_rx_clear = rx_clear;
`else
(* ASYNC_REG = "TRUE" *) reg n_rx_config_hw_mac, n_rx_config_hw_crc;
(* ASYNC_REG = "TRUE" *) reg n_rx_config_hw_mac, n_rx_config_hw_crc,
n_rx_config_ip_check;
(* ASYNC_REG = "TRUE" *) reg r_rx_clear;
reg n_rx_clear;
always @(posedge `RXCLK)
560,8 → 564,8
 
 
reg n_rx_net_err;
wire w_npre, w_rxmin, w_rxcrc, w_rxmac, w_rxip;
wire [3:0] w_npred, w_rxmind, w_rxcrcd, w_rxmacd, w_rxipd;
wire w_npre, w_rxmin, w_rxcrc, w_rxmac;
wire [3:0] w_npred, w_rxmind, w_rxcrcd, w_rxmacd;
wire w_minerr, w_rxcrcerr, w_macerr, w_broadcast, w_iperr;
`ifndef RX_BYPASS_HW_PREAMBLE
rxepreambl rxprei(`RXCLK, rx_clk_stb, 1'b1, (n_rx_net_err),
571,15 → 575,15
assign w_npred = i_net_rxerr;
`endif
 
`ifdef RX_HW_MINLENGTH
`ifdef RX_BYPASS_HW_MINLENGTH
// Insist on a minimum of 64-byte packets
rxeminlen rxmini(`RXCLK, rx_clk_stb, 1'b1, (n_rx_net_err),
w_npre, w_npred, w_rxmin, w_rxmind, w_minerr);
rxemin rxmini(`RXCLK, rx_clk_stb, 1'b1, (n_rx_net_err),
w_npre, w_npred, w_minerr);
`else
assign w_minerr= 1'b0;
`endif
assign w_rxmin = w_npre;
assign w_rxmind= w_npred;
assign w_minerr= 1'b0;
`endif
 
`ifndef RX_BYPASS_HW_CRC
rxecrc rxcrci(`RXCLK, rx_clk_stb, n_rx_config_hw_crc, (n_rx_net_err),
600,12 → 604,13
assign w_rxmacd = w_rxcrcd;
`endif
 
`define RX_HW_IPCHECK
`ifdef RX_HW_IPCHECK
// Check: if this packet is an IP packet, is the IP header checksum
// valid?
rxeipchk rxipci(`RXCLK, rx_clk_stb, n_rx_config_ip_check,(n_rx_net_err),
w_rxcrc, w_rxcrcd, w_iperr);
`else
assign w_rxip = w_rxmac;
assign w_rxipd = w_rxmacd;
assign w_iperr = 1'b0;
`endif
 
614,7 → 619,7
wire [31:0] w_rxdata;
wire [(MAW+1):0] w_rxlen;
 
rxewrite #(MAW) rxememi(`RXCLK, 1'b1, (n_rx_net_err), w_rxip, w_rxipd,
rxewrite #(MAW) rxememi(`RXCLK, 1'b1, (n_rx_net_err), w_rxmac, w_rxmacd,
w_rxwr, w_rxaddr, w_rxdata, w_rxlen);
 
reg last_rxwr, n_rx_valid, n_rxmiss, n_eop, n_rx_busy, n_rx_crcerr,
633,6 → 638,7
// and stays true as long as valid data is coming in
n_rx_net_err <= (i_net_dv)&&((i_net_rxerr)||(i_net_col)
||(w_minerr)||(w_macerr)||(w_rxcrcerr)
||(w_iperr)
||(n_rx_net_err)
||((w_rxwr)&&(n_rx_valid)));
 
640,7 → 646,7
n_eop <= (!w_rxwr)&&(last_rxwr)&&(!n_rx_net_err);
 
n_rx_busy <= (!n_rx_net_err)&&((i_net_dv)||(w_npre)||(w_rxmin)
||(w_rxcrc)||(w_rxmac)||(w_rxip)||(w_rxwr));
||(w_rxcrc)||(w_rxmac)||(w_rxwr));
 
// Oops ... we missed a packet
n_rx_miss <= (n_rx_valid)&&(w_rxwr)||
667,8 → 673,9
 
if ((!i_net_dv)||(n_rx_clear))
begin
n_rx_config_hw_mac <= config_hw_mac;
n_rx_config_hw_crc <= config_hw_crc;
n_rx_config_hw_mac <= config_hw_mac;
n_rx_config_hw_crc <= config_hw_crc;
n_rx_config_ip_check <= config_hw_ip_check;
end
end
 
/rxecrc.v
5,7 → 5,8
// Project: OpenArty, an entirely open SoC based upon the Arty platform
//
// Purpose: To detect any CRC errors in the packet as received. The CRC
// is not stripped as part of this process.
// is not stripped as part of this process. However, any bytes
// following the CRC, up to four, will be stripped from the output.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
67,7 → 68,7
assign lownibble = r_crc[3:0] ^ i_d;
 
wire [31:0] shifted_crc;
assign shifted_crc = { 4'h0, r_crc[27:0] };
assign shifted_crc = { 4'h0, r_crc[31:4] };
always @(posedge i_clk)
if (i_ce)
begin
81,7 → 82,7
r_crc_q6 <= r_crc_q5[ 7:4];
 
r_buf <= { r_buf[9:0], i_v, i_d };
if (((!i_ce)&&(!o_v))||(i_cancel))
if (((!i_v)&&(!o_v))||(i_cancel))
begin
r_crc <= 32'hffff_ffff;
r_err <= 1'b0;
115,17 → 116,17
4'hf: r_crc <= shifted_crc ^ `CRCBIT8 ^ `CRCBIT4 ^ `CRCBIT2 ^ `CRCBIT1;
endcase
 
r_mq[0] <= (i_v)&&(i_d == r_crc[3:0]);
r_mq[1] <= (r_mq[0])&&(i_v)&&(i_d == r_crc_q0[3:0]);
r_mq[2] <= (r_mq[1])&&(i_v)&&(i_d == r_crc_q1[3:0]);
r_mq[3] <= (r_mq[2])&&(i_v)&&(i_d == r_crc_q2[3:0]);
r_mq[4] <= (r_mq[3])&&(i_v)&&(i_d == r_crc_q3[3:0]);
r_mq[5] <= (r_mq[4])&&(i_v)&&(i_d == r_crc_q4[3:0]);
r_mq[6] <= (r_mq[5])&&(i_v)&&(i_d == r_crc_q5[3:0]);
r_mq[0] <= (i_v)&&(i_d == (~r_crc[3:0]));
r_mq[1] <= (r_mq[0])&&(i_v)&&(i_d == (~r_crc_q0[3:0]));
r_mq[2] <= (r_mq[1])&&(i_v)&&(i_d == (~r_crc_q1[3:0]));
r_mq[3] <= (r_mq[2])&&(i_v)&&(i_d == (~r_crc_q2[3:0]));
r_mq[4] <= (r_mq[3])&&(i_v)&&(i_d == (~r_crc_q3[3:0]));
r_mq[5] <= (r_mq[4])&&(i_v)&&(i_d == (~r_crc_q4[3:0]));
r_mq[6] <= (r_mq[5])&&(i_v)&&(i_d == (~r_crc_q5[3:0]));
//r_mq7<=(r_mq6)&&(i_v)&&(i_d == r_crc_q6[3:0]);
 
r_mp <= { r_mp[2:0],
(r_mq[6])&&(i_v)&&(i_d == r_crc_q6[3:0]) };
(r_mq[6])&&(i_v)&&(i_d == (~r_crc_q6[3:0])) };
 
// Now, we have an error if ...
// On the first empty, none of the prior N matches
/rxehwmac.v
49,6 → 49,21
output wire o_err;
output reg o_broadcast;
 
wire [47:0] mac_remapped;
 
assign mac_remapped[47:44] = i_hwmac[43:40];
assign mac_remapped[43:40] = i_hwmac[47:44];
assign mac_remapped[39:36] = i_hwmac[35:32];
assign mac_remapped[35:32] = i_hwmac[39:36];
assign mac_remapped[31:28] = i_hwmac[27:24];
assign mac_remapped[27:24] = i_hwmac[31:28];
assign mac_remapped[23:20] = i_hwmac[19:16];
assign mac_remapped[19:16] = i_hwmac[23:20];
assign mac_remapped[15:12] = i_hwmac[11: 8];
assign mac_remapped[11: 8] = i_hwmac[15:12];
assign mac_remapped[ 7: 4] = i_hwmac[ 3: 0];
assign mac_remapped[ 3: 0] = i_hwmac[ 7: 4];
 
reg [47:0] r_hwmac;
reg r_cancel, r_err, r_hwmatch, r_broadcast;
reg [19:0] r_buf;
70,6 → 85,9
r_broadcast<= 1'b0;
end
 
if ((i_v)&&(r_p[11]))
r_hwmac <= { r_hwmac[43:0], 4'h0 };
 
r_err <= (i_en)&&(!r_hwmatch)&&(!r_broadcast)&&(i_v);
o_broadcast <= (r_broadcast)&&(!r_p[11])&&(i_v);
 
77,7 → 95,7
if (((!i_v)&&(!o_v))||(i_cancel))
begin
r_p <= 30'h3fff_ffff;
r_hwmac <= i_hwmac;
r_hwmac <= mac_remapped;
r_hwmatch <= 1'b1;
r_broadcast <= 1'b1;
r_buf[ 4] <= 1'b0;
/rxeipchk.v
0,0 → 1,99
////////////////////////////////////////////////////////////////////////////////
//
// Filename: rxeipchk.v
//
// Project: OpenArty, an entirely open SoC based upon the Arty platform
//
// Purpose: To cull any IP packets (EtherType=0x0806) from the stream
// whose packet header checksums don't match.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module rxeipchk(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_err);
input i_clk, i_ce, i_en, i_cancel;
input i_v; // Valid
input [3:0] i_d; // Data nibble
output reg o_err;
 
reg r_v;
reg [15:0] r_word;
reg [7:0] r_cnt;
reg [5:0] r_idx;
always @(posedge i_clk)
if (i_ce)
begin
if ((!i_v)||(i_cancel))
begin
r_cnt <= 0;
r_idx <= 0;
end else if(i_v)
begin
if (!(&r_cnt))
r_cnt <= r_cnt + 1'b1;
if (&r_cnt)
r_v <= 1'b0;
else
r_v <= (r_cnt[1:0] == 2'b11);
if (r_cnt[1:0]==2'b11)
r_idx[5:0] <= r_cnt[7:2];
if (!r_cnt[0])
r_word <= { r_word[7:0], 4'h0, i_d };
else
r_word[7:4] <= i_d;
end
end
 
reg r_ip;
reg [5:0] r_hlen;
reg [16:0] r_check;
always @(posedge i_clk)
if (i_ce)
begin
if ((!i_v)||(i_cancel))
begin
o_err <= 0;
r_check <= 0;
r_ip <= 0;
end else if (r_v)
begin
if (r_idx == 6'h6)
r_ip <= (r_word == 16'h0800);
else if (r_idx == r_hlen)
r_ip <= 1'b0;
if (r_idx == 6'h7)
r_hlen <= {r_word[11:8], 1'b0 } + 5'h7;
if (r_idx == r_hlen)
o_err <= (r_ip)&&(i_en)&&(r_check[15:0] != 16'hffff);
if (r_ip)
r_check <= r_check[15:0] + r_word + { 15'h0, r_check[16]};
end
end
 
endmodule
/rxemin.v
0,0 → 1,70
////////////////////////////////////////////////////////////////////////////////
//
// Filename: rxemin.v
//
// Project: OpenArty, an entirely open SoC based upon the Arty platform
//
// Purpose: To force the minimum received packet size of an ethernet frame
// to be a minimum of 64 bytes. Packets less than 64-bytes
// (including CRC) need to be dropped. This module handles that
// logic.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module rxemin(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_v, o_d, o_err);
parameter MINNIBBLES=120;
localparam LGNCOUNT=(MINNIBBLES<63)? 6
:((MINNIBBLES<127)? 7:((MINNIBBLES<255)? 8:9));
input i_clk, i_ce, i_en, i_cancel;
input i_v; // Valid
input [3:0] i_d; // Data nibble
output reg o_err;
 
reg last_v;
reg [(LGNCOUNT-1):0] r_ncnt;
initial o_v = 1'b0;
initial last_v = 1'b0;
always @(posedge i_clk)
if (i_ce)
begin
last_v <= i_v;
 
if (((!i_v)&&(!o_v))||(i_cancel))
begin
r_ncnt <= 0;
o_err <= 0;
end else if (i_v)
begin
r_ncnt <= (r_ncnt<MINNIBBLES) ? r_ncnt+1'b1 : r_ncnt;
end else if (last_v)
o_err <= (i_en)&&(r_ncnt < MINNIBBLES);
end
 
endmodule

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