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URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

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  • This comparison shows the changes necessary to convert path 
    /openarty/trunk
    from Rev 59 to Rev 60
    ↔ Reverse comparison
  •

Rev 59 → Rev 60

/Makefile
13,7 → 13,7
##
################################################################################
##
## Copyright (C) 2015, Gisselquist Technology, LLC
## Copyright (C) 2015-2017, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
25,8 → 25,13
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http:##www.gnu.org/licenses/gpl.html
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
33,11 → 38,12
##
##
.PHONY: all
all: archive datestamp rtl bench sw
# all: verilated sw bench bit
all: archive datestamp rtl sim sw
# all: datestamp archive rtl sw sim bench bit
#
# Could also depend upon load, if desired, but not necessary
BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
SIM := `find sim -name Makefile` `find sim -name "*.cpp"` `find sim -name "*.h"` `find sim -name "*.c"`
RTL := `find rtl -name "*.v"` `find rtl -name Makefile`
NOTES := `find . -name "*.txt"` `find . -name "*.html"`
SW := `find sw -name "*.cpp"` `find sw -name "*.c"` \
48,8 → 54,9
`find sw-board -name Makefile`
PROJ :=
BIN := `find xilinx -name "*.bit"`
CONSTRAINTS := arty.xdc
CONSTRAINTS := arty.xdc migmem.xdc
YYMMDD:=`date +%Y%m%d`
SUBMAKE := $(MAKE) --no-print-directory
 
.PHONY: datestamp
datestamp:
58,24 → 65,44
 
.PHONY: archive
archive:
tar --transform s,^,$(YYMMDD)-arty/, -chjf $(YYMMDD)-arty.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS)
tar --transform s,^,$(YYMMDD)-arty/, -chjf $(YYMMDD)-arty.tjz $(BENCH) $(SW) $(RTL) $(SIM) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS) README.md
 
.PHONY: verilated
verilated: datestamp
cd rtl ; $(MAKE) --no-print-directory
$(SUBMAKE) --no-print-directory --directory=rtl
 
.PHONY: rtl
rtl: verilated
 
.PHONY: bench
bench: rtl
cd bench/cpp ; $(MAKE) --no-print-directory
.PHONY: sim
sim: rtl
$(SUBMAKE) --directory=sim/verilated
 
# .PHONY: bench
# bench: sw
# cd sim/verilated ; $(MAKE) --no-print-directory
 
.PHONY: sw
sw:
cd sw/host ; $(MAKE) --no-print-directory
sw: sw-host sw-board sw-zlib
 
.PHONY: sw-host
sw-host:
$(SUBMAKE) --directory=sw/host
 
.PHONY: sw-zlib
sw-zlib:
$(SUBMAKE) --directory=sw/zlib
 
.PHONY: sw-board
sw-board: sw-zlib
$(SUBMAKE) --directory=sw/board
 
# .PHONY: bit
# bit:
# cd xilinx ; $(MAKE) --no-print-directory xula.bit
 
.PHONY: clean
$(SUBMAKE) --directory=rtl clean
$(SUBMAKE) --directory=sw/host clean
$(SUBMAKE) --directory=sw/board clean
$(SUBMAKE) --directory=sim/verilated clean
/README.md
15,16 → 15,16
 
# Current Status
 
I currently have all the hardware on my desk.
This version of the OpenArty project is designed to support an 8-bit byte branch of the ZipCPU. Once the ZipCPU is proven here and in some other locations, the 8-bit branch of the ZipCPU will become the master.
 
The design builds, as of 20160910, at an 81.25 MHz clock speed.
The design builds, as of 201710, at an 81.25 MHz clock speed, with the ZipCPU 8-bit byte updates. As of this writing, the design builds only. It has yet to be tested on the hardware (again--the trunk works on the hardware).
 
- ZipCPU: The ZipCPU should be fully functional at the current clock speed. I'd like to boost it to twice this speed, but that may remain a longer term project.
- Flash: the flash controller has now passedd all of the tests given it, both simulated and live. It can read and write the flash, and so it can place configurations onto the flash as desired. As built, though, the controller is optimized for a 200MHz clock speed, and a 100MHz bus speed. It's being run at an 81.25MHz clock speed though (40.625MHz bus speed), so some performance improvement might yet be achieved.
- SDRAM: I intend to implement work from the DDR3 SDRAM controller for the Arty. For now, the project builds with a Xilinx Memory Interface Generated (MIG) core, and a pipelind wishbone to AXI translator.
- NET: The entire network functionality has now been built, and preliminary testing suggests that it is fully functional.
- Flash: Working completely. An option remains to increase the clock speed from one half of the system clock 81.25MHz, up to the actual system clock speed or perhaps even twice that speed.
- SDRAM: I would still like to implement the work from the DDR3 SDRAM controller for the Arty. For now, the project builds with a Xilinx Memory Interface Generated (MIG) core, and a pipelind wishbone to AXI translator.
- NET: Working on the trunk using a simple program that can send and receive ARP packets, respond to ARP requests, respond to pings, and even ping a local host.
- SD: The SDSPI controller has been integrated into the device, yet not tested yet. I don't expect issues with it, as it is a proven controller--just not one proven (yet) in this platform. Work remains to turn this from a SPI controller to an SDIO based driver.
- OLEDRGB: this driver is built, and has been integrated into the project, but testing hasn't started yet.
- OLEDRGB: Working on the trunk
 
So ... it's a work in progress.
 
/arty.xdc
77,10 → 77,10
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports o_gps_tx]
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports i_gps_rx]
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports i_gps_pps]
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports i_aux_rts]
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports i_aux_cts_n]
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports o_aux_tx]
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports i_aux_rx]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports o_aux_cts]
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports o_aux_rts_n]
 
##Pmod Header JD: SD-Card
 
175,9 → 175,9
## ChipKit SPI
 
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { o_ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { o_ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { o_ck_csn }]; #IO_L16N_T2_35 Sch=ck_ss
 
## ChipKit I2C
 

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