URL
https://opencores.org/ocsvn/opencores/opencores/trunk
Subversion Repositories opencores
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/tags/arelease/rtl/inst_exec.v
0,0 → 1,1224
/////////////////////////////////////////////////////////////////////////////////////////////////// |
// // |
// file name: inst_exec.v // |
// description: main execution engine for wishbone z80 // |
// project: wb_z80 // |
// // |
// Author: B.J. Porcella // |
// e-mail: bporcella@sbcglobal.net // |
// // |
// // |
// // |
/////////////////////////////////////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2000-2002 B.J. Porcella // |
// Real Time Solutions // |
// // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY // |
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // |
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS // |
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR // |
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, // |
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES // |
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE // |
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // |
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // |
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // |
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT // |
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // |
// POSSIBILITY OF SUCH DAMAGE. // |
// // |
//-------1---------2---------3--------Comments on file -------------7---------8---------9--------0 |
// |
// This file contains the data related registers of the z80 and the |
// logic required to update them. Included registers are: |
// ar fr |
// br cr |
// dr er |
// hr lr |
// ixr |
// iyr |
// intr |
// |
// and the "prime" registers |
// ap fp |
// bp cp |
// dp ep |
// hp lp |
// |
// This logic can be considered a "slave" to the memstate sequencer (in memstate2.v). |
// as memstate sequencer executes any instruction from ir1 (the of - os pipe) the instruction |
// gets transferred to ir2 - which now becomes active. |
// |
// In the case of any memory type instruction (HL) , the pipeline must stall 1 tick to get the |
// operand into the nn register. This file logic needs not understand any of that -- just |
// execute when told to (ir2_val). |
// |
// From a block diagram standpoint this file is somewhat messy. There are multiple ALU's and |
// multiple source multiplexors. Part of the reason for this is hardware speed - the |
// various additions start pretty early in the cycle ( as not much decode logic is needed to |
// get them started. In parallel with that - the destination selectors ( which require more |
// complex decoding logic ) are "doing thier thing" No claim that this is absolute optimum - any |
// good synthesizer should be able to make the basic structure faster when flattened. However, |
// the intention is that even if the synthesizer is pretty primitive -- reasonably fast hardware |
// will be produced. |
// |
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0 |
// |
// $Id: inst_exec.v,v 1.1.1.1 2004-06-18 08:38:42 mihal Exp $ |
// |
// $Date: 2004-06-18 08:38:42 $ |
// $Revision: 1.1.1.1 $ |
// $Author: mihal $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2004/04/13 23:49:54 bporcella |
// import first files |
// |
// |
// |
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0 |
module inst_exec( br_eq0, |
cr_eq0, |
upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr, |
ar, fr, br, cr, dr, er, hr, lr, intr, |
ixr, iyr, add16, |
exec_ir2, |
exec_decbc, exec_decb, |
ir2, |
clk, |
rst, |
nn, sp, |
dd_grp, |
fd_grp |
); |
|
//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0 |
output br_eq0; |
output cr_eq0; |
output upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr; |
output [7:0] ar, fr, br, cr, dr, er, hr, lr, intr; |
output [15:0] ixr, iyr; |
output [15:0] add16; |
//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0 |
input exec_ir2; |
input exec_decbc; // in general this needs to happen at different time from exec |
input exec_decb; // in general - we don't have the EB instruction (yet) when this hits |
input [9:0] ir2; |
input clk; |
input rst; |
input [15:0] nn, sp; |
input dd_grp; // this must be ir2 |
input fd_grp; |
|
//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0 |
`include "opcodes.v" |
|
//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0 |
|
wire [7:0] src_pqr; // arithmetic sources gven by ir2[2:0] |
wire [7:0] src_hr ; |
wire [7:0] src_lr ; |
wire [7:0] alu_out; // {CF. 8bit_result} |
wire alu_cry; |
|
wire c_in0, c_out7, c_in8, c_out11, cout15; |
wire [15:0] src_a, src_b; |
wire [15:0] add16; |
wire sf, zf, f5f, hf, f3f, pvf, nf, cf; |
wire [7:0] daa_alu; // {cry, number} hf goes to 0 always. |
wire daa_cry; |
wire upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_fr, upd_hr, upd_lr; |
wire c_8out3; |
wire [7:0] add_8bit; |
|
wire src_dblhr ; |
wire src_cb_r20 ; |
wire src_pqr20 ; |
wire src_pqr53 ; |
wire src_dbl ; |
wire [7:0] alu8_fr ; |
wire alu8_nf ; |
wire c_8out7 ; |
wire alu8_cry ; |
wire alu8_hcry ; |
wire [7:0] alu8_out ; |
wire add16_ofl ; |
wire c_16out7 ; |
wire c_16out11 ; |
wire c_16out15 ; |
wire c_16in0 ; |
wire sh_cry ; |
wire [7:0] sh_alu ; |
wire sh_alu_act ; |
wire bit_alu_act ; |
wire [7:0] bit_alu ; |
wire [7:0] decc_alu ; |
wire [7:0] decb_alu ; |
wire upd_a_alu8 ; |
wire up_a_sh_alu ; |
wire up_a_src_pqr ; |
wire up_a_n ; |
wire upd_b_alu8 ; |
wire up_b_src_pqr ; |
wire up_b_add16 ; |
wire [7:0] sh_src ; |
|
wire up_c_add16 ; |
wire upd_c_alu8 ; |
wire up_c_src_pqr ; |
wire up_d_add16 ; |
wire upd_d_alu8 ; |
wire up_d_src_pqr ; |
wire up_e_add16 ; |
wire upd_e_alu8 ; |
wire up_e_src_pqr ; |
wire up_h_add16 ; |
wire upd_h_alu8 ; |
wire upd_h_src_pqr ; |
wire up_l_add16 ; |
wire upd_l_alu8 ; |
wire upd_l_src_pqr ; |
|
wire upd_fr_alu8 ; |
wire upd_fr_add16 ; |
wire upd_fr_edadd16 ; |
wire upd_fr_sh ; |
wire upd_fr_cbsh ; |
wire eb_blk_mv ; |
|
//-------1---------2---------3--------Registers------------6---------7---------8---------9--------0 |
|
reg [7:0] ar, fr, br, cr, dr, er, hr, lr, intr; |
reg [7:0] ap, fp, bp, cp, dp, ep, hp, lp; |
reg [15:0] ixr, iyr; |
//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0 |
|
// it appears that dd and fd as a prefix to cb has a significantly modfied fuction...... |
// specifically, it is assumed that a memory operation is to be implemented (ix + d) |
// , In fact the |
// pipeline is such that we can make a fetch for free - so we will do that..... the |
// prefix flags should not be set here -- all we will know on execution is that it is a |
// cb instruction. ---- src is always nn |
|
|
assign src_hr = dd_grp ? ixr[15:8] : |
fd_grp ? iyr[15:8] : |
hr ; |
|
assign src_lr = dd_grp ? ixr[7:0] : |
fd_grp ? iyr[7:0] : |
lr ; |
|
assign src_dblhr = dd_grp ? ixr : // ed grp instructions (ADC HL ; SBC HL are not affected - |
fd_grp ? iyr : // instruction assembler assures this - ed_grp has no prefix |
{hr, lr} ; |
|
assign src_cb_r20 = (ddcb_grp | fdcb_grp) ? nn[7:0] : |
cb_grp ? src_pqr20 : |
ar ; |
|
|
assign src_pqr20 = {8{ir2[2:0]==REG8_B }} & br | |
{8{ir2[2:0]==REG8_C }} & cr | |
{8{ir2[2:0]==REG8_D }} & dr | |
{8{ir2[2:0]==REG8_E }} & er | |
{8{ir2[2:0]==REG8_H }} & src_hr | |
{8{ir2[2:0]==REG8_L }} & src_lr | |
{8{ir2[2:0]==REG8_MEM}} & nn[7:0] | |
{8{ir2[2:0]==REG8_A }} & ar ; |
|
assign src_pqr53 = {8{ir2[5:3]==REG8_B }} & br | |
{8{ir2[5:3]==REG8_C }} & cr | |
{8{ir2[5:3]==REG8_D }} & dr | |
{8{ir2[5:3]==REG8_E }} & er | |
{8{ir2[5:3]==REG8_H }} & src_hr | |
{8{ir2[5:3]==REG8_L }} & src_lr | |
{8{ir2[5:3]==REG8_MEM}} & nn[7:0] | |
{8{ir2[5:3]==REG8_A }} & ar ; |
|
|
assign src_dbl = {16{ir2[5:4]==2'b00}} & {br, cr} | |
{16{ir2[5:4]==2'b01}} & {dr, er} | |
{16{ir2[5:4]==2'b10}} & src_sshr | |
{16{ir2[5:4]==2'b11}} & sp ; |
|
|
|
|
|
// I wonder how well the synthesizer can reduce this??? - It is probably worth spending |
// some time during physical design to see if a more low level description would help -- |
// there is somebody out there who knows - and there is probably a good low level description. |
// |
// guess its kind of important to understand precisely what the synthesizer does |
// with some of the status things we need also. |
// |
// |
// The nastiest status to get is HF. Really need 4 bit adders to do that ( or reproduce a lot |
// of logic.) I don't have a lot of confdence in the synthesier's ability to minimize arithmetic |
// operations -- Its a moving target of course, but I've seen some really silly stuff come out |
// of synthesis when you use a "+" operator. guess I will be pretty explicit here. |
// Documentation of the HF is srange. IN and OUT operators are defined as X -- but 16 bit operations |
// get set by CRY from bit 11. (Do I care??? ) well probably not but it is documented - so should |
// be tested i guess. |
// |
// |
// may want to re-define as a module with carry look-ahead ? |
// |
// Had a notion to define a single adder - subtractor for both 8 and 16 bit operations, but |
// getting into source mux issues that solution scared me..... Worry the cry flag might |
// become a worst case path. As defined, a good chunk of the decode process can go on in |
// parallel with the cry computation --- with final decisions made using a small mux at |
// the flag register. |
// ------------ 8 bit adder for accumulator ops plus the INC DEC ops --------------------- |
// It is documented that the hf is modified by the INC and DEC ops even if ar is not the |
// destination of result --- clearly hf and nf are pretty usless on a INC B but ours is |
// not to reason why :-) ---- well its fun to bitch about silly stuff like this. |
// ( not as much fun to deal with instruction tests testing "features" -- or worse programmers |
// who figure out ways to use theses "features". ) |
// |
// 8 bit adder with cry out of bit 3 used for most operations on A as well as the |
// inc/dec instructions. also need to get ED44 (ar <= -ar) working here |
wire [7:0] src_pqri; // use just here and below |
wire [7:0] src_aor_cnst = ed_blk_cp ? ar : // CPI CPIR CPD CPDR |
ed_grp ? 8'h0 : // for ed44 -a |
ir2[7] ? ar : |
ir2[0] ? 8'hff : |
8'h00 ; |
|
//--------------- the "standard" flag logic ----------------------------- |
// sf zf f5f hf |
assign alu8_fr ={alu8_out[7], ~|alu8_out, alu8_out[5], alu8_hcry, |
// f3f fpv fn fc |
alu8_out[3], alu8_out[7], alu8_nf, c_8out7 }; |
|
//assign alu8_pvf = (ir2[7:3]==5'b10100 | ir2[7:3]==5'b10101 | ir2[7:3]==5'b10110) ? |
// ~^alu8_out : // even parity |
// (src_aor_cnst[7]==src_pqri[7]) & (src_aor_cnst[7]!=alu8_out[7]) ; // ofl |
|
assign alu8_nf = (ir2[7:3]==5'b10010) | |
(ir2[7:3]==5'b10011) | |
(ir2[7:6]==2'b00) & ir2[0] | |
ed_grp ; |
|
|
assign {c_8out3, add_8bit[3:0]} = {1'b0, src_aor_cnst[3:0]} + {1'b0, src_pqri[3:0]} + {4'b0, c_8in0}; |
//wire [4:0] ha_temp = {1'b0, src_aor_cnst[3:0]} + {1'b0, src_pqri[3:0]} + {4'b0, c_8in0}; |
//assign c_8out3 |
|
assign {c_8out7, add_8bit[7:4]} = {1'b0, src_aor_cnst[7:4]} + {1'b0, src_pqri[7:4]} + {4'b0, c_8out3}; |
|
// notice that both inputs and outputs of the adder are being selected below. |
// making ed_blk_cp high priority kind of negates the origional idea of making the |
// decodes fast here --- course when all is included this can't be too fast. |
// Just note for syntheses that this is a slow path that could be improved with some thought. |
// |
assign {alu8_cry, alu8_hcry, alu8_out, src_pqri, c_8in0 }= |
|
ed_blk_cp ? {c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1} : //CPI CPIR CPD CPDR |
|
{14{ir2[7:3]==5'b10000}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, 1'b0} ) |// a+src |
{14{ir2[7:3]==5'b10001}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, cf} ) |// a+src+cf |
{14{ir2[7:3]==5'b10010}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1} ) |// a-src |
{14{ir2[7:3]==5'b10011}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, ~cf } ) |// a-src-cf |
{14{ir2[7:3]==5'b10100}} & ({1'b0 ,1'b1 , ar & src_pqr, src_pqr20, 1'b0} ) |// a&src |
{14{ir2[7:3]==5'b10101}} & ({1'b0 ,1'b0 , ar ^ src_pqr, src_pqr20, 1'b0} ) |// a^src |
{14{ir2[7:3]==5'b10110}} & ({1'b0 ,1'b0 , ar | src_pqr, src_pqr20, 1'b0} ) |// a|src |
{14{ir2[7:3]==5'b10111}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, 1'h1}) |// a-src |
{14{(ir2[7:6]==2'b00)& ~ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h1}) |// inc_r main |
{14{(ir2[7:6]==2'b00)& ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h0}) |// dec_r |
{14{(ir2[7:6]==2'b01) }}& ({c_8out7,c_8out3, add_8bit, ~a, 1'h1}) ;// ed44 -a |
|
|
// do some hand decoding here |
// ADDsHL_BC = 'h09, DECsBC = 'h0B, INCsBC = 'h03 compair with {ir2[7:6],ir2[3:0]} |
// ADDsHL_DE = 'h19, DECsDE = 'h1B INCsDE = 'h13 ED_SBCsHL_REG = 6'b01__0010 |
// ADDsHL_HL = 'h29, DECsHL = 'h2B INCsHL = 'h23 ED_ADCsHL_REG = 6'b01__1010 |
// ADDsHL_SP = 'h39, DECsSP = 'h3B INCsSP = 'h33 |
// by inspection just use ir2[3:0] - i guess in a pinch we do't need ir2[2] = but let the |
// synthesizer figure that out. - it should be able to. |
// |
|
|
// ---------------- 16 bit adder with bit 11 carrry out and bit 8 carry in ------------------ |
// |
assign add16_ofl = (src_a[15] == src_b[15]) & (src_a[15] != add16[15]); |
|
assign {c_16out7, add16[7:0]} = {1'b0, src_a[7:0]} + {1'b0, src_b[7:0] } + {8'b0, c_16in0}; |
assign {c_16out11, add16[11:8]} = {1'b0, src_a[11:8]} + {1'b0, src_b[11:8] } + {4'b0, c_16out7}; |
assign {c_16out15, add16[15:12]} = {1'b0, src_a[15:12]} + {1'b0, src_b[15:12]} + {4'b0, c_16out11}; |
|
assign { src_a, src_b, c_16in0} = |
{17{ir2[3:0] == 4'h9}} & {src_dblhr, src_dbl ,1'b0 } | //ADD |
{17{ir2[3:0] == 4'hb}} & {16'hffff , src_dbl ,1'b0 } | //DEC |
{17{ir2[3:0] == 4'h3}} & {16'h0001 , src_dbl ,1'b0 } | //INC |
{17{ir2[3:0] == 4'h2}} & {src_dblhr, ~src_dbl , ~cf } | //SBC |
{17{ir2[3:0] == 4'ha}} & {src_dblhr, src_dbl , cf } ; //ADC |
|
//-------------------------- sh alu -------------------------------------------------- |
// shift insructions. Think of these as 8 shift types: |
// RLC RL RRC RR SLA SLL SRA SRL The SLL types appear to be undocumented -- but possibly used |
// in assembly code as they appear to have some utility - and by all accounts operate reliably. |
// The first four are implemented in a single byte inaruction . (A <= sh_op A ) |
// All 8 are implemented in the CB group with all registers as potential sources (and dests). |
// if dd_grp or fd_grp is prefix..... source is always the memory. This is undocumented - but |
// may be a useful hint for simplyfing the total machine. Destination registers |
// (if any) get a copy of the updated memory location (This is also true of the bit set and |
// clear instructions in the cb_grp. |
|
assign {sh_cry, sh_alu} = {9{ir2[5:3]==3'b000}} & {sh_src, sh_src[7] } | //RLC |
{9{ir2[5:3]==3'b001}} & {sh_src[0], sh_src[0], sh_src[7:1]} | // RRC |
{9{ir2[5:3]==3'b010}} & {sh_src, cf } | //RL |
{9{ir2[5:3]==3'b011}} & {sh_src[0], cf, sh_src[7:1] } | // RR |
{9{ir2[5:3]==3'b100}} & {sh_src, 1'b0} | //SLA |
{9{ir2[5:3]==3'b101}} & {sh_src[0], sh_src[7], sh_src[7:1]} | //SRA |
{9{ir2[5:3]==3'b110}} & {sh_src, 1-b1} | //SLL |
{9{ir2[5:3]==3'b111}} & {sh_src[0], 1'b0, sh_src[7:1]} ; //SRL |
|
|
// shift insts |
assign sh_alu_act = ir2[9:6] == 4'b0100; |
//CB_RLC = 7'b01_00_000, // these must be compaired with ir2[9:3] |
//CB_RRC = 7'b01_00_001, // these must be compaired with ir2[9:3] |
//CB_RL = 7'b01_00_010, // these must be compaired with ir2[9:3] |
//CB_RR = 7'b01_00_011, // these must be compaired with ir2[9:3] |
//CB_SLA = 7'b01_00_100, // these must be compaired with ir2[9:3] |
//CB_SRA = 7'b01_00_101, // these must be compaired with ir2[9:3] |
//CB_SLL = 7'b01_00_110, // these must be compaired with ir2[9:3] |
//CB_SRL = 7'b01_00_111, // these must be compaired with ir2[9:3] |
|
//---------------------------- bit test alu --------------------------------------- |
// bit test insts |
//CB_BIT = 4'b01_01, // these must be compaired with ir2[9:6] |
//CB_RES = 4'b01_10, // these must be compaired with ir2[9:6]assign |
//CB_SET = 4'b01_11, // these must be compaired with ir2[9:6] |
assign bit_alu_act = ir2[9:6] == CB_BIT | |
ir2[9:6] == CB_RES | |
ir2[9:6] == CB_RES ; |
|
wire bit_decode = {8{ir2[5:3] == 3'h0}} & 8'h01 | |
{8{ir2[5:3] == 3'h1}} & 8'h02 | |
{8{ir2[5:3] == 3'h2}} & 8'h04 | |
{8{ir2[5:3] == 3'h3}} & 8'h08 | |
{8{ir2[5:3] == 3'h4}} & 8'h10 | |
{8{ir2[5:3] == 3'h5}} & 8'h20 | |
{8{ir2[5:3] == 3'h6}} & 8'h40 | |
{8{ir2[5:3] == 3'h7}} & 8'h80 ; |
|
assign bit_alu = {8{ir2[9:6] == CB_BIT}} & ( sh_src & bit_decode) | |
{8{ir2[9:6] == CB_RES}} & ( sh_src & ~bit_decode) | |
{8{ir2[9:6] == CB_RES}} & ( shPsrc | bit_decode) ; |
|
|
//------------ dec bc alu --------------------------------------------- |
//exec_decbc; these are all we know (in general) |
//exec_decb; |
assign decc_alu = cr + 8'hff ; |
assign decb_alu = br + ( exec_decb ? 8'hff : // just dec b if io blk move |
cr_eq0 ? 8'hff : // cry out if c in this case |
8'h00 ); // only dec c reg this tick |
// ------------------ daa alu ------------------------------------------------------- |
// the documentation does not cover all cases here -- only those that matter (i suppose). |
// ( documentation assumes you are operating with 2 daa'd numbers -- but of course the |
// ar can contain many values that don't fit that assumption when this instruction is executed. |
// Any arbitrary instruction test may test un-documented cases. |
// |
// this leaves me to guess what the actual logic is - and how to match it. |
// So I am doing that -- see what happens. If an instruction test breaks this... I should be |
// able to fix it easily. |
// |
wire [3:0] ls_nbl = (!nf & hf) ? 4'h6: |
(!nf & (ar[3:0] > 4'h9)) ? 4'h6: |
(nf & hf ) ? 4'ha: |
4'h0; |
|
wire [4:0] ms_nbl = (!nf & cf) ? 5'h16: // includes new cry |
(!nf & (ar[3:0] > 4'h9)) ? 5'h16: |
(!nf & (ar[3:0] == 4'h9) & |
(ar[3:0] > 4'h9)) ? 5'h16: |
(nf & !cf & hf ) ? 5'h0f: |
(nf & cf & !hf ) ? 5'h1a: |
(nf & cf & hf ) ? 5'h19: |
5'h00; |
|
|
assign {daa_cry, daa_alu} = { ms_nbl[4], {ar + { ms_nbl[3:0], ls_nbl}} } ; |
|
|
//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0 |
|
// update ar |
|
assign upd_a_alu8 = |
ADDsA_B == ir2 | SUBsB == ir2 | ANDsB == ir2 | ORsB == ir2 | |
ADDsA_C == ir2 | SUBsC == ir2 | ANDsC == ir2 | ORsC == ir2 | |
ADDsA_D == ir2 | SUBsD == ir2 | ANDsD == ir2 | ORsD == ir2 | |
ADDsA_E == ir2 | SUBsE == ir2 | ANDsE == ir2 | ORsE == ir2 | |
ADDsA_H == ir2 | SUBsH == ir2 | ANDsH == ir2 | ORsH == ir2 | |
ADDsA_L == ir2 | SUBsL == ir2 | ANDsL == ir2 | ORsL == ir2 | |
ADDsA_6HL7 == ir2 | SUBs6HL7 == ir2 | ANDs6HL7 == ir2 | ORs6HL7 == ir2 | |
ADDsA_A == ir2 | SUBsA == ir2 | ANDsA == ir2 | ORsA == ir2 | |
ADCsA_B == ir2 | SBCsB == ir2 | XORsB == ir2 | |
ADCsA_C == ir2 | SBCsC == ir2 | XORsC == ir2 | INCsA == ir2 | |
ADCsA_D == ir2 | SBCsD == ir2 | XORsD == ir2 | DECsA == ir2 | |
ADCsA_E == ir2 | SBCsE == ir2 | XORsE == ir2 | |
ADCsA_H == ir2 | SBCsH == ir2 | XORsH == ir2 | |
ADCsA_L == ir2 | SBCsL == ir2 | XORsL == ir2 | |
ADCsA_6HL7 == ir2 | SBCs6HL7 == ir2 | XORs6HL7 == ir2 | |
ADCsA_A == ir2 | SBCsA == ir2 | XORsA == ir2 | |
ADDsA_N == ir2 | // ADD A,N ; C6 XX ADDsA_6HL7 = 'h86 |
ADCsA_N == ir2 | // ADC A,N ; CE XX ADCsA_6HL7 = 'h8E |
SUBsN == ir2 | // SUB N ; D6 XX SUBs6HL7 = 'h96 |
SBCsA_N == ir2 | // SBC A,N ; DE XX |
ANDsN == ir2 | // AND N ; E6 XX |
XORsN == ir2 | // XOR N ; EE XX |
ORsN == ir2 ; // OR N ; F6 XX |
assign up_a_sh_alu = |
RLCA == ir2 | // RLCA ; 07 |
RRCA == ir2 | // RRCA ; 0F |
RRA == ir2 | // RRA ; 1F |
RLA == ir2 ; // RLA ; 17 |
assign up_a_src_pqr = |
LDsA_B == ir2 | // LD A,B ; 78 |
LDsA_C == ir2 | // LD A,C ; 79 |
LDsA_D == ir2 | // LD A,D ; 7A |
LDsA_E == ir2 | // LD A,E ; 7B |
LDsA_H == ir2 | // LD A,H ; 7C |
LDsA_L == ir2 | // LD A,L ; 7D |
LDsA_6HL7 == ir2 | // LD A,(HL) ; 7E |
LDsA_A == ir2 ; // LD A,A ; 7F |
assign up_a_n = |
LDsA_N == ir2 | // LD A,N ; 3E XX |
LDsA_6BC7 == ir2 | // LD A,(BC) ; 0A |
LDsA_6DE7 == ir2 | // LD A,(DE) ; 1A |
LDsA_6NN7 == ir2 | // LD A,(NN) ; 3A XX XX |
INsA_6N7 == ir2 | // IN A,(N) ; DB XX |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_A) ; |
|
|
//EXsAF_AFp = 10'h08,// EX AF,AF' ; 08 |
//EXX = 10'hD9,// EXX ; D9 |
//DAA = 10'h27,// DAA ; 27 |
//CPL = 10'h2F,// CPL ; 2F a <= ~a |
//POPsAF = 10'hF1,// POP AF ; F1 |
// don't forget these beauties not affected by prefixes |
//ED_RRD = 'h67// RRD ; compair with {ir2[9:6],ir2[3:0]} all |
//ED_RLD = 'h6F// RLD ; ED 6F nibble roates A (HL) |
//ED_NEG = 5'b01___100, // A<= -A compair with {ir2[9:6],ir2[2:0]} |
|
//------------------------------- ar ------------------------------------------ |
|
assign upd_ar = upd_a_alu8 | up_a_sh_alu | up_a_src_pqr | up_a_n | ir2 == EXsAF_AFp | |
ir2 == EXX | ir2 == DAA | ir2 == CPL | ir2 == POPsAF | |
ir2[2:0] == REG8_A & bit_alu_act | ir2[2:0] == REG8_A & sh_alu_act | |
{ir2[9:6], ir2[3:0]} == ED_RRD | {ir2[9:6], ir2[2:0]} == ED_NEG | |
ir2 == ED_LDsA_I ; |
|
always @(posedge clk) |
begin |
if (upd_a_alu8 & exec_ir2) ar <= alu8_out; |
if (up_a_sh_alu & exec_ir2) ar <= sh_alu; |
if (up_a_src_pqr & exec_ir2) ar <= src_pqr; |
if (up_a_n & exec_ir2) ar <= nn[7:0]; |
if (ir2 == EXsAF_AFp & exec_ir2) ar <= ap; |
if (ir2 == EXX & exec_ir2) ar <= ap; |
if (ir2 == DAA & exec_ir2) ar <= daa_alu; |
if (ir2 == CPL & exec_ir2) ar <= ~ar; |
if (ir2 == POPsAF & exec_ir2) ar <= nn[15:8]; |
if (ir2[2:0] == REG8_A & |
bit_alu_act & exec_ir2) ar <= bit_alu; |
if (ir2[2:0] == REG8_A & |
sh_alu_act & exec_ir2) ar <= sh_alu; |
if ({ir2[9:6], ir2[3:0]} == ED_RRD & exec_ir2) ar[3:0] <= nn[3:0]; |
if ({ir2[9:6], ir2[3:0]} == ED_RLD & exec_ir2) ar[3:0] <= nn[7:4]; |
if ({ir2[9:6], ir2[2:0]} == ED_NEG & exec_ir2) ar <= alu8_out; // ED44 this done by alu8 for flags |
if (ir2 == ED_LDsA_I & exec_ir2) ar <= ir2 ; |
end |
|
|
|
|
// update br |
//assign upd_b_decbc = |
// ED_LDI == ir2 | // LDI ; ED A0 |
// ED_CPI == ir2 | // CPI ; ED A1 |
// ED_LDD == ir2 | // LDD ; ED A8 |
// ED_CPD == ir2 | // CPD ; ED A9 |
// ED_LDIR == ir2 | // LDIR ; ED B0 |
// ED_CPIR == ir2 | // CPIR ; ED B1 |
// ED_LDDR == ir2 | // LDDR ; ED B8 |
// ED_CPDR == ir2 ;// CPDR ; ED B9 |
|
//assign eb_io = |
|
// ED_INI == ir2 | // INI ; ED A2 |
// ED_IND == ir2 | // IND ; ED AA |
// ED_OUTD == ir2 | // OUTD ; ED AB |
// ED_OUTI == ir2 | // OUTI ; ED A3 |
// ED_INIR == ir2 | // INIR ; ED B2 |
// ED_OTIR == ir2 | // OTIR ; ED B3 |
// ED_INDR == ir2 | // INDR ; ED BA |
// ED_OTDR == ir2 ; // OTDR ; ED BB |
|
assign upd_b_alu8 = |
INCsB == ir2 |// INC B ; 04 |
DECsB == ir2 ;// DEC B ; 05 |
|
|
assign up_b_src_pqr = |
LDsB_B == ir2 |// LD B,B ; 40 |
LDsB_C == ir2 |// LD B,C ; 41 |
LDsB_D == ir2 |// LD B,D ; 42 |
LDsB_E == ir2 |// LD B,E ; 43 |
LDsB_H == ir2 |// LD B,H ; 44 |
LDsB_L == ir2 |// LD B,L ; 45 |
LDsB_6HL7 == ir2 |// LD B,(HL) ; 46 |
LDsB_A == ir2 ;// LD B,A ; 47 |
assign up_b_add16 = |
INCsBC == ir2 |// INC BC ; 03 |
DECsBC == ir2 ;// DEC BC ; 0B |
//LDsBC_nn = 10'h01,// LD BC,NN ; 01 XX XX |
//POPsBC = 10'hC1,// POP BC ; C1 |
//EXX = 10'hD9,// EXX ; D9 |
//LDsB_N = 10'h06,// LD B,N ; 06 XX |
//DJNZs$t2 = 10'h10,// DJNZ $+2 ; 10 XX //pre dec br |
//ED_RRD = 'h67// RRD ; ED 67 nibble roates A HL |
//ED_RLD = 'h6F// RLD ; ED 6F nibble roates A HL |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
|
//------------------------------- br ----------------------------------------- |
|
assign upd_br = upd_b_alu8 | up_b_src_pqr | up_b_add16 | LDsBC_NN == ir2 | |
POPsBC == ir2 | EXX == ir2 | LDsB_N == ir2 | |
ir2[2:0] == REG8_B & bit_alu_act | ir2[2:0] == REG8_B & sh_alu_act | |
DJNZs$t2 == ir2 | (ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_B); |
|
|
always @(posedge clk) |
begin |
if ( upd_b_alu8 & exec_ir2) br <= alu8_out; |
if ( up_b_src_pqr & exec_ir2) br <= src_pqr; |
if ( up_b_add16 & exec_ir2) br <= add16[15:8]; |
if ( LDsBC_NN == ir2 & exec_ir2) br <= nn[15:8]; |
if ( POPsBC == ir2 & exec_ir2) br <= nn[15:8]; |
if ( EXX == ir2 & exec_ir2) br <= bp; |
if ( LDsB_N == ir2 & exec_ir2) br <= nn[7:0]; |
if (ir2[2:0] == REG8_B & |
bit_alu_act & exec_ir2) br <= bit_alu; |
if (ir2[2:0] == REG8_B & |
sh_alu_act & exec_ir2) br <= sh_alu; |
if ( DJNZs$t2 == ir2 & exec_ir2) br <= br + 8'hff; // use seperate adder here as no flags |
// change -- we need br==0. for now |
// use |br. If we need more speed add |
// a ff. |
if (exec_decb | exec_decbc) br <= decb_alu; |
if ( (ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_B) & exec_ir2 ) |
br <= nn[7:0]; |
end |
|
|
// update cr |
assign up_c_add16 = |
INCsBC == ir2 |// INC BC ; 03 |
DECsBC == ir2 ;// DEC BC ; 0B, |
assign upd_c_alu8 = |
INCsC == ir2 |// INC C ; 0C |
DECsC == ir2 ;// DEC C ; 0D |
assign up_c_src_pqr = |
LDsC_B == ir2 |// LD C,B ; 48 |
LDsC_C == ir2 |// LD C,C ; 49 |
LDsC_D == ir2 |// LD C,D ; 4A |
LDsC_E == ir2 |// LD C,E ; 4B |
LDsC_H == ir2 |// LD C,H ; 4C |
LDsC_L == ir2 |// LD C,L ; 4D |
LDsC_6HL7 == ir2 |// LD C,(HL) ; 4E |
LDsC_A == ir2 ;// LD C,A ; 4F |
|
|
//LDsC_N == ir2 |// LD C,N ; 0E XX |
//LDsBC_NN = 10'h01,// LD BC,NN ; 01 XX XX |
//POPsBC = 10'hC1,// POP BC ; C1 |
//EXX = 10'hD9,// EXX ; D9 |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
|
//------------------------------- cr ----------------------------------------- |
assign upd_cr = upd_c_alu8 | up_c_src_pqr | up_c_add16 | LDsBC_NN == ir2 | |
POPsBC == ir2 | EXX == ir2 | LDsC_N == ir2 | |
ir2[2:0] == REG8_C & bit_alu_act | ir2[2:0] == REG8_C & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_C); |
|
|
|
always @(posedge clk) |
begin |
if ( upd_c_alu8 & exec_ir2) cr <= alu8_out; |
if ( up_c_src_pqr & exec_ir2) cr <= src_pqr; |
if ( up_c_add16 & exec_ir2) cr <= add16[7:0]; |
if ( LDsBC_NN == ir2 & exec_ir2) cr <= nn[7:0]; |
if ( POPsBC == ir2 & exec_ir2) cr <= nn[7:0]; |
if ( EXX == ir2 & exec_ir2) cr <= cp; |
if ( LDsC_N == ir2 & exec_ir2) cr <= nn[7:0]; |
if (ir2[2:0] == REG8_C & |
bit_alu_act & exec_ir2) cr <= bit_alu; |
if (ir2[2:0] == REG8_C & |
sh_alu_act & exec_ir2) cr <= sh_alu; |
if ( exec_decbc) cr <= decc_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_C) & exec_ir2) |
cr <= nn[7:0]; |
|
end |
|
|
// update dr |
assign up_d_add16 = |
INCsDE == 10'h13 | // INC DE ; 13 |
DECsDE == 10'h1B ; // DEC DE ; 1B |
|
assign upd_d_alu8 = |
INCsD == 10'h14 | // INC D ; 14 |
DECsD == 10'h15 ; // DEC D ; 15 |
assign up_d_src_pqr = |
LDsD_B == ir2 | //LD D,B ; 50 |
LDsD_C == ir2 | //LD D,C ; 51 |
LDsD_D == ir2 | //LD D,D ; 52 |
LDsD_E == ir2 | //LD D,E ; 53 |
LDsD_H == ir2 | //LD D,H ; 54 |
LDsD_L == ir2 | //LD D,L ; 55 |
LDsD_6HL7 == ir2 | //LD D,(HL) ; 56endmodule |
LDsD_A == ir2 ; //LD D,A ; 57 |
|
|
//LDsD_N = 10'h16,// LD D,N ; 16 XX |
//LDsDE_NN = 10'h11,// LD DE,NN ; 11 XX XX |
//POPsDE = 10'hD1,// POP DE ; D1 |
//EXX = 10'hD9,// EXX ; D9 |
//EXsDE_HL = 10'hEB,// EX DE,HL ; EB |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
|
//---------------------------------- dr ------------------------------------ |
|
assign upd_dr = upd_d_alu8 | up_d_src_pqr | up_d_add16 | LDsDE_NN == ir2 | |
POPsDE == ir2 | EXX == ir2 | EXsDE_HL == ir2 | LDsD_N == ir2 | |
ir2[2:0] == REG8_D & bit_alu_act | ir2[2:0] == REG8_D & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_D); |
|
|
|
|
|
|
always @(posedge clk) |
begin |
if ( upd_d_alu8 & exec_ir2) dr <= alu8_out; |
if ( up_d_src_pqr & exec_ir2) dr <= src_pqr; |
if ( up_d_add16 & exec_ir2) dr <= add16[15:8]; |
if ( LDsDE_NN == ir2 & exec_ir2) dr <= nn[15:8]; |
if ( POPsDE == ir2 & exec_ir2) dr <= nn[15:8]; |
if ( EXX == ir2 & exec_ir2) dr <= dp; |
if ( EXsDE_HL == ir2 & exec_ir2) dr <= hr; |
if ( LDsD_N == ir2 & exec_ir2) dr <= nn[7:0]; |
if (ir2[2:0] == REG8_D & |
bit_alu_act & exec_ir2) dr <= bit_alu; |
if (ir2[2:0] == REG8_D & |
sh_alu_act & exec_ir2) dr <= sh_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) |
& (ir2[5:3] == REG8_D) & exec_ir2) |
dr <= nn[7:0]; |
|
end |
|
// update er |
assign up_e_add16 = |
INCsDE == ir2 |// INC DE ; 13 |
DECsDE == ir2 ;// DEC DE ; 1B |
assign upd_e_alu8 = |
INCsE == ir2 |// INC E ; 1C |
DECsE == ir2 ;// DEC E ; 1D |
assign up_e_src_pqr = |
LDsE_B == ir2 |// LD E,B ; 58 |
LDsE_C == ir2 |// LD E,C ; 59 |
LDsE_D == ir2 |// LD E,D ; 5A |
LDsE_E == ir2 |// LD E,E ; 5B |
LDsE_H == ir2 |// LD E,H ; 5C |
LDsE_L == ir2 |// LD E,L ; 5D |
LDsE_6HL7 == ir2 |// LD E,(HL) ; 5E |
LDsE_A == ir2 ;// LD E,A ; 5F |
|
//LDsE_N = 10'h1E,// LD E,N ; 1E XX |
//LDsDE_NN = 10'h11,// LD DE,NN ; 11 XX XX |
//POPsDE = 10'hD1,// POP DE ; D1 |
//EXX = 10'hD9,// EXX ; D9 |
//EXsDE_HL = 10'hEB,// EX DE,HL ; EB |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
|
//---------------------------------- er ------------------------------------ |
|
|
assign upd_er = upd_e_alu8 | up_e_src_pqr | up_e_add16 | LDsDE_NN == ir2 | |
POPsDE == ir2 | EXX == ir2 | EXsDE_HL == ir2 | LDsD_N == ir2 | |
ir2[2:0] == REG8_E & bit_alu_act | ir2[2:0] == REG8_E & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_E); |
|
|
|
|
|
|
|
|
|
always @(posedge clk) |
begin |
if ( upd_e_alu8 & exec_ir2) er <= alu8_out; |
if ( up_e_src_pqr & exec_ir2) er <= src_pqr; |
if ( up_e_add16 & exec_ir2) er <= add16; |
if ( LDsDE_NN == ir2 & exec_ir2) er <= nn[7:0]; |
if ( POPsDE == ir2 & exec_ir2) er <= nn[7:0]; |
if ( EXX == ir2 & exec_ir2) er <= ep; |
if ( EXsDE_HL == ir2 & exec_ir2) er <= hr; |
if ( LDsE_N == ir2 & exec_ir2) er <= nn[7:0]; |
if (ir2[2:0] == REG8_E & |
bit_alu_act & exec_ir2) er <= bit_alu; |
if (ir2[2:0] == REG8_E & |
sh_alu_act & exec_ir2) er <= sh_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_E) & exec_ir2) |
er <= nn[7:0]; |
|
end |
|
|
// update hr |
assign up_h_add16 = |
ADDsHL_BC == ir2 | // ADD HL,BC ; 09 |
ADDsHL_DE == ir2 | // ADD HL,DE ; 19 |
ADDsHL_HL == ir2 | // ADD HL,HL ; 29 |
ADDsHL_SP == ir2 | // ADD HL,SP ; 39 |
INCsHL == ir2 | // INC HL ; 23 |
DECsHL == ir2 ; // DEC HL ; 2B |
assign upd_h_alu8 = |
INCsH == ir2 | // INC H ; 24 |
DECsH == ir2 ; // DEC H ; 25 |
assign upd_h_src_pqr = |
LDsH_B == ir2 | // LD H,B ; 60 |
LDsH_C == ir2 | // LD H,C ; 61 |
LDsH_D == ir2 | // LD H,D ; 62 |
LDsH_E == ir2 | // LD H,E ; 63 |
LDsH_H == ir2 | // LD H,H ; 64 |
LDsH_L == ir2 | // LD H,L ; 65 |
LDsH_6HL7 == ir2 | // LD H,(HL) ; 66 |
LDsH_A == ir2 ; // LD H,A ; 67 |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
|
//POPsHL = 10'hE1,// POP HL ; E1 |
//EXs6SP7_HL = 10'hE3,// EX (SP),HL ; E3 |
//LDsHL_NN = 10'h21,// LD HL,NN ; 21 XX XX |
//LDsHL_6NN7 = 10'h2A,// LD HL,(NN) ; 2A XX XX |
//LDsH_N = 10'h26,// LD H,N ; 26 XX |
|
// only these are not affected by dd and fd prefixes |
//EXsDE_HL = 10'hEB,// EX DE,HL ; EB |
//EXX = 10'hD9,// EXX ; D9 |
|
//---------------------------------- hr ------------------------------------ |
// we just check hr and lr - the prefixes for use of ix and iy imply that something |
// pretty strange has to happen for a hazard related to use of those registers. We can |
// assume upd hr impies upd ix and iy without adverse timing consequences. |
// |
assign upd_hr = upd_h_alu8 | up_h_src_pqr | up_h_add16 | LDsHL_NN == ir2 | LDsHL_6NN7== ir2 | |
POPsHL == ir2 | EXX == ir2 | EXsDE_HL == ir2 | LDsH_N == ir2 | |
ir2[2:0] == REG8_H & bit_alu_act | ir2[2:0] == REG8_H & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_H); |
|
|
|
|
wire exec_hlir2 = exec_ir2 & !(dd_grp | fd_grp); |
|
always @(posedge clk) |
begin |
if ( upd_h_alu8 & exec_hlir2) hr <= alu8_out; |
if ( up_h_src_pqr & exec_hlir2) hr <= src_pqr; |
if ( up_h_add16 & exec_hlir2) hr <= add16[15:8]; |
if ( LDsHL_NN == ir2 & exec_hlir2) hr <= nn[15:8]; |
if ( LDsHL_6NN7== ir2 & exec_hlir2) hr <= nn[15:8]; |
if ( POPsHL == ir2 & exec_hlir2) hr <= nn[15:8]; |
if ( EXs6SP7_HL== ir2 & exec_hlir2) hr <= nn[15:8]; |
if ( EXX == ir2 & exec_ir2) hr <= hp; |
if ( EXsDE_HL == ir2 & exec_ir2) hr <= dr; |
if ( LDsH_N == ir2 & exec_hlir2) hr <= nn[7:0]; |
if (ir2[2:0] == REG8_H & |
bit_alu_act & exec_hlir2) hr <= bit_alu; |
if (ir2[2:0] == REG8_H & |
sh_alu_act & exec_hlir2) hr <= sh_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_H) & exec_ir2) |
hr <= nn[7:0]; |
|
end |
|
// update lr |
assign up_l_add16 = |
ADDsHL_BC == ir2 |// ADD HL,BC ; 09 |
ADDsHL_DE == ir2 |// ADD HL,DE ; 19 |
ADDsHL_HL == ir2 |// ADD HL,HL ; 29 |
ADDsHL_SP == ir2 |// ADD HL,SP ; 39 |
INCsHL == ir2 |// INC HL ; 23 |
DECsHL == ir2 ;// DEC HL ; 2B |
assign upd_l_alu8 = |
INCsL == ir2 |// INC L ; 2C |
DECsL == ir2 ;// DEC L ; 2D |
assign upd_l_src_pqr = |
LDsL_B == ir2 |// LD L,B ; 68 |
LDsL_C == ir2 |// LD L,C ; 69 |
LDsL_D == ir2 |// LD L,D ; 6A |
LDsL_E == ir2 |// LD L,E ; 6B |
LDsL_H == ir2 |// LD L,H ; 6C |
LDsL_L == ir2 |// LD L,L ; 6D |
LDsL_6HL7 == ir2 |// LD L,(HL) ; 6E |
LDsL_A == ir2 ;// LD L,A ; 6F |
//EXX = 10'hD9,// EXX ; D9 |
//POPsHL = 10'hE1,// POP HL ; E1 |
//EXs6SP7_HL = 10'hE3,// EX (SP),HL ; E3 |
//EXsDE_HL = 10'hEB,// EX DE,HL ; EB |
//LDsHL_NN = 10'h21,// LD HL,NN ; 21 XX XX |
//LDsHL_6NN7 = 10'h2A,// LD HL,(NN) ; 2A XX XX |
//LDsL_N = 10'h2E,// LD L,N ; 2E XX |
//ED_INsREG_6C7 |
|
|
|
//---------------------------------- lr ------------------------------------ |
assign upd_lr = upd_l_alu8 | up_l_src_pqr | up_l_add16 | LDsHL_NN == ir2 | LDsHL_6NN7== ir2 | |
POPsHL == ir2 | EXX == ir2 | EXsDE_HL == ir2 | LDsL_N == ir2 | |
ir2[2:0] == REG8_L & bit_alu_act | ir2[2:0] == REG8_L & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_L); |
|
|
|
always @(posedge clk) |
begin |
if ( upd_l_alu8 & exec_hlir2) lr <= alu8_out; |
if ( up_l_src_pqr & exec_hlir2) lr <= src_pqr; |
if ( up_l_add16 & exec_hlir2) lr <= add16[7:0]; |
if ( LDsHL_NN == ir2 & exec_hlir2) lr <= nn[7:0]; |
if ( LDsHL_6NN7== ir2 & exec_hlir2) lr <= nn[7:0]; |
if ( POPsHL == ir2 & exec_hlir2) lr <= nn[7:0]; |
if ( EXs6SP7_HL== ir2 & exec_hlir2) lr <= nn[7:0]; |
if ( EXX == ir2 & exec_ir2) lr <= lp; |
if ( EXsDE_HL == ir2 & exec_ir2) lr <= er; |
if ( LDsL_N == ir2 & exec_hlir2) lr <= nn[7:0]; |
if (ir2[2:0] == REG8_L & |
bit_alu_act & exec_hlir2) lr <= bit_alu; |
if (ir2[2:0] == REG8_L & |
sh_alu_act & exec_hlir2) lr <= sh_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_L) & exec_ir2) |
lr <= nn[7:0]; |
|
end |
//------------------------ ixr --------------------------------------------- |
wire exec_ixir2 = exec_ir2 & dd_grp; |
always @(posedge clk) |
begin |
if ( upd_l_alu8 & exec_ixir2) ixr[7:0] <= alu8_out; |
if ( up_l_src_pqr & exec_ixir2) ixr[7:0] <= src_pqr; |
if ( up_l_add16 & exec_ixir2) ixr[7:0] <= add16[7:0]; |
if ( LDsHL_NN == ir2 & exec_ixir2) ixr[7:0] <= nn[7:0]; |
if ( LDsHL_6NN7== ir2 & exec_ixir2) ixr[7:0] <= nn[7:0]; |
if ( POPsHL == ir2 & exec_ixir2) ixr[7:0] <= nn[7:0]; |
if ( EXs6SP7_HL== ir2 & exec_ixir2) ixr[7:0] <= nn[7:0]; |
|
if ( LDsL_N == ir2 & exec_ixir2) ixr[7:0] <= nn[7:0]; |
if (ir2[2:0] == REG8_L & |
bit_alu_act & exec_ixir2) ixr[7:0] <= bit_alu; |
if (ir2[2:0] == REG8_L & |
sh_alu_act & exec_ixir2) ixr[7:0] <= sh_alu; |
|
end |
|
always @(posedge clk) |
begin |
if ( upd_h_alu8 & exec_ixir2) ixr[15:8] <= alu8_out; |
if ( up_h_src_pqr & exec_ixir2) ixr[15:8] <= src_pqr; |
if ( up_h_add16 & exec_ixir2) ixr[15:8] <= add16[15:8]; |
if ( LDsHL_NN == ir2 & exec_ixir2) ixr[15:8] <= nn[15:8]; |
if ( LDsHL_6NN7== ir2 & exec_ixir2) ixr[15:8] <= nn[15:8]; |
if ( POPsHL == ir2 & exec_ixir2) ixr[15:8] <= nn[15:8]; |
if ( EXs6SP7_HL== ir2 & exec_ixir2) ixr[15:8] <= nn[15:8]; |
|
if ( LDsH_N == ir2 & exec_ixir2) ixr[15:8] <= nn[7:0]; |
if (ir2[2:0] == REG8_H & |
bit_alu_act & exec_ixir2) ixr[15:8] <= bit_alu; |
if (ir2[2:0] == REG8_H & |
sh_alu_act & exec_ixir2) ixr[15:8] <= sh_alu; |
|
end |
|
//------------------------ iyr --------------------------------------------- |
wire exec_iyir2 = exec_ir2 & fd_grp; |
always @(posedge clk) |
begin |
if ( upd_l_alu8 & exec_iyir2) iyr[7:0] <= alu8_out; |
if ( up_l_src_pqr & exec_iyir2) iyr[7:0] <= src_pqr; |
if ( up_l_add16 & exec_iyir2) iyr[7:0] <= add16[7:0]; |
if ( LDsHL_NN == ir2 & exec_iyir2) iyr[7:0] <= nn[7:0]; |
if ( LDsHL_6NN7== ir2 & exec_iyir2) iyr[7:0] <= nn[7:0]; |
if ( POPsHL == ir2 & exec_iyir2) iyr[7:0] <= nn[7:0]; |
if ( EXs6SP7_HL== ir2 & exec_iyir2) iyr[7:0] <= nn[7:0]; |
|
if ( LDsL_N == ir2 & exec_iyir2) iyr[7:0] <= nn[7:0]; |
if (ir2[2:0] == REG8_L & |
bit_alu_act & exec_iyir2) iyr[7:0] <= bit_alu; |
if (ir2[2:0] == REG8_L & |
sh_alu_act & exec_iyir2) iyr[7:0] <= sh_alu; |
|
end |
|
always @(posedge clk) |
begin |
if ( upd_h_alu8 & exec_iyir2) iyr[15:8] <= alu8_out; |
if ( up_h_src_pqr & exec_iyir2) iyr[15:8] <= src_pqr; |
if ( up_h_add16 & exec_iyir2) iyr[15:8] <= add16[15:8]; |
if ( LDsHL_NN == ir2 & exec_iyir2) iyr[15:8] <= nn[15:8]; |
if ( LDsHL_6NN7== ir2 & exec_iyir2) iyr[15:8] <= nn[15:8]; |
if ( POPsHL == ir2 & exec_iyir2) iyr[15:8] <= nn[15:8]; |
if ( EXs6SP7_HL== ir2 & exec_iyir2) iyr[15:8] <= nn[15:8]; |
|
if ( LDsH_N == ir2 & exec_iyir2) iyr[15:8] <= nn[7:0]; |
if (ir2[2:0] == REG8_H & |
bit_alu_act & exec_iyir2) iyr[15:8] <= bit_alu; |
if (ir2[2:0] == REG8_H & |
sh_alu_act & exec_iyir2) iyr[15:8] <= sh_alu; |
|
end |
|
|
//---------------------------- prime regiters (shadows?) ---------------- |
|
always @(posedge clk) |
begin |
if (ir2 == EXsAF_AFp & exec_ir2) |
begin |
ap <= ar; |
fp <= fr; |
end |
if (ir2 == EXX & exec_ir2) |
begin |
ap <= ar; |
fp <= fr; |
bp <= br; |
cp <= cr; |
dp <= dr; |
ep <= er; |
hp <= hr; |
lp <= lr; |
end |
end |
//-------------------------- flag registers ------------------------------- |
// This is a mess - There is in general no reasonable way to get this stuff to follow |
// z80 exactly. --- in some of the undocumented cases, there is not even a |
// guess expressed about what is actually done. In some of the other undocumented |
// cases, what is claimed happens is soo silly that It is hard for me to believe |
// it matters ( unfortunately i am far too aware that one man's garbage can be |
// anothers treasure --- or....., its amazing how silly |
// behavior (bug?) can become a feature. In any case, The attempt (at first blush) is |
// only to get the documented stuff right -- although if undocumented behavior |
// falls out, great. For exmple, I will typically update f3f and f5f with alu output - |
// these flags are documented as "undefined". |
// |
// some of the wierd stuff to worry about: |
// 16 bit ops: |
// the ed insts SBC ADC muck with all flags but |
// the ADD inst doesn't change sf zf or pvf. |
// and the 16 bit INC and DEC insts touch nothing |
// |
// the ED_RLD and RRD instructions muck with flags based on ar -- these operations |
// should be correct rleative to subsequent DAA's i suppose. |
|
// update all flags from alu8 for logic operations pv <= parity else ofl |
// INC and DEC same as but no cf change oh my god why? done in logic above |
|
assign upd_fr_alu8 = |
ADCsA_A == ir2 | ANDsA == ir2 | ORsA == ir2 | SUBsA == ir2 | DECsA == ir2 | |
ADCsA_B == ir2 | ANDsB == ir2 | ORsB == ir2 | SUBsB == ir2 | DECsB == ir2 | |
ADCsA_C == ir2 | ANDsC == ir2 | ORsC == ir2 | SUBsC == ir2 | DECsC == ir2 | |
ADCsA_D == ir2 | ANDsD == ir2 | ORsD == ir2 | SUBsD == ir2 | DECsD == ir2 | |
ADCsA_E == ir2 | ANDsE == ir2 | ORsE == ir2 | SUBsE == ir2 | DECsE == ir2 | |
ADCsA_H == ir2 | ANDsH == ir2 | ORsH == ir2 | SUBsH == ir2 | DECsH == ir2 | |
ADCsA_L == ir2 | ANDsL == ir2 | ORsL == ir2 | SUBsL == ir2 | DECsL == ir2 | |
ADCsA_6HL7==ir2 | ANDs6HL7 ==ir2 | ORs6HL7 ==ir2 | SUBs6HL7 ==ir2 | INCsA == ir2 | |
ADDsA_A == ir2 | CPsA == ir2 | SBCsA == ir2 | XORsA == ir2 | INCsB == ir2 | |
ADDsA_B == ir2 | CPsB == ir2 | SBCsA_6HL7==ir2 | XORsB == ir2 | INCsC == ir2 | |
ADDsA_C == ir2 | CPsC == ir2 | SBCsB == ir2 | XORsC == ir2 | INCsD == ir2 | |
ADDsA_D == ir2 | CPsD == ir2 | SBCsC == ir2 | XORsD == ir2 | INCsE == ir2 | |
ADDsA_E == ir2 | CPsE == ir2 | SBCsD == ir2 | XORsE == ir2 | INCsH == ir2 | |
ADDsA_H == ir2 | CPsH == ir2 | SBCsE == ir2 | XORsH == ir2 | INCsL == ir2 | |
ADDsA_L == ir2 | CPsL == ir2 | SBCsH == ir2 | XORsL == ir2 | INCs6HL7 == ir2 | |
ADDsA_6HL7== ir2| CPs6HL7 ==ir2 | SBCsL == ir2 | XORs6HL7 == ir2 | DECs6HL7 == ir2 | |
ED_NEG == {ir2[9:6],ir2[2:0]} ; //7'b1001___100, A<= -A |
|
|
|
// update h n c (f5, f3) from alu16 |
assign upd_fr_add16 = |
ADDsHL_BC == ir2 | // ADD HL,BC ; 09 |
ADDsHL_DE == ir2 | // ADD HL,DE ; 19 |
ADDsHL_HL == ir2 | // ADD HL,HL ; 29 |
ADDsHL_SP == ir2 ; // ADD HL,SP ; 39 |
// INCsBC == ir2 | // INC BC ; 03 no flag changes for these |
// INCsDE == ir2 | // INC DE ; 13 |
// INCsHL == ir2 | // INC HL ; 23 |
// INCsSP == ir2 ; // INC SP ; 33 |
|
// update all flags from alu16 |
assign upd_fr_edadd16 = |
ED_SBCsHL_REG == {ir2[7:6],ir2[3:0]} | // compair with {ir2[7:6],ir2[3:0]} |
ED_ADCsHL_REG == {ir2[7:6],ir2[3:0]} ; // compair with {ir2[7:6],ir2[3:0]} |
|
|
// the shifts probably muck with all flags (some operations are |
// guarenteed not to change certain flags ) |
// docs say sf and zf never change for these ops. |
assign upd_fr_sh = |
RLA == ir2 |// RLA ; 17 |
RLCA == ir2 |// RLCA ; 07 |
RRA == ir2 |// RRA ; 1F |
RRCA == ir2 ;// RRCA ; 0F |
// sf and zf do change for theses |
assign upd_fr_cbsh = |
CB_RLC == ir2[9:3] | // these must be compaired with ir2[9:3] |
CB_RRC == ir2[9:3] | // these must be compaired with ir2[9:3] |
CB_RL == ir2[9:3] | // these must be compaired with ir2[9:3] |
CB_RR == ir2[9:3] | // these must be compaired with ir2[9:3] |
CB_SLA == ir2[9:3] | // these must be compaired with ir2[9:3] |
CB_SRA == ir2[9:3] | // these must be compaired with ir2[9:3] |
CB_SLL == ir2[9:3] | // these must be compaired with ir2[9:3] |
CB_SRL == ir2[9:3] ; // these must be compaired with ir2[9:3] |
|
// pretty nomal stuff here |
//CB_BIT = 4'b01_01, // these must be compaired with ir2[9:6] |
// which alu? -- done from alu8 |
//ED_NEG = 5'b01___100, // compair with {ir2[7:6],ir2[2:0]} all A<= -A |
|
// rmw 8 types these handled by standard INC and DEC logic done. |
//INCs6HL7 = 'h34,// INC (HL) ; 34 |
//DECs6HL7 = 'h35,// DEC (HL) ; 35 |
|
// ED Block Move messyness upd_b_decbc |
// hf and nf <= 0 pnf<= BC==0 |
assign eb_blk_mv = |
ED_LDI == ir2 | // LDI ; ED A0 (DE++) <= (HL++) , BC-- |
ED_LDD == ir2 | // LDD ; ED A8 (DE--) <= (HL--) , BC-- |
ED_LDIR == ir2 | // LDIR ; ED B0 (DE++) <= (HL++) , BC-- Repeat til BC==0 |
ED_LDDR == ir2 ;// LDDR ; ED B8 (DE--) <= (HL--) , BC-- Repeat til BC==0 |
// only c not affected - nf<=1 ? |
assign ed_blk_cp = |
ED_CPI == ir2 | // CPI ; ED A1 A - (HL++) , BC-- |
ED_CPD == ir2 | // CPD ; ED A9 A - (HL--) , BC-- |
ED_CPIR == ir2 | // CPIR ; ED B1 A - (HL++) , BC-- repeat if(|B |
ED_CPDR == ir2 ;// CPDR ; ED B9 A - (HL--) , BC-- repeat if(|B |
|
// all the ed i/o muck with all flags -- wonderful cf? |
// use the aluoutput for the b-1 computation. |
// --------- eb_io |
//ED_INI = 'hA2// INI ; ED A2 (HL++) <- (Cio) , B-- |
//ED_IND = 'hAA// IND ; ED AA (HL--) <- (Cio) , B-- |
//ED_INIR = 'hB2// INIR ; ED B2 (HL++) <- (Cio) , B-- repeat if(|B) |
//ED_INDR = 'hBA// INDR ; ED BA (HL--) <- (Cio) , B-- repeat if(|B) |
//ED_OUTI = 'hA3// OUTI ; ED A3 (Cio) <-(HL++) , B-- |
//ED_OUTD = 'hAB// OUTD ; ED AB (Cio) <-(HL--) , B-- |
//ED_OTIR = 'hB3// OTIR ; ED B3 (Cio) <-(HL++) , B-- rpt if(|B) |
//ED_OTDR = 'hBB// OTDR ; ED BB (Cio) <-(HL--) , B-- rpt if(|B) |
|
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
|
|
|
// special problems -- lol more special problems ???? |
//CCF = 'h3F,// CCF ; 3F // h<=c c<=~C N<=0 F3,F5? |
//CPL = 'h2F,// CPL ; 2F // H<=1 N<=1 F3,F5? |
//DAA = 'h27,// DAA ; 27 // H<=0??? |
//SCF = 'h37,// SCF ; 37 |
//ED_RRD = 'h67// RRD ; ED 67 nibble roates A HL |
//ED_RLD = 'h6F// RLD ; ED 6F nibble roates A HL |
//ED_LDsA_I = 'h57// LD A,I ; ED 57 move I to A |
|
assign { sf, zf, f5f, hf, f3f, pvf, nf, cf} = fr; |
// gotta say those little ~^ operators down there worry me. Only 4 levels of xor - but jeeze |
// there are a lot of them. I guess in most FPGA's it doesn't matter what the op is - just |
// how many terms. |
|
|
// do we need the exe_ir2 term here? isn't it added in the hazard term anyway? |
assign upd_fr = exec_ir2 & ( ( upd_fr_alu8 ) | |
( upd_fr_add16) | |
( upd_fr_edadd16) | |
( upd_fr_sh ) | |
( upd_fr_cbsh ) | |
(CB_BIT == ir2[9:6]) | |
( ed_blk_cp ) | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) | |
(CCF == ir2 ) | |
(CPL == ir2 ) | |
(DAA == ir2 ) | |
(SCF == ir2 ) | |
(ED_RRD == ir2) | |
(ED_RLD == ir2) | |
(ED_LDsA_I == ir2) ) ; |
|
|
|
wire iff2 = 1'b0; // this is supposed to be int ff #2 which is not (yet) implmented |
always @(posedge clk) |
begin |
if (exec_ir2) |
begin |
if ( upd_fr_alu8 ) fr <= alu8_fr; // assembled above with 8 bit ALU |
if ( upd_fr_add16) fr <= {sf, zf, add16[13], c_16out11, add16[11], pvf, 1'b0, c_16out15}; |
if ( upd_fr_edadd16) fr <= {add16[15], ~|add16, add16[13], c_out11, |
add16[11], add16_ofl, ~ir2[3], c_16out15}; |
if ( upd_fr_sh ) fr <= {sf, zf, sh_alu[5], 1'b0, sh_alu[3], pvf, 1'b0, sh_cry}; |
if ( upd_fr_cbsh ) fr <= {sh_alu[7], ~|sh_alu, sh_alu[5], 1'b0, |
sh_alu[3], ~^sh_alu, 1'b0, sh_cry}; |
if (CB_BIT == ir2[9:6]) fr <={bit_alu[7], ~|bit_alu, bit_alu[5], 1'b1, //no idea why hf<=1 |
bit_alu[3], ~|bit_alu, 1'b0 , cf };// pvf == zf ??? |
if ( ed_blk_cp ) fr <= {alu8_out[7], ~|alu8_out, alu8_out[5], alu8_hcry,//std a-n stuff |
alu8_out[3], alu8_out[7], 1'b1, cf }; //cept nf and cf |
if (ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) |
fr <= {nn[7], ~|nn[7:0], nn[5], 1'b0, nn[3], ~^nn[7:0], 1'b0, cf}; |
if (CCF == ir2 ) fr <= {sf, zf, f5f, cf, f3f, pvf, nf, ~cf}; |
if (CPL == ir2 ) fr <= {sf, zf, ar[5], 1'b1, ar[3], pvf, 1'b1, cf}; |
if (DAA == ir2 ) fr <= {daa_alu[7], ~|daa_alu, daa_alu[5], 1'b0, // hf sb (logically) 0 |
daa_alu[3], ~^daa_alu, nf, daa_cry }; |
if (SCF == ir2 ) fr <= { sf, zf, ar[5], 1'b0, ar[3], pvf, 1'b0, 1'b1 }; // very strange |
if (ED_RRD == ir2) fr <= { sf, ~|{ar[7:4],nn[3:0]}, ar[5], 1'b0, |
ar[3], ~^{ar[7:4],nn[3:0]}, 1'b0 , cf }; |
if (ED_RLD == ir2) fr <= { sf, ~|{ar[7:4],nn[7:4]}, ar[5], 1'b0, |
ar[3], ~^{ar[7:4],nn[7:4]}, 1'b0 , cf }; |
if (ED_LDsA_I == ir2) fr <= { ir2[7], ~|ir2, ir2[5], 1'b0, ir2[3], iff2, 1'b0, cf }; // iff2 ? |
|
end |
// in the case of blk_cp the update above is executed 2nd - and so these are don't cares. |
if (exec_decb ) fr <= {decb_alu[7], ~|decb_alu, decb_alu[5], hf, |
decb_alu[3], pvf, 1'b0, cf }; |
if (exec_decbc ) fr[5:1] <= { decb_alu[5], 1'b0, decb_alu[3], ~|decb_alu, 1'b0 }; |
end |
|
|
//----------------------- intr ----------------------------------------------------------- |
|
always @(posedge clk) |
begin |
if (( ED_LDsI_A == ir2) & exec_ir2) intr <= ar; |
end |
|
|
endmodule |
/tags/arelease/rtl/memstate2.v
0,0 → 1,1598
/////////////////////////////////////////////////////////////////////////////////////////////////// |
// // |
// file name: memstate2.v // |
// description: memory opertions for z80 // |
// project: wb_z80 // |
// // |
// Author: B.J. Porcella // |
// e-mail: bporcella@sbcglobal.net // |
// // |
// // |
// // |
/////////////////////////////////////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2000-2002 B.J. Porcella // |
// Real Time Solutions // |
// // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY // |
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED // |
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS // |
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR // |
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, // |
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES // |
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE // |
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // |
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // |
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // |
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT // |
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // |
// POSSIBILITY OF SUCH DAMAGE. // |
// // |
//-------1---------2---------3--------Comments on file -------------7---------8---------9--------0 |
// The memory state controller controls the wb bus, and provides address sequencing. |
// Insructions are fetched in order (using PC) until the istate machine indicates that |
// a complete instruction is in the first pipline stage (ir1). In general, operands are being |
// fetched (stored) to satisfy ir1 while concurrently instructions are being executed from ir2. |
// this situation can result in a number of potential hazards. As an example, if the ir2 |
// instruction changes the flag register and the ir1 instruction is a conditional jump, |
// a hazard is generated by the hazard logic, and execution of the ir1 operation is delayed |
// until the completion of the flag update. |
// |
// Reset starts execution at 0. |
// The PC and SP are described in this file. modifications to other index registers - |
// HL IX and IY are computed here -- |
// For the block moves address updates are computed here -- and commanded here. |
// Strobes for the second address update are generally co-incident with count updates, but |
// we provide seperate strobe update lines for clarity. |
// |
// BASIC ARCHITECTURE OF THIS FILE pc and sp not shown, but are inputs to src mux. |
// _____ and may be updated from adder output. |
// | | |
// | | pc-1 register is required to implement relative jumps. |
// | | |
// _____ |lit | |\ |
// | | | | | \ |
// | | |src2 | | \ _____ _____ |
// | | | |----->| | | | | | |
// |src | |_____| |adder|------->| | | | |
// |mux | | | | | | | |
// | |------------------->| / |2/1 |------->|wb | |
// | | | | / |mux | |adr | |
// |_____| | |/ | | | | |
// ------------------->| | | | |
// |_____| |_____| |
// |
// |
// |
// |
// Operand Stores: |
// At first cut, I thought I'ld execute operand stores immediately from the memory sequencer |
// (essentially before ir2 got the store data). While this might be modestly faster in |
// systems that take multiple clocks to complete a memory store, On consideration, I decided |
// to forgo the extra speed for conceptual simplicity.... execute operand stores on op_ph1, |
// and let the inst_exec engine suply the operand. |
// |
// On second thought, above is not only wastful of time, but also inconsistent with the overall |
// schems of things - and so somewhat more complex. If we simply execute the OS from ir1, |
// There is less state to contdend with, as well as extra speed. |
// |
// Block Moves fundamentally execute from ir2. We initiate the first operand fetch from ir1. |
// |
// 3/18/2004 Second time through. In impleenting the execution logic it became clear that |
// there were "minor" problems with the handling of the DD and FD prefix insts (especially |
// DDCD and FDCB --- collectively called PFxCB below. On review, I had to question the |
// value of "breaking up" the ir0 execution engine between the istate sequencer and the |
// memstate sequencer. While I dislike state sequencers of much more than 16 states -- |
// the interaction between these sequencers was becomming harder to track than a single |
// state macine. Thus - this file is getting re-worked. I will call it memstate2 (at least |
// for awhile) as I wish to keep the old file around. I want to show (in the state machine |
// logic) what the next memory operation is.... guess the best method consistent with my |
// documentation practices is to define a register (mem_op) = { if, wb_we, wb_cyc }. |
// This will require auxillary logic for computing the address --- but most of the decodes |
// required will be there anyway. |
// On further reflection, I think I will bite-the-bullet and use an always to define next_state. |
// I don't like to use always to define wires, but I also want to dicument the setting of |
// exec_ir2 in the same place - that is 3 different things. |
// |
// Hazards: |
// There are 2 kinds of hazards: mem_hazard => we are storing into the next instruction location |
// reg_hazard => we are modifying a register (ir2) that we are using |
// here (ir1) |
// In the former case, we throw out the instruction that arrives on the next tick, and restart the |
// instruction pipeline, In the latter case, we simply wait a tick for the ir2 operaton to |
// complete before starting the ir1 operation |
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0 |
// |
// $Id: memstate2.v,v 1.1.1.1 2004-06-18 08:38:46 mihal Exp $ |
// |
// $Date: 2004-06-18 08:38:46 $ |
// $Revision: 1.1.1.1 $ |
// $Author: mihal $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2004/04/16 18:16:57 bporcella |
// try lint |
// |
// Revision 1.3 2004/04/16 17:06:54 bporcella |
// no code change - added a comment and test lint |
// |
// Revision 1.2 2004/04/16 16:21:04 bporcella |
// no code change - added a comment and test lint |
// |
// Revision 1.1.1.1 2004/04/13 23:50:19 bporcella |
// import first files |
// |
// |
// |
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0 |
module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o, add_out, |
exec_ir2, ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp, |
|
upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr, |
beq0, ceq0, |
ar, fr, br, cr, dr, er, hr, lr, |
ixr, iyr, |
wb_dat_i, wb_ack, clk, rst, |
wb_int_rq, |
add16 |
|
|
); |
|
//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0 |
// mod only to checkout lint |
// mod again for lint check -- first check pretty wierd |
// 3rd lint try |
output [15:0] wb_adr; |
output wb_we; |
output wb_cyc; |
output wb_stb; |
output wb_lock; // bit set and clear insts should be atomic - could matter sometime |
output wb_tga_io; |
output wb_dat_o; // from nn |
output [15:0] add_out; // output of adder (may not wb_adr) |
|
output exec_ir2; |
output [9:0] ir1, ir2; |
output ir1dd, ir2dd; |
output ir1fd, ir2fd; |
output [15:0] nn; |
output [15:0] sp; |
|
|
|
|
//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0 |
input upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr; |
|
input beq0, ceq0; |
input [7:0] ar, fr, br, cr, dr, er, hr, lr; |
input [15:0] ixr, iyr; |
input [7:0] wb_dat_i; |
input wb_ack, clk, rst; |
input wb_int_rq; |
input [15:0] add16; // ir2 execution engine output for sp updates |
|
|
//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0 |
`include "opcodes.v" // states of the main memory sequencer |
|
|
parameter TAG_IO = 2'b01, // need to review general wb usage to undrstand how best to |
TAG_INT = 2'b10; // document this. |
// 12na |
parameter IPIPE_NOP = 4'b0000, |
IPIPE_A2 = 4'b0001, |
IPIPE_ENN = 4'b0010, |
IPIPE_ENNA2 = 4'b0011, |
IPIPE_EN2 = 4'b0100, |
IPIPE_EN2A2 = 4'b0101, |
IPIPE_ENNEN2 = 4'b0110, |
IPIPE_ENNEN2A2 = 4'b0111, |
IPIPE_EN1 = 4'b1000, |
IPIPE_EN1A2 = 4'b1001, |
IPIPE_BOGUS = 4'b1010, // no reason (yet) to load both n and ir1 |
IPIPE_BOUS2 = 4'b1011, |
IPIPE_EN12 = 4'b1100, |
IPIPE_EN12A2 = 4'b1101, |
IPIPE_BOGUS3 = 4'b1110, |
IPIPE_BOGUS4 = 4'b1111; |
|
// well at first cut I tried to make this 2 state macines both less than 16 states. |
// this is 56 states at first cut. Assignemnt is subject to change. |
|
// ------ mem state decoder state machine states -------------------------------- |
parameter DEC_IDLE = 6'h00, |
DEC_HALT = 6'h01, |
DEC_IF1 = 6'h02, |
DEC_IF2 = 6'h03, |
DEC_IF2A = 6'h04, |
DEC_EXEC = 6'h05, |
DEC_CB = 6'h06, |
DEC_DDFD = 6'h07, |
DEC_ED = 6'h08, |
DEC_EDNN1 = 6'h09, |
DEC_EDNN2 = 6'h0a, |
DEC_EDRD1 = 6'h0b, |
DEC_EDRD2 = 6'h0c, |
DEC_EDWR = 6'h0d, |
DEC_EDBCP1 = 6'h0e, |
DEC_EDBCP2 = 6'h0f, |
DEC_EDBCP3 = 6'h10, |
DEC_EDBIN1 = 6'h11, |
DEC_EDBIN2 = 6'h12, |
DEC_EDBIN3 = 6'h13, |
DEC_EDBOUT1 = 6'h14, |
DEC_EDBOUT2 = 6'h15, |
DEC_EDBOUT3 = 6'h16, |
DEC_EDBMV1 = 6'h17, |
DEC_EDBMV2 = 6'h18, |
DEC_EDBMV3 = 6'h19, |
DEC_N = 6'h1a, |
DEC_NIN = 6'h1b, |
DEC_NN = 6'h1c, |
DEC_NNCALL1 = 6'h1d, |
DEC_NNCALL2 = 6'h1e, |
DEC_NNOS1 = 6'h1f, |
DEC_NNOS2 = 6'h20, |
DEC_NNOS3 = 6'h21, |
DEC_NNOF1 = 6'h22, |
DEC_NNOF2 = 6'h23, |
DEC_NNOF3 = 6'h24, |
DEC_NNOF4 = 6'h25, |
DEC_DDOS = 6'h26, |
DEC_DDOF = 6'h27, |
DEC_OF = 6'h28, |
DEC_POP = 6'h29, |
DEC_PUSH = 6'h2a, |
DEC_RMW = 6'h2b, |
DEC_RMW2 = 6'h2c, |
DEC_CBM = 6'h2d, |
DEC_PFxCB = 6'h2e, |
DEC_PFxCB2 = 6'h2f, |
DEC_PFxCB3 = 6'h30, |
DEC_PFxCB4 = 6'h31, |
DEC_INT1 = 6'h32, |
DEC_INT2 = 6'h33, |
DEC_INT3 = 6'h34, |
DEC_INT4 = 6'h35, |
DEC_INT5 = 6'h36, |
DEC_RET = 6'h37, |
DEC_NNJMP = 6'h38, |
DEC_RET2 = 6'h39 ; |
|
// initial decode assignemnts. These assignemens are made to wires on an initial decode |
// to help document next state transitions |
parameter I1_CB = 4'h0, |
I1_DDFD = 4'h1, |
I1_ED = 4'h2, |
I1_JMP = 4'h3, |
I1_N = 4'h4, |
I1_NN = 4'h5, |
I1_OF = 4'h6, |
I1_OS = 4'h7, |
I1_POP = 4'h8, |
I1_PUSH = 4'h9, |
I1_RET = 4'ha, |
I1_RMW = 4'hb, |
I1_RST = 4'hc, |
I1_R2R = 4'hd ; |
|
|
// A note here on the choices of mnemonics..... in general, the target registers of |
// memory ops are specified by an instruction register (ir1 for stores ir2 for loads). |
// so Menomics in general are specifying the address source. However, there are exceptions. |
// |
parameter MEM_NOP = 5'h00, |
MEM_IFPP1 = 5'h01, |
MEM_OS1 = 5'h02, // only invoked on I1 OS multiple address sources and data sources |
MEM_OF1 = 5'h03, // Address from HL unless LD A,(BC) or LD A,(DE) (used for rmw) |
MEM_OFSP = 5'h04, // works for both POP and RET |
MEM_OSSP = 5'h05, // if DEC_EXEC op from ir1 else msb nn (implies we store from lsb nn) |
// used in CALL also. |
MEM_OFIXpD = 5'h06, // used for prefix op fetches - all single bytes |
MEM_OSIXpD = 5'h07, // data source is same as MEM_OS1 |
MEM_OSADR = 5'h08, // used (at lesat) for prefixed rmw -- perhaps others. |
|
MEM_CALL = 5'h09, // pc<=nn, nn<=pc, wb_adr<=sp OS |
MEM_OSNN = 5'h0a, // if DEC_EXEC op from ir1 else msb nn |
MEM_OFNN = 5'h0b, // striaghtfoward |
MEM_OFADRP1 = 5'h0c, // used (at least) when double ops above |
MEM_OSADRP1 = 5'h0d, // "" "" "" |
|
MEM_IFRST = 5'h0e, // special address transfer |
MEM_IFREL_N = 5'h0f, // special address transfer for jmp rel |
MEM_JMPHL = 5'h10, // another special jump transfer |
MEM_IFNN = 5'h11, // used by call and return |
|
|
MEM_OFHL_PM = 5'h12, // special block move ops |
MEM_OSHL_PM = 5'h13, // special block move ops |
MEM_OSDE_PM = 5'h14, // special block move ops |
|
MEM_IOF_C = 5'h15, // special i/o ops |
MEM_IOS_C = 5'h16, // operand is ar |
MEM_IOF_N = 5'h17, |
MEM_IOS_N = 5'h18, |
MEM_OS_HL_N = 5'h19, |
|
MEM_OSSP_PCM2 = 5'h1a, // int code (call |
MEM_OSSP_P = 5'h1b, // |
MEM_INTA = 5'h1c, |
MEM_IFINT = 5'h1d, |
MEM_DECPC = 5'h1e ; |
|
|
|
|
|
|
|
|
|
//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0 |
|
|
wire use_sp; |
wire use_pc; |
wire use_hl; |
wire use_de; |
wire use_bc; |
wire use_flags; |
wire cb_mem; |
wire br_test8t; // branch test true (8 test field) |
wire br_test4t; // branch test true (4 test field) |
|
wire ofos; |
wire any_os; // most terms above only valid on mem_exec this includes all stores |
wire wb_rdy_nhz; |
wire dec_blk_inc; |
wire we_next; |
wire hazard; |
wire wb_int; |
wire [15:0] hl, de, bc; |
wire mem_exec_dec; |
|
wire use_a ; |
wire use_b ; |
wire use_c ; |
wire use_d ; |
wire use_e ; |
wire use_h ; |
wire use_l ; |
// don't forget that as 1r1 is executed it is transferred to ir2. Anything I need to know |
// about subsequent operations must be stored. |
// 6 5 4 15 |
// assign {next_dec_state, next_mem_state, next_pipe_state} = next_state; |
wire [5:0] next_dec_state; |
wire [4:0] next_mem_state; |
wire [3:0] next_pipe_state; |
wire ed_dbl_rd; |
//-------1---------2---------3--------Registers------------6---------7---------8---------9--------0 |
|
reg [15:0] pc; |
reg [15:0] sp; |
reg [15:0] wb_adr; |
reg wb_we; |
reg wb_cyc; |
reg wb_stb; |
reg wb_lock; |
reg wb_tga_io; |
|
reg blk_inc_flg; |
reg [9:0] ir1, ir2; |
reg ir1dd, ir2dd; |
reg ir1fd, ir2fd; |
reg [15:0] nn; |
|
reg [15:0] next_state; // a wire assigned in an alowys loop. |
|
reg [5:0] dec_state; // the register set each clock from next_dec_state; |
|
reg of16_reg, os16_reg, rmw8_reg, call_reg, ret_reg, ioi; |
reg push_reg; |
reg pop_reg; |
reg inst_haz; |
reg exec_ir2; |
reg blk_rpt_flg; |
reg blk_io_flg; |
reg flag_os1; |
reg int_en, en_int_next; |
reg wb_irq_sync; |
//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0 |
// |
// ir is 10 bits most significant codes ir1[9:8] = { EDgrp, CBgrp } DDgrp and FDgrp are modifiers |
|
|
assign wb_dat_o = nn[15:8]; |
|
wire sf, zf, f5f, hf, f3f, pvf, nf, cf; |
assign { sf, zf, f5f, hf, f3f, pvf, nf, cf} = fr; |
|
|
assign hl = {hr, lr}; |
assign de = {dr, er}; |
assign bc = {br, cr}; |
|
|
// this "groups" the instructions to determine first memory operation |
|
parameter I1DCNT = 4; // parameter used below simply to make possible change easier. |
assign mem_exec_dec = |
{I1DCNT {CBgrp == ir1}} & I1_CB |// CBgrp is rotates and bi |
{I1DCNT {DDgrp == ir1}} & I1_DDFD|// DDgrp |
{I1DCNT {FDgrp == ir1}} & I1_DDFD|// FDgrp FD |
{I1DCNT {EDgrp == ir1}} & I1_ED |// EDgrp ED |
{I1DCNT {JPsHL == ir1}} & I1_JMP |// JP HL ; E9 // doc |
{I1DCNT {ADCsA_N == ir1}} & I1_N |// ADC A,N ; CE XX |
{I1DCNT {ADDsA_N == ir1}} & I1_N |// ADD A,N ; C6 XX |
{I1DCNT {ANDsN == ir1}} & I1_N |// AND N ; E6 XX |
{I1DCNT {CPsN == ir1}} & I1_N |// CP N ; FE XX |
{I1DCNT {INsA_6N7 == ir1}} & I1_N |// IN A,(N) ; DB XX |
{I1DCNT {JRs$t2 == ir1}} & I1_N |// JR $+2 ; 18 XX |
{I1DCNT {JRsC_$t2 == ir1}} & I1_N |// JR C,$+2 ; 38 XX |
{I1DCNT {JRsNC_$t2 == ir1}} & I1_N |// JR NC,$+2 ; 30 XX |
{I1DCNT {JRsZ_$t2 == ir1}} & I1_N |// JR Z,$+2 ; 28 XX |
{I1DCNT {JRsNZ_$t2 == ir1}} & I1_N |// JR NZ,$+2 ; 20 XX |
{I1DCNT {LDs6HL7_N == ir1}} & I1_N |// LD (HL),N ; 36 XX |
{I1DCNT {LDsA_N == ir1}} & I1_N |// LD A,N ; 3E XX |
{I1DCNT {LDsB_N == ir1}} & I1_N |// LD B,N ; 06 XX |
{I1DCNT {LDsC_N == ir1}} & I1_N |// LD C,N ; 0E XX |
{I1DCNT {LDsD_N == ir1}} & I1_N |// LD D,N ; 16 XX |
{I1DCNT {LDsE_N == ir1}} & I1_N |// LD E,N ; 1E XX |
{I1DCNT {LDsH_N == ir1}} & I1_N |// LD H,N ; 26 XX |
{I1DCNT {LDsL_N == ir1}} & I1_N |// LD L,N ; 2E XX |
{I1DCNT {ORsN == ir1}} & I1_N |// OR N ; F6 XX |
{I1DCNT {OUTs6N7_A == ir1}} & I1_N |// OUT (N),A ; D3 XX |
{I1DCNT {SBCsA_N == ir1}} & I1_N |// SBC A,N ; DE XX |
{I1DCNT {SUBsN == ir1}} & I1_N |// SUB N ; D6 XX |
{I1DCNT {XORsN == ir1}} & I1_N |// XOR N ; EE XX |
{I1DCNT {CALLsC_NN == ir1}} & I1_NN |// CALL C,NN ; DC XX XX |
{I1DCNT {CALLsNC_NN == ir1}} & I1_NN |// CALL NC,NN ; D4 XX XX |
{I1DCNT {CALLsNN == ir1}} & I1_NN |// CALL NN ; CD XX XX |
{I1DCNT {CALLsNZ_NN == ir1}} & I1_NN |// CALL NZ,NN ; C4 XX XX |
{I1DCNT {CALLsPE_NN == ir1}} & I1_NN |// CALL PE,NN ; EC XX XX |
{I1DCNT {CALLsPO_NN == ir1}} & I1_NN |// CALL PO,NN ; E4 XX XX |
{I1DCNT {CALLsP_NN == ir1}} & I1_NN |// CALL P,NN ; F4 XX XX |
{I1DCNT {CALLsZ_NN == ir1}} & I1_NN |// CALL Z,NN ; CC XX XX |
{I1DCNT {CALLsM_NN == ir1}} & I1_NN |// CALL M,NN ; FC XX XX |
{I1DCNT {JP == ir1}} & I1_NN |// JP ; C3 XX XX |
{I1DCNT {JPsC == ir1}} & I1_NN |// JP C ; DA XX XX |
{I1DCNT {JPsM == ir1}} & I1_NN |// JP M, ; FA XX XX |
{I1DCNT {JPsNC == ir1}} & I1_NN |// JP NC, ; D2 XX XX |
{I1DCNT {JPsNZ == ir1}} & I1_NN |// JP NZ ; C2 XX XX |
{I1DCNT {JPsP == ir1}} & I1_NN |// JP P ; F2 XX XX |
{I1DCNT {JPsPE == ir1}} & I1_NN |// JP PE, ; EA XX XX |
{I1DCNT {JPsPO == ir1}} & I1_NN |// JP PO ; E2 XX XX |
{I1DCNT {JPsZ == ir1}} & I1_NN |// JP Z ; CA XX XX |
{I1DCNT {LDs6NN7_A == ir1}} & I1_NN |// LD (NN),A ; 32 XX XX |
{I1DCNT {LDs6NN7_HL == ir1}} & I1_NN |// LD (NN),HL ; 22 XX XX |
{I1DCNT {LDsA_6NN7 == ir1}} & I1_NN |// LD A,(NN) ; 3A XX XX |
{I1DCNT {LDsBC_NN == ir1}} & I1_NN |// LD BC,NN ; 01 XX XX |
{I1DCNT {LDsDE_NN == ir1}} & I1_NN |// LD DE,NN ; 11 XX XX |
{I1DCNT {LDsHL_6NN7 == ir1}} & I1_NN |// LD HL,(NN) ; 2A XX XX |
{I1DCNT {LDsHL_NN == ir1}} & I1_NN |// LD HL,NN ; 21 XX XX |
{I1DCNT {LDsSP_NN == ir1}} & I1_NN |// LD SP,NN ; 31 XX XX |
{I1DCNT {ADCsA_6HL7 == ir1}} & I1_OF |// ADC A,(HL) ; 8E |
{I1DCNT {ADDsA_6HL7 == ir1}} & I1_OF |// ADD A,(HL) ; 86 |
{I1DCNT {ANDs6HL7 == ir1}} & I1_OF |// AND (HL) ; A6 |
{I1DCNT {CPs6HL7 == ir1}} & I1_OF |// CP (HL) ; BE |
{I1DCNT {LDsA_6BC7 == ir1}} & I1_OF |// LD A,(BC) ; 0A |
{I1DCNT {LDsA_6DE7 == ir1}} & I1_OF |// LD A,(DE) ; 1A |
{I1DCNT {LDsA_6HL7 == ir1}} & I1_OF |// LD A,(HL) ; 7E |
{I1DCNT {LDsB_6HL7 == ir1}} & I1_OF |// LD B,(HL) ; 46 |
{I1DCNT {LDsC_6HL7 == ir1}} & I1_OF |// LD C,(HL) ; 4E |
{I1DCNT {LDsD_6HL7 == ir1}} & I1_OF |// LD D,(HL) ; 56 |
{I1DCNT {LDsE_6HL7 == ir1}} & I1_OF |// LD E,(HL) ; 5E |
{I1DCNT {LDsH_6HL7 == ir1}} & I1_OF |// LD H,(HL) ; 66 |
{I1DCNT {LDsL_6HL7 == ir1}} & I1_OF |// LD L,(HL) ; 6E |
{I1DCNT {ORs6HL7 == ir1}} & I1_OF |// OR (HL) ; B6 |
{I1DCNT {SBCs6HL7 == ir1}} & I1_OF |// SBC (HL) ; 9E |
{I1DCNT {SUBs6HL7 == ir1}} & I1_OF |// SUB (HL) ; 96 |
{I1DCNT {XORs6HL7 == ir1}} & I1_OF |// XOR (HL) ; AE |
{I1DCNT {LDs6BC7_A == ir1}} & I1_OS |// LD (BC),A ; 02 |
{I1DCNT {LDs6DE7_A == ir1}} & I1_OS |// LD (DE),A ; 12 |
{I1DCNT {LDs6HL7_A == ir1}} & I1_OS |// LD (HL),A ; 77 |
{I1DCNT {LDs6HL7_B == ir1}} & I1_OS |// LD (HL),B ; 70 |
{I1DCNT {LDs6HL7_C == ir1}} & I1_OS |// LD (HL),C ; 71 |
{I1DCNT {LDs6HL7_D == ir1}} & I1_OS |// LD (HL),D ; 72 |
{I1DCNT {LDs6HL7_E == ir1}} & I1_OS |// LD (HL),E ; 73 |
{I1DCNT {LDs6HL7_H == ir1}} & I1_OS |// LD (HL),H ; 74 |
{I1DCNT {LDs6HL7_L == ir1}} & I1_OS |// LD (HL),L ; 75 |
{I1DCNT {POPsAF == ir1}} & I1_POP |// POP AF ; F1 |
{I1DCNT {POPsBC == ir1}} & I1_POP |// POP BC ; C1 |
{I1DCNT {POPsDE == ir1}} & I1_POP |// POP DE ; D1 |
{I1DCNT {POPsHL == ir1}} & I1_POP |// POP HL ; E1 |
{I1DCNT {PUSHsAF == ir1}} & I1_PUSH|// PUSH AF ; F5 |
{I1DCNT {PUSHsBC == ir1}} & I1_PUSH|// PUSH BC ; C5 |
{I1DCNT {PUSHsDE == ir1}} & I1_PUSH|// PUSH DE ; D5 |
{I1DCNT {PUSHsHL == ir1}} & I1_PUSH|// PUSH HL ; E5 |
{I1DCNT {ADCsA_A == ir1}} & I1_R2R |// ADC A,A ; 8F |
{I1DCNT {ADCsA_B == ir1}} & I1_R2R |// ADC A,B ; 88 |
{I1DCNT {ADCsA_C == ir1}} & I1_R2R |// ADC A,C ; 89 |
{I1DCNT {ADCsA_D == ir1}} & I1_R2R |// ADC A,D ; 8A |
{I1DCNT {ADCsA_E == ir1}} & I1_R2R |// ADC A,E ; 8B |
{I1DCNT {ADCsA_H == ir1}} & I1_R2R |// ADC A,H ; 8C |
{I1DCNT {ADCsA_L == ir1}} & I1_R2R |// ADC A,L ; 8D |
{I1DCNT {ADDsA_A == ir1}} & I1_R2R |// ADD A,A ; 87 |
{I1DCNT {ADDsA_B == ir1}} & I1_R2R |// ADD A,B ; 80 |
{I1DCNT {ADDsA_C == ir1}} & I1_R2R |// ADD A,C ; 81 |
{I1DCNT {ADDsA_D == ir1}} & I1_R2R |// ADD A,D ; 82 |
{I1DCNT {ADDsA_E == ir1}} & I1_R2R |// ADD A,E ; 83 |
{I1DCNT {ADDsA_H == ir1}} & I1_R2R |// ADD A,H ; 84 |
{I1DCNT {ADDsA_L == ir1}} & I1_R2R |// ADD A,L ; 85 |
{I1DCNT {ADDsHL_BC == ir1}} & I1_R2R |// ADD HL,BC ; 09 |
{I1DCNT {ADDsHL_DE == ir1}} & I1_R2R |// ADD HL,DE ; 19 |
{I1DCNT {ADDsHL_HL == ir1}} & I1_R2R |// ADD HL,HL ; 29 |
{I1DCNT {ADDsHL_SP == ir1}} & I1_R2R |// ADD HL,SP ; 39 |
{I1DCNT {ANDsA == ir1}} & I1_R2R |// AND A ; A7 |
{I1DCNT {ANDsB == ir1}} & I1_R2R |// AND B ; A0 |
{I1DCNT {ANDsC == ir1}} & I1_R2R |// AND C ; A1 |
{I1DCNT {ANDsD == ir1}} & I1_R2R |// AND D ; A2 |
{I1DCNT {ANDsE == ir1}} & I1_R2R |// AND E ; A3 |
{I1DCNT {ANDsH == ir1}} & I1_R2R |// AND H ; A4 |
{I1DCNT {ANDsL == ir1}} & I1_R2R |// AND L ; A5 |
{I1DCNT {CCF == ir1}} & I1_R2R |// CCF ; 3F |
{I1DCNT {CPL == ir1}} & I1_R2R |// CPL ; 2F |
{I1DCNT {CPsA == ir1}} & I1_R2R |// CP A ; BF |
{I1DCNT {CPsB == ir1}} & I1_R2R |// CP B ; B8 |
{I1DCNT {CPsC == ir1}} & I1_R2R |// CP C ; B9 |
{I1DCNT {CPsD == ir1}} & I1_R2R |// CP D ; BA |
{I1DCNT {CPsE == ir1}} & I1_R2R |// CP E ; BB |
{I1DCNT {CPsH == ir1}} & I1_R2R |// CP H ; BC |
{I1DCNT {CPsL == ir1}} & I1_R2R |// CP L ; BD |
{I1DCNT {DAA == ir1}} & I1_R2R |// DAA ; 27 |
{I1DCNT {DECsA == ir1}} & I1_R2R |// DEC A ; 3D |
{I1DCNT {DECsB == ir1}} & I1_R2R |// DEC B ; 05 |
{I1DCNT {DECsBC == ir1}} & I1_R2R |// DEC BC ; 0B |
{I1DCNT {DECsC == ir1}} & I1_R2R |// DEC C ; 0D |
{I1DCNT {DECsD == ir1}} & I1_R2R |// DEC D ; 15 |
{I1DCNT {DECsDE == ir1}} & I1_R2R |// DEC DE ; 1B |
{I1DCNT {DECsE == ir1}} & I1_R2R |// DEC E ; 1D |
{I1DCNT {DECsH == ir1}} & I1_R2R |// DEC H ; 25 |
{I1DCNT {DECsHL == ir1}} & I1_R2R |// DEC HL ; 2B |
{I1DCNT {DECsL == ir1}} & I1_R2R |// DEC L ; 2D |
{I1DCNT {DECsSP == ir1}} & I1_R2R |// DEC SP ; 3B |
{I1DCNT {DI == ir1}} & I1_R2R |// DI ; F3 |
{I1DCNT {DJNZs$t2 == ir1}} & I1_R2R |// DJNZ $+2 ; 10 XX |
{I1DCNT {EI == ir1}} & I1_R2R |// EI ; FB |
{I1DCNT {EXX == ir1}} & I1_R2R |// EXX ; D9 |
{I1DCNT {EXsAF_AFp == ir1}} & I1_R2R |// EX AF,AF' ; 08 |
{I1DCNT {EXsDE_HL == ir1}} & I1_R2R |// EX DE,HL ; EB |
{I1DCNT {HALT == ir1}} & I1_R2R |// HALT ; 76 |
{I1DCNT {INCsA == ir1}} & I1_R2R |// INC A ; 3C |
{I1DCNT {INCsB == ir1}} & I1_R2R |// INC B ; 04 |
{I1DCNT {INCsBC == ir1}} & I1_R2R |// INC BC ; 03 |
{I1DCNT {INCsC == ir1}} & I1_R2R |// INC C ; 0C |
{I1DCNT {INCsD == ir1}} & I1_R2R |// INC D ; 14 |
{I1DCNT {INCsDE == ir1}} & I1_R2R |// INC DE ; 13 |
{I1DCNT {INCsE == ir1}} & I1_R2R |// INC E ; 1C |
{I1DCNT {INCsH == ir1}} & I1_R2R |// INC H ; 24 |
{I1DCNT {INCsHL == ir1}} & I1_R2R |// INC HL ; 23 |
{I1DCNT {INCsL == ir1}} & I1_R2R |// INC L ; 2C |
{I1DCNT {INCsSP == ir1}} & I1_R2R |// INC SP ; 33 |
{I1DCNT {LDsA_A == ir1}} & I1_R2R |// LD A,A ; 7F |
{I1DCNT {LDsA_B == ir1}} & I1_R2R |// LD A,B ; 78 |
{I1DCNT {LDsA_C == ir1}} & I1_R2R |// LD A,C ; 79 |
{I1DCNT {LDsA_D == ir1}} & I1_R2R |// LD A,D ; 7A |
{I1DCNT {LDsA_E == ir1}} & I1_R2R |// LD A,E ; 7B |
{I1DCNT {LDsA_H == ir1}} & I1_R2R |// LD A,H ; 7C |
{I1DCNT {LDsA_L == ir1}} & I1_R2R |// LD A,L ; 7D |
{I1DCNT {LDsB_A == ir1}} & I1_R2R |// LD B,A ; 47 |
{I1DCNT {LDsB_B == ir1}} & I1_R2R |// LD B,B ; 40 |
{I1DCNT {LDsB_C == ir1}} & I1_R2R |// LD B,C ; 41 |
{I1DCNT {LDsB_D == ir1}} & I1_R2R |// LD B,D ; 42 |
{I1DCNT {LDsB_E == ir1}} & I1_R2R |// LD B,E ; 43 |
{I1DCNT {LDsB_H == ir1}} & I1_R2R |// LD B,H ; 44 |
{I1DCNT {LDsB_L == ir1}} & I1_R2R |// LD B,L ; 45 |
{I1DCNT {LDsC_A == ir1}} & I1_R2R |// LD C,A ; 4F |
{I1DCNT {LDsC_B == ir1}} & I1_R2R |// LD C,B ; 48 |
{I1DCNT {LDsC_C == ir1}} & I1_R2R |// LD C,C ; 49 |
{I1DCNT {LDsC_D == ir1}} & I1_R2R |// LD C,D ; 4A |
{I1DCNT {LDsC_E == ir1}} & I1_R2R |// LD C,E ; 4B |
{I1DCNT {LDsC_H == ir1}} & I1_R2R |// LD C,H ; 4C |
{I1DCNT {LDsC_L == ir1}} & I1_R2R |// LD C,L ; 4D |
{I1DCNT {LDsD_A == ir1}} & I1_R2R |// LD D,A ; 57 |
{I1DCNT {LDsD_B == ir1}} & I1_R2R |// LD D,B ; 50 |
{I1DCNT {LDsD_C == ir1}} & I1_R2R |// LD D,C ; 51 |
{I1DCNT {LDsD_D == ir1}} & I1_R2R |// LD D,D ; 52 |
{I1DCNT {LDsD_E == ir1}} & I1_R2R |// LD D,E ; 53 |
{I1DCNT {LDsD_H == ir1}} & I1_R2R |// LD D,H ; 54 |
{I1DCNT {LDsD_L == ir1}} & I1_R2R |// LD D,L ; 55 |
{I1DCNT {LDsE_A == ir1}} & I1_R2R |// LD E,A ; 5F |
{I1DCNT {LDsE_B == ir1}} & I1_R2R |// LD E,B ; 58 |
{I1DCNT {LDsE_C == ir1}} & I1_R2R |// LD E,C ; 59 |
{I1DCNT {LDsE_D == ir1}} & I1_R2R |// LD E,D ; 5A |
{I1DCNT {LDsE_E == ir1}} & I1_R2R |// LD E,E ; 5B |
{I1DCNT {LDsE_H == ir1}} & I1_R2R |// LD E,H ; 5C |
{I1DCNT {LDsE_L == ir1}} & I1_R2R |// LD E,L ; 5D |
{I1DCNT {LDsH_A == ir1}} & I1_R2R |// LD H,A ; 67 |
{I1DCNT {LDsH_B == ir1}} & I1_R2R |// LD H,B ; 60 |
{I1DCNT {LDsH_C == ir1}} & I1_R2R |// LD H,C ; 61 |
{I1DCNT {LDsH_D == ir1}} & I1_R2R |// LD H,D ; 62 |
{I1DCNT {LDsH_E == ir1}} & I1_R2R |// LD H,E ; 63 |
{I1DCNT {LDsH_H == ir1}} & I1_R2R |// LD H,H ; 64 |
{I1DCNT {LDsH_L == ir1}} & I1_R2R |// LD H,L ; 65 |
{I1DCNT {LDsL_A == ir1}} & I1_R2R |// LD L,A ; 6F |
{I1DCNT {LDsL_B == ir1}} & I1_R2R |// LD L,B ; 68 |
{I1DCNT {LDsL_C == ir1}} & I1_R2R |// LD L,C ; 69 |
{I1DCNT {LDsL_D == ir1}} & I1_R2R |// LD L,D ; 6A |
{I1DCNT {LDsL_E == ir1}} & I1_R2R |// LD L,E ; 6B |
{I1DCNT {LDsL_H == ir1}} & I1_R2R |// LD L,H ; 6C |
{I1DCNT {LDsL_L == ir1}} & I1_R2R |// LD L,L ; 6D |
{I1DCNT {LDsSP_HL == ir1}} & I1_R2R |// LD SP,HL ; F9 |
{I1DCNT {NOP == ir1}} & I1_R2R |// NOP ; 00 |
{I1DCNT {ORsA == ir1}} & I1_R2R |// OR A ; B7 |
{I1DCNT {ORsB == ir1}} & I1_R2R |// OR B ; B0 |
{I1DCNT {ORsC == ir1}} & I1_R2R |// OR C ; B1 |
{I1DCNT {ORsD == ir1}} & I1_R2R |// OR D ; B2 |
{I1DCNT {ORsE == ir1}} & I1_R2R |// OR E ; B3 |
{I1DCNT {ORsH == ir1}} & I1_R2R |// OR H ; B4 |
{I1DCNT {ORsL == ir1}} & I1_R2R |// OR L ; B5 |
{I1DCNT {RLA == ir1}} & I1_R2R |// RLA ; 17 |
{I1DCNT {RLCA == ir1}} & I1_R2R |// RLCA ; 07 |
{I1DCNT {RRA == ir1}} & I1_R2R |// RRA ; 1F |
{I1DCNT {RRCA == ir1}} & I1_R2R |// RRCA ; 0F |
{I1DCNT {SBCsA == ir1}} & I1_R2R |// SBC A ; 9F |
{I1DCNT {SBCsB == ir1}} & I1_R2R |// SBC B ; 98 |
{I1DCNT {SBCsC == ir1}} & I1_R2R |// SBC C ; 99 |
{I1DCNT {SBCsD == ir1}} & I1_R2R |// SBC D ; 9A |
{I1DCNT {SBCsE == ir1}} & I1_R2R |// SBC E ; 9B |
{I1DCNT {SBCsH == ir1}} & I1_R2R |// SBC H ; 9C |
{I1DCNT {SBCsL == ir1}} & I1_R2R |// SBC L ; 9D |
{I1DCNT {SCF == ir1}} & I1_R2R |// SCF ; 37 |
{I1DCNT {SUBsA == ir1}} & I1_R2R |// SUB A ; 97 |
{I1DCNT {SUBsB == ir1}} & I1_R2R |// SUB B ; 90 |
{I1DCNT {SUBsC == ir1}} & I1_R2R |// SUB C ; 91 |
{I1DCNT {SUBsD == ir1}} & I1_R2R |// SUB D ; 92 |
{I1DCNT {SUBsE == ir1}} & I1_R2R |// SUB E ; 93 |
{I1DCNT {SUBsH == ir1}} & I1_R2R |// SUB H ; 94 |
{I1DCNT {SUBsL == ir1}} & I1_R2R |// SUB L ; 95 |
{I1DCNT {XORsA == ir1}} & I1_R2R |// XOR A ; AF |
{I1DCNT {XORsB == ir1}} & I1_R2R |// XOR B ; A8 |
{I1DCNT {XORsC == ir1}} & I1_R2R |// XOR C ; A9 |
{I1DCNT {XORsD == ir1}} & I1_R2R |// XOR D ; AA |
{I1DCNT {XORsE == ir1}} & I1_R2R |// XOR E ; AB |
{I1DCNT {XORsH == ir1}} & I1_R2R |// XOR H ; AC |
{I1DCNT {XORsL == ir1}} & I1_R2R |// XOR L ; AD |
{I1DCNT {RET == ir1}} & I1_RET |// RET ; C9 |
{I1DCNT {RETsC == ir1 & cf }} & I1_RET |// RET C ; D8 |
{I1DCNT {RETsM == ir1 & sf }} & I1_RET |// RET M ; F8 |
{I1DCNT {RETsNC== ir1 & ~cf }} & I1_RET |// RET NC ; D0 |
{I1DCNT {RETsP == ir1 & ~sf }} & I1_RET |// RET P ; F0 |
{I1DCNT {RETsPE== ir1 & pvf }} & I1_RET |// RET PE ; E8 |
{I1DCNT {RETsPO== ir1 & ~pvf}} & I1_RET |// RET PO ; E0 |
{I1DCNT {RETsNZ== ir1 & ~zf }} & I1_RET |// RET NZ ; C0 |
{I1DCNT {RETsZ == ir1 & zf }} & I1_RET |// RET Z ; C8 |
{I1DCNT {EXs6SP7_HL == ir1}} & I1_RMW |// EX (SP),HL ; E3 |
{I1DCNT {DECs6HL7 == ir1}} & I1_RMW |// DEC (HL) ; 35 |
{I1DCNT {INCs6HL7 == ir1}} & I1_RMW |// INC (HL) ; 34 |
{I1DCNT {RSTs0 == ir1}} & I1_RST |// RST 0 ; C7 |
{I1DCNT {RSTs10H == ir1}} & I1_RST |// RST 10H ; D7 |
{I1DCNT {RSTs18H == ir1}} & I1_RST |// RST 18H ; DF |
{I1DCNT {RSTs20H == ir1}} & I1_RST |// RST 20H ; E7 |
{I1DCNT {RSTs28H == ir1}} & I1_RST |// RST 28H ; EF |
{I1DCNT {RSTs30H == ir1}} & I1_RST |// RST 30H ; F7 |
{I1DCNT {RSTs38H == ir1}} & I1_RST |// RST 38H ; FF |
{I1DCNT {RSTs8H == ir1}} & I1_RST ;// RST 8H ; CF |
|
//-------- CB decodes ----------------------- |
|
// First cut below |
// CB_RLC = 7'b01_00_000, // these must be compaired with ir[9:3] |
// CB_RRC = 7'b01_00_001, // these must be compaired with ir[9:3] |
// CB_RL = 7'b01_00_010, // these must be compaired with ir[9:3] |
// CB_RR = 7'b01_00_011, // these must be compaired with ir[9:3] |
// CB_SLA = 7'b01_00_100, // these must be compaired with ir[9:3] |
// CB_SRA = 7'b01_00_101, // these must be compaired with ir[9:3] |
// CB_SLL = 7'b01_00_110, // these must be compaired with ir[9:3] |
// CB_SRL = 7'b01_00_111, // these must be compaired with ir[9:3] |
|
// CB_BIT = 4'b01_01, // these must be compaired with ir[9:6] |
// CB_RES = 4'b01_10, // these must be compaired with ir[9:6] |
// CB_SET = 4'b01_11, // these must be compaired with ir[9:6] |
|
// note these are all read-modify-writ except CB_BIT |
assign cb_mem = (CB_MEM == ir1[2:0]); // this must be compaired with ir[2:0] |
|
// The ED Group |
// These are the "unique instructions in the 46, 47 rows that NEED? to be implemented |
// Not sure I want to worry about all undocumented stuff in these rows - hard to believe |
// It will matter.(IM modes are very system dependent - hard to believe even a programmer |
// would use undocumented instructions to muck with this stuff) |
// reg 2 reg simply executed by ir2 logic |
// ED_IMs0 = 10'h246// IM 0 ; ED 46 set IM0 |
// ED_LDsI_A = 10'h247// LD I,A ; ED 47 move a to I |
// ED_IMs1 = 10'h256// IM 1 ; ED 56 set IM1 |
// ED_LDsA_I = 10'h257// LD A,I ; ED 57 move I to A |
// ED_IMs2 = 10'h25E// IM 2 ; ED 5E set IM2 |
// ED_RRD = 10'h267// RRD ; ED 67 nibble roates A HL |
// ED_RLD = 10'h26F// RLD ; ED 6F nibble roates A HL |
|
// set (or clear) repeat flag at DEC_EB. |
// set (or clear) inc flag at DEC_EB. |
// seperate flows for LD, CP, IN, OUT. |
// ED_LDI == ir1// LDI ; ED A0 These are block move |
// ED_CPI == ir1// CPI ; ED A1 type insts that don't repeat |
// ED_INI == ir1// INI ; ED A2 |
// ED_OUTI == ir1// OUTI ; ED A3 |
// ED_LDD == ir1// LDD ; ED A8 |
// ED_CPD == ir1// CPD ; ED A9 |
// ED_IND == ir1// IND ; ED AA |
// ED_OUTD == ir1// OUTD ; ED AB |
wire dec_blk_rpt = |
ED_LDIR == ir1 |// LDIR ; ED B0 These are block move |
ED_CPIR == ir1 |// CPIR ; ED B1 type insts that DO repeat |
ED_INIR == ir1 |// INIR ; ED B2 |
ED_OTIR == ir1 |// OTIR ; ED B3 |
ED_LDDR == ir1 |// LDDR ; ED B8 |
ED_CPDR == ir1 |// CPDR ; ED B9 |
ED_INDR == ir1 |// INDR ; ED BA |
ED_OTDR == ir1 ;// OTDR ; ED BB |
wire ed_blk_mv = ED_LDIR == ir1 | ED_LDI == ir1 | |
ED_LDDR == ir1 | ED_LDD == ir1 ; |
wire ed_blk_cp = ED_CPIR == ir1 | ED_CPI == ir1 | |
ED_CPDR == ir1 | ED_CPD == ir1 ; |
wire ed_blk_in = ED_INIR == ir1 | ED_INI == ir1 | |
ED_INDR == ir1 | ED_IND == ir1 ; |
|
wire ed_blk_out = ED_OTIR == ir1 | ED_OUTI == ir1 | |
ED_OTDR == ir1 | ED_OUTD == ir1 ; |
|
wire dec_blk_io = ed_blk_in | ed_blk_in; |
|
wire blk_done = ~blk_rpt_flg | beq0 & ceq0 | blk_io_flg & ceq0; |
|
assign dec_blk_inc = ED_LDIR == ir1 | |
ED_CPIR == ir1 | |
ED_INIR == ir1 | |
ED_OTIR == ir1 | |
ED_LDI == ir1 | |
ED_CPI == ir1 | |
ED_INI == ir1 | |
ED_OUTI == ir1 ; |
|
|
//The ED70 instruction reads from I/O port C, |
//but does not store the result. |
//It just affects the flags. Hard to test. like the other IN x,(C) instruction. |
// |
//ED71 simply outs the value 0 to I/O port C. |
// This suggests that we should decode as follows: |
// I hope if I don't get all the IM duplicates right it won't be a tragedy |
// ED_INsREG_6C7 = 7'b1001___000,// compair with {ir[7:6],ir[2:0]} |
// |
// ED_SBCsHL_REG = 8'b1001__0010, // compair with {ir[9:6],ir[3:0]} |
// ED_ADCsHL_REG = 8'b1001__1010, // compair with {ir[9:6],ir[3:0]} |
// ED_LDs6NN7_REG = 8'b1001__0011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP |
// ED_LDsREG_6NN7 = 8'b1001__1011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP |
// ED_NEG = 7'b1001___100, // compair with {ir[9:6],ir[2:0]} all A<= -A |
// ED_RETN = 7'b1001___101, // compair with {ir[9:6],ir[2:0]} and !reti |
wire ed_nn = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} | |
ED_LDsREG_6NN7 == {ir1[9:6],ir1[3:0]} ; |
|
// we use all these to enable interrupts |
wire ed_retn = ED_RETN == {ir1[9:6],ir1[2:0]}; |
|
assign ed_dbl_rd = ED_LDsREG_6NN7 == {ir1[9:6],ir1[3:0]}; |
|
|
// assign cb_mem = CB_MEM = ir1[2:0]; // CB_MEM = 3'h110, |
|
|
|
|
wire jmpr_true = |
JRs$t2 == ir1 | |
JRsC_$t2 == ir1 & fr[0] | |
JRsNC_$t2 == ir1 & ~fr[0] | |
JRsZ_$t2 == ir1 & fr[6] | |
JRsNZ_$t2 == ir1 & ~fr[6] ; |
|
//assign { sf, zf. f5f, hf, f3f, pvf, nf, cf} = fr; |
wire callnn_true = CALLsC_NN == ir1 & cf | |
CALLsNC_NN == ir1 & ~cf | |
CALLsNN == ir1 | |
CALLsNZ_NN == ir1 & ~zf | |
CALLsPE_NN == ir1 & pvf | |
CALLsPO_NN == ir1 & ~pvf| |
CALLsP_NN == ir1 & ~sf | |
CALLsZ_NN == ir1 & zf | |
CALLsM_NN == ir1 & sf ; |
|
wire jmpnn_true = JPsC == ir1 & cf | |
JPsNC == ir1 & ~cf | |
JP == ir1 | |
JPsNZ == ir1 & ~zf | |
JPsPE == ir1 & pvf | |
JPsPO == ir1 & ~pvf| |
JPsP == ir1 & ~sf | |
JPsZ == ir1 & zf | |
JPsM == ir1 & sf ; |
|
// PUSHsAF == ir1 |
// PUSHsBC == ir1 |
// PUSHsDE == ir1 |
// PUSHsHL == ir1 |
|
wire os_a = LDs6BC7_A == ir1 | // LD (BC),A ; 02 |
LDs6DE7_A == ir1 | // LD (DE),A ; 12 |
LDs6HL7_A == ir1 | // LD (HL),A ; 77 |
LDs6NN7_A == ir1 | // LD (NN),A ; 32 XX XX |
PUSHsAF == ir1 | |
OUTs6N7_A == ir1 | |
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0] && REG8_A == ir1[5:3]} ; |
|
wire os_b = LDs6HL7_B == ir1 | // LD (HL),B ; 70 |
ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_BC == ir1[5:4] | |
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_B == ir1[5:3] ; |
|
wire os_c = LDs6HL7_C == ir1 | // LD (HL),C ; 71 |
PUSHsBC == ir1 | // PUSH BC |
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_C == ir1[5:3] ; |
|
wire os_d = LDs6HL7_D == ir1 | // LD (HL),D ; 72 |
ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_DE == ir1[5:4] | |
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_D == ir1[5:3] ; |
|
|
wire os_e = LDs6HL7_E == ir1 | // LD (HL),E ; 73 |
PUSHsDE == ir1 | // PUSH DE |
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_E == ir1[5:3] ; |
|
wire os_h = LDs6HL7_H == ir1 | // LD (HL),H ; 74 |
LDs6NN7_HL == ir1 | // LD (NN),HL ; 22 XX XX |
ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_HL == ir1[5:4] | |
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_H == ir1[5:3] ; |
|
wire os_l = LDs6HL7_L == ir1 | // LD (HL),L ; 75 |
PUSHsHL == ir1 | |
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_L == ir1[5:3] ; |
|
wire os_sp = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_SP == ir1[5:4]; |
|
wire os_f = PUSHsAF == ir1 ; |
|
|
//---------------- inst hazard ---------------------------------------------------------- |
// |
// On some reflection, I don't think I'm going to worry about this immediately - it |
// should be easy to kludge in a fix if necessary -- and there are more important things |
// todo. It is a very bad programming practice to muck with the instruction stream in any |
// case -- I have to believe most target applications do not do this -- although I'll probably |
// get hit pretty early with a instruction test that does. Oh well -- if that happens we fix |
// it. |
// Well -- think some here -- the hazard is because of a change in design. |
// If used to any extent.. Somebody WILL |
// want this to act the same way as the origional - even if the programming is "poor". |
// >>>>>>>> bite the bullet and do it. |
// |
// if we do an operand store and the address == pc-1 its an inst hazard, We need to execute the |
// store decrement pc and re-fetch. This is a high priority interrupt. |
// what about multi-byte stores - like LDs6NN7_A or LDs6NN7_HL - i guess we do an IF - to start |
// the pipe before the os -- same logic. |
// |
|
|
//-----------------data hazard ---------------------------------------------------------- |
// |
// Issues here have evolved to a degree as the design progressed. However the |
// Key has always been that for each instruction (no matter how complex) there |
// is only a single state in which the previous instruction can also be active |
// and that is the DEC_EXEC state. If there is a data hazard, we need to delay |
// execution of that state until the ir2 execution completes (which it always does |
// in a single tick). Note that only the RET instructions test the flag register |
// on DEC_EXEC. |
// |
// WARNING: be very careful about this. Data hazard logic is very difficult to |
// verify as there are so many instruction pairs to test. |
// |
// Situations 1) operand stores from ir1 when register is updated in ir2 |
// 2) flag tests when fr is being updated |
// 3) sp issues see below LDsSP_HL DECsSP INCsSP |
// ANY OTHERS ??? |
// |
// upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr, |
wire use_hl_exec = LDsSP_HL == ir1; |
wire use_sp_exec = MEM_OFSP == next_mem_state | |
MEM_OSSP == next_mem_state ; |
wire upd_sp_exec = DECsSP == ir2 | |
INCsSP == ir2 ; |
|
|
|
wire use_fr_exec = ( RETsC == ir1 | |
RETsM == ir1 | |
RETsNC == ir1 | |
RETsP == ir1 | |
RETsPE == ir1 | |
RETsPO == ir1 | |
RETsNZ == ir1 | |
RETsZ == ir1 ) ; |
|
assign hazard = (dec_state == DEC_EXEC & exec_ir2 ) & ( upd_fr & use_fr_exec | |
upd_ar & os_a | |
upd_br & os_b | |
upd_cr & os_c | |
upd_dr & os_d | |
upd_er & os_e | |
upd_hr & os_h | |
upd_lr & os_l | |
upd_hr & use_hl_exec | |
upd_lr & use_hl_exec | |
upd_sp_exec & use_sp_exec ); |
|
|
|
|
|
|
// does not include extension stuff as we are mostly looking for hazards here |
// course we do use these terms to build more decodes |
// |
wire opadr_bc = LDsA_6BC7 == ir1 | LDs6BC7_A == ir1; |
wire opadr_de = LDsA_6DE7 == ir1 | LDs6DE7_A == ir1; |
wire opadr_hl = LDsB_6HL7 == ir1 | ORs6HL7 == ir1 | LDs6HL7_B == ir1 | |
LDsD_6HL7 == ir1 | LDsC_6HL7 == ir1 | LDs6HL7_C == ir1 | |
LDsH_6HL7 == ir1 | LDsE_6HL7 == ir1 | LDs6HL7_D == ir1 | |
ADDsA_6HL7 == ir1 | LDsL_6HL7 == ir1 | LDs6HL7_E == ir1 | |
SUBs6HL7 == ir1 | LDsA_6HL7 == ir1 | LDs6HL7_H == ir1 | |
ANDs6HL7 == ir1 | ADCsA_6HL7 == ir1 | LDs6HL7_L == ir1 | |
XORs6HL7 == ir1 | SBCs6HL7 == ir1 | CPs6HL7 == ir1 ; |
|
assign use_a = os_a; |
assign use_b = os_b | opadr_bc; |
assign use_c = os_c | opadr_bc; |
assign use_d = os_d | opadr_de; |
assign use_e = os_e | opadr_de; |
assign use_h = os_h | opadr_hl; |
assign use_l = os_l | opadr_hl; |
|
|
|
assign use_flags = c_jmp8 | c_jmp4 | c_call | c_ret; |
|
|
|
wire bc_eq0 = beq0 & ceq0; |
// ??? not used ? why defined ? |
//assign rpt_blk_mv = (blk_mv_reg ) & !bc_eq0 | |
// (blk_cmp_reg) & !bc_eq0 & (nn[7:0] != 8'h0) | |
// (blk_in_reg | blk_out_reg) & !b_eq0 ; |
|
|
|
|
|
|
|
// BASIC ARCHITECTURE OF THIS FILE pc and sp not shown, but are inputs to src mux. |
// _____ and may be updated from adder output. |
// | | |
// | | pc-1 register is required to implement relative jumps. |
// | | |
// _____ |lit | |\ |
// | | | | | \ |
// | | |src2 | | \ _____ _____ |
// | | | |----->| | | | | | |
// |src | |_____| |adder|------->| | | | |
// |mux | | | | | | | |
// | |------------------->| / |2/1 |------->|wb | |
// | | | | / |mux | |adr | |
// |_____| | |/ | | | | |
// ------------------->| | | | |
// |_____| |_____| |
// MEM_NOP |
// MEM_IFPP1 MEM_OFIXpD MEM_CALL MEM_IFRST MEM_OFHL_PM MEM_IOF_C |
// MEM_OS1, MEM_OSIXpD MEM_OSNN, MEM_IFREL_N MEM_OSHL_PM MEM_IOS_C |
// MEM_OF1, MEM_OSADR MEM_OFNN MEM_JMPHL MEM_OSDE_PM MEM_IOF_N |
// MEM_OFSP MEM_OSSP_PCM2 MEM_OFADRP1 MEM_IFNN MEM_INTA MEM_IOS_N |
// MEM_OSSP MEM_OSSP_P MEM_OSADRP1 MEM_IFINT MEM_OS_HL_N |
// |
|
wire src_sp = next_mem_state == MEM_OF1 & EXs6SP7_HL == ir1 | //special case rmw |
next_mem_state == MEM_OFSP | |
next_mem_state == MEM_OSSP | |
next_mem_state == MEM_CALL ; |
wire src_pc = next_mem_state == MEM_IFPP1 | |
next_mem_state == MEM_IFREL_N ; |
|
wire src_nn = next_mem_state == MEM_IFNN | |
next_mem_state == MEM_OSNN | |
next_mem_state == MEM_OFNN ; |
|
|
wire src_de = dec_state == DEC_EXEC & LDsA_6DE7 == ir1 | // MEM_OS1 MEM_OF1 |
dec_state == DEC_EXEC & LDs6DE7_A == ir1 | // are both true at this time |
next_mem_state == MEM_OSDE_PM ; |
wire src_bc = dec_state == DEC_EXEC & LDsA_6BC7 == ir1 | |
dec_state == DEC_EXEC & LDs6BC7_A == ir1 | |
next_mem_state ==MEM_IOF_C | |
next_mem_state ==MEM_IOS_C ; |
|
|
// don't forget that hl source can be modified by prefix |
// this gets messy as we use wb_adr for some of these. |
// |
wire src_hl = next_mem_state == MEM_OF1 & |
(dec_state == DEC_EXEC) & |
!src_de & !src_bc & !src_sp | |
next_mem_state == MEM_OS1 & |
(dec_state == DEC_EXEC) & |
!src_de & !src_bc | |
next_mem_state == MEM_OFHL_PM | |
next_mem_state == MEM_OSHL_PM | |
next_mem_state == MEM_OS_HL_N | |
next_mem_state == MEM_JMPHL ; |
|
wire src_ix = next_mem_state == MEM_OFIXpD & ir1dd | |
next_mem_state == MEM_OSIXpD & ir1dd ; |
|
wire src_iy = next_mem_state == MEM_OFIXpD & ir1fd | |
next_mem_state == MEM_OSIXpD & ir1fd ; |
|
wire src_adr = next_mem_state == MEM_OFADRP1 | |
next_mem_state == MEM_OSADRP1 | |
next_mem_state == MEM_NOP | |
next_mem_state == MEM_OSADR ; |
|
wire src_int = next_mem_state == MEM_IOF_N | |
next_mem_state == MEM_IOS_N ; |
|
|
|
wire src_mux = {16{ src_sp }} & sp | |
{16{ src_pc }} & pc | |
{16{ src_nn }} & nn | |
{16{ src_hl }} & hl | |
{16{ src_de }} & de | |
{16{ src_bc }} & bc | |
{16{ src_ix }} & ixr | |
{16{ src_iy }} & iyr | |
{16{ src_adr }} & wb_adr | |
{16{ src_int }} & { intr, nn[15:8] } | |
{16{next_mem_state == MEM_IFRST}} & {10'h0, ir1[6:4], 3'h0} ; |
|
wire block_mv_inc = (dec_state == DEC_ED) ? dec_blk_inc : blk_inc_flg; // flag set at DEC_ED |
|
|
|
wire inc_s2 = next_mem_state ==MEM_OFADRP1 | |
next_mem_state ==MEM_OSADRP1 | |
next_mem_state ==MEM_OFHL_PM & block_mv_inc | |
next_mem_state ==MEM_OSHL_PM & block_mv_inc | |
next_mem_state ==MEM_OSDE_PM & block_mv_inc | |
next_mem_state ==MEM_OFSP | |
next_mem_state ==MEM_IFPP1 | |
next_mem_state ==MEM_OSSP_PCM2 | |
next_mem_state ==MEM_OSSP_P ; |
|
wire dec_s2 = next_mem_state ==MEM_OFHL_PM & ~block_mv_inc | |
next_mem_state ==MEM_OSHL_PM & ~block_mv_inc | |
next_mem_state ==MEM_OSDE_PM & ~block_mv_inc | |
next_mem_state == MEM_OFSP ; |
|
|
wire reln_s2 = next_mem_state == MEM_IFREL_N | |
next_mem_state == MEM_OFIXpD | |
next_mem_state == MEM_OSIXpD ; |
|
wire src2 = {16{ inc }} & 16'h0001 | |
{16{ dec }} & 16'hffff | |
{16{ rel }} & {{8{nn[15]}},nn[15:8]}| |
{16{~(rel_jmp|inc|dec)}} & 16'h0 ; |
|
wire adr_alu = src2 + src_mux; |
|
|
wire pre_inc_dec = next_mem_state == MEM_CALL | |
next_mem_state == MEM_OSSP_P | |
next_mem_state == MEM_OSSP ; |
|
|
wire mux21 = pre_inc_dec ? alu : src_mux; |
|
assign wb_rdy_nhz = (!wb_cyc | wb_ack ) & ~hazard; // wishbone ready with no hazard |
wire wb_rdy = !wb_cyc | wb_ack; |
|
assign we_next = next_mem_state == MEM_OS1 | |
next_mem_state == MEM_OSP | |
next_mem_state == MEM_OSIXpD | |
next_mem_state == MEM_OSADR | |
next_mem_state == MEM_OSSP_PCM2 | |
next_mem_state == MEM_OSSP_P | |
next_mem_state == MEM_CALL | |
next_mem_state == MEM_OSNN | |
next_mem_state == MEM_OSADRP1 | |
next_mem_state == MEM_OSHL_PM | |
next_mem_state == MEM_OSDE_PM | |
next_mem_state == MEM_OS_HL_N | |
next_mem_state == MEM_IOS_C | |
next_mem_state == MEM_IOS_N ; |
|
|
//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0 |
// we do this just to save virtual paper below. |
// 6 5 4 15 |
assign {next_dec_state, next_mem_state, next_pipe_state} = next_state; |
|
always @(ir1 or wb_int or inst_haz or wb_int or dec_state or mem_exec_dec or cb_mem or ed_nn or |
ed_blk_cp or ed_blk_in or ed_blk_out or ed_retn or ed_blk_mv or ed_dbl_rd or blk_done or |
fr or jmpr_true or callnn_true or jmpnn_true ) |
|
begin |
case (dec_state) |
DEC_IDLE: next_state = {DEC_IF1, MEM_NOP, IPIPE_NOP}; |
|
DEC_HALT: |
if (wb_int) next_state = {DEC_INT1,MEM_NOP ,IPIPE_NOP};// stay here until interrupt or reset |
else next_state = {DEC_HALT,MEM_NOP ,IPIPE_NOP}; |
DEC_IF1 : next_state = {DEC_IF2 ,MEM_IFPP1 ,IPIPE_NOP}; |
DEC_IF2 : next_state = {DEC_EXEC,MEM_IFPP1 ,IPIPE_EN1}; |
DEC_IF2A: next_state = {DEC_EXEC,MEM_IFPP1 ,IPIPE_NOP}; |
DEC_EXEC: |
if (inst_haz) next_state = {DEC_IF1, MEM_DECPC , IPIPE_NOP}; |
else if (wb_int) next_state = {DEC_INT1,MEM_NOP ,IPIPE_NOP}; |
else |
case (mem_exec_dec) // full case but can all tools understand ? just make a default |
I1_CB : next_state = {DEC_CB, MEM_IFPP1, IPIPE_EN1};// IF2_NOP -> nn <= (MEM) |
I1_DDFD : next_state = {DEC_DDFD, MEM_IFPP1, IPIPE_EN1};// gets real inst |
I1_ED : next_state = {DEC_ED, MEM_IFPP1, IPIPE_EN1}; |
I1_JMP : next_state = {DEC_IF2, MEM_JMPHL, IPIPE_NOP}; |
I1_N : next_state = {DEC_N, MEM_IFPP1, IPIPE_ENN}; |
I1_NN : next_state = {DEC_NN, MEM_IFPP1, IPIPE_ENN}; |
I1_OF : next_state = {DEC_OF, MEM_OF1, IPIPE_EN12};//transfer, don't activate |
I1_OS : next_state = {DEC_IF2, MEM_OS1, IPIPE_EN1}; // -> ir2_NOP |
I1_POP : next_state = {DEC_POP, MEM_OFSP, IPIPE_EN12}; |
I1_PUSH : next_state = {DEC_PUSH, MEM_OSSP, IPIPE_EN12}; |
I1_RET : next_state = {DEC_RET, MEM_OFSP, IPIPE_EN12}; |
I1_RMW : next_state = {DEC_RMW, MEM_OF1, IPIPE_EN12};//can't activate till data rdy |
I1_RST : next_state = {DEC_IF2, MEM_IFRST, IPIPE_ENN}; |
I1_R2R : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; |
default : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; //I1_R2R |
endcase |
DEC_CB: if (cb_mem) next_state = {DEC_CBM, MEM_OF1, IPIPE_EN12}; |
else next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; |
DEC_DDFD: // except for CB and EB these all act the same H and L get modified by prefix |
case (mem_exec_dec) |
I1_CB : next_state = {DEC_PFxCB,MEM_IFPP1, IPIPE_EN1};// IF2_NOP -> nn <= (MEM) |
I1_DDFD : next_state = {DEC_DDFD, MEM_IFPP1, IPIPE_EN1}; |
I1_ED : next_state = {DEC_ED, MEM_IFPP1, IPIPE_EN1};//How do we clear the prefix? |
I1_JMP : next_state = {DEC_IF2, MEM_JMPHL, IPIPE_NOP}; |
I1_N : next_state = {DEC_N, MEM_IFPP1, IPIPE_ENN}; |
I1_NN : next_state = {DEC_NN, MEM_IFPP1, IPIPE_ENN}; |
I1_OF : next_state = {DEC_DDOF, MEM_IFPP1, IPIPE_ENN}; // d to nn - need to get d |
// LD A,(BC) LD A,(DE) will |
// become ix+d - do we care ? |
// i hope not |
I1_OS : next_state = {DEC_DDOS, MEM_IFPP1, IPIPE_ENN}; // d to nn |
I1_POP : next_state = {DEC_POP, MEM_OFSP, IPIPE_EN12}; |
I1_PUSH : next_state = {DEC_PUSH, MEM_OSSP, IPIPE_EN12}; |
I1_RET : next_state = {DEC_RET, MEM_OFSP, IPIPE_EN12}; |
I1_RMW : next_state = {DEC_RMW, MEM_OF1, IPIPE_EN12}; |
I1_RST : next_state = {DEC_IF2, MEM_IFRST, IPIPE_NOP}; // just dump next inst |
I1_R2R : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; //I1_R2R |
default : next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; //I1_R2R |
endcase |
DEC_ED: |
if (ed_nn) next_state = {DEC_EDNN1, MEM_IFPP1, IPIPE_ENN}; |
// we need to set inc and io and repeat flags on this state for continued block |
// processing -- keep the states of this machine somewhat manageable. |
else if (ed_blk_cp ) next_state = {DEC_EDBCP1, MEM_OFHL_PM, IPIPE_EN12};// MEM_OFHL_PM triggers --BC |
else if (ed_blk_in ) next_state = {DEC_EDBIN1, MEM_IOF_C, IPIPE_EN12};// MEM_IOF_C triggers --B |
else if (ed_blk_out) next_state = {DEC_EDBOUT1,MEM_OFHL_PM, IPIPE_EN12}; |
else if (ed_blk_mv ) next_state = {DEC_EDBMV1, MEM_OFHL_PM, IPIPE_EN12}; |
else if (ed_retn ) next_state = {DEC_RET, MEM_OFSP, IPIPE_EN12};// see int logic below |
else next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2}; |
// double register reads and writes here |
DEC_EDNN1: next_state = {DEC_EDNN2, MEM_NOP, IPIPE_ENN}; // address to nn |
DEC_EDNN2: |
if (ed_dbl_rd) next_state = {DEC_EDRD1, MEM_OFNN, IPIPE_NOP}; |
else next_state = {DEC_EDWR, MEM_OSNN, IPIPE_NOP};// OSNN selects data ok? |
DEC_EDRD1: next_state = {DEC_EDRD2, MEM_OFADRP1, IPIPE_ENN}; // 1st byte 2n |
DEC_EDRD2: next_state = {DEC_IF2, MEM_IFPP1, IPIPE_ENNA2}; // 2nd byte 2nn |
DEC_EDWR: next_state = {DEC_IF1, MEM_OSADRP1, IPIPE_NOP}; |
|
// ED block moves |
DEC_EDBCP1: |
if (blk_done) next_state = {DEC_EXEC, MEM_IFPP1,IPIPE_ENNA2}; |
else if(wb_int) next_state = {DEC_INT1, MEM_NOP, IPIPE_ENNA2}; |
else next_state = {DEC_EDBCP2, MEM_NOP, IPIPE_ENNA2};//set flags |
DEC_EDBCP2: next_state = {DEC_EDBCP3, MEM_NOP, IPIPE_NOP};//wait for fr. alu_out is slow |
DEC_EDBCP3: if (fr[7]) next_state = {DEC_EXEC , MEM_IFPP1, IPIPE_NOP}; |
else next_state = {DEC_EDBCP1, MEM_OFHL_PM, IPIPE_NOP}; |
|
DEC_EDBIN1: next_state = {DEC_EDBIN2, MEM_NOP, IPIPE_ENN}; |
DEC_EDBIN2: if (blk_done) next_state = {DEC_IF2A, MEM_OSHL_PM,IPIPE_NOP}; // implies nn |
else if (wb_int) next_state = {DEC_INT1, MEM_OSHL_PM,IPIPE_NOP}; |
else next_state = {DEC_EDBIN1,MEM_OSHL_PM,IPIPE_NOP};//set flags |
DEC_EDBIN3: next_state = {DEC_EDBIN1, MEM_IOF_C, IPIPE_NOP}; |
|
DEC_EDBOUT1: next_state = {DEC_EDBOUT2, MEM_NOP, IPIPE_ENN}; |
DEC_EDBOUT2:if (blk_done) next_state = {DEC_EXEC, MEM_IOS_C,IPIPE_NOP}; |
else if (wb_int) next_state = {DEC_INT1, MEM_IOS_C,IPIPE_NOP}; // DEC_EDBOUT: if (blk_rpt) |
else next_state = {DEC_EDBOUT3,MEM_IOS_C,IPIPE_NOP}; |
|
DEC_EDBOUT3: next_state = {DEC_EDBOUT1,MEM_OFHL_PM, IPIPE_NOP}; |
|
DEC_EDBMV1: next_state = {DEC_EDBMV2, MEM_NOP, IPIPE_ENN}; |
DEC_EDBMV2: if (blk_done) next_state = {DEC_EXEC, MEM_OSDE_PM,IPIPE_NOP}; |
else if (wb_int) next_state = {DEC_INT1, MEM_OSDE_PM,IPIPE_NOP}; //DEC_EDBOUT: if (blk_rpt) |
else next_state = {DEC_EDBMV3,MEM_OSDE_PM,IPIPE_NOP}; |
|
DEC_EDBMV3: next_state = {DEC_EDBMV1,MEM_OFHL_PM, IPIPE_NOP}; |
|
DEC_N: |
if (INsA_6N7== ir1) next_state = {DEC_NIN, MEM_IOF_N, IPIPE_EN12}; |
else if (OUTs6N7_A==ir1) next_state = {DEC_IF1, MEM_IOS_N, IPIPE_EN12}; |
else if (LDs6HL7_N==ir1) next_state = {DEC_IF1, MEM_OS_HL_N, IPIPE_EN12}; |
else if (jmpr_true) next_state = {DEC_IF2, MEM_IFREL_N, IPIPE_NOP}; |
else next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_EN12A2};//r2r or false jumps |
DEC_NIN: next_state = {DEC_IF2, MEM_IFPP1, IPIPE_ENNA2}; |
|
|
//ISSUES: LDsSP_NN - load commanded from ir2 decode? and mechaninsm for updating PC on |
// JMP and CALL |
// on CALL We have IFNN for JMP |
// For CALL Use MEM_CALL to transfer pc<=nn, nn<=pc, adr<=sp then MEM_OSSP then IFPP1 |
// For LDsSP_NN yes update from ir2 decode. |
DEC_NN: |
if (callnn_true) next_state = {DEC_NNCALL1, MEM_NOP, IPIPE_ENN}; // this gets new adr in nn |
// if we store from nn we can't do |
// a mem op now |
|
else if (jmpnn_true) next_state = {DEC_NNJMP, MEM_NOP, IPIPE_ENN}; // gotta get nn before we can |
// transfer to adr. |
else if (LDs6NN7_A==ir1) next_state = {DEC_NNOS3, MEM_IFPP1, IPIPE_ENN}; |
else if (LDs6NN7_HL==ir1) next_state = {DEC_NNOS1, MEM_IFPP1, IPIPE_ENN}; |
else if (LDsA_6NN7==ir1) next_state = {DEC_NNOF3, MEM_IFPP1, IPIPE_ENN}; |
else if (LDsHL_6NN7==ir1) next_state = {DEC_NNOF1, MEM_IFPP1, IPIPE_ENN}; |
else next_state = { DEC_IF2, MEM_IFPP1, IPIPE_ENNEN2A2}; |
|
DEC_NNCALL1: next_state = {DEC_NNCALL2, MEM_CALL , IPIPE_NOP}; |
DEC_NNCALL2: next_state = {DEC_IF1, MEM_OSSP, IPIPE_ENN};//A1 activates r2r xfers from ir1 |
DEC_NNJMP: next_state = {DEC_IF2, MEM_IFNN , IPIPE_NOP}; |
|
// ISSUE: we blow out ir1 here - so need to keep some status to execute OSNN2. |
// general solution if not DEC_EXEC we get op frmo nn high byte. |
// note that first MEM_OSNN trabsferrs nn to wb_adr. |
DEC_NNOS1: next_state = {DEC_NNOS2, MEM_OSNN, IPIPE_EN1}; |
DEC_NNOS2: next_state = {DEC_IF2A, MEM_OSNN, IPIPE_NOP}; |
DEC_NNOS3: next_state = {DEC_IF2A, MEM_OSNN, IPIPE_EN1}; |
|
DEC_NNOF1: next_state = {DEC_NNOF2, MEM_OFNN, IPIPE_EN12}; |
DEC_NNOF2: next_state = {DEC_NNOF4, MEM_OFNN, IPIPE_ENN}; |
DEC_NNOF3: next_state = {DEC_NNOF4, MEM_OFNN, IPIPE_EN12}; |
DEC_NNOF4: next_state = {DEC_EXEC, MEM_IFPP1, IPIPE_ENNA2}; |
|
DEC_DDOS: next_state = {DEC_IF2A, MEM_OSIXpD, IPIPE_EN12}; |
DEC_DDOF: next_state = {DEC_OF , MEM_OFIXpD, IPIPE_EN12}; |
|
|
DEC_OF: next_state = {DEC_EXEC, MEM_IFPP1 , IPIPE_ENNA2}; |
DEC_POP: next_state = {DEC_NNOF4, MEM_OFSP, IPIPE_ENN }; |
DEC_PUSH: next_state = {DEC_IF2A , MEM_OSSP, IPIPE_NOP }; |
|
|
DEC_RET: next_state = { DEC_RET2, MEM_OFSP, IPIPE_ENN }; |
DEC_RET2: next_state = { DEC_NNCALL2, MEM_NOP, IPIPE_ENN }; |
// blow off a tick so we don't gronk adr |
DEC_RMW: next_state = {DEC_RMW2, MEM_NOP, IPIPE_ENNA2}; //activate |
DEC_RMW2: next_state = {DEC_IF1 , MEM_OSADR, IPIPE_NOP }; // from nn |
|
|
// IF memory -- rmw else these are all reg 2 reg |
DEC_CBM: if (CB_BIT==ir1[9:6]) next_state = {DEC_IF2, MEM_IFPP1, IPIPE_ENNA2}; |
else next_state = {DEC_RMW2 , MEM_NOP, IPIPE_ENNA2}; |
|
// The DDCB anf FDCB all assume memory operands |
// These beauties always rmw memory. If a register op is default, they also |
// update the register. Programmers think of this as 2 ops for the price of 1. |
// unfortunately it is 2 ops for the price of 4.-- its not the number of lines |
// of assembler code that count but the number of bytes assembled. Oh well I signed |
// up for this...... and had a notion of what I was getting into. |
// |
DEC_PFxCB: next_state = { DEC_PFxCB2, MEM_IFPP1, IPIPE_ENN}; // this gets d |
DEC_PFxCB2: next_state = { DEC_PFxCB3, MEM_OFIXpD, IPIPE_EN1}; //actual inst |
DEC_PFxCB3: next_state = { DEC_PFxCB4, MEM_IFPP1, IPIPE_ENNEN2A2}; |
DEC_PFxCB4: next_state = { DEC_IF2A, MEM_OSADR, IPIPE_EN1}; //execute ir2 |
|
// crap gotta subtract 2 (we always increment pc 2 times relative to the inst |
// that got interrupted. also can't push and dec pc without 2 adders. |
// choices: 1) fix up pc in 2 ticks 2) fix in 1 tick 3) add adder and do it fast |
// if there's anyone who knows is there anyone who cares. |
// guess I'll do it fast -- just a 16 bit subtractor. heck silicon is |
// cheap. |
DEC_INT1: next_state <= {DEC_INT2, MEM_OSSP_PCM2, IPIPE_NOP}; //must derement PC |
DEC_INT2: next_state <= {DEC_INT3, MEM_OSSP_P, IPIPE_NOP}; //must dec sp and PC 2 ops? |
DEC_INT3: next_state <= {DEC_INT4, MEM_INTA, IPIPE_NOP}; |
DEC_INT4: next_state <= {DEC_INT5, MEM_NOP, IPIPE_ENN}; |
DEC_INT5: next_state <= {DEC_IF2, MEM_IFINT, IPIPE_NOP}; |
default: next_state <= {DEC_IDLE, MEM_NOP, IPIPE_NOP}; |
endcase |
end |
|
|
always @(posedge clk or posedge rst) |
if (rst) dec_state <= DEC_IDLE; |
else if (wb_rdy_nhz ) dec_state <= next_dec_state; |
|
|
//-----------------------instruction register #1 ---------------------------------- |
// // next_pipe_state {ir1,ir2,nn,act_ir2} |
|
wire update_prefix = dec_state == DEC_EXEC | dec_state == DEC_DDFD; |
|
always @(posedge clk or posedge rst) |
if (rst) ir1 <= NOP; |
else if (wb_rdy_nhz & next_pipe_state[3]) ir1 <= {2'b0, wb_dat_i} ; |
else if ( wb_rdy_nhz &update_prefix ) ir1 <= {ir1[7:0]==8'hed, ir1[7:0]==8'hcd, ir1[7:0]}; |
|
//----------- prefix states ----------------------------------------- |
// strings of prefix insts are ignored up to last one. Also dded and fded are ignored |
// but ddcd and fdcd are defined prefix sets. |
// |
always @(posedge clk) |
if (wb_rdy_nhz & next_pipe_state[3]) {ir1dd, ir1fd } <= 2'b0; |
else if ( wb_rdy_nhz & update_prefix ) |
{ir1dd, ir1fd } <= {ir1dd | (ir1[7:0]==8'hdd ) & (ir1[7:0]!=8'hed) & (ir1[7:0]!=8'hfd), |
ir1fd | (ir1[7:0]==8'hfd ) & (ir1[7:0]!=8'hed) & (ir1[7:0]!=8'hdd) }; |
|
//------------------- inst reg #2 ----------------------------------- |
// This stuff is key to the data hazard logic. Hazards arise only AFTER activation of |
// a previous instruction. Fundamentally all state changes related to ir1 may be |
// delayed eithor by a delay in wb response, or by a hazard. Ir2 state changes |
// are keyed off exec_ir2 - and always happen immediately. ( exec_ir2 always is |
// immediately reset - unless of course a new instruction is transferred and executed. |
// |
// |
// |
always @(posedge clk or posedge rst) |
if (rst) ir2 <= 10'h0; |
else if (wb_rdy_nhz & next_pipe_state[2]) ir2 <= ir1; |
|
always @(posedge clk or posedge rst) |
if (rst) |
begin |
ir2dd <= 1'b0; |
ir2fd <= 1'b0; |
end |
else if (wb_rdy_nhz & next_pipe_state[2]) |
begin |
ir2dd <= ir1dd; |
ir2fd <= ir1fd; |
end |
|
always @(posedge clk ) |
if (wb_rdy_nhz & next_pipe_state[0]) exec_ir2 <= 1'b1; |
else exec_ir2 <= 1'b0; |
|
|
|
|
|
//--------------- block move flags ------------------------ |
always @(posedge clk) |
if (dec_state == DEC_ED) blk_inc_flg <= dec_blk_inc; |
|
always @(posedge clk) |
if (dec_state == DEC_ED) blk_rpt_flg <= dec_blk_rpt; |
|
|
always @(posedge clk) |
if (dec_state == DEC_ED) blk_io_flg <= dec_blk_io; |
|
|
//-------------------------- memory interface stuff ---------------------------- |
|
|
// -- wb_adr |
always @(posedge clk) if (wb_rdy) wb_adr <= mux21; |
|
// -- wb_we; |
|
always @(posedge clk or posedge rst) |
if (rst) wb_we <= 1'b0; |
else if (wb_rdy_nhz) wb_we <= we_next; |
|
|
|
// -- wb_cyc |
|
wire no_wb_start = mem_idle | mem_halt | mem_op3 & blk_cmp_reg | mem_op1 & rmw_reg; |
always @(posedge clk or posedge rst) |
if (rst) wb_cyc <= 1'b0; |
else if (wb_rdy_nhz) wb_cyc <= next_mem_state != MEM_NOP ; |
|
// -- wb_stb; |
|
always @(posedge clk or posedge rst) |
if (rst) wb_stb <= 1'b0; |
else if (wb_rdy_nhz) wb_stb <= next_mem_state != MEM_NOP ; |
|
|
// -- wb_lock lets not worry about lock unless somebody thinks it matters. |
|
// -- wb_tga_io |
always @(posedge clk or posedge rst) |
if (rst) wb_tga_io <= 2'b0; |
else if (wb_rdy_nhz) |
begin |
if (next_mem_state == MEM_IOF_C | |
next_mem_state == MEM_IOS_C | |
next_mem_state == MEM_IOF_N | |
next_mem_state == MEM_IOS_N ) wb_tga_io <= TAG_IO; |
|
else if (next_mem_state == MEM_INTA ) wb_tga_io <= TAG_INT; |
else wb_tga_io <= 2'b0 ; |
end |
|
//------------ the input-output data register (nn) ----------------------------------------- |
// basicaly we store lsb's folowed by msb's |
// input is always to msb (of input regiser) first (if a 2 byte operand, lsb<=msb before transfer) |
// this gets nn to position { msb, lsb } before we execute 2 byte transfer. |
// |
// if we don't update - we byte swap as well as |
// when we read |
// IMPORTANT We store from MSB's so that on block moves read and write from same place. |
// this makes the output look somewhat bass-ackwards but who is looking? |
// |
// There is probably a simpler way to do this. Unfortunately there are a lot of |
// dependencies here. Ill continue as planned till it proves untractable. |
// Issue is that we are using ir1 to provide the op specification -- but in general |
// ir1 gets gronked before 2nd store (if it happens) - so we need to capture both |
// data first time OSIXpD OS1 OSSP, and MEM_OSNN |
// |
// on consideration lets make a flag flag_firstos that gets set on first store after |
// DEC_EXEC |
// ISSUE reads both here and in ir1 need to execute on wb_ack ? |
// I recall wb_ack must stay active until a change in cycle ? |
// need to review wb spec. |
// |
//issue: how is EXs6SP7_HL implemented -- it is known as a rmw - and only trick for this file is |
// that nn must be properly updates with ir2 |
|
always @(posedge clk or posedge rst) |
if (rst) flag_os1 <= 1'b0; |
else if ((DEC_EXEC == next_dec_state) & wb_rdy) flag_os1 <= 1'b0; |
else if ( we_next ) flag_os1 <= 1'b1; |
|
|
wire [15:0] pc_2 = pc - 16'h2; |
always @(posedge clk) |
if (wb_rdy_nhz) |
begin |
if ( we_next & flag_os1) nn <= { nn[7:0], nn[15:8] } ; |
else if(we_next & ( next_mem_state == MEM_CALL)) nn <= {pc[7:0], pc[15:8]}; |
else if(we_next & ( next_mem_state == MEM_OSSP_PCM2)) nn <= {pc_2[7:0], pc_2[15:8]}; |
else if(EXs6SP7_HL== ir2 & ir2dd & exec_ir2) nn <= ixr; |
else if(EXs6SP7_HL== ir2 & ir2fd & exec_ir2) nn <= iyr; |
else if(EXs6SP7_HL== ir2 & exec_ir2) nn <= hl; |
// these are the general cases with ir1 providing register specification |
else if(we_next & ( next_mem_state == MEM_OS1 | |
next_mem_state == MEM_OSIXpD | |
next_mem_state == MEM_OSSP | |
next_mem_state == MEM_OSNN ) ) |
begin |
if (os_a) nn[15:8] <= ar; |
if (os_b) nn[15:8] <= br; |
if (os_c) nn <= {cr, br }; // use for PUSHsBC |
if (os_d) nn[15:8] <= dr; |
if (os_e) nn <= {er, dr }; // use for PUSHsDE |
if (os_h) nn[15:8] <= hr; |
if (os_l) nn <= {lr, hr }; // use for PUSHsHL |
if (os_f) nn <= {fr, ar }; // use for PUSHsAF |
end |
|
else nn <= { wb_dat_i, nn[15:8] }; |
end |
|
|
|
//------------------- pc and sp ---------------------------------------------------- |
always @(posedge clk or posedge rst) |
if (rst) pc <= 16'h0; |
else if (wb_rdy_nhz) |
begin |
if (next_mem_state == MEM_DECPC) pc <= pc - 16'h1; // decrementer could perhaps be shared. |
if (next_mem_state == MEM_IFPP1) pc <= adr_alu; |
if (next_mem_state == MEM_CALL ) pc <= nn; //Use MEM_CALL to exchange pc<=>nn |
if (next_mem_state == MEM_IFRST) pc <= src_mux; |
if (next_mem_state == MEM_JMPHL) pc <= src_mux; |
if (next_mem_state == MEM_IFNN ) pc <= src_mux; |
if (next_mem_state == MEM_IFINT) pc <= src_mux; |
end |
|
//---------------------------------- sp ----------------------------------------------------- |
// |
// with pc updates are always made from ir1 as the PC is so critical to instruction flow. |
// (this of course creates the possibility of an "inst_hazard" - where data is stored in an |
// instruction already fetched - see below) |
// with sp the situation is not so simple. |
// Issues - especially regarding hazards. |
// |
// LDsSP_NN this should be done from ir2 - no hazard as active state is ALWAYS IF2 |
// |
// ADDsHL_SP The add is a pre-add so sp cannot be modified before inst is executed from ir2 |
// DECsSP Just do it with ir1 at DEC_EXEC gotcha need -- IFPP1 in general use ir2 -> hazard |
// EXs6SP7_HL rmw - no change to sp - no issue here |
// INCsSP Just do it with ir1 at DEC_EXEC gotcha -- IFPP1 use ir2 -> hazard |
// LDsSP_HL do from ir1 and use standard hazard logic (if H or L is being |
// updated -- wait) |
// |
// ED_LDs6NN7_REG REG== SP // needs to be done from ir2 |
// ED_LDsREG_6NN7 REG== SP // do from ir2 - no hazard as executed on IF2 - refill pipe |
|
always @(posedge clk ) |
if (exec_ir2 ) // this has priority of course |
begin |
if (LDsSP_NN == ir2) sp <= nn; |
if (ED_LDsREG_6NN7 == ir2) sp <= nn; |
if ( DECsSP == ir2 ) sp <= add16; |
if ( INCsSP == ir2 ) sp <= add16; |
end |
else if (wb_rdy_nhz) |
begin |
if ( DECsSP == ir1 & dec_state == DEC_EXEC) sp <= adr_alu; |
if ( INCsSP == ir1 & dec_state == DEC_EXEC) sp <= adr_alu; |
if ( LDsSP_HL == ir1 & dec_state == DEC_EXEC) sp <= {hr,lr}; |
if (next_mem_state == MEM_OFSP ) sp <= adr_alu; |
if (next_mem_state == MEM_OSSP ) sp <= adr_alu; |
if (next_mem_state == MEM_OSSP_PCM2 ) sp <= adr_alu; |
if (next_mem_state == MEM_OSSP_P ) sp <= adr_alu; |
end |
//----------------- inst hazard logic ------------------------------------------ |
|
|
|
always @(posedge clk or posedge rst) |
if (rst) inst_haz <= 1'b0; |
else if (we_next & (pc - 16'h1) == mux21) inst_haz <= 1'b1; |
else if (dec_state == DEC_EXEC) inst_haz <= 1'b0; // highest priority interrupt |
|
//-------------------- int logic ---------------------------------------- |
// We have a wishbone interrupt system - which i guess does not preclude a |
// non-maskable interrupt...... but bottom line is that such an interrupt is |
// definately out of favor with current system thinking. Within an embedded system |
// ( the target application here ) a single interrupt controller capable of handeling |
// as many interrupts as desired is the best choice. |
// Therefore we enable only mode 2 interrupts and a single enable ff. |
// |
// This begs the question of what to do with the "RETI" instruction -- ED4D. We opt to |
// enable interrupts with this instruction (and all its "aliases"). |
// |
always @(posedge clk or posedge rst) |
if (rst) int_en <= 1'b0; |
else if (wb_rdy_nhz) |
begin |
if ((dec_state == DEC_EXEC) & (DI== ir1)) int_en <= 1'b0; |
else if ((dec_state == DEC_EXEC) & en_int_next) int_en <= 1'b1; |
else if ((dec_state == DEC_ED) & ed_retn) int_en <= 1'b0; |
if (dec_state == DEC_INT1) int_en <= 1'b0; |
end |
|
|
always @(posedge clk or posedge rst) |
if (rst) en_int_next <=1'b0; |
else if (wb_rdy_nhz) |
begin |
if ((dec_state == DEC_EXEC) & (EI== ir1)) en_int_next <=1'b1; |
else if (dec_state == DEC_EXEC) en_int_next <=1'b0; |
end |
|
always @(posedge clk) |
wb_irq_sync <= wb_int_rq; |
|
assign wb_int = wb_irq_sync & int_en; |
|
endmodule |
|
/tags/arelease/rts_header.v
0,0 → 1,65
/////////////////////////////////////////////////////////////////////////////////////////////////// |
//// //// |
//// WISHBONE Connection Matrix Top Level //// |
//// //// |
//// //// |
//// Author: B.J. Porcella //// |
//// bporcella@sbcglobal.net //// |
//// //// |
//// //// |
//// //// |
/////////////////////////////////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000-2002 B.J. Porcella //// |
//// Real Time Solutions //// |
//// //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
/////////////////////////////////////////////////////////////////////////////////////////////////// |
// CVS Log |
// |
// $Id: rts_header.v,v 1.1.1.1 2004-06-18 08:38:39 mihal Exp $ |
// |
// $Date: 2004-06-18 08:38:39 $ |
// $Revision: 1.1.1.1 $ |
// $Author: mihal $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2004/04/13 23:47:42 bporcella |
// import first files |
// |
// |
// |
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0 |
module |
|
//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0 |
//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0 |
//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0 |
//-------1---------2---------3--------Wires------5---------6---------7---------8---------9--------0 |
//-------1---------2---------3--------Registers--5---------6---------7---------8---------9--------0 |
//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0 |
//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0 |
|
endmodule |
/tags/arelease/doc/work_xx.v
0,0 → 1,171
Searching for: XX |
// dec_n1 |
LDsB_N ; 06 XX |
LDsC_N ; 0E XX |
LDsD_N ; 16 XX |
LDsE_N ; 1E XX |
LDsH_N ; 26 XX |
LDsL_N ; 2E XX |
LDs6HL7_N ; 36 XX |
LDsA_N ; 3E XX |
ADDsA_N ; C6 XX |
ADCsA_N ; CE XX |
OUTs6N7_A ; D3 XX |
SUBsN ; D6 XX |
INsA_6N7 ; DB XX |
|
|
|
//dec_n2 |
LDsBC_NN ; 01 XX XX |
LDsDE_NN ; 11 XX XX |
LDsHL_NN ; 21 XX XX |
LDs6NN7_HL ; 22 XX XX |
LDsHL_6NN7 ; 2A XX XX |
LDsSP_NN ; 31 XX XX |
LDs6NN7_A ; 32 XX XX |
LDsA_6NN7 ; 3A XX XX |
CALLsNZ_NN ; C4 XX XX |
CALLsZ_NN ; CC XX XX |
CALLsNN ; CD XX XX |
CALLsNC_NN ; D4 XX XX |
CALLsNC_NN ; D4 XX XX |
CALLsC_NN ; DC XX XX |
|
|
|
|
|
LD IX,NN ; DD 21 XX XX |
LD (NN),IX ; DD 22 XX XX |
LD IX,(NN) ; DD 2A XX XX |
INC (IX+N) ; DD 34 XX |
DEC (IX+N) ; DD 35 XX |
LD (IX+N),N ; DD 36 XX XX |
LD B,(IX+N) ; DD 46 XX |
LD C,(IX+N) ; DD 4E XX |
LD D,(IX+N) ; DD 56 XX |
LD E,(IX+N) ; DD 5E XX |
LD H,(IX+N) ; DD 66 XX |
LD L,(IX+N) ; DD 6E XX |
LD (IX+N),B ; DD 70 XX |
LD (IX+N),C ; DD 71 XX |
LD (IX+N),D ; DD 72 XX |
LD (IX+N),E ; DD 73 XX |
LD (IX+N),H ; DD 74 XX |
LD (IX+N),L ; DD 75 XX |
LD (IX+N),A ; DD 77 XX |
LD A,(IX+N) ; DD 7E XX |
ADD A,(IX+N) ; DD 86 XX |
ADC A,(IX+N) ; DD 8E XX |
SUB (IX+N) ; DD 96 XX |
SBC A,(IX+N) ; DD 9E XX |
AND (IX+N) ; DD A6 XX |
XOR (IX+N) ; DD AE XX |
OR (IX+N) ; DD B6 XX |
CP (IX+N) ; DD BE XX |
RLC (IX+N) ; DD CB XX 06 |
RRC (IX+N) ; DD CB XX 0E |
RL (IX+N) ; DD CB XX 16 |
RR (IX+N) ; DD CB XX 1E |
SLA (IX+N) ; DD CB XX 26 |
SRA (IX+N) ; DD CB XX 2E |
BIT 0,(IX+N) ; DD CB XX 46 |
BIT 1,(IX+N) ; DD CB XX 4E |
BIT 2,(IX+N) ; DD CB XX 56 |
BIT 3,(IX+N) ; DD CB XX 5E |
BIT 4,(IX+N) ; DD CB XX 66 |
BIT 5,(IX+N) ; DD CB XX 6E |
BIT 6,(IX+N) ; DD CB XX 76 |
BIT 7,(IX+N) ; DD CB XX 7E |
RES 0,(IX+N) ; DD CB XX 86 |
RES 1,(IX+N) ; DD CB XX 8E |
RES 2,(IX+N) ; DD CB XX 96 |
RES 3,(IX+N) ; DD CB XX 9E |
RES 4,(IX+N) ; DD CB XX A6 |
RES 5,(IX+N) ; DD CB XX AE |
RES 6,(IX+N) ; DD CB XX B6 |
RES 7,(IX+N) ; DD CB XX BE |
SET 0,(IX+N) ; DD CB XX C6 |
SET 1,(IX+N) ; DD CB XX CE |
SET 2,(IX+N) ; DD CB XX D6 |
SET 3,(IX+N) ; DD CB XX DE |
SET 4,(IX+N) ; DD CB XX E6 |
SET 5,(IX+N) ; DD CB XX EE |
SET 6,(IX+N) ; DD CB XX F6 |
SET 7,(IX+N) ; DD CB XX FE |
SBC A,N ; DE XX |
CALL PO,NN ; E4 XX XX |
AND N ; E6 XX |
CALL PE,NN ; EC XX XX |
LD (NN),BC ; ED 43 XX XX |
LD BC,(NN) ; ED 4B XX XX |
LD (NN),DE ; ED 53 XX XX |
LD DE,(NN) ; ED 5B XX XX |
LD (NN),SP ; ED 73 XX XX |
LD SP,(NN) ; ED 7B XX XX |
XOR N ; EE XX |
CALL P,NN ; F4 XX XX |
OR N ; F6 XX |
CALL M,NN ; FC XX XX |
LD IY,NN ; FD 21 XX XX |
LD (NN),IY ; FD 22 XX XX |
LD IY,(NN) ; FD 2A XX XX |
INC (IY+N) ; FD 34 XX |
DEC (IY+N) ; FD 35 XX |
LD (IY+N),N ; FD 36 XX XX |
LD B,(IY+N) ; FD 46 XX |
LD C,(IY+N) ; FD 4E XX |
LD D,(IY+N) ; FD 56 XX |
LD E,(IY+N) ; FD 5E XX |
LD H,(IY+N) ; FD 66 XX |
LD L,(IY+N) ; FD 6E XX |
LD (IY+N),B ; FD 70 XX |
LD (IY+N),C ; FD 71 XX |
LD (IY+N),D ; FD 72 XX |
LD (IY+N),E ; FD 73 XX |
LD (IY+N),H ; FD 74 XX |
LD (IY+N),L ; FD 75 XX |
LD (IY+N),A ; FD 77 XX |
LD A,(IY+N) ; FD 7E XX |
ADD A,(IY+N) ; FD 86 XX |
ADC A,(IY+N) ; FD 8E XX |
SUB (IY+N) ; FD 96 XX |
SBC A,(IY+N) ; FD 9E XX |
AND (IY+N) ; FD A6 XX |
XOR (IY+N) ; FD AE XX |
OR (IY+N) ; FD B6 XX |
CP (IY+N) ; FD BE XX |
RLC (IY+N) ; FD CB XX 06 |
RRC (IY+N) ; FD CB XX 0E |
RL (IY+N) ; FD CB XX 16 |
RR (IY+N) ; FD CB XX 1E |
SLA (IY+N) ; FD CB XX 26 |
SRA (IY+N) ; FD CB XX 2E |
BIT 0,(IY+N) ; FD CB XX 46 |
BIT 1,(IY+N) ; FD CB XX 4E |
BIT 2,(IY+N) ; FD CB XX 56 |
BIT 3,(IY+N) ; FD CB XX 5E |
BIT 4,(IY+N) ; FD CB XX 66 |
BIT 5,(IY+N) ; FD CB XX 6E |
BIT 6,(IY+N) ; FD CB XX 76 |
BIT 7,(IY+N) ; FD CB XX 7E |
RES 0,(IY+N) ; FD CB XX 86 |
RES 1,(IY+N) ; FD CB XX 8E |
RES 2,(IY+N) ; FD CB XX 96 |
RES 3,(IY+N) ; FD CB XX 9E |
RES 4,(IY+N) ; FD CB XX A6 |
RES 5,(IY+N) ; FD CB XX AE |
RES 6,(IY+N) ; FD CB XX B6 |
RES 7,(IY+N) ; FD CB XX BE |
SET 0,(IY+N) ; FD CB XX C6 |
SET 1,(IY+N) ; FD CB XX CE |
SET 2,(IY+N) ; FD CB XX D6 |
SET 3,(IY+N) ; FD CB XX DE |
SET 4,(IY+N) ; FD CB XX E6 |
SET 5,(IY+N) ; FD CB XX EE |
SET 6,(IY+N) ; FD CB XX F6 |
SET 7,(IY+N) ; FD CB XX FE |
CP N ; FE XX |
Found 159 occurrence(s) in 1 file(s) |
|
/tags/arelease/doc/work_ofos.txt
0,0 → 1,362
ADCsA_A = 'h8F,// ADC A,A ; 8F |
ADCsA_B = 'h88,// ADC A,B ; 88 |
ADCsA_C = 'h89,// ADC A,C ; 89 |
ADCsA_D = 'h8A,// ADC A,D ; 8A |
ADCsA_E = 'h8B,// ADC A,E ; 8B |
ADCsA_H = 'h8C,// ADC A,H ; 8C |
ADCsA_L = 'h8D,// ADC A,L ; 8D |
ADCsA_N = 'hCE,// ADC A,N ; CE XX |
ADDsA_A = 'h87,// ADD A,A ; 87 |
ADDsA_B = 'h80,// ADD A,B ; 80 |
ADDsA_C = 'h81,// ADD A,C ; 81 |
ADDsA_D = 'h82,// ADD A,D ; 82 |
ADDsA_E = 'h83,// ADD A,E ; 83 |
ADDsA_H = 'h84,// ADD A,H ; 84 |
ADDsA_L = 'h85,// ADD A,L ; 85 |
ADDsA_N = 'hC6,// ADD A,N ; C6 XX |
ADDsHL_BC = 'h09,// ADD HL,BC ; 09 |
ADDsHL_DE = 'h19,// ADD HL,DE ; 19 |
ADDsHL_HL = 'h29,// ADD HL,HL ; 29 |
ADDsHL_SP = 'h39,// ADD HL,SP ; 39 |
ANDsA = 'hA7,// AND A ; A7 |
ANDsB = 'hA0,// AND B ; A0 |
ANDsC = 'hA1,// AND C ; A1 |
ANDsD = 'hA2,// AND D ; A2 |
ANDsE = 'hA3,// AND E ; A3 |
ANDsH = 'hA4,// AND H ; A4 |
ANDsL = 'hA5,// AND L ; A5 |
ANDsN = 'hE6,// AND N ; E6 XX |
CCF = 'h3F,// CCF ; 3F |
CPL = 'h2F,// CPL ; 2F |
CPsA = 'hBF,// CP A ; BF |
CPsB = 'hB8,// CP B ; B8 |
CPsC = 'hB9,// CP C ; B9 |
CPsD = 'hBA,// CP D ; BA |
CPsE = 'hBB,// CP E ; BB |
CPsH = 'hBC,// CP H ; BC |
CPsL = 'hBD,// CP L ; BD |
CPsN = 'hFE,// CP N ; FE XX |
DAA = 'h27,// DAA ; 27 |
DECsA = 'h3D,// DEC A ; 3D |
DECsB = 'h05,// DEC B ; 05 |
DECsBC = 'h0B,// DEC BC ; 0B |
DECsC = 'h0D,// DEC C ; 0D |
DECsD = 'h15,// DEC D ; 15 |
DECsDE = 'h1B,// DEC DE ; 1B |
DECsE = 'h1D,// DEC E ; 1D |
DECsH = 'h25,// DEC H ; 25 |
DECsHL = 'h2B,// DEC HL ; 2B |
DECsL = 'h2D,// DEC L ; 2D |
DECsSP = 'h3B,// DEC SP ; 3B |
DI = 'hF3,// DI ; F3 |
EI = 'hFB,// EI ; FB |
EXX = 'hD9,// EXX ; D9 |
EXsAF_AFp = 'h08,// EX AF,AF' ; 08 |
EXsDE_HL = 'hEB,// EX DE,HL ; EB |
HALT = 'h76,// HALT ; 76 |
INCsA = 'h3C,// INC A ; 3C |
INCsB = 'h04,// INC B ; 04 |
INCsBC = 'h03,// INC BC ; 03 |
INCsC = 'h0C,// INC C ; 0C |
INCsD = 'h14,// INC D ; 14 |
INCsDE = 'h13,// INC DE ; 13 |
INCsE = 'h1C,// INC E ; 1C |
INCsH = 'h24,// INC H ; 24 |
INCsHL = 'h23,// INC HL ; 23 |
INCsL = 'h2C,// INC L ; 2C |
INCsSP = 'h33,// INC SP ; 33 |
LDsA_A = 'h7F,// LD A,A ; 7F |
LDsA_B = 'h78,// LD A,B ; 78 |
LDsA_C = 'h79,// LD A,C ; 79 |
LDsA_D = 'h7A,// LD A,D ; 7A |
LDsA_E = 'h7B,// LD A,E ; 7B |
LDsA_H = 'h7C,// LD A,H ; 7C |
LDsA_L = 'h7D,// LD A,L ; 7D |
LDsA_N = 'h3E,// LD A,N ; 3E XX |
LDsBC_nn = 'h01,// LD BC,NN ; 01 XX XX |
LDsB_A = 'h47,// LD B,A ; 47 |
LDsB_B = 'h40,// LD B,B ; 40 |
LDsB_C = 'h41,// LD B,C ; 41 |
LDsB_D = 'h42,// LD B,D ; 42 |
LDsB_E = 'h43,// LD B,E ; 43 |
LDsB_H = 'h44,// LD B,H ; 44 |
LDsB_L = 'h45,// LD B,L ; 45 |
LDsB_N = 'h06,// LD B,N ; 06 XX |
LDsC_A = 'h4F,// LD C,A ; 4F |
LDsC_B = 'h48,// LD C,B ; 48 |
LDsC_C = 'h49,// LD C,C ; 49 |
LDsC_D = 'h4A,// LD C,D ; 4A |
LDsC_E = 'h4B,// LD C,E ; 4B |
LDsC_H = 'h4C,// LD C,H ; 4C |
LDsC_L = 'h4D,// LD C,L ; 4D |
LDsC_N = 'h0E,// LD C,N ; 0E XX |
LDsDE_NN = 'h11,// LD DE,NN ; 11 XX XX |
LDsD_A = 'h57,// LD D,A ; 57 |
LDsD_B = 'h50,// LD D,B ; 50 |
LDsD_C = 'h51,// LD D,C ; 51 |
LDsD_D = 'h52,// LD D,D ; 52 |
LDsD_E = 'h53,// LD D,E ; 53 |
LDsD_H = 'h54,// LD D,H ; 54 |
LDsD_L = 'h55,// LD D,L ; 55 |
LDsD_N = 'h16,// LD D,N ; 16 XX |
LDsE_A = 'h5F,// LD E,A ; 5F |
LDsE_B = 'h58,// LD E,B ; 58 |
LDsE_C = 'h59,// LD E,C ; 59 |
LDsE_D = 'h5A,// LD E,D ; 5A |
LDsE_E = 'h5B,// LD E,E ; 5B |
LDsE_H = 'h5C,// LD E,H ; 5C |
LDsE_L = 'h5D,// LD E,L ; 5D |
LDsE_N = 'h1E,// LD E,N ; 1E XX |
LDsHL_NN = 'h21,// LD HL,NN ; 21 XX XX |
LDsH_A = 'h67,// LD H,A ; 67 |
LDsH_B = 'h60,// LD H,B ; 60 |
LDsH_C = 'h61,// LD H,C ; 61 |
LDsH_D = 'h62,// LD H,D ; 62 |
LDsH_E = 'h63,// LD H,E ; 63 |
LDsH_H = 'h64,// LD H,H ; 64 |
LDsH_L = 'h65,// LD H,L ; 65 |
LDsH_N = 'h26,// LD H,N ; 26 XX |
LDsL_A = 'h6F,// LD L,A ; 6F |
LDsL_B = 'h68,// LD L,B ; 68 |
LDsL_C = 'h69,// LD L,C ; 69 |
LDsL_D = 'h6A,// LD L,D ; 6A |
LDsL_E = 'h6B,// LD L,E ; 6B |
LDsL_H = 'h6C,// LD L,H ; 6C |
LDsL_L = 'h6D,// LD L,L ; 6D |
LDsL_N = 'h2E,// LD L,N ; 2E XX |
LDsSP_HL = 'hF9,// LD SP,HL ; F9 |
LDsSP_NN = 'h31,// LD SP,NN ; 31 XX XX |
NOP = 'h00,// NOP ; 00 |
ORsA = 'hB7,// OR A ; B7 |
ORsB = 'hB0,// OR B ; B0 |
ORsC = 'hB1,// OR C ; B1 |
ORsD = 'hB2,// OR D ; B2 |
ORsE = 'hB3,// OR E ; B3 |
ORsH = 'hB4,// OR H ; B4 |
ORsL = 'hB5,// OR L ; B5 |
ORsN = 'hF6,// OR N ; F6 XX |
RLA = 'h17,// RLA ; 17 |
RLCA = 'h07,// RLCA ; 07 |
RRA = 'h1F,// RRA ; 1F |
RRCA = 'h0F,// RRCA ; 0F |
SBCsA = 'h9F,// SBC A ; 9F |
SBCsA_N = 'hDE,// SBC A,N ; DE XX |
SBCsB = 'h98,// SBC B ; 98 |
SBCsC = 'h99,// SBC C ; 99 |
SBCsD = 'h9A,// SBC D ; 9A |
SBCsE = 'h9B,// SBC E ; 9B |
SBCsH = 'h9C,// SBC H ; 9C |
SBCsL = 'h9D,// SBC L ; 9D |
SCF = 'h37,// SCF ; 37 |
SUBsA = 'h97,// SUB A ; 97 |
SUBsB = 'h90,// SUB B ; 90 |
SUBsC = 'h91,// SUB C ; 91 |
SUBsD = 'h92,// SUB D ; 92 |
SUBsE = 'h93,// SUB E ; 93 |
SUBsH = 'h94,// SUB H ; 94 |
SUBsL = 'h95,// SUB L ; 95 |
SUBsN = 'hD6,// SUB N ; D6 XX |
XORsA = 'hAF,// XOR A ; AF |
XORsB = 'hA8,// XOR B ; A8 |
XORsC = 'hA9,// XOR C ; A9 |
XORsD = 'hAA,// XOR D ; AA |
XORsE = 'hAB,// XOR E ; AB |
XORsH = 'hAC,// XOR H ; AC |
XORsL = 'hAD,// XOR L ; AD |
XORsN = 'hEE,// XOR N ; EE XX |
ED_SBCsHL_REG = 6'b01__0010, // compair with {ir[7:6],ir[3:0]} |
ED_ADCsHL_REG = 6'b01__1010, // compair with {ir[7:6],ir[3:0]} |
~CB_MEM & CB_RLC = 5'b00_000, // these must be compaired with ir[7:3] |
~CB_MEM & CB_RRC = 5'b00_001, // these must be compaired with ir[7:3] |
~CB_MEM & CB_RL = 5'b00_010, // these must be compaired with ir[7:3] |
~CB_MEM & CB_RR = 5'b00_011, // these must be compaired with ir[7:3] |
~CB_MEM & CB_SLA = 5'b00_100, // these must be compaired with ir[7:3] |
~CB_MEM & CB_SRA = 5'b00_101, // these must be compaired with ir[7:3] |
~CB_MEM & CB_SLL = 5'b00_110, // these must be compaired with ir[7:3] |
~CB_MEM & CB_SRL = 5'b00_111, // these must be compaired with ir[7:3] |
|
~CB_MEM & CB_BIT = 2'b01, // these must be compaired with ir[7:6] |
~CB_MEM & CB_RES = 2'b10, // these must be compaired with ir[7:6] |
~CB_MEM & CB_SET = 2'b11, // these must be compaired with ir[7:6] |
ED_NEG = 5'b01___100, // compair with {ir[7:6],ir[2:0]} all A<= -A |
ED_IMs0 = 'h46// IM 0 ; ED 46 set IM0 |
ED_LDsI_A = 'h47// LD I,A ; ED 47 move a to I |
ED_IMs1 = 'h56// IM 1 ; ED 56 set IM1 |
ED_LDsA_I = 'h57// LD A,I ; ED 57 move I to A |
ED_IMs2 = 'h5E// IM 2 ; ED 5E set IM2 |
|
|
|
|
|
|
|
|
// load 8 types |
LDsA_6BC7 = 'h0A,// LD A,(BC) ; 0A |
LDsA_6DE7 = 'h1A,// LD A,(DE) ; 1A |
LDsB_6HL7 = 'h46,// LD B,(HL) ; 46 |
LDsD_6HL7 = 'h56,// LD D,(HL) ; 56 |
LDsH_6HL7 = 'h66,// LD H,(HL) ; 66 |
ADDsA_6HL7 = 'h86,// ADD A,(HL) ; 86 |
SUBs6HL7 = 'h96,// SUB (HL) ; 96 |
ANDs6HL7 = 'hA6,// AND (HL) ; A6 |
ORs6HL7 = 'hB6,// OR (HL) ; B6 |
LDsC_6HL7 = 'h4E,// LD C,(HL) ; 4E |
LDsE_6HL7 = 'h5E,// LD E,(HL) ; 5E |
LDsL_6HL7 = 'h6E,// LD L,(HL) ; 6E |
LDsA_6HL7 = 'h7E,// LD A,(HL) ; 7E |
ADCsA_6HL7 = 'h8E,// ADC A,(HL) ; 8E |
SBCs6HL7 = 'h9E,// SBC (HL) ; 9E |
XORs6HL7 = 'hAE,// XOR (HL) ; AE |
CPs6HL7 = 'hBE,// CP (HL) ; BE |
LDsA_6NN7 = 'h3A,// LD A,(NN) ; 3A XX XX |
CB_MEM & CB_BIT = 2'b01, // (HL) these must be compaired with ir[7:6] |
|
|
|
// load 16 types |
LDsHL_6NN7 = 'h2A,// LD HL,(NN) ; 2A XX XX |
POPsAF = 'hF1,// POP AF ; F1 AF<- (SP++ ++) |
POPsBC = 'hC1,// POP BC ; C1 BC<- (SP++ ++) |
POPsDE = 'hD1,// POP DE ; D1 DE<- (SP++ ++) |
POPsHL = 'hE1,// POP HL ; E1 HL<- (SP++ ++) |
ED_LDsREG_6NN7 = 6'b01__1011, // compair with {ir[7:6],ir[3:0]} REG = BC,DE,HL,SP |
|
|
// store 8 types |
LDs6HL7_N = 'h36,// LD (HL),N ; 36 XX |
LDs6BC7_A = 'h02,// LD (BC),A ; 02 |
LDs6DE7_A = 'h12,// LD (DE),A ; 12 |
LDs6HL7_A = 'h77,// LD (HL),A ; 77 |
LDs6HL7_B = 'h70,// LD (HL),B ; 70 |
LDs6HL7_C = 'h71,// LD (HL),C ; 71 |
LDs6HL7_D = 'h72,// LD (HL),D ; 72 |
LDs6HL7_E = 'h73,// LD (HL),E ; 73 |
LDs6HL7_H = 'h74,// LD (HL),H ; 74 |
LDs6HL7_L = 'h75,// LD (HL),L ; 75 |
LDs6NN7_A = 'h32,// LD (NN),A ; 32 XX XX |
|
// store 16 types |
PUSHsAF = 'hF5,// PUSH AF ; F5 (-- --SP) <- AF |
PUSHsBC = 'hC5,// PUSH BC ; C5 (-- --SP) <- BC |
PUSHsDE = 'hD5,// PUSH DE ; D5 (-- --SP) <- DE |
PUSHsHL = 'hE5,// PUSH HL ; E5 (-- --SP) <- HL |
LDs6NN7_HL = 'h22,// LD (NN),HL ; 22 XX XX |
ED_LDs6NN7_REG = 6'b01__0011,// XX XX compair with {ir[7:6],ir[3:0]} REG = BC,DE,HL,SP |
|
// rmw 8 types |
INCs6HL7 = 'h34,// INC (HL) ; 34 |
DECs6HL7 = 'h35,// DEC (HL) ; 35 |
|
ED_RRD = 'h67// RRD ; ED 67 nibble roates A (HL) no prefix |
ED_RLD = 'h6F// RLD ; ED 6F nibble roates A (HL) no prefix |
//CB_MEM = 3'h110, // this must be compaired with ir[2:0] |
CB_MEM & CB_RLC = 5'b00_000, // these must be compaired with ir[7:3] (HL) |
CB_MEM & CB_RRC = 5'b00_001, // these must be compaired with ir[7:3] (HL) |
CB_MEM & CB_RL = 5'b00_010, // these must be compaired with ir[7:3] (HL) |
CB_MEM & CB_RR = 5'b00_011, // these must be compaired with ir[7:3] (HL) |
CB_MEM & CB_SLA = 5'b00_100, // these must be compaired with ir[7:3] (HL) |
CB_MEM & CB_SRA = 5'b00_100, // these must be compaired with ir[7:3] (HL) |
CB_MEM & CB_SRL = 5'b00_110, // these must be compaired with ir[7:3] (HL) |
CB_MEM & CB_RES = 2'b10, // these must be compaired with ir[7:6] (HL) |
CB_MEM & CB_SET = 2'b11, // these must be compaired with ir[7:6] (HL) |
|
|
|
// rmw 16 types |
EXs6SP7_HL = 'hE3,// EX (SP),HL ; E3 |
|
// Jumps only trick here is that next inst is not valid - ignore it |
JRs$t2 = 'h18,// JR $+2 ; 18 XX |
JRsC_$t2 = 'h38,// JR C,$+2 ; 38 |
JRsNC_$t2 = 'h30,// JR NC,$+2 ; 30 |
JRsNZ_$t2 = 'h20,// JR NZ,$+2 ; 20 |
JRsZ_$t2 = 'h28,// JR Z,$+2 ; 28 |
DJNZs$t2 = 'h10,// DJNZ $+2 ; 10 XX XX |
JPs = 'hC3,// JP $+3 ; C3 XX XX |
JPsC = 'hDA,// JP C,$+3 ; DA XX XX |
JPsHL = 'hE9,// JP HL ; E9 // documented as indirect IS NOT |
JPsM = 'hFA,// JP M,$+3 ; FA XX XX |
JPsNC = 'hD2,// JP NC,$+3 ; D2 XX XX |
JPsNZ = 'hC2,// JP NZ,$+3 ; C2 XX XX |
JPsPE = 'hEA,// JP PE,$+3 ; EA XX XX |
JPsPO = 'hE2,// JP PO,$+3 ; E2 XX XX |
JPsP = 'hF2,// JP P,$+3 ; F2 XX XX |
JPsZ = 'hCA,// JP Z,$+3 ; CA XX XX |
RSTs0 = 'hC7,// RST 0 ; C7 |
RSTs8H = 'hCF,// RST 8H ; CF |
RSTs10H = 'hD7,// RST 10H ; D7 |
RSTs18H = 'hDF,// RST 18H ; DF |
RSTs20H = 'hE7,// RST 20H ; E7 |
RSTs28H = 'hEF,// RST 28H ; EF |
RSTs30H = 'hF7,// RST 30H ; F7 |
RSTs38H = 'hFF,// RST 38H ; FF |
|
|
// calls |
CALLsC_NN = 'hDC,// CALL C,NN ; DC XX XX (-- --SP) <- PC, PC<-NN |
CALLsM_NN = 'hFC,// CALL M,NN ; FC XX XX (-- --SP) <- PC, PC<-NN |
CALLsNC_NN = 'hD4,// CALL NC,NN ; D4 XX XX (-- --SP) <- PC, PC<-NN |
CALLsNN = 'hCD,// CALL NN ; CD XX XX (-- --SP) <- PC, PC<-NN |
CALLsNZ_NN = 'hC4,// CALL NZ,NN ; C4 XX XX (-- --SP) <- PC, PC<-NN |
CALLsPE_NN = 'hEC,// CALL PE,NN ; EC XX XX (-- --SP) <- PC, PC<-NN |
CALLsPO_NN = 'hE4,// CALL PO,NN ; E4 XX XX (-- --SP) <- PC, PC<-NN |
CALLsP_NN = 'hF4,// CALL P,NN ; F4 XX XX (-- --SP) <- PC, PC<-NN |
CALLsZ_NN = 'hCC,// CALL Z,NN ; CC XX XX (-- --SP) <- PC, PC<-NN |
|
//returns |
RET = 'hC9,// RET ; C9 PC <- (SP++ ++) |
RETsC = 'hD8,// RET C ; D8 PC <- (SP++ ++) |
RETsM = 'hF8,// RET M ; F8 PC <- (SP++ ++) |
RETsNC = 'hD0,// RET NC ; D0 PC <- (SP++ ++) |
RETsNZ = 'hC0,// RET NZ ; C0 PC <- (SP++ ++) |
RETsP = 'hF0,// RET P ; F0 PC <- (SP++ ++) |
RETsPE = 'hE8,// RET PE ; E8 PC <- (SP++ ++) |
RETsPO = 'hE0,// RET PO ; E0 PC <- (SP++ ++) |
RETsZ = 'hC8,// RET Z ; C8 PC <- (SP++ ++) |
ED_RETN = 5'b01___101; // compair with {ir[7:6],ir[2:0]} and !reti |
|
|
//io input |
INsA_6N7 = 'hDB,// IN A,(N) ; DB XX A<-(Nio)//silly |
ED_INsREG_6C7 = 5'b01___000,// compair with {ir[7:6],ir[2:0]} really (BCio) |
|
//io output |
OUTs6N7_A = 'hD3,// OUT (N),A ; D3 XX A-> (Nio) |
ED_OUTs6C7_REG = 5'b01___001,// compair with {ir[7:6],ir[2:0]} |
|
// ED Block Move messyness |
// |
ED_LDI = 'hA0// LDI ; ED A0 (DE++) <= (HL++) , BC-- |
ED_LDD = 'hA8// LDD ; ED A8 (DE--) <= (HL--) , BC-- |
ED_LDIR = 'hB0// LDIR ; ED B0 (DE++) <= (HL++) , BC-- Repeat til BC==0 |
ED_LDDR = 'hB8// LDDR ; ED B8 (DE--) <= (HL--) , BC-- Repeat til BC==0 |
|
|
ED_CPI = 'hA1// CPI ; ED A1 A - (HL++) , BC-- |
ED_CPD = 'hA9// CPD ; ED A9 A - (HL--) , BC-- |
ED_CPIR = 'hB1// CPIR ; ED B1 A - (HL++) , BC-- repeat if(|B |
ED_CPDR = 'hB9// CPDR ; ED B9 A - (HL--) , BC-- repeat if(|B |
|
|
ED_INI = 'hA2// INI ; ED A2 (HL++) <- (Cio) , B-- |
ED_IND = 'hAA// IND ; ED AA (HL--) <- (Cio) , B-- |
ED_INIR = 'hB2// INIR ; ED B2 (HL++) <- (Cio) , B-- repeat if(|B) |
ED_INDR = 'hBA// INDR ; ED BA (HL--) <- (Cio) , B-- repeat if(|B) |
|
|
|
ED_OUTI = 'hA3// OUTI ; ED A3 (Cio) <-(HL++) , B-- |
ED_OUTD = 'hAB// OUTD ; ED AB (Cio) <-(HL--) , B-- |
ED_OTIR = 'hB3// OTIR ; ED B3 (Cio) <-(HL++) , B-- rpt if(|B) |
ED_OTDR = 'hBB// OTDR ; ED BB (Cio) <-(HL--) , B-- rpt if(|B) |
|
|
|
|
|
CBgrp = 'hCB,// CBgrp is rotates and bit munging below |
EDgrp = 'hED,// EDgrp ED |
FDgrp = 'hFD,// FDgrp FD |
DDgrp = 'hDD,// DDgrp |
/tags/arelease/doc/work_flag.txt
0,0 → 1,358
// update all flags from alu8 for logic operations pv <= parity else ofl |
ADCsA_A = 'h8F,// ADC A,A ; 8F |
ADCsA_B = 'h88,// ADC A,B ; 88 |
ADCsA_C = 'h89,// ADC A,C ; 89 |
ADCsA_D = 'h8A,// ADC A,D ; 8A |
ADCsA_E = 'h8B,// ADC A,E ; 8B |
ADCsA_H = 'h8C,// ADC A,H ; 8C |
ADCsA_L = 'h8D,// ADC A,L ; 8D |
ADCsA_N = 'hCE,// ADC A,N ; CE XX |
ADDsA_A = 'h87,// ADD A,A ; 87 |
ADDsA_B = 'h80,// ADD A,B ; 80 |
ADDsA_C = 'h81,// ADD A,C ; 81 |
ADDsA_D = 'h82,// ADD A,D ; 82 |
ADDsA_E = 'h83,// ADD A,E ; 83 |
ADDsA_H = 'h84,// ADD A,H ; 84 |
ADDsA_L = 'h85,// ADD A,L ; 85 |
ADDsA_N = 'hC6,// ADD A,N ; C6 XX |
ANDsA = 'hA7,// AND A ; A7 |
ANDsB = 'hA0,// AND B ; A0 |
ANDsC = 'hA1,// AND C ; A1 |
ANDsD = 'hA2,// AND D ; A2 |
ANDsE = 'hA3,// AND E ; A3 |
ANDsH = 'hA4,// AND H ; A4 |
ANDsL = 'hA5,// AND L ; A5 |
ANDsN = 'hE6,// AND N ; E6 XX |
CPsA = 'hBF,// CP A ; BF |
CPsB = 'hB8,// CP B ; B8 |
CPsC = 'hB9,// CP C ; B9 |
CPsD = 'hBA,// CP D ; BA |
CPsE = 'hBB,// CP E ; BB |
CPsH = 'hBC,// CP H ; BC |
CPsL = 'hBD,// CP L ; BD |
CPsN = 'hFE,// CP N ; FE XX |
ORsA = 'hB7,// OR A ; B7 |
ORsB = 'hB0,// OR B ; B0 |
ORsC = 'hB1,// OR C ; B1 |
ORsD = 'hB2,// OR D ; B2 |
ORsE = 'hB3,// OR E ; B3 |
ORsH = 'hB4,// OR H ; B4 |
ORsL = 'hB5,// OR L ; B5 |
ORsN = 'hF6,// OR N ; F6 XX |
SBCsA = 'h9F,// SBC A ; 9F |
SBCsA_N = 'hDE,// SBC A,N ; DE XX |
SBCsB = 'h98,// SBC B ; 98 |
SBCsC = 'h99,// SBC C ; 99 |
SBCsD = 'h9A,// SBC D ; 9A |
SBCsE = 'h9B,// SBC E ; 9B |
SBCsH = 'h9C,// SBC H ; 9C |
SBCsL = 'h9D,// SBC L ; 9D |
SUBsA = 'h97,// SUB A ; 97 |
SUBsB = 'h90,// SUB B ; 90 |
SUBsC = 'h91,// SUB C ; 91 |
SUBsD = 'h92,// SUB D ; 92 |
SUBsE = 'h93,// SUB E ; 93 |
SUBsH = 'h94,// SUB H ; 94 |
SUBsL = 'h95,// SUB L ; 95 |
SUBsN = 'hD6,// SUB N ; D6 XX |
XORsA = 'hAF,// XOR A ; AF |
XORsB = 'hA8,// XOR B ; A8 |
XORsC = 'hA9,// XOR C ; A9 |
XORsD = 'hAA,// XOR D ; AA |
XORsE = 'hAB,// XOR E ; AB |
XORsH = 'hAC,// XOR H ; AC |
XORsL = 'hAD,// XOR L ; AD |
XORsN = 'hEE,// XOR N ; EE XX |
|
// same as above but no cf change oh my god why? |
DECsA = 'h3D,// DEC A ; 3D |
DECsB = 'h05,// DEC B ; 05 |
DECsC = 'h0D,// DEC C ; 0D |
DECsD = 'h15,// DEC D ; 15 |
DECsE = 'h1D,// DEC E ; 1D |
DECsH = 'h25,// DEC H ; 25 |
DECsL = 'h2D,// DEC L ; 2D |
INCsA = 'h3C,// INC A ; 3C |
INCsB = 'h04,// INC B ; 04 |
INCsC = 'h0C,// INC C ; 0C |
INCsD = 'h14,// INC D ; 14 |
INCsE = 'h1C,// INC E ; 1C |
INCsH = 'h24,// INC H ; 24 |
INCsL = 'h2C,// INC L ; 2C |
|
// update h n c (f5, f3) from alu16 |
ADDsHL_BC = 'h09,// ADD HL,BC ; 09 |
ADDsHL_DE = 'h19,// ADD HL,DE ; 19 |
ADDsHL_HL = 'h29,// ADD HL,HL ; 29 |
ADDsHL_SP = 'h39,// ADD HL,SP ; 39 |
INCsBC = 'h03,// INC BC ; 03 |
INCsDE = 'h13,// INC DE ; 13 |
INCsHL = 'h23,// INC HL ; 23 |
INCsSP = 'h33,// INC SP ; 33 |
// update all flags from alu16 |
ED_SBCsHL_REG = 6'b01__0010, // compair with {ir[7:6],ir[3:0]} |
ED_ADCsHL_REG = 6'b01__1010, // compair with {ir[7:6],ir[3:0]} |
|
|
// the shifts probably muck with all flags (some operations are |
// guarenteed not to change certain flags ) |
// crap docs say sf and zf never change for these ops. |
RLA = 'h17,// RLA ; 17 |
RLCA = 'h07,// RLCA ; 07 |
RRA = 'h1F,// RRA ; 1F |
RRCA = 'h0F,// RRCA ; 0F |
// sf and zf do change for theses |
CB_RLC = 5'b00_000, // these must be compaired with ir[7:3] |
CB_RRC = 5'b00_001, // these must be compaired with ir[7:3] |
CB_RL = 5'b00_010, // these must be compaired with ir[7:3] |
CB_RR = 5'b00_011, // these must be compaired with ir[7:3] |
CB_SLA = 5'b00_100, // these must be compaired with ir[7:3] |
CB_SRA = 5'b00_101, // these must be compaired with ir[7:3] |
CB_SLL = 5'b00_110, // these must be compaired with ir[7:3] |
CB_SRL = 5'b00_111, // these must be compaired with ir[7:3] |
|
// pretty nomal stuff here |
CB_BIT = 2'b01, // these must be compaired with ir[7:6] |
// which alu? -- |
ED_NEG = 5'b01___100, // compair with {ir[7:6],ir[2:0]} all A<= -A |
// rmw 8 types |
INCs6HL7 = 'h34,// INC (HL) ; 34 |
DECs6HL7 = 'h35,// DEC (HL) ; 35 |
|
// ED Block Move messyness |
// hf and nf <= 0 pnf<= BC==0 |
ED_LDI = 'hA0// LDI ; ED A0 (DE++) <= (HL++) , BC-- |
ED_LDD = 'hA8// LDD ; ED A8 (DE--) <= (HL--) , BC-- |
ED_LDIR = 'hB0// LDIR ; ED B0 (DE++) <= (HL++) , BC-- Repeat til BC==0 |
ED_LDDR = 'hB8// LDDR ; ED B8 (DE--) <= (HL--) , BC-- Repeat til BC==0 |
// only c not affected - nf<=1 ? |
ED_CPI = 'hA1// CPI ; ED A1 A - (HL++) , BC-- |
ED_CPD = 'hA9// CPD ; ED A9 A - (HL--) , BC-- |
ED_CPIR = 'hB1// CPIR ; ED B1 A - (HL++) , BC-- repeat if(|B |
ED_CPDR = 'hB9// CPDR ; ED B9 A - (HL--) , BC-- repeat if(|B |
|
// all the ed i/o muck with all flags -- wonderful cf? |
// use the aluoutput for the b-1 computation. |
ED_INI = 'hA2// INI ; ED A2 (HL++) <- (Cio) , B-- |
ED_IND = 'hAA// IND ; ED AA (HL--) <- (Cio) , B-- |
ED_INIR = 'hB2// INIR ; ED B2 (HL++) <- (Cio) , B-- repeat if(|B) |
ED_INDR = 'hBA// INDR ; ED BA (HL--) <- (Cio) , B-- repeat if(|B) |
ED_OUTI = 'hA3// OUTI ; ED A3 (Cio) <-(HL++) , B-- |
ED_OUTD = 'hAB// OUTD ; ED AB (Cio) <-(HL--) , B-- |
ED_OTIR = 'hB3// OTIR ; ED B3 (Cio) <-(HL++) , B-- rpt if(|B) |
ED_OTDR = 'hBB// OTDR ; ED BB (Cio) <-(HL--) , B-- rpt if(|B) |
|
ED_INsREG_6C7 = 5'b01___000,// compair with {ir[7:6],ir[2:0]} really (BCio) |
ED_OUTs6C7_REG = 5'b01___001,// compair with {ir[7:6],ir[2:0]} |
|
|
|
// special problems |
CCF = 'h3F,// CCF ; 3F // h<=c c<=1C N<=0 F3,F5? |
CPL = 'h2F,// CPL ; 2F // H<=1 N<=1 F3,F5? |
DAA = 'h27,// DAA ; 27 // H<=0??? |
SCF = 'h37,// SCF ; 37 |
ED_RRD = 'h67// RRD ; ED 67 nibble roates A HL |
ED_RLD = 'h6F// RLD ; ED 6F nibble roates A HL |
ED_LDsA_I = 'h57// LD A,I ; ED 57 move I to A |
|
|
|
// no changes |
CB_RES = 2'b10, // these must be compaired with ir[7:6] |
CB_SET = 2'b11, // these must be compaired with ir[7:6] |
DECsBC = 'h0B,// DEC BC ; 0B |
DECsDE = 'h1B,// DEC DE ; 1B |
DECsHL = 'h2B,// DEC HL ; 2B |
DECsSP = 'h3B,// DEC SP ; 3B |
DI = 'hF3,// DI ; F3 |
EI = 'hFB,// EI ; FB |
EXX = 'hD9,// EXX ; D9 |
EXsAF_AFp = 'h08,// EX AF,AF' ; 08 |
EXsDE_HL = 'hEB,// EX DE,HL ; EB |
HALT = 'h76,// HALT ; 76 |
LDsA_A = 'h7F,// LD A,A ; 7F |
LDsA_B = 'h78,// LD A,B ; 78 |
LDsA_C = 'h79,// LD A,C ; 79 |
LDsA_D = 'h7A,// LD A,D ; 7A |
LDsA_E = 'h7B,// LD A,E ; 7B |
LDsA_H = 'h7C,// LD A,H ; 7C |
LDsA_L = 'h7D,// LD A,L ; 7D |
LDsA_N = 'h3E,// LD A,N ; 3E XX |
LDsBC_nn = 'h01,// LD BC,NN ; 01 XX XX |
LDsB_A = 'h47,// LD B,A ; 47 |
LDsB_B = 'h40,// LD B,B ; 40 |
LDsB_C = 'h41,// LD B,C ; 41 |
LDsB_D = 'h42,// LD B,D ; 42 |
LDsB_E = 'h43,// LD B,E ; 43 |
LDsB_H = 'h44,// LD B,H ; 44 |
LDsB_L = 'h45,// LD B,L ; 45 |
LDsB_N = 'h06,// LD B,N ; 06 XX |
LDsC_A = 'h4F,// LD C,A ; 4F |
LDsC_B = 'h48,// LD C,B ; 48 |
LDsC_C = 'h49,// LD C,C ; 49 |
LDsC_D = 'h4A,// LD C,D ; 4A |
LDsC_E = 'h4B,// LD C,E ; 4B |
LDsC_H = 'h4C,// LD C,H ; 4C |
LDsC_L = 'h4D,// LD C,L ; 4D |
LDsC_N = 'h0E,// LD C,N ; 0E XX |
LDsDE_NN = 'h11,// LD DE,NN ; 11 XX XX |
LDsD_A = 'h57,// LD D,A ; 57 |
LDsD_B = 'h50,// LD D,B ; 50 |
LDsD_C = 'h51,// LD D,C ; 51 |
LDsD_D = 'h52,// LD D,D ; 52 |
LDsD_E = 'h53,// LD D,E ; 53 |
LDsD_H = 'h54,// LD D,H ; 54 |
LDsD_L = 'h55,// LD D,L ; 55 |
LDsD_N = 'h16,// LD D,N ; 16 XX |
LDsE_A = 'h5F,// LD E,A ; 5F |
LDsE_B = 'h58,// LD E,B ; 58 |
LDsE_C = 'h59,// LD E,C ; 59 |
LDsE_D = 'h5A,// LD E,D ; 5A |
LDsE_E = 'h5B,// LD E,E ; 5B |
LDsE_H = 'h5C,// LD E,H ; 5C |
LDsE_L = 'h5D,// LD E,L ; 5D |
LDsE_N = 'h1E,// LD E,N ; 1E XX |
LDsHL_NN = 'h21,// LD HL,NN ; 21 XX XX |
LDsH_A = 'h67,// LD H,A ; 67 |
LDsH_B = 'h60,// LD H,B ; 60 |
LDsH_C = 'h61,// LD H,C ; 61 |
LDsH_D = 'h62,// LD H,D ; 62 |
LDsH_E = 'h63,// LD H,E ; 63 |
LDsH_H = 'h64,// LD H,H ; 64 |
LDsH_L = 'h65,// LD H,L ; 65 |
LDsH_N = 'h26,// LD H,N ; 26 XX |
LDsL_A = 'h6F,// LD L,A ; 6F |
LDsL_B = 'h68,// LD L,B ; 68 |
LDsL_C = 'h69,// LD L,C ; 69 |
LDsL_D = 'h6A,// LD L,D ; 6A |
LDsL_E = 'h6B,// LD L,E ; 6B |
LDsL_H = 'h6C,// LD L,H ; 6C |
LDsL_L = 'h6D,// LD L,L ; 6D |
LDsL_N = 'h2E,// LD L,N ; 2E XX |
LDsSP_HL = 'hF9,// LD SP,HL ; F9 |
LDsSP_NN = 'h31,// LD SP,NN ; 31 XX XX |
NOP = 'h00,// NOP ; 00 |
ED_IMs0 = 'h46// IM 0 ; ED 46 set IM0 |
ED_LDsI_A = 'h47// LD I,A ; ED 47 move a to I |
ED_IMs1 = 'h56// IM 1 ; ED 56 set IM1 |
ED_IMs2 = 'h5E// IM 2 ; ED 5E set IM2 |
// load 8 types |
LDsA_6BC7 = 'h0A,// LD A,(BC) ; 0A |
LDsA_6DE7 = 'h1A,// LD A,(DE) ; 1A |
LDsB_6HL7 = 'h46,// LD B,(HL) ; 46 |
LDsD_6HL7 = 'h56,// LD D,(HL) ; 56 |
LDsH_6HL7 = 'h66,// LD H,(HL) ; 66 |
ADDsA_6HL7 = 'h86,// ADD A,(HL) ; 86 |
SUBs6HL7 = 'h96,// SUB (HL) ; 96 |
ANDs6HL7 = 'hA6,// AND (HL) ; A6 |
ORs6HL7 = 'hB6,// OR (HL) ; B6 |
LDsC_6HL7 = 'h4E,// LD C,(HL) ; 4E |
LDsE_6HL7 = 'h5E,// LD E,(HL) ; 5E |
LDsL_6HL7 = 'h6E,// LD L,(HL) ; 6E |
LDsA_6HL7 = 'h7E,// LD A,(HL) ; 7E |
ADCsA_6HL7 = 'h8E,// ADC A,(HL) ; 8E |
SBCs6HL7 = 'h9E,// SBC (HL) ; 9E |
XORs6HL7 = 'hAE,// XOR (HL) ; AE |
CPs6HL7 = 'hBE,// CP (HL) ; BE |
LDsA_6NN7 = 'h3A,// LD A,(NN) ; 3A XX XX |
CB_MEM & CB_BIT = 2'b01, // (HL) these must be compaired with ir[7:6] |
// load 16 types |
LDsHL_6NN7 = 'h2A,// LD HL,(NN) ; 2A XX XX |
POPsAF = 'hF1,// POP AF ; F1 AF<- (SP++ ++) |
POPsBC = 'hC1,// POP BC ; C1 BC<- (SP++ ++) |
POPsDE = 'hD1,// POP DE ; D1 DE<- (SP++ ++) |
POPsHL = 'hE1,// POP HL ; E1 HL<- (SP++ ++) |
ED_LDsREG_6NN7 = 6'b01__1011, // compair with {ir[7:6],ir[3:0]} REG = BC,DE,HL,SP |
// store 8 types |
LDs6HL7_N = 'h36,// LD (HL),N ; 36 XX |
LDs6BC7_A = 'h02,// LD (BC),A ; 02 |
LDs6DE7_A = 'h12,// LD (DE),A ; 12 |
LDs6HL7_A = 'h77,// LD (HL),A ; 77 |
LDs6HL7_B = 'h70,// LD (HL),B ; 70 |
LDs6HL7_C = 'h71,// LD (HL),C ; 71 |
LDs6HL7_D = 'h72,// LD (HL),D ; 72 |
LDs6HL7_E = 'h73,// LD (HL),E ; 73 |
LDs6HL7_H = 'h74,// LD (HL),H ; 74 |
LDs6HL7_L = 'h75,// LD (HL),L ; 75 |
LDs6NN7_A = 'h32,// LD (NN),A ; 32 XX XX |
// store 16 types |
PUSHsAF = 'hF5,// PUSH AF ; F5 (-- --SP) <- AF |
PUSHsBC = 'hC5,// PUSH BC ; C5 (-- --SP) <- BC |
PUSHsDE = 'hD5,// PUSH DE ; D5 (-- --SP) <- DE |
PUSHsHL = 'hE5,// PUSH HL ; E5 (-- --SP) <- HL |
LDs6NN7_HL = 'h22,// LD (NN),HL ; 22 XX XX |
ED_LDs6NN7_REG = 6'b01__0011,// XX XX compair with {ir[7:6],ir[3:0]} REG = BC,DE,HL,SP |
|
|
|
|
// rmw 16 types |
EXs6SP7_HL = 'hE3,// EX (SP),HL ; E3 |
|
// Jumps only trick here is that next inst is not valid - ignore it |
JRs$t2 = 'h18,// JR $+2 ; 18 XX |
JRsC_$t2 = 'h38,// JR C,$+2 ; 38 |
JRsNC_$t2 = 'h30,// JR NC,$+2 ; 30 |
JRsNZ_$t2 = 'h20,// JR NZ,$+2 ; 20 |
JRsZ_$t2 = 'h28,// JR Z,$+2 ; 28 |
DJNZs$t2 = 'h10,// DJNZ $+2 ; 10 XX XX |
JPs = 'hC3,// JP $+3 ; C3 XX XX |
JPsC = 'hDA,// JP C,$+3 ; DA XX XX |
JPsHL = 'hE9,// JP HL ; E9 // documented as indirect IS NOT |
JPsM = 'hFA,// JP M,$+3 ; FA XX XX |
JPsNC = 'hD2,// JP NC,$+3 ; D2 XX XX |
JPsNZ = 'hC2,// JP NZ,$+3 ; C2 XX XX |
JPsPE = 'hEA,// JP PE,$+3 ; EA XX XX |
JPsPO = 'hE2,// JP PO,$+3 ; E2 XX XX |
JPsP = 'hF2,// JP P,$+3 ; F2 XX XX |
JPsZ = 'hCA,// JP Z,$+3 ; CA XX XX |
RSTs0 = 'hC7,// RST 0 ; C7 |
RSTs8H = 'hCF,// RST 8H ; CF |
RSTs10H = 'hD7,// RST 10H ; D7 |
RSTs18H = 'hDF,// RST 18H ; DF |
RSTs20H = 'hE7,// RST 20H ; E7 |
RSTs28H = 'hEF,// RST 28H ; EF |
RSTs30H = 'hF7,// RST 30H ; F7 |
RSTs38H = 'hFF,// RST 38H ; FF |
|
|
// calls |
CALLsC_NN = 'hDC,// CALL C,NN ; DC XX XX (-- --SP) <- PC, PC<-NN |
CALLsM_NN = 'hFC,// CALL M,NN ; FC XX XX (-- --SP) <- PC, PC<-NN |
CALLsNC_NN = 'hD4,// CALL NC,NN ; D4 XX XX (-- --SP) <- PC, PC<-NN |
CALLsNN = 'hCD,// CALL NN ; CD XX XX (-- --SP) <- PC, PC<-NN |
CALLsNZ_NN = 'hC4,// CALL NZ,NN ; C4 XX XX (-- --SP) <- PC, PC<-NN |
CALLsPE_NN = 'hEC,// CALL PE,NN ; EC XX XX (-- --SP) <- PC, PC<-NN |
CALLsPO_NN = 'hE4,// CALL PO,NN ; E4 XX XX (-- --SP) <- PC, PC<-NN |
CALLsP_NN = 'hF4,// CALL P,NN ; F4 XX XX (-- --SP) <- PC, PC<-NN |
CALLsZ_NN = 'hCC,// CALL Z,NN ; CC XX XX (-- --SP) <- PC, PC<-NN |
|
//returns |
RET = 'hC9,// RET ; C9 PC <- (SP++ ++) |
RETsC = 'hD8,// RET C ; D8 PC <- (SP++ ++) |
RETsM = 'hF8,// RET M ; F8 PC <- (SP++ ++) |
RETsNC = 'hD0,// RET NC ; D0 PC <- (SP++ ++) |
RETsNZ = 'hC0,// RET NZ ; C0 PC <- (SP++ ++) |
RETsP = 'hF0,// RET P ; F0 PC <- (SP++ ++) |
RETsPE = 'hE8,// RET PE ; E8 PC <- (SP++ ++) |
RETsPO = 'hE0,// RET PO ; E0 PC <- (SP++ ++) |
RETsZ = 'hC8,// RET Z ; C8 PC <- (SP++ ++) |
ED_RETN = 5'b01___101; // compair with {ir[7:6],ir[2:0]} and !reti |
|
|
//io input no flag chnges for this one |
INsA_6N7 = 'hDB,// IN A,(N) ; DB XX A<-(Nio)//silly |
|
//io output |
OUTs6N7_A = 'hD3,// OUT (N),A ; D3 XX A-> (Nio) |
|
|
|
|
|
|
CBgrp = 'hCB,// CBgrp is rotates and bit munging below |
EDgrp = 'hED,// EDgrp ED |
FDgrp = 'hFD,// FDgrp FD |
DDgrp = 'hDD,// DDgrp |
/tags/arelease/doc/opcodes.txt
0,0 → 1,696
NN EQU 1234H ; a sixteen bit number |
N EQU 56H ; an eight bit number |
|
NOP ; 00 |
LD BC,NN ; 01 XX XX |
LD (BC),A ; 02 |
INC BC ; 03 |
INC B ; 04 |
DEC B ; 05 |
LD B,N ; 06 XX |
RLCA ; 07 |
EX AF,AF' ; 08 |
ADD HL,BC ; 09 |
LD A,(BC) ; 0A |
DEC BC ; 0B |
INC C ; 0C |
DEC C ; 0D |
LD C,N ; 0E XX |
RRCA ; 0F |
DJNZ $+2 ; 10 |
LD DE,NN ; 11 XX XX |
LD (DE),A ; 12 |
INC DE ; 13 |
INC D ; 14 |
DEC D ; 15 |
LD D,N ; 16 XX |
RLA ; 17 |
JR $+2 ; 18 |
ADD HL,DE ; 19 |
LD A,(DE) ; 1A |
DEC DE ; 1B |
INC E ; 1C |
DEC E ; 1D |
LD E,N ; 1E XX |
RRA ; 1F |
JR NZ,$+2 ; 20 |
LD HL,NN ; 21 XX XX |
LD (NN),HL ; 22 XX XX |
INC HL ; 23 |
INC H ; 24 |
DEC H ; 25 |
LD H,N ; 26 XX |
DAA ; 27 |
JR Z,$+2 ; 28 |
ADD HL,HL ; 29 |
LD HL,(NN) ; 2A XX XX |
DEC HL ; 2B |
INC L ; 2C |
DEC L ; 2D |
LD L,N ; 2E XX |
CPL ; 2F |
JR NC,$+2 ; 30 |
LD SP,NN ; 31 XX XX |
LD (NN),A ; 32 XX XX |
INC SP ; 33 |
INC (HL) ; 34 |
DEC (HL) ; 35 |
LD (HL),N ; 36 XX |
SCF ; 37 |
JR C,$+2 ; 38 |
ADD HL,SP ; 39 |
LD A,(NN) ; 3A XX XX |
DEC SP ; 3B |
INC A ; 3C |
DEC A ; 3D |
LD A,N ; 3E XX |
CCF ; 3F |
LD B,B ; 40 |
LD B,C ; 41 |
LD B,D ; 42 |
LD B,E ; 43 |
LD B,H ; 44 |
LD B,L ; 45 |
LD B,(HL) ; 46 |
LD B,A ; 47 |
LD C,B ; 48 |
LD C,C ; 49 |
LD C,D ; 4A |
LD C,E ; 4B |
LD C,H ; 4C |
LD C,L ; 4D |
LD C,(HL) ; 4E |
LD C,A ; 4F |
LD D,B ; 50 |
LD D,C ; 51 |
LD D,D ; 52 |
LD D,E ; 53 |
LD D,H ; 54 |
LD D,L ; 55 |
LD D,(HL) ; 56 |
LD D,A ; 57 |
LD E,B ; 58 |
LD E,C ; 59 |
LD E,D ; 5A |
LD E,E ; 5B |
LD E,H ; 5C |
LD E,L ; 5D |
LD E,(HL) ; 5E |
LD E,A ; 5F |
LD H,B ; 60 |
LD H,C ; 61 |
LD H,D ; 62 |
LD H,E ; 63 |
LD H,H ; 64 |
LD H,L ; 65 |
LD H,(HL) ; 66 |
LD H,A ; 67 |
LD L,B ; 68 |
LD L,C ; 69 |
LD L,D ; 6A |
LD L,E ; 6B |
LD L,H ; 6C |
LD L,L ; 6D |
LD L,(HL) ; 6E |
LD L,A ; 6F |
LD (HL),B ; 70 |
LD (HL),C ; 71 |
LD (HL),D ; 72 |
LD (HL),E ; 73 |
LD (HL),H ; 74 |
LD (HL),L ; 75 |
HALT ; 76 |
LD (HL),A ; 77 |
LD A,B ; 78 |
LD A,C ; 79 |
LD A,D ; 7A |
LD A,E ; 7B |
LD A,H ; 7C |
LD A,L ; 7D |
LD A,(HL) ; 7E |
LD A,A ; 7F |
ADD A,B ; 80 |
ADD A,C ; 81 |
ADD A,D ; 82 |
ADD A,E ; 83 |
ADD A,H ; 84 |
ADD A,L ; 85 |
ADD A,(HL) ; 86 |
ADD A,A ; 87 |
ADC A,B ; 88 |
ADC A,C ; 89 |
ADC A,D ; 8A |
ADC A,E ; 8B |
ADC A,H ; 8C |
ADC A,L ; 8D |
ADC A,(HL) ; 8E |
ADC A,A ; 8F |
SUB B ; 90 |
SUB C ; 91 |
SUB D ; 92 |
SUB E ; 93 |
SUB H ; 94 |
SUB L ; 95 |
SUB (HL) ; 96 |
SUB A ; 97 |
SBC B ; 98 |
SBC C ; 99 |
SBC D ; 9A |
SBC E ; 9B |
SBC H ; 9C |
SBC L ; 9D |
SBC (HL) ; 9E |
SBC A ; 9F |
AND B ; A0 |
AND C ; A1 |
AND D ; A2 |
AND E ; A3 |
AND H ; A4 |
AND L ; A5 |
AND (HL) ; A6 |
AND A ; A7 |
XOR B ; A8 |
XOR C ; A9 |
XOR D ; AA |
XOR E ; AB |
XOR H ; AC |
XOR L ; AD |
XOR (HL) ; AE |
XOR A ; AF |
OR B ; B0 |
OR C ; B1 |
OR D ; B2 |
OR E ; B3 |
OR H ; B4 |
OR L ; B5 |
OR (HL) ; B6 |
OR A ; B7 |
CP B ; B8 |
CP C ; B9 |
CP D ; BA |
CP E ; BB |
CP H ; BC |
CP L ; BD |
CP (HL) ; BE |
CP A ; BF |
RET NZ ; C0 |
POP BC ; C1 |
JP NZ,$+3 ; C2 |
JP $+3 ; C3 |
CALL NZ,NN ; C4 XX XX |
PUSH BC ; C5 |
ADD A,N ; C6 XX |
RST 0 ; C7 |
RET Z ; C8 |
RET ; C9 |
JP Z,$+3 ; CA |
RLC B ; CB 00 |
RLC C ; CB 01 |
RLC D ; CB 02 |
RLC E ; CB 03 |
RLC H ; CB 04 |
RLC L ; CB 05 |
RLC (HL) ; CB 06 |
RLC A ; CB 07 |
RRC B ; CB 08 |
RRC C ; CB 09 |
RRC D ; CB 0A |
RRC E ; CB 0B |
RRC H ; CB 0C |
RRC L ; CB 0D |
RRC (HL) ; CB 0E |
RRC A ; CB 0F |
RL B ; CB 10 |
RL C ; CB 11 |
RL D ; CB 12 |
RL E ; CB 13 |
RL H ; CB 14 |
RL L ; CB 15 |
RL (HL) ; CB 16 |
RL A ; CB 17 |
RR B ; CB 18 |
RR C ; CB 19 |
RR D ; CB 1A |
RR E ; CB 1B |
RR H ; CB 1C |
RR L ; CB 1D |
RR (HL) ; CB 1E |
RR A ; CB 1F |
SLA B ; CB 20 |
SLA C ; CB 21 |
SLA D ; CB 22 |
SLA E ; CB 23 |
SLA H ; CB 24 |
SLA L ; CB 25 |
SLA (HL) ; CB 26 |
SLA A ; CB 27 |
SRA B ; CB 28 |
SRA C ; CB 29 |
SRA D ; CB 2A |
SRA E ; CB 2B |
SRA H ; CB 2C |
SRA L ; CB 2D |
SRA (HL) ; CB 2E |
SRA A ; CB 2F |
SRL B ; CB 38 |
SRL C ; CB 39 |
SRL D ; CB 3A |
SRL E ; CB 3B |
SRL H ; CB 3C |
SRL L ; CB 3D |
SRL (HL) ; CB 3E |
SRL A ; CB 3F |
BIT 0,B ; CB 40 |
BIT 0,C ; CB 41 |
BIT 0,D ; CB 42 |
BIT 0,E ; CB 43 |
BIT 0,H ; CB 44 |
BIT 0,L ; CB 45 |
BIT 0,(HL) ; CB 46 |
BIT 0,A ; CB 47 |
BIT 1,B ; CB 48 |
BIT 1,C ; CB 49 |
BIT 1,D ; CB 4A |
BIT 1,E ; CB 4B |
BIT 1,H ; CB 4C |
BIT 1,L ; CB 4D |
BIT 1,(HL) ; CB 4E |
BIT 1,A ; CB 4F |
BIT 2,B ; CB 50 |
BIT 2,C ; CB 51 |
BIT 2,D ; CB 52 |
BIT 2,E ; CB 53 |
BIT 2,H ; CB 54 |
BIT 2,L ; CB 55 |
BIT 2,(HL) ; CB 56 |
BIT 2,A ; CB 57 |
BIT 3,B ; CB 58 |
BIT 3,C ; CB 59 |
BIT 3,D ; CB 5A |
BIT 3,E ; CB 5B |
BIT 3,H ; CB 5C |
BIT 3,L ; CB 5D |
BIT 3,(HL) ; CB 5E |
BIT 3,A ; CB 5F |
BIT 4,B ; CB 60 |
BIT 4,C ; CB 61 |
BIT 4,D ; CB 62 |
BIT 4,E ; CB 63 |
BIT 4,H ; CB 64 |
BIT 4,L ; CB 65 |
BIT 4,(HL) ; CB 66 |
BIT 4,A ; CB 67 |
BIT 5,B ; CB 68 |
BIT 5,C ; CB 69 |
BIT 5,D ; CB 6A |
BIT 5,E ; CB 6B |
BIT 5,H ; CB 6C |
BIT 5,L ; CB 6D |
BIT 5,(HL) ; CB 6E |
BIT 5,A ; CB 6F |
BIT 6,B ; CB 70 |
BIT 6,C ; CB 71 |
BIT 6,D ; CB 72 |
BIT 6,E ; CB 73 |
BIT 6,H ; CB 74 |
BIT 6,L ; CB 75 |
BIT 6,(HL) ; CB 76 |
BIT 6,A ; CB 77 |
BIT 7,B ; CB 78 |
BIT 7,C ; CB 79 |
BIT 7,D ; CB 7A |
BIT 7,E ; CB 7B |
BIT 7,H ; CB 7C |
BIT 7,L ; CB 7D |
BIT 7,(HL) ; CB 7E |
BIT 7,A ; CB 7F |
RES 0,B ; CB 80 |
RES 0,C ; CB 81 |
RES 0,D ; CB 82 |
RES 0,E ; CB 83 |
RES 0,H ; CB 84 |
RES 0,L ; CB 85 |
RES 0,(HL) ; CB 86 |
RES 0,A ; CB 87 |
RES 1,B ; CB 88 |
RES 1,C ; CB 89 |
RES 1,D ; CB 8A |
RES 1,E ; CB 8B |
RES 1,H ; CB 8C |
RES 1,L ; CB 8D |
RES 1,(HL) ; CB 8E |
RES 1,A ; CB 8F |
RES 2,B ; CB 90 |
RES 2,C ; CB 91 |
RES 2,D ; CB 92 |
RES 2,E ; CB 93 |
RES 2,H ; CB 94 |
RES 2,L ; CB 95 |
RES 2,(HL) ; CB 96 |
RES 2,A ; CB 97 |
RES 3,B ; CB 98 |
RES 3,C ; CB 99 |
RES 3,D ; CB 9A |
RES 3,E ; CB 9B |
RES 3,H ; CB 9C |
RES 3,L ; CB 9D |
RES 3,(HL) ; CB 9E |
RES 3,A ; CB 9F |
RES 4,B ; CB A0 |
RES 4,C ; CB A1 |
RES 4,D ; CB A2 |
RES 4,E ; CB A3 |
RES 4,H ; CB A4 |
RES 4,L ; CB A5 |
RES 4,(HL) ; CB A6 |
RES 4,A ; CB A7 |
RES 5,B ; CB A8 |
RES 5,C ; CB A9 |
RES 5,D ; CB AA |
RES 5,E ; CB AB |
RES 5,H ; CB AC |
RES 5,L ; CB AD |
RES 5,(HL) ; CB AE |
RES 5,A ; CB AF |
RES 6,B ; CB B0 |
RES 6,C ; CB B1 |
RES 6,D ; CB B2 |
RES 6,E ; CB B3 |
RES 6,H ; CB B4 |
RES 6,L ; CB B5 |
RES 6,(HL) ; CB B6 |
RES 6,A ; CB B7 |
RES 7,B ; CB B8 |
RES 7,C ; CB B9 |
RES 7,D ; CB BA |
RES 7,E ; CB BB |
RES 7,H ; CB BC |
RES 7,L ; CB BD |
RES 7,(HL) ; CB BE |
RES 7,A ; CB BF |
SET 0,B ; CB C0 |
SET 0,C ; CB C1 |
SET 0,D ; CB C2 |
SET 0,E ; CB C3 |
SET 0,H ; CB C4 |
SET 0,L ; CB C5 |
SET 0,(HL) ; CB C6 |
SET 0,A ; CB C7 |
SET 1,B ; CB C8 |
SET 1,C ; CB C9 |
SET 1,D ; CB CA |
SET 1,E ; CB CB |
SET 1,H ; CB CC |
SET 1,L ; CB CD |
SET 1,(HL) ; CB CE |
SET 1,A ; CB CF |
SET 2,B ; CB D0 |
SET 2,C ; CB D1 |
SET 2,D ; CB D2 |
SET 2,E ; CB D3 |
SET 2,H ; CB D4 |
SET 2,L ; CB D5 |
SET 2,(HL) ; CB D6 |
SET 2,A ; CB D7 |
SET 3,B ; CB D8 |
SET 3,C ; CB D9 |
SET 3,D ; CB DA |
SET 3,E ; CB DB |
SET 3,H ; CB DC |
SET 3,L ; CB DD |
SET 3,(HL) ; CB DE |
SET 3,A ; CB DF |
SET 4,B ; CB E0 |
SET 4,C ; CB E1 |
SET 4,D ; CB E2 |
SET 4,E ; CB E3 |
SET 4,H ; CB E4 |
SET 4,L ; CB E5 |
SET 4,(HL) ; CB E6 |
SET 4,A ; CB E7 |
SET 5,B ; CB E8 |
SET 5,C ; CB E9 |
SET 5,D ; CB EA |
SET 5,E ; CB EB |
SET 5,H ; CB EC |
SET 5,L ; CB ED |
SET 5,(HL) ; CB EE |
SET 5,A ; CB EF |
SET 6,B ; CB F0 |
SET 6,C ; CB F1 |
SET 6,D ; CB F2 |
SET 6,E ; CB F3 |
SET 6,H ; CB F4 |
SET 6,L ; CB F5 |
SET 6,(HL) ; CB F6 |
SET 6,A ; CB F7 |
SET 7,B ; CB F8 |
SET 7,C ; CB F9 |
SET 7,D ; CB FA |
SET 7,E ; CB FB |
SET 7,H ; CB FC |
SET 7,L ; CB FD |
SET 7,(HL) ; CB FE |
SET 7,A ; CB FF |
CALL Z,NN ; CC XX XX |
CALL NN ; CD XX XX |
ADC A,N ; CE XX |
RST 8H ; CF |
RET NC ; D0 |
POP DE ; D1 |
JP NC,$+3 ; D2 |
OUT (N),A ; D3 XX |
CALL NC,NN ; D4 XX XX |
PUSH DE ; D5 |
SUB N ; D6 XX |
RST 10H ; D7 |
RET C ; D8 |
EXX ; D9 |
JP C,$+3 ; DA |
IN A,(N) ; DB XX |
CALL C,NN ; DC XX XX |
ADD IX,BC ; DD 09 |
ADD IX,DE ; DD 19 |
LD IX,NN ; DD 21 XX XX |
LD (NN),IX ; DD 22 XX XX |
INC IX ; DD 23 |
ADD IX,IX ; DD 29 |
LD IX,(NN) ; DD 2A XX XX |
DEC IX ; DD 2B |
INC (IX+N) ; DD 34 XX |
DEC (IX+N) ; DD 35 XX |
LD (IX+N),N ; DD 36 XX XX |
ADD IX,SP ; DD 39 |
LD B,(IX+N) ; DD 46 XX |
LD C,(IX+N) ; DD 4E XX |
LD D,(IX+N) ; DD 56 XX |
LD E,(IX+N) ; DD 5E XX |
LD H,(IX+N) ; DD 66 XX |
LD L,(IX+N) ; DD 6E XX |
LD (IX+N),B ; DD 70 XX |
LD (IX+N),C ; DD 71 XX |
LD (IX+N),D ; DD 72 XX |
LD (IX+N),E ; DD 73 XX |
LD (IX+N),H ; DD 74 XX |
LD (IX+N),L ; DD 75 XX |
LD (IX+N),A ; DD 77 XX |
LD A,(IX+N) ; DD 7E XX |
ADD A,(IX+N) ; DD 86 XX |
ADC A,(IX+N) ; DD 8E XX |
SUB (IX+N) ; DD 96 XX |
SBC A,(IX+N) ; DD 9E XX |
AND (IX+N) ; DD A6 XX |
XOR (IX+N) ; DD AE XX |
OR (IX+N) ; DD B6 XX |
CP (IX+N) ; DD BE XX |
RLC (IX+N) ; DD CB XX 06 |
RRC (IX+N) ; DD CB XX 0E |
RL (IX+N) ; DD CB XX 16 |
RR (IX+N) ; DD CB XX 1E |
SLA (IX+N) ; DD CB XX 26 |
SRA (IX+N) ; DD CB XX 2E |
BIT 0,(IX+N) ; DD CB XX 46 |
BIT 1,(IX+N) ; DD CB XX 4E |
BIT 2,(IX+N) ; DD CB XX 56 |
BIT 3,(IX+N) ; DD CB XX 5E |
BIT 4,(IX+N) ; DD CB XX 66 |
BIT 5,(IX+N) ; DD CB XX 6E |
BIT 6,(IX+N) ; DD CB XX 76 |
BIT 7,(IX+N) ; DD CB XX 7E |
RES 0,(IX+N) ; DD CB XX 86 |
RES 1,(IX+N) ; DD CB XX 8E |
RES 2,(IX+N) ; DD CB XX 96 |
RES 3,(IX+N) ; DD CB XX 9E |
RES 4,(IX+N) ; DD CB XX A6 |
RES 5,(IX+N) ; DD CB XX AE |
RES 6,(IX+N) ; DD CB XX B6 |
RES 7,(IX+N) ; DD CB XX BE |
SET 0,(IX+N) ; DD CB XX C6 |
SET 1,(IX+N) ; DD CB XX CE |
SET 2,(IX+N) ; DD CB XX D6 |
SET 3,(IX+N) ; DD CB XX DE |
SET 4,(IX+N) ; DD CB XX E6 |
SET 5,(IX+N) ; DD CB XX EE |
SET 6,(IX+N) ; DD CB XX F6 |
SET 7,(IX+N) ; DD CB XX FE |
POP IX ; DD E1 |
EX (SP),IX ; DD E3 |
PUSH IX ; DD E5 |
JP (IX) ; DD E9 // horrible syntax PC <- IX |
LD SP,IX ; DD F9 |
SBC A,N ; DE XX |
RST 18H ; DF |
RET PO ; E0 |
POP HL ; E1 |
JP PO,$+3 ; E2 |
EX (SP),HL ; E3 |
CALL PO,NN ; E4 XX XX |
PUSH HL ; E5 |
AND N ; E6 XX |
RST 20H ; E7 |
RET PE ; E8 |
JP (HL) ; E9 // PC <- HL |
JP PE,$+3 ; EA |
EX DE,HL ; EB |
CALL PE,NN ; EC XX XX |
IN B,(C) ; ED 40 |
OUT (C),B ; ED 41 |
SBC HL,BC ; ED 42 |
LD (NN),BC ; ED 43 XX XX |
NEG ; ED 44 |
RETN ; ED 45 |
IM 0 ; ED 46 |
LD I,A ; ED 47 |
IN C,(C) ; ED 48 |
OUT (C),C ; ED 49 |
ADC HL,BC ; ED 4A |
LD BC,(NN) ; ED 4B XX XX |
RETI ; ED 4D |
IN D,(C) ; ED 50 |
OUT (C),D ; ED 51 |
SBC HL,DE ; ED 52 |
LD (NN),DE ; ED 53 XX XX |
IM 1 ; ED 56 |
LD A,I ; ED 57 |
IN E,(C) ; ED 58 |
OUT (C),E ; ED 59 |
ADC HL,DE ; ED 5A |
LD DE,(NN) ; ED 5B XX XX |
IM 2 ; ED 5E |
IN H,(C) ; ED 60 |
OUT (C),H ; ED 61 |
SBC HL,HL ; ED 62 |
RRD ; ED 67 |
IN L,(C) ; ED 68 |
OUT (C),L ; ED 69 |
ADC HL,HL ; ED 6A |
RLD ; ED 6F |
SBC HL,SP ; ED 72 |
LD (NN),SP ; ED 73 XX XX |
IN A,(C) ; ED 78 |
OUT (C),A ; ED 79 |
ADC HL,SP ; ED 7A |
LD SP,(NN) ; ED 7B XX XX |
LDI ; ED A0 |
CPI ; ED A1 |
INI ; ED A2 |
OUTI ; ED A3 |
LDD ; ED A8 |
CPD ; ED A9 |
IND ; ED AA |
OUTD ; ED AB |
LDIR ; ED B0 |
CPIR ; ED B1 |
INIR ; ED B2 |
OTIR ; ED B3 |
LDDR ; ED B8 |
CPDR ; ED B9 |
INDR ; ED BA |
OTDR ; ED BB |
XOR N ; EE XX |
RST 28H ; EF |
RET P ; F0 |
POP AF ; F1 |
JP P,$+3 ; F2 |
DI ; F3 |
CALL P,NN ; F4 XX XX |
PUSH AF ; F5 |
OR N ; F6 XX |
RST 30H ; F7 |
RET M ; F8 |
LD SP,HL ; F9 |
JP M,$+3 ; FA |
EI ; FB |
CALL M,NN ; FC XX XX |
ADD IY,BC ; FD 09 |
ADD IY,DE ; FD 19 |
LD IY,NN ; FD 21 XX XX |
LD (NN),IY ; FD 22 XX XX |
INC IY ; FD 23 |
ADD IY,IY ; FD 29 |
LD IY,(NN) ; FD 2A XX XX |
DEC IY ; FD 2B |
INC (IY+N) ; FD 34 XX |
DEC (IY+N) ; FD 35 XX |
LD (IY+N),N ; FD 36 XX XX |
ADD IY,SP ; FD 39 |
LD B,(IY+N) ; FD 46 XX |
LD C,(IY+N) ; FD 4E XX |
LD D,(IY+N) ; FD 56 XX |
LD E,(IY+N) ; FD 5E XX |
LD H,(IY+N) ; FD 66 XX |
LD L,(IY+N) ; FD 6E XX |
LD (IY+N),B ; FD 70 XX |
LD (IY+N),C ; FD 71 XX |
LD (IY+N),D ; FD 72 XX |
LD (IY+N),E ; FD 73 XX |
LD (IY+N),H ; FD 74 XX |
LD (IY+N),L ; FD 75 XX |
LD (IY+N),A ; FD 77 XX |
LD A,(IY+N) ; FD 7E XX |
ADD A,(IY+N) ; FD 86 XX |
ADC A,(IY+N) ; FD 8E XX |
SUB (IY+N) ; FD 96 XX |
SBC A,(IY+N) ; FD 9E XX |
AND (IY+N) ; FD A6 XX |
XOR (IY+N) ; FD AE XX |
OR (IY+N) ; FD B6 XX |
CP (IY+N) ; FD BE XX |
RLC (IY+N) ; FD CB XX 06 |
RRC (IY+N) ; FD CB XX 0E |
RL (IY+N) ; FD CB XX 16 |
RR (IY+N) ; FD CB XX 1E |
SLA (IY+N) ; FD CB XX 26 |
SRA (IY+N) ; FD CB XX 2E |
BIT 0,(IY+N) ; FD CB XX 46 |
BIT 1,(IY+N) ; FD CB XX 4E |
BIT 2,(IY+N) ; FD CB XX 56 |
BIT 3,(IY+N) ; FD CB XX 5E |
BIT 4,(IY+N) ; FD CB XX 66 |
BIT 5,(IY+N) ; FD CB XX 6E |
BIT 6,(IY+N) ; FD CB XX 76 |
BIT 7,(IY+N) ; FD CB XX 7E |
RES 0,(IY+N) ; FD CB XX 86 |
RES 1,(IY+N) ; FD CB XX 8E |
RES 2,(IY+N) ; FD CB XX 96 |
RES 3,(IY+N) ; FD CB XX 9E |
RES 4,(IY+N) ; FD CB XX A6 |
RES 5,(IY+N) ; FD CB XX AE |
RES 6,(IY+N) ; FD CB XX B6 |
RES 7,(IY+N) ; FD CB XX BE |
SET 0,(IY+N) ; FD CB XX C6 |
SET 1,(IY+N) ; FD CB XX CE |
SET 2,(IY+N) ; FD CB XX D6 |
SET 3,(IY+N) ; FD CB XX DE |
SET 4,(IY+N) ; FD CB XX E6 |
SET 5,(IY+N) ; FD CB XX EE |
SET 6,(IY+N) ; FD CB XX F6 |
SET 7,(IY+N) ; FD CB XX FE |
POP IY ; FD E1 |
EX (SP),IY ; FD E3 |
PUSH IY ; FD E5 |
JP (IY) ; FD E9 PC <- IY horrible syntax seems somewhat global |
LD SP,IY ; FD F9 |
CP N ; FE XX |
RST 38H ; FF |
|
/tags/arelease/doc/work_i2.txt
0,0 → 1,198
dec i2n1 |
INCs6IXtN7 ; DD 34 XX |
DECs6IXtN7 ; DD 35 XX |
LDsB_6IXtN7 ; DD 46 XX |
LDsC_6IXtN7 ; DD 4E XX |
LDsD_6IXtN7 ; DD 56 XX |
LDsE_6IXtN7 ; DD 5E XX |
LDsH_6IXtN7 ; DD 66 XX |
LDsL_6IXtN7 ; DD 6E XX |
LDs6IXtN7_B ; DD 70 XX |
LDs6IXtN7_C ; DD 71 XX |
LDs6IXtN7_D ; DD 72 XX |
LDs6IXtN7_E ; DD 73 XX |
LDs6IXtN7_H ; DD 74 XX |
LDs6IXtN7_L ; DD 75 XX |
LDs6IXtN7_A ; DD 77 XX |
LDsA_6IXtN7 ; DD 7E XX |
ADDsA_6IXtN7 ; DD 86 XX |
ADCsA_6IXtN7 ; DD 8E XX |
SUBs6IXtN7 ; DD 96 XX |
SBCsA_6IXtN7 ; DD 9E XX |
ANDs6IXtN7 ; DD A6 XX |
XORs6IXtN7 ; DD AE XX |
ORs6IXtN7 ; DD B6 XX |
CPs6IXtN7 ; DD BE XX |
INCs6IYtN7 ; FD 34 XX |
DECs6IYtN7 ; FD 35 XX |
LDsB_6IYtN7 ; FD 46 XX |
LDsC_6IYtN7 ; FD 4E XX |
LDsD_6IYtN7 ; FD 56 XX |
LDsE_6IYtN7 ; FD 5E XX |
LDsH_6IYtN7 ; FD 66 XX |
LDsL_6IYtN7 ; FD 6E XX |
LDs6IYtN7_B ; FD 70 XX |
LDs6IYtN7_C ; FD 71 XX |
LDs6IYtN7_D ; FD 72 XX |
LDs6IYtN7_E ; FD 73 XX |
LDs6IYtN7_H ; FD 74 XX |
LDs6IYtN7_L ; FD 75 XX |
LDs6IYtN7_A ; FD 77 XX |
LDsA_6IYtN7 ; FD 7E XX |
ADDsA_6IYtN7 ; FD 86 XX |
ADCsA_6IYtN7 ; FD 8E XX |
SUBs6IYtN7 ; FD 96 XX |
SBCsA_6IYtN7 ; FD 9E XX |
ANDs6IYtN7 ; FD A6 XX |
XORs6IYtN7 ; FD AE XX |
ORs6IYtN7 ; FD B6 XX |
CPs6IYtN7 ; FD BE XX |
|
dec_i2n2 |
LDsIX_NN ; DD 21 XX XX |
LDs6NN7_IX ; DD 22 XX XX |
LDsIX_6NN7 ; DD 2A XX XX |
LDs6IXtN7_N ; DD 36 XX XX |
LDs6NN7_BC ; ED 43 XX XX |
LDsBC_6NN7 ; ED 4B XX XX |
LDs6NN7_DE ; ED 53 XX XX |
LDsDE_6NN7 ; ED 5B XX XX |
LDs6NN7_SP ; ED 73 XX XX |
LDsSP_6NN7 ; ED 7B XX XX |
LDsIY_NN ; FD 21 XX XX |
LDs6NN7_IY ; FD 22 XX XX |
LDsIY_6NN7 ; FD 2A XX XX |
LDs6IYtN7_N ; FD 36 XX XX |
|
dec_ni3 = fdcb | ddcb |
RLC (IX+N) ; DD CB XX 06 |
RRC (IX+N) ; DD CB XX 0E |
RL (IX+N) ; DD CB XX 16 |
RR (IX+N) ; DD CB XX 1E |
SLA (IX+N) ; DD CB XX 26 |
SRA (IX+N) ; DD CB XX 2E |
BIT 0,(IX+N) ; DD CB XX 46 |
BIT 1,(IX+N) ; DD CB XX 4E |
BIT 2,(IX+N) ; DD CB XX 56 |
BIT 3,(IX+N) ; DD CB XX 5E |
BIT 4,(IX+N) ; DD CB XX 66 |
BIT 5,(IX+N) ; DD CB XX 6E |
BIT 6,(IX+N) ; DD CB XX 76 |
BIT 7,(IX+N) ; DD CB XX 7E |
RES 0,(IX+N) ; DD CB XX 86 |
RES 1,(IX+N) ; DD CB XX 8E |
RES 2,(IX+N) ; DD CB XX 96 |
RES 3,(IX+N) ; DD CB XX 9E |
RES 4,(IX+N) ; DD CB XX A6 |
RES 5,(IX+N) ; DD CB XX AE |
RES 6,(IX+N) ; DD CB XX B6 |
RES 7,(IX+N) ; DD CB XX BE |
SET 0,(IX+N) ; DD CB XX C6 |
SET 1,(IX+N) ; DD CB XX CE |
SET 2,(IX+N) ; DD CB XX D6 |
SET 3,(IX+N) ; DD CB XX DE |
SET 4,(IX+N) ; DD CB XX E6 |
SET 5,(IX+N) ; DD CB XX EE |
SET 6,(IX+N) ; DD CB XX F6 |
SET 7,(IX+N) ; DD CB XX FE |
RLC (IY+N) ; FD CB XX 06 |
RRC (IY+N) ; FD CB XX 0E |
RL (IY+N) ; FD CB XX 16 |
RR (IY+N) ; FD CB XX 1E |
SLA (IY+N) ; FD CB XX 26 |
SRA (IY+N) ; FD CB XX 2E |
BIT 0,(IY+N) ; FD CB XX 46 |
BIT 1,(IY+N) ; FD CB XX 4E |
BIT 2,(IY+N) ; FD CB XX 56 |
BIT 3,(IY+N) ; FD CB XX 5E |
BIT 4,(IY+N) ; FD CB XX 66 |
BIT 5,(IY+N) ; FD CB XX 6E |
BIT 6,(IY+N) ; FD CB XX 76 |
BIT 7,(IY+N) ; FD CB XX 7E |
RES 0,(IY+N) ; FD CB XX 86 |
RES 1,(IY+N) ; FD CB XX 8E |
RES 2,(IY+N) ; FD CB XX 96 |
RES 3,(IY+N) ; FD CB XX 9E |
RES 4,(IY+N) ; FD CB XX A6 |
RES 5,(IY+N) ; FD CB XX AE |
RES 6,(IY+N) ; FD CB XX B6 |
RES 7,(IY+N) ; FD CB XX BE |
SET 0,(IY+N) ; FD CB XX C6 |
SET 1,(IY+N) ; FD CB XX CE |
SET 2,(IY+N) ; FD CB XX D6 |
SET 3,(IY+N) ; FD CB XX DE |
SET 4,(IY+N) ; FD CB XX E6 |
SET 5,(IY+N) ; FD CB XX EE |
SET 6,(IY+N) ; FD CB XX F6 |
SET 7,(IY+N) ; FD CB XX FE |
|
|
default |
ADD IX,BC ; DD 09 |
ADD IX,DE ; DD 19 |
INC IX ; DD 23 |
ADD IX,IX ; DD 29 |
DEC IX ; DD 2B |
ADD IX,SP ; DD 39 |
POP IX ; DD E1 |
EX (SP),IX ; DD E3 |
PUSH IX ; DD E5 |
JP (IX) ; DD E9 |
LD SP,IX ; DD F9 |
IN B,(C) ; ED 40 |
OUT (C),B ; ED 41 |
SBC HL,BC ; ED 42 |
NEG ; ED 44 |
RETN ; ED 45 |
IM 0 ; ED 46 |
LD I,A ; ED 47 |
IN C,(C) ; ED 48 |
OUT (C),C ; ED 49 |
ADC HL,BC ; ED 4A |
RETI ; ED 4D |
IN D,(C) ; ED 50 |
OUT (C),D ; ED 51 |
SBC HL,DE ; ED 52 |
IM 1 ; ED 56 |
LD A,I ; ED 57 |
IN E,(C) ; ED 58 |
OUT (C),E ; ED 59 |
ADC HL,DE ; ED 5A |
IM 2 ; ED 5E |
IN H,(C) ; ED 60 |
OUT (C),H ; ED 61 |
SBC HL,HL ; ED 62 |
RRD ; ED 67 |
IN L,(C) ; ED 68 |
OUT (C),L ; ED 69 |
ADC HL,HL ; ED 6A |
RLD ; ED 6F |
SBC HL,SP ; ED 72 |
LDI ; ED A0 |
CPI ; ED A1 |
INI ; ED A2 |
OUTI ; ED A3 |
LDD ; ED A8 |
CPD ; ED A9 |
IND ; ED AA |
OUTD ; ED AB |
LDIR ; ED B0 |
CPIR ; ED B1 |
INIR ; ED B2 |
OTIR ; ED B3 |
LDDR ; ED B8 |
CPDR ; ED B9 |
INDR ; ED BA |
OTDR ; ED BB |
ADD IY,BC ; FD 09 |
ADD IY,DE ; FD 19 |
INC IY ; FD 23 |
ADD IY,IY ; FD 29 |
DEC IY ; FD 2B |
ADD IY,SP ; FD 39 |
POP IY ; FD E1 |
EX (SP),IY ; FD E3 |
PUSH IY ; FD E5 |
JP (IY) ; FD E9 |
LD SP,IY ; FD F9 |
|
/tags/arelease/wb_z80.tws
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
tags/arelease/wb_z80.tws
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/arelease/inc/opcodes.v
===================================================================
--- tags/arelease/inc/opcodes.v (nonexistent)
+++ tags/arelease/inc/opcodes.v (revision 3)
@@ -0,0 +1,491 @@
+///////////////////////////////////////////////////////////////////////////////////////////////////
+// //
+// file name: opcodes.v //
+// description: opcode parameters for z80 //
+// project: wb_z80 //
+// //
+// Author: B.J. Porcella //
+// e-mail: bporcella@sbcglobal.net //
+// //
+// //
+// //
+///////////////////////////////////////////////////////////////////////////////////////////////////
+// //
+// Copyright (C) 2000-2002 B.J. Porcella //
+// Real Time Solutions //
+// //
+// //
+// This source file may be used and distributed without //
+// restriction provided that this copyright statement is not //
+// removed from the file and that any derivative work contains //
+// the original copyright notice and the associated disclaimer. //
+// //
+// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //
+// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //
+// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //
+// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //
+// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //
+// POSSIBILITY OF SUCH DAMAGE. //
+// //
+//-------1---------2---------3--------Comments on file -------------7---------8---------9--------0
+// This file is fundamentally a hack of an opcode file found on:
+// http://www.z80.info/ (perhaps written by Thomas Scherrer)
+//
+// The purpose of the origiional file was to aid in low level z80 software debug.
+// Here, we are trying to make the parameters we use for instruction decoding
+// as easy to understand as possible.
+//
+// The origional file is included as a comment below. (this is a very long file)
+// It is then re-produced with transformations -- so the significance of the parameters should
+// be very clear.
+//
+// Note how assembler syntax is transformed
+// into verilog symbols.
+//
+//
+// I'm going to define all parameters as standard integer length as they will be used
+// in comparisons of various lengths..............
+// generally 8 bits, but there is 3 bit extension that may apply to any parameter...
+// 0
+// 1 CBgrp (shifts and Bit banging)
+// 2 DDgrp (mostly indexed addressing)
+// 3 DDCBgrp (indexed bit banging)
+// 3 EDgrp (a wild mix of stuff )
+// 4 FDgrp (more indexed stuff )
+// 5 FDCBgrp (indexed bit banging)
+//
+//
+//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
+//
+// $Id: opcodes.v,v 1.1.1.1 2004-06-18 08:38:40 mihal Exp $
+//
+// $Date: 2004-06-18 08:38:40 $
+// $Revision: 1.1.1.1 $
+// $Author: mihal $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/04/13 23:47:56 bporcella
+// import first files
+//
+//
+//
+//-------1---------2---------3--------Comments on file -------------7---------8---------9--------0
+//
+parameter NOP = 10'h00,// NOP ; 00
+ LDsBC_NN = 10'h01,// LD BC,NN ; 01 XX XX
+ LDs6BC7_A = 10'h02,// LD (BC),A ; 02
+ INCsBC = 10'h03,// INC BC ; 03
+ INCsB = 10'h04,// INC B ; 04
+ DECsB = 10'h05,// DEC B ; 05
+ LDsB_N = 10'h06,// LD B,N ; 06 XX
+ RLCA = 10'h07,// RLCA ; 07
+ EXsAF_AFp = 10'h08,// EX AF,AF' ; 08
+ ADDsHL_BC = 10'h09,// ADD HL,BC ; 09
+ LDsA_6BC7 = 10'h0A,// LD A,(BC) ; 0A
+ DECsBC = 10'h0B,// DEC BC ; 0B
+ INCsC = 10'h0C,// INC C ; 0C
+ DECsC = 10'h0D,// DEC C ; 0D
+ LDsC_N = 10'h0E,// LD C,N ; 0E XX
+ RRCA = 10'h0F,// RRCA ; 0F
+ DJNZs$t2 = 10'h10,// DJNZ $+2 ; 10 XX
+ LDsDE_NN = 10'h11,// LD DE,NN ; 11 XX XX
+ LDs6DE7_A = 10'h12,// LD (DE),A ; 12
+ INCsDE = 10'h13,// INC DE ; 13
+ INCsD = 10'h14,// INC D ; 14
+ DECsD = 10'h15,// DEC D ; 15
+ LDsD_N = 10'h16,// LD D,N ; 16 XX
+ RLA = 10'h17,// RLA ; 17
+ JRs$t2 = 10'h18,// JR $+2 ; 18 XX
+ ADDsHL_DE = 10'h19,// ADD HL,DE ; 19
+ LDsA_6DE7 = 10'h1A,// LD A,(DE) ; 1A
+ DECsDE = 10'h1B,// DEC DE ; 1B
+ INCsE = 10'h1C,// INC E ; 1C
+ DECsE = 10'h1D,// DEC E ; 1D
+ LDsE_N = 10'h1E,// LD E,N ; 1E XX
+ RRA = 10'h1F,// RRA ; 1F
+ JRsNZ_$t2 = 10'h20,// JR NZ,$+2 ; 20
+ LDsHL_NN = 10'h21,// LD HL,NN ; 21 XX XX
+ LDs6NN7_HL = 10'h22,// LD (NN),HL ; 22 XX XX
+ INCsHL = 10'h23,// INC HL ; 23
+ INCsH = 10'h24,// INC H ; 24
+ DECsH = 10'h25,// DEC H ; 25
+ LDsH_N = 10'h26,// LD H,N ; 26 XX
+ DAA = 10'h27,// DAA ; 27
+ JRsZ_$t2 = 10'h28,// JR Z,$+2 ; 28 XX
+ ADDsHL_HL = 10'h29,// ADD HL,HL ; 29
+ LDsHL_6NN7 = 10'h2A,// LD HL,(NN) ; 2A XX XX
+ DECsHL = 10'h2B,// DEC HL ; 2B
+ INCsL = 10'h2C,// INC L ; 2C
+ DECsL = 10'h2D,// DEC L ; 2D
+ LDsL_N = 10'h2E,// LD L,N ; 2E XX
+ CPL = 10'h2F,// CPL ; 2F
+ JRsNC_$t2 = 10'h30,// JR NC,$+2 ; 30 XX
+ LDsSP_NN = 10'h31,// LD SP,NN ; 31 XX XX
+ LDs6NN7_A = 10'h32,// LD (NN),A ; 32 XX XX
+ INCsSP = 10'h33,// INC SP ; 33
+ INCs6HL7 = 10'h34,// INC (HL) ; 34
+ DECs6HL7 = 10'h35,// DEC (HL) ; 35
+ LDs6HL7_N = 10'h36,// LD (HL),N ; 36 XX
+ SCF = 10'h37,// SCF ; 37
+ JRsC_$t2 = 10'h38,// JR C,$+2 ; 38 XX
+ ADDsHL_SP = 10'h39,// ADD HL,SP ; 39
+ LDsA_6NN7 = 10'h3A,// LD A,(NN) ; 3A XX XX
+ DECsSP = 10'h3B,// DEC SP ; 3B
+ INCsA = 10'h3C,// INC A ; 3C
+ DECsA = 10'h3D,// DEC A ; 3D
+ LDsA_N = 10'h3E,// LD A,N ; 3E XX
+ CCF = 10'h3F,// CCF ; 3F
+ LDsB_B = 10'h40,// LD B,B ; 40
+ LDsB_C = 10'h41,// LD B,C ; 41
+ LDsB_D = 10'h42,// LD B,D ; 42
+ LDsB_E = 10'h43,// LD B,E ; 43
+ LDsB_H = 10'h44,// LD B,H ; 44
+ LDsB_L = 10'h45,// LD B,L ; 45
+ LDsB_6HL7 = 10'h46,// LD B,(HL) ; 46
+ LDsB_A = 10'h47,// LD B,A ; 47
+ LDsC_B = 10'h48,// LD C,B ; 48
+ LDsC_C = 10'h49,// LD C,C ; 49
+ LDsC_D = 10'h4A,// LD C,D ; 4A
+ LDsC_E = 10'h4B,// LD C,E ; 4B
+ LDsC_H = 10'h4C,// LD C,H ; 4C
+ LDsC_L = 10'h4D,// LD C,L ; 4D
+ LDsC_6HL7 = 10'h4E,// LD C,(HL) ; 4E
+ LDsC_A = 10'h4F,// LD C,A ; 4F
+ LDsD_B = 10'h50,// LD D,B ; 50
+ LDsD_C = 10'h51,// LD D,C ; 51
+ LDsD_D = 10'h52,// LD D,D ; 52
+ LDsD_E = 10'h53,// LD D,E ; 53
+ LDsD_H = 10'h54,// LD D,H ; 54
+ LDsD_L = 10'h55,// LD D,L ; 55
+ LDsD_6HL7 = 10'h56,// LD D,(HL) ; 56
+ LDsD_A = 10'h57,// LD D,A ; 57
+ LDsE_B = 10'h58,// LD E,B ; 58
+ LDsE_C = 10'h59,// LD E,C ; 59
+ LDsE_D = 10'h5A,// LD E,D ; 5A
+ LDsE_E = 10'h5B,// LD E,E ; 5B
+ LDsE_H = 10'h5C,// LD E,H ; 5C
+ LDsE_L = 10'h5D,// LD E,L ; 5D
+ LDsE_6HL7 = 10'h5E,// LD E,(HL) ; 5E
+ LDsE_A = 10'h5F,// LD E,A ; 5F
+ LDsH_B = 10'h60,// LD H,B ; 60
+ LDsH_C = 10'h61,// LD H,C ; 61
+ LDsH_D = 10'h62,// LD H,D ; 62
+ LDsH_E = 10'h63,// LD H,E ; 63
+ LDsH_H = 10'h64,// LD H,H ; 64
+ LDsH_L = 10'h65,// LD H,L ; 65
+ LDsH_6HL7 = 10'h66,// LD H,(HL) ; 66
+ LDsH_A = 10'h67,// LD H,A ; 67
+ LDsL_B = 10'h68,// LD L,B ; 68
+ LDsL_C = 10'h69,// LD L,C ; 69
+ LDsL_D = 10'h6A,// LD L,D ; 6A
+ LDsL_E = 10'h6B,// LD L,E ; 6B
+ LDsL_H = 10'h6C,// LD L,H ; 6C
+ LDsL_L = 10'h6D,// LD L,L ; 6D
+ LDsL_6HL7 = 10'h6E,// LD L,(HL) ; 6E
+ LDsL_A = 10'h6F,// LD L,A ; 6F
+ LDs6HL7_B = 10'h70,// LD (HL),B ; 70
+ LDs6HL7_C = 10'h71,// LD (HL),C ; 71
+ LDs6HL7_D = 10'h72,// LD (HL),D ; 72
+ LDs6HL7_E = 10'h73,// LD (HL),E ; 73
+ LDs6HL7_H = 10'h74,// LD (HL),H ; 74
+ LDs6HL7_L = 10'h75,// LD (HL),L ; 75
+ HALT = 10'h76,// HALT ; 76
+ LDs6HL7_A = 10'h77,// LD (HL),A ; 77
+ LDsA_B = 10'h78,// LD A,B ; 78
+ LDsA_C = 10'h79,// LD A,C ; 79
+ LDsA_D = 10'h7A,// LD A,D ; 7A
+ LDsA_E = 10'h7B,// LD A,E ; 7B
+ LDsA_H = 10'h7C,// LD A,H ; 7C
+ LDsA_L = 10'h7D,// LD A,L ; 7D
+ LDsA_6HL7 = 10'h7E,// LD A,(HL) ; 7E
+ LDsA_A = 10'h7F,// LD A,A ; 7F
+ ADDsA_B = 10'h80,// ADD A,B ; 80
+ ADDsA_C = 10'h81,// ADD A,C ; 81
+ ADDsA_D = 10'h82,// ADD A,D ; 82
+ ADDsA_E = 10'h83,// ADD A,E ; 83
+ ADDsA_H = 10'h84,// ADD A,H ; 84
+ ADDsA_L = 10'h85,// ADD A,L ; 85
+ ADDsA_6HL7 = 10'h86,// ADD A,(HL) ; 86
+ ADDsA_A = 10'h87,// ADD A,A ; 87
+ ADCsA_B = 10'h88,// ADC A,B ; 88
+ ADCsA_C = 10'h89,// ADC A,C ; 89
+ ADCsA_D = 10'h8A,// ADC A,D ; 8A
+ ADCsA_E = 10'h8B,// ADC A,E ; 8B
+ ADCsA_H = 10'h8C,// ADC A,H ; 8C
+ ADCsA_L = 10'h8D,// ADC A,L ; 8D
+ ADCsA_6HL7 = 10'h8E,// ADC A,(HL) ; 8E
+ ADCsA_A = 10'h8F,// ADC A,A ; 8F
+ SUBsB = 10'h90,// SUB B ; 90
+ SUBsC = 10'h91,// SUB C ; 91
+ SUBsD = 10'h92,// SUB D ; 92
+ SUBsE = 10'h93,// SUB E ; 93
+ SUBsH = 10'h94,// SUB H ; 94
+ SUBsL = 10'h95,// SUB L ; 95
+ SUBs6HL7 = 10'h96,// SUB (HL) ; 96
+ SUBsA = 10'h97,// SUB A ; 97
+ SBCsB = 10'h98,// SBC B ; 98
+ SBCsC = 10'h99,// SBC C ; 99
+ SBCsD = 10'h9A,// SBC D ; 9A
+ SBCsE = 10'h9B,// SBC E ; 9B
+ SBCsH = 10'h9C,// SBC H ; 9C
+ SBCsL = 10'h9D,// SBC L ; 9D
+ SBCs6HL7 = 10'h9E,// SBC (HL) ; 9E
+ SBCsA = 10'h9F,// SBC A ; 9F
+ ANDsB = 10'hA0,// AND B ; A0
+ ANDsC = 10'hA1,// AND C ; A1
+ ANDsD = 10'hA2,// AND D ; A2
+ ANDsE = 10'hA3,// AND E ; A3
+ ANDsH = 10'hA4,// AND H ; A4
+ ANDsL = 10'hA5,// AND L ; A5
+ ANDs6HL7 = 10'hA6,// AND (HL) ; A6
+ ANDsA = 10'hA7,// AND A ; A7
+ XORsB = 10'hA8,// XOR B ; A8
+ XORsC = 10'hA9,// XOR C ; A9
+ XORsD = 10'hAA,// XOR D ; AA
+ XORsE = 10'hAB,// XOR E ; AB
+ XORsH = 10'hAC,// XOR H ; AC
+ XORsL = 10'hAD,// XOR L ; AD
+ XORs6HL7 = 10'hAE,// XOR (HL) ; AE
+ XORsA = 10'hAF,// XOR A ; AF
+ ORsB = 10'hB0,// OR B ; B0
+ ORsC = 10'hB1,// OR C ; B1
+ ORsD = 10'hB2,// OR D ; B2
+ ORsE = 10'hB3,// OR E ; B3
+ ORsH = 10'hB4,// OR H ; B4
+ ORsL = 10'hB5,// OR L ; B5
+ ORs6HL7 = 10'hB6,// OR (HL) ; B6
+ ORsA = 10'hB7,// OR A ; B7
+ CPsB = 10'hB8,// CP B ; B8
+ CPsC = 10'hB9,// CP C ; B9
+ CPsD = 10'hBA,// CP D ; BA
+ CPsE = 10'hBB,// CP E ; BB
+ CPsH = 10'hBC,// CP H ; BC
+ CPsL = 10'hBD,// CP L ; BD
+ CPs6HL7 = 10'hBE,// CP (HL) ; BE
+ CPsA = 10'hBF,// CP A ; BF
+ RETsNZ = 10'hC0,// RET NZ ; C0
+ POPsBC = 10'hC1,// POP BC ; C1
+ JPsNZ = 10'hC2,// JP NZ ; C2 XX XX
+ JP = 10'hC3,// JP ; C3 XX XX
+ CALLsNZ_NN = 10'hC4,// CALL NZ,NN ; C4 XX XX
+ PUSHsBC = 10'hC5,// PUSH BC ; C5
+ ADDsA_N = 10'hC6,// ADD A,N ; C6 XX
+ RSTs0 = 10'hC7,// RST 0 ; C7
+ RETsZ = 10'hC8,// RET Z ; C8
+ RET = 10'hC9,// RET ; C9
+ JPsZ = 10'hCA,// JP Z ; CA XX XX
+ CALLsZ_NN = 10'hCC,// CALL Z,NN ; CC XX XX
+ CBgrp = 10'hCB,// CBgrp is rotates and bit munging below
+ CALLsNN = 10'hCD,// CALL NN ; CD XX XX
+ ADCsA_N = 10'hCE,// ADC A,N ; CE XX
+ RSTs8H = 10'hCF,// RST 8H ; CF
+ RETsNC = 10'hD0,// RET NC ; D0
+ POPsDE = 10'hD1,// POP DE ; D1
+ JPsNC = 10'hD2,// JP NC, ; D2 XX XX
+ OUTs6N7_A = 10'hD3,// OUT (N),A ; D3 XX
+ CALLsNC_NN = 10'hD4,// CALL NC,NN ; D4 XX XX
+ PUSHsDE = 10'hD5,// PUSH DE ; D5
+ SUBsN = 10'hD6,// SUB N ; D6 XX
+ RSTs10H = 10'hD7,// RST 10H ; D7
+ RETsC = 10'hD8,// RET C ; D8
+ EXX = 10'hD9,// EXX ; D9
+ JPsC = 10'hDA,// JP C ; DA XX XX
+ INsA_6N7 = 10'hDB,// IN A,(N) ; DB XX
+ CALLsC_NN = 10'hDC,// CALL C,NN ; DC XX XX
+ DDgrp = 10'hDD,// DDgrp
+ SBCsA_N = 10'hDE,// SBC A,N ; DE XX
+ RSTs18H = 10'hDF,// RST 18H ; DF
+ RETsPO = 10'hE0,// RET PO ; E0
+ POPsHL = 10'hE1,// POP HL ; E1
+ JPsPO = 10'hE2,// JP PO ; E2 XX XX
+ EXs6SP7_HL = 10'hE3,// EX (SP),HL ; E3
+ CALLsPO_NN = 10'hE4,// CALL PO,NN ; E4 XX XX
+ PUSHsHL = 10'hE5,// PUSH HL ; E5
+ ANDsN = 10'hE6,// AND N ; E6 XX
+ RSTs20H = 10'hE7,// RST 20H ; E7
+ RETsPE = 10'hE8,// RET PE ; E8
+ JPsHL = 10'hE9,// JP HL ; E9 // documented as indirect IS NOT
+ JPsPE = 10'hEA,// JP PE, ; EA XX XX
+ EXsDE_HL = 10'hEB,// EX DE,HL ; EB
+ CALLsPE_NN = 10'hEC,// CALL PE,NN ; EC XX XX
+ EDgrp = 10'hED,// EDgrp ED
+ XORsN = 10'hEE,// XOR N ; EE XX
+ RSTs28H = 10'hEF,// RST 28H ; EF
+ RETsP = 10'hF0,// RET P ; F0
+ POPsAF = 10'hF1,// POP AF ; F1
+ JPsP = 10'hF2,// JP P ; F2 XX XX
+ DI = 10'hF3,// DI ; F3
+ CALLsP_NN = 10'hF4,// CALL P,NN ; F4 XX XX
+ PUSHsAF = 10'hF5,// PUSH AF ; F5
+ ORsN = 10'hF6,// OR N ; F6 XX
+ RSTs30H = 10'hF7,// RST 30H ; F7
+ RETsM = 10'hF8,// RET M ; F8
+ LDsSP_HL = 10'hF9,// LD SP,HL ; F9
+ JPsM = 10'hFA,// JP M, ; FA XX XX
+ EI = 10'hFB,// EI ; FB
+ CALLsM_NN = 10'hFC,// CALL M,NN ; FC XX XX
+ FDgrp = 10'hFD,// FDgrp FD
+ CPsN = 10'hFE,// CP N ; FE XX
+ RSTs38H = 10'hFF,// RST 38H ; FF
+
+// the CB set
+// These have enough structure that I don't believe I will define a parameter for each
+// First cut below
+ CB_RLC = 7'b01_00_000, // these must be compaired with ir[9:3]
+ CB_RRC = 7'b01_00_001, // these must be compaired with ir[9:3]
+ CB_RL = 7'b01_00_010, // these must be compaired with ir[9:3]
+ CB_RR = 7'b01_00_011, // these must be compaired with ir[9:3]
+ CB_SLA = 7'b01_00_100, // these must be compaired with ir[9:3]
+ CB_SRA = 7'b01_00_101, // these must be compaired with ir[9:3]
+ CB_SLL = 7'b01_00_110, // these must be compaired with ir[9:3]
+ CB_SRL = 7'b01_00_111, // these must be compaired with ir[9:3]
+
+ CB_BIT = 4'b01_01, // these must be compaired with ir[9:6]
+ CB_RES = 4'b01_10, // these must be compaired with ir[9:6]
+ CB_SET = 4'b01_11, // these must be compaired with ir[9:6]
+
+ CB_MEM = 3'b110, // this must be compaired with ir[2:0]
+ // note these are all read-modify-writ except CB_BIT
+
+// The ED Group
+// These are the "unique instructions in the 46, 47 rows that NEED? to be implemented
+// Not sure I want to worry about all undocumented stuff in these rows - hard to believe
+// It will matter.(IM modes are very system dependent - hard to believe even a programmer
+// would use undocumented instructions to muck with this stuff)
+ ED_IMs0 = 10'h246, // IM 0 ; ED 46 set IM0
+ ED_LDsI_A = 10'h247, // LD I,A ; ED 47 move a to I
+ ED_IMs1 = 10'h256, // IM 1 ; ED 56 set IM1
+ ED_LDsA_I = 10'h257, // LD A,I ; ED 57 move I to A
+ ED_IMs2 = 10'h25E, // IM 2 ; ED 5E set IM2
+ ED_RRD = 10'h267, // RRD ; ED 67 nibble roates A HL
+ ED_RLD = 10'h26F, // RLD ; ED 6F nibble roates A HL
+
+
+ ED_LDI = 10'h2A0, // LDI ; ED A0 These are block move
+ ED_CPI = 10'h2A1, // CPI ; ED A1 type insts that don't repeat
+ ED_INI = 10'h2A2, // INI ; ED A2
+ ED_OUTI = 10'h2A3, // OUTI ; ED A3
+ ED_LDD = 10'h2A8, // LDD ; ED A8
+ ED_CPD = 10'h2A9, // CPD ; ED A9
+ ED_IND = 10'h2AA, // IND ; ED AA
+ ED_OUTD = 10'h2AB, // OUTD ; ED AB
+ ED_LDIR = 10'h2B0, // LDIR ; ED B0 These are block move
+ ED_CPIR = 10'h2B1, // CPIR ; ED B1 type insts that DO repeat
+ ED_INIR = 10'h2B2, // INIR ; ED B2
+ ED_OTIR = 10'h2B3, // OTIR ; ED B3
+ ED_LDDR = 10'h2B8, // LDDR ; ED B8
+ ED_CPDR = 10'h2B9, // CPDR ; ED B9
+ ED_INDR = 10'h2BA, // INDR ; ED BA
+ ED_OTDR = 10'h2BB, // OTDR ; ED BB
+
+// the ED gropu definitions from 40 to 7f from document on undocumented insts.....
+//
+// ED40 IN B,(C) ED50 IN D,(C) ED60 IN H,(C) ED70 IN (C) / IN F,(C)
+// ED41 OUT (C),B ED51 OUT (C),D ED61 OUT (C),H ED71 OUT (C),0*
+// ED42 SBC HL,BC ED52 SBC HL,DE ED62 SBC HL,HL ED72 SBC HL,SP
+// ED43 LD (nn),BC ED53 LD (nn),DE ED63 LD (nn),HL ED73 LD (nn),SP
+// ED44 NEG ED54 NEG* ED64 NEG* ED74 NEG*
+// ED45 RETN ED55 RETN* ED65 RETN* ED75 RETN*
+// ED46 IM 0 ED56 IM 1 ED66 IM 0* ED76 IM 1*
+// ED47 LD I,A ED57 LD A,I ED67 RRD ED77 NOP*
+
+// ED48 IN C,(C) ED58 IN E,(C) ED68 IN L,(C) ED78 IN A,(C)
+// ED49 OUT (C),C ED59 OUT (C),E ED69 OUT (C),L ED79 OUT (C),A
+// ED4A ADC HL,BC ED5A ADC HL,DE ED6A ADC HL,HL ED7A ADC HL,SP
+// ED4B LD BC,(nn) ED5B LD DE,(nn) ED6B LD HL,(nn) ED7B LD SP,(nn)
+// ED4C NEG* ED5C NEG* ED6C NEG* ED7C NEG*
+// ED4D RETI ED5D RETN* ED6D RETN* ED7D RETN*
+// ED4E IM 0* ED5E IM 2 ED6E IM 0* ED7E IM 2*
+// ED4F LD R,A ED5F LD A,R ED6F RLD ED7F NOP*
+
+
+//The ED70 instruction reads from I/O port C,
+//but does not store the result.
+//It just affects the flags. Hard to test. like the other IN x,(C) instruction.
+//
+//ED71 simply outs the value 0 to I/O port C.
+// This suggests that we should decode as follows:
+// I hope if I don't get all the IM duplicates right it won't be a tragedy
+ ED_INsREG_6C7 = 7'b1001___000, // compair with {ir[9:6],ir[2:0]}
+ ED_OUTs6C7_REG = 7'b1001___001, // compair with {ir[9:6],ir[2:0]}
+ ED_SBCsHL_REG = 8'b1001__0010, // compair with {ir[9:6],ir[3:0]}
+ ED_ADCsHL_REG = 8'b1001__1010, // compair with {ir[9:6],ir[3:0]}
+ ED_LDs6NN7_REG = 8'b1001__0011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
+ ED_LDsREG_6NN7 = 8'b1001__1011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
+ ED_NEG = 7'b1001___100, // compair with {ir[9:6],ir[2:0]} all A<= -A
+ ED_RETN = 7'b1001___101, // compair with {ir[9:6],ir[2:0]} and !reti
+
+ DBL_REG_BC = 2'b00, // compair with ir[5:4]
+ DBL_REG_DE = 2'b00, // compair with ir[5:4]
+ DBL_REG_HL = 2'b00, // compair with ir[5:4]
+ DBL_REG_SP = 2'b00, // compair with ir[5:4]
+
+ REG8_B = 3'b000,
+ REG8_C = 3'b001,
+ REG8_D = 3'b010,
+ REG8_E = 3'b011,
+ REG8_H = 3'b100,
+ REG8_L = 3'b101,
+ REG8_MEM = 3'b110,
+ REG8_A = 3'b111;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
Index: tags/arelease/inc/work_updreg.v
===================================================================
--- tags/arelease/inc/work_updreg.v (nonexistent)
+++ tags/arelease/inc/work_updreg.v (revision 3)
@@ -0,0 +1,528 @@
+///////////////////////////////////////////////////////////////////////////////////////////////////
+// //
+// file name: work_updr.v //
+// description: opcode parameters for z80 //
+// project: wb_z80 //
+// //
+// Author: B.J. Porcella //
+// e-mail: bporcella@sbcglobal.net //
+// //
+// //
+// //
+///////////////////////////////////////////////////////////////////////////////////////////////////
+// //
+// Copyright (C) 2000-2002 B.J. Porcella //
+// Real Time Solutions //
+// //
+// //
+// This source file may be used and distributed without //
+// restriction provided that this copyright statement is not //
+// removed from the file and that any derivative work contains //
+// the original copyright notice and the associated disclaimer. //
+// //
+// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //
+// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //
+// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //
+// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //
+// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //
+// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //
+// POSSIBILITY OF SUCH DAMAGE. //
+// //
+//-------1---------2---------3--------Comments on file -------------7---------8---------9--------0
+//
+// not really a source file -- more of a work file -- as named.
+// but I probably will keep it around.
+//
+// dice up all defined instructions for updating each register.
+//
+//
+//
+//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
+//
+// $Id: work_updreg.v,v 1.1.1.1 2004-06-18 08:38:41 mihal Exp $
+//
+// $Date: 2004-06-18 08:38:41 $
+// $Revision: 1.1.1.1 $
+// $Author: mihal $
+// $Locker: $
+// $State: Exp $
+//
+// Change History:
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2004/04/13 23:48:00 bporcella
+// import first files
+//
+//
+//
+//-------1---------2---------3--------Comments on file -------------7---------8---------9--------0
+//
+NOP = 10'h00,// NOP ; 00
+
+// update ar
+RLCA = 10'h07,// RLCA ; 07
+EXsAF_AFp = 10'h08,// EX AF,AF' ; 08
+LDsA_6BC7 = 10'h0A,// LD A,(BC) ; 0A
+RRCA = 10'h0F,// RRCA ; 0F
+RLA = 10'h17,// RLA ; 17
+LDsA_6DE7 = 10'h1A,// LD A,(DE) ; 1A
+RRA = 10'h1F,// RRA ; 1F
+DAA = 10'h27,// DAA ; 27
+CPL = 10'h2F,// CPL ; 2F a <= ~a
+LDsA_6NN7 = 10'h3A,// LD A,(NN) ; 3A XX XX
+INCsA = 10'h3C,// INC A ; 3C
+DECsA = 10'h3D,// DEC A ; 3D
+LDsA_N = 10'h3E,// LD A,N ; 3E XX
+LDsA_B = 10'h78,// LD A,B ; 78
+LDsA_C = 10'h79,// LD A,C ; 79
+LDsA_D = 10'h7A,// LD A,D ; 7A
+LDsA_E = 10'h7B,// LD A,E ; 7B
+LDsA_H = 10'h7C,// LD A,H ; 7C
+LDsA_L = 10'h7D,// LD A,L ; 7D
+LDsA_6HL7 = 10'h7E,// LD A,(HL) ; 7E
+LDsA_A = 10'h7F,// LD A,A ; 7F
+ADDsA_B = 10'h80,// ADD A,B ; 80
+ADDsA_C = 10'h81,// ADD A,C ; 81
+ADDsA_D = 10'h82,// ADD A,D ; 82
+ADDsA_E = 10'h83,// ADD A,E ; 83
+ADDsA_H = 10'h84,// ADD A,H ; 84
+ADDsA_L = 10'h85,// ADD A,L ; 85
+ADDsA_6HL7 = 10'h86,// ADD A,(HL) ; 86
+ADDsA_A = 10'h87,// ADD A,A ; 87
+ADCsA_B = 10'h88,// ADC A,B ; 88
+ADCsA_C = 10'h89,// ADC A,C ; 89
+ADCsA_D = 10'h8A,// ADC A,D ; 8A
+ADCsA_E = 10'h8B,// ADC A,E ; 8B
+ADCsA_H = 10'h8C,// ADC A,H ; 8C
+ADCsA_L = 10'h8D,// ADC A,L ; 8D
+ADCsA_6HL7 = 10'h8E,// ADC A,(HL) ; 8E
+ADCsA_A = 10'h8F,// ADC A,A ; 8F
+SUBsB = 10'h90,// SUB B ; 90
+SUBsC = 10'h91,// SUB C ; 91
+SUBsD = 10'h92,// SUB D ; 92
+SUBsE = 10'h93,// SUB E ; 93
+SUBsH = 10'h94,// SUB H ; 94
+SUBsL = 10'h95,// SUB L ; 95
+SUBs6HL7 = 10'h96,// SUB (HL) ; 96
+SUBsA = 10'h97,// SUB A ; 97
+SBCsB = 10'h98,// SBC B ; 98
+SBCsC = 10'h99,// SBC C ; 99
+SBCsD = 10'h9A,// SBC D ; 9A
+SBCsE = 10'h9B,// SBC E ; 9B
+SBCsH = 10'h9C,// SBC H ; 9C
+SBCsL = 10'h9D,// SBC L ; 9D
+SBCs6HL7 = 10'h9E,// SBC (HL) ; 9E
+SBCsA = 10'h9F,// SBC A ; 9F
+ANDsB = 10'hA0,// AND B ; A0
+ANDsC = 10'hA1,// AND C ; A1
+ANDsD = 10'hA2,// AND D ; A2
+ANDsE = 10'hA3,// AND E ; A3
+ANDsH = 10'hA4,// AND H ; A4
+ANDsL = 10'hA5,// AND L ; A5
+ANDs6HL7 = 10'hA6,// AND (HL) ; A6
+ANDsA = 10'hA7,// AND A ; A7
+XORsB = 10'hA8,// XOR B ; A8
+XORsC = 10'hA9,// XOR C ; A9
+XORsD = 10'hAA,// XOR D ; AA
+XORsE = 10'hAB,// XOR E ; AB
+XORsH = 10'hAC,// XOR H ; AC
+XORsL = 10'hAD,// XOR L ; AD
+XORs6HL7 = 10'hAE,// XOR (HL) ; AE
+XORsA = 10'hAF,// XOR A ; AF
+ORsB = 10'hB0,// OR B ; B0
+ORsC = 10'hB1,// OR C ; B1
+ORsD = 10'hB2,// OR D ; B2
+ORsE = 10'hB3,// OR E ; B3
+ORsH = 10'hB4,// OR H ; B4
+ORsL = 10'hB5,// OR L ; B5
+ORs6HL7 = 10'hB6,// OR (HL) ; B6
+ORsA = 10'hB7,// OR A ; B7
+ADDsA_N = 10'hC6,// ADD A,N ; C6 XX
+ADCsA_N = 10'hCE,// ADC A,N ; CE XX
+SUBsN = 10'hD6,// SUB N ; D6 XX
+EXX = 10'hD9,// EXX ; D9
+INsA_6N7 = 10'hDB,// IN A,(N) ; DB XX
+SBCsA_N = 10'hDE,// SBC A,N ; DE XX
+ANDsN = 10'hE6,// AND N ; E6 XX
+XORsN = 10'hEE,// XOR N ; EE XX
+POPsAF = 10'hF1,// POP AF ; F1
+ORsN = 10'hF6,// OR N ; F6 XX
+ED_NEG = 5'b01___100, // compair with {ir[7:6],ir[2:0]} all A<= -A
+
+// update br
+LDsBC_nn = 10'h01,// LD BC,NN ; 01 XX XX
+INCsBC = 10'h03,// INC BC ; 03
+INCsB = 10'h04,// INC B ; 04
+DECsB = 10'h05,// DEC B ; 05
+LDsB_N = 10'h06,// LD B,N ; 06 XX
+DECsBC = 10'h0B,// DEC BC ; 0B
+DJNZs$t2 = 10'h10,// DJNZ $+2 ; 10 XX //pre dec br
+LDsB_B = 10'h40,// LD B,B ; 40
+LDsB_C = 10'h41,// LD B,C ; 41
+LDsB_D = 10'h42,// LD B,D ; 42
+LDsB_E = 10'h43,// LD B,E ; 43
+LDsB_H = 10'h44,// LD B,H ; 44
+LDsB_L = 10'h45,// LD B,L ; 45
+LDsB_6HL7 = 10'h46,// LD B,(HL) ; 46
+LDsB_A = 10'h47,// LD B,A ; 47
+POPsBC = 10'hC1,// POP BC ; C1
+EXX = 10'hD9,// EXX ; D9
+// update cr
+LDsBC_nn = 10'h01,// LD BC,NN ; 01 XX XX
+INCsBC = 10'h03,// INC BC ; 03
+DECsBC = 10'h0B,// DEC BC ; 0B
+INCsC = 10'h0C,// INC C ; 0C
+DECsC = 10'h0D,// DEC C ; 0D
+LDsC_N = 10'h0E,// LD C,N ; 0E XX
+LDsC_B = 10'h48,// LD C,B ; 48
+LDsC_C = 10'h49,// LD C,C ; 49
+LDsC_D = 10'h4A,// LD C,D ; 4A
+LDsC_E = 10'h4B,// LD C,E ; 4B
+LDsC_H = 10'h4C,// LD C,H ; 4C
+LDsC_L = 10'h4D,// LD C,L ; 4D
+LDsC_6HL7 = 10'h4E,// LD C,(HL) ; 4E
+LDsC_A = 10'h4F,// LD C,A ; 4F
+POPsBC = 10'hC1,// POP BC ; C1
+EXX = 10'hD9,// EXX ; D9
+// update dr
+LDsDE_NN = 10'h11,// LD DE,NN ; 11 XX XX
+INCsDE = 10'h13,// INC DE ; 13
+INCsD = 10'h14,// INC D ; 14
+DECsD = 10'h15,// DEC D ; 15
+LDsD_N = 10'h16,// LD D,N ; 16 XX
+DECsDE = 10'h1B,// DEC DE ; 1B
+LDsD_B = 10'h50,// LD D,B ; 50
+LDsD_C = 10'h51,// LD D,C ; 51
+LDsD_D = 10'h52,// LD D,D ; 52
+LDsD_E = 10'h53,// LD D,E ; 53
+LDsD_H = 10'h54,// LD D,H ; 54
+LDsD_L = 10'h55,// LD D,L ; 55
+LDsD_6HL7 = 10'h56,// LD D,(HL) ; 56
+LDsD_A = 10'h57,// LD D,A ; 57
+POPsDE = 10'hD1,// POP DE ; D1
+EXX = 10'hD9,// EXX ; D9
+EXsDE_HL = 10'hEB,// EX DE,HL ; EB
+// update er
+LDsDE_NN = 10'h11,// LD DE,NN ; 11 XX XX
+INCsDE = 10'h13,// INC DE ; 13
+DECsDE = 10'h1B,// DEC DE ; 1B
+INCsE = 10'h1C,// INC E ; 1C
+DECsE = 10'h1D,// DEC E ; 1D
+LDsE_N = 10'h1E,// LD E,N ; 1E XX
+LDsE_B = 10'h58,// LD E,B ; 58
+LDsE_C = 10'h59,// LD E,C ; 59
+LDsE_D = 10'h5A,// LD E,D ; 5A
+LDsE_E = 10'h5B,// LD E,E ; 5B
+LDsE_H = 10'h5C,// LD E,H ; 5C
+LDsE_L = 10'h5D,// LD E,L ; 5D
+LDsE_6HL7 = 10'h5E,// LD E,(HL) ; 5E
+LDsE_A = 10'h5F,// LD E,A ; 5F
+POPsDE = 10'hD1,// POP DE ; D1
+EXX = 10'hD9,// EXX ; D9
+EXsDE_HL = 10'hEB,// EX DE,HL ; EB
+// update hr
+ADDsHL_BC = 10'h09,// ADD HL,BC ; 09
+ADDsHL_DE = 10'h19,// ADD HL,DE ; 19
+LDsHL_NN = 10'h21,// LD HL,NN ; 21 XX XX
+INCsHL = 10'h23,// INC HL ; 23
+INCsH = 10'h24,// INC H ; 24
+DECsH = 10'h25,// DEC H ; 25
+LDsH_N = 10'h26,// LD H,N ; 26 XX
+ADDsHL_HL = 10'h29,// ADD HL,HL ; 29
+LDsHL_6NN7 = 10'h2A,// LD HL,(NN) ; 2A XX XX
+DECsHL = 10'h2B,// DEC HL ; 2B
+ADDsHL_SP = 10'h39,// ADD HL,SP ; 39
+LDsH_B = 10'h60,// LD H,B ; 60
+LDsH_C = 10'h61,// LD H,C ; 61
+LDsH_D = 10'h62,// LD H,D ; 62
+LDsH_E = 10'h63,// LD H,E ; 63
+LDsH_H = 10'h64,// LD H,H ; 64
+LDsH_L = 10'h65,// LD H,L ; 65
+LDsH_6HL7 = 10'h66,// LD H,(HL) ; 66
+LDsH_A = 10'h67,// LD H,A ; 67
+EXX = 10'hD9,// EXX ; D9
+POPsHL = 10'hE1,// POP HL ; E1
+EXs6SP7_HL = 10'hE3,// EX (SP),HL ; E3
+EXsDE_HL = 10'hEB,// EX DE,HL ; EB
+// update lr
+ADDsHL_BC = 10'h09,// ADD HL,BC ; 09
+ADDsHL_DE = 10'h19,// ADD HL,DE ; 19
+LDsHL_NN = 10'h21,// LD HL,NN ; 21 XX XX
+INCsHL = 10'h23,// INC HL ; 23
+ADDsHL_HL = 10'h29,// ADD HL,HL ; 29
+LDsHL_6NN7 = 10'h2A,// LD HL,(NN) ; 2A XX XX
+DECsHL = 10'h2B,// DEC HL ; 2B
+INCsL = 10'h2C,// INC L ; 2C
+DECsL = 10'h2D,// DEC L ; 2D
+LDsL_N = 10'h2E,// LD L,N ; 2E XX
+ADDsHL_SP = 10'h39,// ADD HL,SP ; 39
+LDsL_B = 10'h68,// LD L,B ; 68
+LDsL_C = 10'h69,// LD L,C ; 69
+LDsL_D = 10'h6A,// LD L,D ; 6A
+LDsL_E = 10'h6B,// LD L,E ; 6B
+LDsL_H = 10'h6C,// LD L,H ; 6C
+LDsL_L = 10'h6D,// LD L,L ; 6D
+LDsL_6HL7 = 10'h6E,// LD L,(HL) ; 6E
+LDsL_A = 10'h6F,// LD L,A ; 6F
+EXX = 10'hD9,// EXX ; D9
+POPsHL = 10'hE1,// POP HL ; E1
+EXs6SP7_HL = 10'hE3,// EX (SP),HL ; E3
+EXsDE_HL = 10'hEB,// EX DE,HL ; EB
+// update ixr
+// update iyr
+// update fr
+SCF = 10'h37,// SCF ; 37
+EXsAF_AFp = 10'h08,// EX AF,AF' ; 08
+CCF = 10'h3F,// CCF ; 3F
+CPsB = 10'hB8,// CP B ; B8
+CPsC = 10'hB9,// CP C ; B9
+CPsD = 10'hBA,// CP D ; BA
+CPsE = 10'hBB,// CP E ; BB
+CPsH = 10'hBC,// CP H ; BC
+CPsL = 10'hBD,// CP L ; BD
+CPs6HL7 = 10'hBE,// CP (HL) ; BE
+CPsA = 10'hBF,// CP A ; BF
+CPsN = 10'hFE,// CP N ; FE XX
+EXX = 10'hD9,// EXX ; D9
+POPsAF = 10'hF1,// POP AF ; F1
+
+// update shadow register
+EXsAF_AFp = 10'h08,// EX AF,AF' ; 08
+EXX = 10'hD9,// EXX ; D9
+
+// stuff to worry about
+LDsSP_NN = 10'h31,// LD SP,NN ; 31 XX XX
+INCsSP = 10'h33,// INC SP ; 33
+DECsSP = 10'h3B,// DEC SP ; 3B
+
+
+// memory stors and others
+LDs6DE7_A = 10'h12,// LD (DE),A ; 12
+LDs6BC7_A = 10'h02,// LD (BC),A ; 02
+JRs$t2 = 10'h18,// JR $+2 ; 18 XX
+JRsNZ_$t2 = 10'h20,// JR NZ,$+2 ; 20
+LDs6NN7_HL = 10'h22,// LD (NN),HL ; 22 XX XX
+JRsZ_$t2 = 10'h28,// JR Z,$+2 ; 28 XX
+JRsNC_$t2 = 10'h30,// JR NC,$+2 ; 30 XX
+LDs6NN7_A = 10'h32,// LD (NN),A ; 32 XX XX
+INCs6HL7 = 10'h34,// INC (HL) ; 34
+DECs6HL7 = 10'h35,// DEC (HL) ; 35
+LDs6HL7_N = 10'h36,// LD (HL),N ; 36 XX
+JRsC_$t2 = 10'h38,// JR C,$+2 ; 38 XX
+LDs6HL7_B = 10'h70,// LD (HL),B ; 70
+LDs6HL7_C = 10'h71,// LD (HL),C ; 71
+LDs6HL7_D = 10'h72,// LD (HL),D ; 72
+LDs6HL7_E = 10'h73,// LD (HL),E ; 73
+LDs6HL7_H = 10'h74,// LD (HL),H ; 74
+LDs6HL7_L = 10'h75,// LD (HL),L ; 75
+HALT = 10'h76,// HALT ; 76
+LDs6HL7_A = 10'h77,// LD (HL),A ; 77
+RETsNZ = 10'hC0,// RET NZ ; C0
+JPsNZ = 10'hC2,// JP NZ ; C2 XX XX
+JP = 10'hC3,// JP ; C3 XX XX
+CALLsNZ_NN = 10'hC4,// CALL NZ,NN ; C4 XX XX
+PUSHsBC = 10'hC5,// PUSH BC ; C5
+RSTs0 = 10'hC7,// RST 0 ; C7
+RETsZ = 10'hC8,// RET Z ; C8
+RET = 10'hC9,// RET ; C9
+JPsZ = 10'hCA,// JP Z ; CA XX XX
+CALLsZ_NN = 10'hCC,// CALL Z,NN ; CC XX XX
+CBgrp = 10'hCB,// CBgrp is rotates and bit munging below
+CALLsNN = 10'hCD,// CALL NN ; CD XX XX
+RSTs8H = 10'hCF,// RST 8H ; CF
+RETsNC = 10'hD0,// RET NC ; D0
+JPsNC = 10'hD2,// JP NC, ; D2 XX XX
+OUTs6N7_A = 10'hD3,// OUT (N),A ; D3 XX
+CALLsNC_NN = 10'hD4,// CALL NC,NN ; D4 XX XX
+PUSHsDE = 10'hD5,// PUSH DE ; D5
+RSTs10H = 10'hD7,// RST 10H ; D7
+RETsC = 10'hD8,// RET C ; D8
+JPsC = 10'hDA,// JP C ; DA XX XX
+CALLsC_NN = 10'hDC,// CALL C,NN ; DC XX XX
+DDgrp = 10'hDD,// DDgrp
+RSTs18H = 10'hDF,// RST 18H ; DF
+RETsPO = 10'hE0,// RET PO ; E0 // ret if positive
+JPsPO = 10'hE2,// JP PO ; E2 XX XX
+EXs6SP7_HL = 10'hE3,// EX (SP),HL ; E3
+CALLsPO_NN = 10'hE4,// CALL PO,NN ; E4 XX XX
+PUSHsHL = 10'hE5,// PUSH HL ; E5
+RSTs20H = 10'hE7,// RST 20H ; E7
+RETsPE = 10'hE8,// RET PE ; E8
+JPsHL = 10'hE9,// JP HL ; E9 // documented as indirect IS NOT
+JPsPE = 10'hEA,// JP PE, ; EA XX XX
+CALLsPE_NN = 10'hEC,// CALL PE,NN ; EC XX XX
+EDgrp = 10'hED,// EDgrp ED
+
+RSTs28H = 10'hEF,// RST 28H ; EF
+RETsP = 10'hF0,// RET P ; F0
+JPsP = 10'hF2,// JP P ; F2 XX XX
+DI = 10'hF3,// DI ; F3
+CALLsP_NN = 10'hF4,// CALL P,NN ; F4 XX XX
+PUSHsAF = 10'hF5,// PUSH AF ; F5
+RSTs30H = 10'hF7,// RST 30H ; F7
+RETsM = 10'hF8,// RET M ; F8
+LDsSP_HL = 10'hF9,// LD SP,HL ; F9
+JPsM = 10'hFA,// JP M, ; FA XX XX
+EI = 10'hFB,// EI ; FB
+CALLsM_NN = 10'hFC,// CALL M,NN ; FC XX XX
+FDgrp = 10'hFD,// FDgrp FD
+RSTs38H = 10'hFF,// RST 38H ; FF
+
+// the CB set
+// These have enough structure that I don't believe I will define a parameter for each
+// First cut below
+// put together a decode term here for all registers
+
+CB_RLC = 7'b01_00_000, // these must be compaired with ir[9:3]
+CB_RRC = 7'b01_00_001, // these must be compaired with ir[9:3]
+CB_RL = 7'b01_00_010, // these must be compaired with ir[9:3]
+CB_RR = 7'b01_00_011, // these must be compaired with ir[9:3]
+CB_SLA = 7'b01_00_100, // these must be compaired with ir[9:3]
+CB_SRA = 7'b01_00_101, // these must be compaired with ir[9:3]
+CB_SLL = 7'b01_00_110, // these must be compaired with ir[9:3]
+CB_SRL = 7'b01_00_111, // these must be compaired with ir[9:3]
+
+CB_BIT = 4'b01_01, // these must be compaired with ir[9:6]
+CB_RES = 4'b01_10, // these must be compaired with ir[9:6]
+CB_SET = 4'b01_11, // these must be compaired with ir[9:6]
+
+CB_MEM = 3'h110, // this must be compaired with ir[2:0]
+ // note these are all read-modify-writ except CB_BIT
+
+// The ED Group
+// These are the "unique instructions in the 46, 47 rows that NEED? to be implemented
+// Not sure I want to worry about all undocumented stuff in these rows - hard to believe
+// It will matter.(IM modes are very system dependent - hard to believe even a programmer
+// would use undocumented instructions to muck with this stuff)
+ ED_IMs0 = 10'h246// IM 0 ; ED 46 set IM0
+ ED_LDsI_A = 10'h247// LD I,A ; ED 47 move a to I
+ ED_IMs1 = 10'h256// IM 1 ; ED 56 set IM1
+ ED_LDsA_I = 10'h257// LD A,I ; ED 57 move I to A
+ ED_IMs2 = 10'h25E// IM 2 ; ED 5E set IM2
+ ED_RRD = 10'h267// RRD ; ED 67 nibble roates A HL
+ ED_RLD = 10'h26F// RLD ; ED 6F nibble roates A HL
+
+
+ ED_LDI = 10'h2A0// LDI ; ED A0 These are block move
+ ED_CPI = 10'h2A1// CPI ; ED A1 type insts that don't repeat
+ ED_INI = 10'h2A2// INI ; ED A2
+ ED_OUTI = 10'h2A3// OUTI ; ED A3
+ ED_LDD = 10'h2A8// LDD ; ED A8
+ ED_CPD = 10'h2A9// CPD ; ED A9
+ ED_IND = 10'h2AA// IND ; ED AA
+ ED_OUTD = 10'h2AB// OUTD ; ED AB
+ ED_LDIR = 10'h2B0// LDIR ; ED B0 These are block move
+ ED_CPIR = 10'h2B1// CPIR ; ED B1 type insts that DO repeat
+ ED_INIR = 10'h2B2// INIR ; ED B2
+ ED_OTIR = 10'h2B3// OTIR ; ED B3
+ ED_LDDR = 10'h2B8// LDDR ; ED B8
+ ED_CPDR = 10'h2B9// CPDR ; ED B9
+ ED_INDR = 10'h2BA// INDR ; ED BA
+ ED_OTDR = 10'h2BB// OTDR ; ED BB
+
+// the ED gropu definitions from 40 to 7f from document on undocumented insts.....
+//
+// ED40 IN B,(C) ED50 IN D,(C) ED60 IN H,(C) ED70 IN (C) / IN F,(C)
+// ED41 OUT (C),B ED51 OUT (C),D ED61 OUT (C),H ED71 OUT (C),0*
+// ED42 SBC HL,BC ED52 SBC HL,DE ED62 SBC HL,HL ED72 SBC HL,SP
+// ED43 LD (nn),BC ED53 LD (nn),DE ED63 LD (nn),HL ED73 LD (nn),SP
+// ED44 NEG ED54 NEG* ED64 NEG* ED74 NEG*
+// ED45 RETN ED55 RETN* ED65 RETN* ED75 RETN*
+// ED46 IM 0 ED56 IM 1 ED66 IM 0* ED76 IM 1*
+// ED47 LD I,A ED57 LD A,I ED67 RRD ED77 NOP*
+
+// ED48 IN C,(C) ED58 IN E,(C) ED68 IN L,(C) ED78 IN A,(C)
+// ED49 OUT (C),C ED59 OUT (C),E ED69 OUT (C),L ED79 OUT (C),A
+// ED4A ADC HL,BC ED5A ADC HL,DE ED6A ADC HL,HL ED7A ADC HL,SP
+// ED4B LD BC,(nn) ED5B LD DE,(nn) ED6B LD HL,(nn) ED7B LD SP,(nn)
+// ED4C NEG* ED5C NEG* ED6C NEG* ED7C NEG*
+// ED4D RETI ED5D RETN* ED6D RETN* ED7D RETN*
+// ED4E IM 0* ED5E IM 2 ED6E IM 0* ED7E IM 2*
+// ED4F LD R,A ED5F LD A,R ED6F RLD ED7F NOP*
+
+
+//The ED70 instruction reads from I/O port C,
+//but does not store the result.
+//It just affects the flags. Hard to test. like the other IN x,(C) instruction.
+//
+//ED71 simply outs the value 0 to I/O port C.
+// This suggests that we should decode as follows:
+// I hope if I don't get all the IM duplicates right it won't be a tragedy
+ ED_INsREG_6C7 = 5'b01___000,// compair with {ir[7:6],ir[2:0]}
+
+ ED_SBCsHL_REG = 6'b01__0010, // compair with {ir[9:6],ir[3:0]}
+ ED_ADCsHL_REG = 6'b01__1010, // compair with {ir[9:6],ir[3:0]}
+ ED_LDs6NN7_REG = 6'b01__0011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
+ ED_LDsREG_6NN7 = 6'b01__1011, // compair with {ir[9:6],ir[3:0]} REG = BC,DE,HL,SP
+ ED_NEG = 5'b01___100, // compair with {ir[9:6],ir[2:0]} all A<= -A
+ ED_RETN = 5'b01___101, // compair with {ir[9:6],ir[2:0]} and !reti
+
+ DBL_REG_BC = 2'b00, // compair with ir[5:4]
+ DBL_REG_DE = 2'b00, // compair with ir[5:4]
+ DBL_REG_HL = 2'b00, // compair with ir[5:4]
+ DBL_REG_SP = 2'b00, // compair with ir[5:4]
+
+ REG8_B = 3'b000,
+ REG8_C = 3'b001,
+ REG8_D = 3'b010,
+ REG8_E = 3'b011,
+ REG8_H = 3'b100,
+ REG8_L = 3'b101,
+ REG8_A = 3'b110,
+ REG8_A = 3'b111;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
Index: tags/arelease/work.tws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/arelease/work.tws
===================================================================
--- tags/arelease/work.tws (nonexistent)
+++ tags/arelease/work.tws (revision 3)
tags/arelease/work.tws
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property