OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 49 to Rev 50
    ↔ Reverse comparison
  •

Rev 49 → Rev 50

/opencpu32/trunk/hdl/opencpu32/opencpu32.xise
71,7 → 71,7
</file>
<file xil_pn:name="ControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testControlUnit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
85,7 → 85,7
</file>
<file xil_pn:name="openCpu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testOpenCpu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
203,9 → 203,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|openCpu|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="openCpu.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/openCpu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DataPath|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="DataPath.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/openCpu/uDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
263,7 → 263,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="openCpu" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="DataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
275,10 → 275,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="openCpu_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="openCpu_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="openCpu_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="openCpu_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="DataPath_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="DataPath_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="DataPath_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="DataPath_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
298,7 → 298,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="openCpu" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="DataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
/opencpu32/trunk/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/testControlUnit.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/Alu.vhd&quot; into library work</arg>
</msg>
 
</messages>
/opencpu32/trunk/hdl/opencpu32/pkgOpenCPU32.vhd
14,7 → 14,8
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
 
package pkgOpenCPU32 is
 
25,7 → 26,7
--! Number of general registers (r0..r15)
constant numGenRegs : integer := 16;
 
type aluOps is (alu_pass, alu_passB, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and,
type aluOps is (alu_pass, alu_passB, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_udiv, alu_or, alu_and,
alu_xor, alu_not, alu_shfLt, alu_shfRt, alu_roLt, alu_roRt);
type typeEnDis is (enable, disable);
type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
44,6 → 45,7
function muxPos( a: dpMuxInputs) return std_logic_vector;
function muxRegPos(a: dpMuxAluIn) return std_logic_vector;
function opcode2AluOp (opcode : std_logic_vector(5 downto 0)) return aluOps;
function udivision(dividend: unsigned; divisor: unsigned) return unsigned;
 
-- Opcodes
subtype opcodes is std_logic_vector(5 downto 0); -- 6 Bits (64 instructions max)
192,6 → 194,34
when others => valRet := alu_pass;
end case;
return valRet;
end opcode2AluOp;
end opcode2AluOp;
 
-- Code based on Restoring division algorithm
-- http://vhdlguru.blogspot.com.br/2010/03/vhdl-function-for-division-two-signed.html
-- http://en.wikipedia.org/wiki/Division_%28digital%29
function udivision(dividend: unsigned; divisor: unsigned) return unsigned is
variable a1 : unsigned(dividend'length-1 downto 0);
variable b1 : unsigned(divisor'length-1 downto 0);
variable p1 : unsigned(divisor'length downto 0);
variable i : integer;
begin
a1 := dividend;
b1 := divisor;
p1 := (others => '0');
i := 0;
for i in 0 to divisor'length-1 loop
p1(divisor'length-1 downto 1) := p1(divisor'length-2 downto 0);
p1(0) := a1(dividend'length-1);
a1(dividend'length-1 downto 1) := a1(dividend'length-2 downto 0);
p1 := p1-b1;
if(p1(divisor'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end;
 
end pkgOpenCPU32;
/opencpu32/trunk/hdl/opencpu32/opencpu32.gise
68,17 → 68,14
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="ControlUnit.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="ControlUnit.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="ControlUnit.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="ControlUnit.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="ControlUnit.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="ControlUnit.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ControlUnit.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="ControlUnit.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="ControlUnit.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="ControlUnit.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="ControlUnit.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="ControlUnit.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="ControlUnit.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="ControlUnit.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="ControlUnit.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="ControlUnit_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="ControlUnit_guide.ncd" xil_pn:origination="imported"/>
86,14 → 83,9
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ControlUnit_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="ControlUnit_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="ControlUnit_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ControlUnit_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ControlUnit_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="ControlUnit_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="ControlUnit_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ControlUnit_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="ControlUnit_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="ControlUnit_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="ControlUnit_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ControlUnit_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="ControlUnit_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="DataPath.bld"/>
258,6 → 250,10
<transform xil_pn:end_ts="1334761313" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334761313">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="ControlUnit.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
286,10 → 282,16
<transform xil_pn:end_ts="1334733522" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1334733522">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1334761313" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334761313">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="ControlUnit.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
310,7 → 312,10
<transform xil_pn:end_ts="1334761330" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2461943258679370096" xil_pn:start_ts="1334761328">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
322,6 → 327,9
<transform xil_pn:end_ts="1334761330" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5135146925621150594" xil_pn:start_ts="1334761330">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testControlUnit_isim_beh.wdb"/>
330,59 → 338,99
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6268642977942111103" xil_pn:start_ts="1334733483">
<transform xil_pn:end_ts="1334825135" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1242172528803053708" xil_pn:start_ts="1334825135">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1334733483">
<transform xil_pn:end_ts="1334825135" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1334825135">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1334733483">
<transform xil_pn:end_ts="1334825135" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1334825135">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5126426351813824259" xil_pn:start_ts="1334733483">
<transform xil_pn:end_ts="1334825135" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5860233878951780918" xil_pn:start_ts="1334825135">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1334733483">
<transform xil_pn:end_ts="1334825135" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1334825135">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733483" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4767545221551224753" xil_pn:start_ts="1334733483">
<transform xil_pn:end_ts="1334825135" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-154095565103849252" xil_pn:start_ts="1334825135">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334733498" xil_pn:in_ck="-3059529097558291903" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-1259764691931299582" xil_pn:start_ts="1334733483">
<transform xil_pn:end_ts="1334825162" xil_pn:in_ck="-3059529097558291903" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="924943614754068847" xil_pn:start_ts="1334825135">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="ControlUnit.ngr"/>
<outfile xil_pn:name="DataPath.lso"/>
<outfile xil_pn:name="DataPath.ngc"/>
<outfile xil_pn:name="DataPath.ngr"/>
<outfile xil_pn:name="DataPath.prj"/>
<outfile xil_pn:name="DataPath.stx"/>
<outfile xil_pn:name="DataPath.syr"/>
<outfile xil_pn:name="DataPath.xst"/>
<outfile xil_pn:name="DataPath_xst.xrpt"/>
<outfile xil_pn:name="Multiplexer4_1.ngr"/>
<outfile xil_pn:name="RegisterFile.ngr"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="openCpu.lso"/>
<outfile xil_pn:name="openCpu.ngc"/>
<outfile xil_pn:name="openCpu.ngr"/>
<outfile xil_pn:name="openCpu.prj"/>
<outfile xil_pn:name="openCpu.stx"/>
<outfile xil_pn:name="openCpu.syr"/>
<outfile xil_pn:name="openCpu.xst"/>
<outfile xil_pn:name="openCpu_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1334733392" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-8790877965723852007" xil_pn:start_ts="1334733392">
<transform xil_pn:end_ts="1334825306" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="2103587220659863231" xil_pn:start_ts="1334825306">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1334825313" xil_pn:in_ck="-4000809658825063697" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-6459960163180547905" xil_pn:start_ts="1334825306">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="DataPath.bld"/>
<outfile xil_pn:name="DataPath.ngd"/>
<outfile xil_pn:name="DataPath_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1334825323" xil_pn:in_ck="359233437846204431" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1334825313">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="DataPath.pcf"/>
<outfile xil_pn:name="DataPath_map.map"/>
<outfile xil_pn:name="DataPath_map.mrp"/>
<outfile xil_pn:name="DataPath_map.ncd"/>
<outfile xil_pn:name="DataPath_map.ngm"/>
<outfile xil_pn:name="DataPath_map.xrpt"/>
<outfile xil_pn:name="DataPath_summary.xml"/>
<outfile xil_pn:name="DataPath_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1334825390" xil_pn:in_ck="2369703833567262892" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1334825323">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="DataPath.ncd"/>
<outfile xil_pn:name="DataPath.pad"/>
<outfile xil_pn:name="DataPath.par"/>
<outfile xil_pn:name="DataPath.ptwx"/>
<outfile xil_pn:name="DataPath.unroutes"/>
<outfile xil_pn:name="DataPath.xpi"/>
<outfile xil_pn:name="DataPath_pad.csv"/>
<outfile xil_pn:name="DataPath_pad.txt"/>
<outfile xil_pn:name="DataPath_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1334825390" xil_pn:in_ck="9198110386719829755" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1334825380">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="DataPath.twr"/>
<outfile xil_pn:name="DataPath.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform>
</transforms>
 
</generated_project>

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