OpenCores
URL https://opencores.org/ocsvn/openjtag-project/openjtag-project/trunk

Subversion Repositories openjtag-project

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  • This comparison shows the changes necessary to convert path 
    /openjtag-project
    from Rev 17 to Rev 18
    ↔ Reverse comparison
  •

Rev 17 → Rev 18

/trunk/.project
0,0 → 1,11
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>OpenJTAG</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
</buildSpec>
<natures>
</natures>
</projectDescription>
/trunk/OpenJTAG/Quartus_II/Open_JTAG.qws
0,0 → 1,14
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=Open_JTAG.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=True
ptn_Child1=StateMap
/trunk/OpenJTAG/Quartus_II/Open_JTAG.flow.rpt
0,0 → 1,114
Flow report for Open_JTAG
Wed Jun 02 16:01:15 2010
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
 
 
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
 
 
 
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
 
 
 
+------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------+----------------------------------------------+
; Flow Status ; Successful - Wed Jun 02 16:01:15 2010 ;
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name ; Open_JTAG ;
; Top-level Entity Name ; Open_JTAG ;
; Family ; MAX II ;
; Device ; EPM570T100C5 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 245 / 570 ( 43 % ) ;
; Total pins ; 29 / 76 ( 38 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-------------------------+----------------------------------------------+
 
 
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 06/02/2010 16:01:02 ;
; Main task ; Compilation ;
; Revision Name ; Open_JTAG ;
+-------------------+---------------------+
 
 
+--------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+-----------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+-----------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 95639322573.127548726201860 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+---------------------------------------+-----------------------------+---------------+-------------+----------------+
 
 
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 187 MB ; 00:00:04 ;
; Fitter ; 00:00:03 ; 1.0 ; 155 MB ; 00:00:01 ;
; Assembler ; 00:00:01 ; 1.0 ; 142 MB ; 00:00:00 ;
; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 113 MB ; 00:00:01 ;
; Total ; 00:00:10 ; -- ; -- ; 00:00:06 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
+---------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; vaffanculo ; Windows XP ; 5.1 ; i686 ;
; Fitter ; vaffanculo ; Windows XP ; 5.1 ; i686 ;
; Assembler ; vaffanculo ; Windows XP ; 5.1 ; i686 ;
; Classic Timing Analyzer ; vaffanculo ; Windows XP ; 5.1 ; i686 ;
+-------------------------+------------------+------------+------------+----------------+
 
 
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off Open_JTAG -c Open_JTAG
quartus_fit --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG
quartus_asm --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG
quartus_tan --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG
 
 
 
/trunk/OpenJTAG/Quartus_II/serializer.bsf
0,0 → 1,148
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 160 240)
(text "serializer" (rect 5 0 47 12)(font "Arial" ))
(text "inst" (rect 8 208 25 220)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clk" (rect 0 0 14 12)(font "Arial" ))
(text "clk" (rect 21 27 35 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "txe" (rect 0 0 15 12)(font "Arial" ))
(text "txe" (rect 21 43 36 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "rxf" (rect 0 0 14 12)(font "Arial" ))
(text "rxf" (rect 21 59 35 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "pwr" (rect 0 0 16 12)(font "Arial" ))
(text "pwr" (rect 21 75 37 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "rst" (rect 0 0 12 12)(font "Arial" ))
(text "rst" (rect 21 91 33 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "wrk" (rect 0 0 16 12)(font "Arial" ))
(text "wrk" (rect 21 107 37 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 1))
)
(port
(pt 0 128)
(input)
(text "tdo" (rect 0 0 15 12)(font "Arial" ))
(text "tdo" (rect 21 123 36 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 1))
)
(port
(pt 144 32)
(output)
(text "wr" (rect 0 0 10 12)(font "Arial" ))
(text "wr" (rect 113 27 123 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "rd" (rect 0 0 9 12)(font "Arial" ))
(text "rd" (rect 114 43 123 55)(font "Arial" ))
(line (pt 144 48)(pt 128 48)(line_width 1))
)
(port
(pt 144 64)
(output)
(text "siwu" (rect 0 0 21 12)(font "Arial" ))
(text "siwu" (rect 102 59 123 71)(font "Arial" ))
(line (pt 144 64)(pt 128 64)(line_width 1))
)
(port
(pt 144 96)
(output)
(text "tck" (rect 0 0 15 12)(font "Arial" ))
(text "tck" (rect 108 91 123 103)(font "Arial" ))
(line (pt 144 96)(pt 128 96)(line_width 1))
)
(port
(pt 144 112)
(output)
(text "tms" (rect 0 0 18 12)(font "Arial" ))
(text "tms" (rect 105 107 123 119)(font "Arial" ))
(line (pt 144 112)(pt 128 112)(line_width 1))
)
(port
(pt 144 128)
(output)
(text "tdi" (rect 0 0 11 12)(font "Arial" ))
(text "tdi" (rect 112 123 123 135)(font "Arial" ))
(line (pt 144 128)(pt 128 128)(line_width 1))
)
(port
(pt 144 144)
(output)
(text "trst" (rect 0 0 16 12)(font "Arial" ))
(text "trst" (rect 107 139 123 151)(font "Arial" ))
(line (pt 144 144)(pt 128 144)(line_width 1))
)
(port
(pt 144 160)
(output)
(text "new_state[3..0]" (rect 0 0 75 12)(font "Arial" ))
(text "new_state[3..0]" (rect 48 155 123 167)(font "Arial" ))
(line (pt 144 160)(pt 128 160)(line_width 3))
)
(port
(pt 144 176)
(output)
(text "cks[2..0]" (rect 0 0 43 12)(font "Arial" ))
(text "cks[2..0]" (rect 80 171 123 183)(font "Arial" ))
(line (pt 144 176)(pt 128 176)(line_width 3))
)
(port
(pt 144 80)
(bidir)
(text "db[7..0]" (rect 0 0 37 12)(font "Arial" ))
(text "db[7..0]" (rect 86 75 123 87)(font "Arial" ))
(line (pt 144 80)(pt 128 80)(line_width 3))
)
(drawing
(rectangle (rect 16 16 128 208)(line_width 1))
)
)
/trunk/OpenJTAG/Quartus_II/Open_JTAG.fit.summary
0,0 → 1,11
Fitter Status : Successful - Wed Jun 02 16:01:11 2010
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : Open_JTAG
Top-level Entity Name : Open_JTAG
Family : MAX II
Device : EPM570T100C5
Timing Models : Final
Total logic elements : 245 / 570 ( 43 % )
Total pins : 29 / 76 ( 38 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )
/trunk/OpenJTAG/Quartus_II/Open_JTAG.tan.summary
0,0 → 1,56
--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
 
Type : Worst-case tsu
Slack : N/A
Required Time : None
Actual Time : 1.440 ns
From : txe
To : serializer:inst2|ssm[2]
From Clock : --
To Clock : clk
Failed Paths : 0
 
Type : Worst-case tco
Slack : N/A
Required Time : None
Actual Time : 15.899 ns
From : tap_sm:inst|tms
To : tms
From Clock : clk
To Clock : --
Failed Paths : 0
 
Type : Worst-case th
Slack : N/A
Required Time : None
Actual Time : 4.193 ns
From : db[6]
To : serializer:inst2|rbyte[6]
From Clock : --
To Clock : clk
Failed Paths : 0
 
Type : Clock Setup: 'clk'
Slack : N/A
Required Time : None
Actual Time : 78.31 MHz ( period = 12.770 ns )
From : serializer:inst2|cks[0]
To : clock_mux:inst1|wcks
From Clock : clk
To Clock : clk
Failed Paths : 0
 
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
 
--------------------------------------------------------------------------------------
 
/trunk/OpenJTAG/Quartus_II/tap_sm.vwf
0,0 → 1,477
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
 
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
 
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 4000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 100.0;
GRID_DUTY_CYCLE = 50;
}
 
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("tck")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
 
SIGNAL("tms")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
 
SIGNAL("rst")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("new_state")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("new_state[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "new_state";
}
 
SIGNAL("new_state[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "new_state";
}
 
SIGNAL("new_state[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "new_state";
}
 
SIGNAL("new_state[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "new_state";
}
 
SIGNAL("sm")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
 
SIGNAL("sm[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "sm";
}
 
SIGNAL("sm[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "sm";
}
 
SIGNAL("sm[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "sm";
}
 
SIGNAL("sm[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "sm";
}
 
SIGNAL("wrk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
 
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 200;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}
 
TRANSITION_LIST("tck")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 4000.0;
}
}
 
TRANSITION_LIST("tms")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 4000.0;
}
}
 
TRANSITION_LIST("rst")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 4000.0;
}
}
 
TRANSITION_LIST("new_state[3]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 35.6;
LEVEL 1 FOR 3964.4;
}
}
}
 
TRANSITION_LIST("new_state[2]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 35.6;
LEVEL 1 FOR 3964.4;
}
}
}
 
TRANSITION_LIST("new_state[1]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 35.6;
LEVEL 1 FOR 3964.4;
}
}
}
 
TRANSITION_LIST("new_state[0]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 35.6;
LEVEL 1 FOR 3964.4;
}
}
}
 
TRANSITION_LIST("sm[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 4000.0;
}
}
 
TRANSITION_LIST("sm[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 4000.0;
}
}
 
TRANSITION_LIST("sm[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 4000.0;
}
}
 
TRANSITION_LIST("sm[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 4000.0;
}
}
 
TRANSITION_LIST("wrk")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 4000.0;
}
}
 
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "tck";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "tms";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "rst";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "wrk";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "new_state";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 5;
TREE_LEVEL = 0;
CHILDREN = 6, 7, 8, 9;
}
 
DISPLAY_LINE
{
CHANNEL = "new_state[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 5;
}
 
DISPLAY_LINE
{
CHANNEL = "new_state[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 5;
}
 
DISPLAY_LINE
{
CHANNEL = "new_state[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 5;
}
 
DISPLAY_LINE
{
CHANNEL = "new_state[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 9;
TREE_LEVEL = 1;
PARENT = 5;
}
 
DISPLAY_LINE
{
CHANNEL = "sm";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 10;
TREE_LEVEL = 0;
CHILDREN = 11, 12, 13, 14;
}
 
DISPLAY_LINE
{
CHANNEL = "sm[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 11;
TREE_LEVEL = 1;
PARENT = 10;
}
 
DISPLAY_LINE
{
CHANNEL = "sm[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 12;
TREE_LEVEL = 1;
PARENT = 10;
}
 
DISPLAY_LINE
{
CHANNEL = "sm[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 13;
TREE_LEVEL = 1;
PARENT = 10;
}
 
DISPLAY_LINE
{
CHANNEL = "sm[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 14;
TREE_LEVEL = 1;
PARENT = 10;
}
 
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;
/trunk/OpenJTAG/Quartus_II/Main.vwf
0,0 → 1,249
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
 
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
 
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 4.0us\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1\
print_row_height 100";
DATA_OFFSET = 0.0;
DATA_DURATION = 4000.0;
SIMULATION_TIME = 4000.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 100.0;
GRID_DUTY_CYCLE = 50;
}
 
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("wcks")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
 
SIGNAL("cks")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("cks[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "cks";
}
 
SIGNAL("cks[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "cks";
}
 
SIGNAL("cks[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "cks";
}
 
SIGNAL("cks[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "cks";
}
 
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 200;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}
 
TRANSITION_LIST("wcks")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 4000.0;
}
}
 
TRANSITION_LIST("cks[2]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4000.0;
}
}
 
TRANSITION_LIST("cks[1]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 4000.0;
}
}
 
TRANSITION_LIST("cks[0]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 4000.0;
}
}
 
TRANSITION_LIST("cks[3]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 4000.0;
}
}
 
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "wcks";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "cks";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 2;
TREE_LEVEL = 0;
CHILDREN = 3, 4, 5, 6;
}
 
DISPLAY_LINE
{
CHANNEL = "cks[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 2;
}
 
DISPLAY_LINE
{
CHANNEL = "cks[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 2;
}
 
DISPLAY_LINE
{
CHANNEL = "cks[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 2;
}
 
DISPLAY_LINE
{
CHANNEL = "cks[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Hexadecimal;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 2;
}
 
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;
/trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cbx.xml
0,0 → 1,5
<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="Open_JTAG">
</PROJECT>
</LOG_ROOT>
/trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.kpt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.kpt
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.hdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.hdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.hdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(1).cnf.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.qmsg =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.qmsg (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.qmsg (revision 18) @@ -0,0 +1,15 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 02 16:01:02 2010 " "Info: Processing started: Wed Jun 02 16:01:02 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Open_JTAG -c Open_JTAG " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Open_JTAG -c Open_JTAG" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tap_sm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tap_sm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tap_sm-rtl " "Info: Found design unit 1: tap_sm-rtl" { } { { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 29 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 tap_sm " "Info: Found entity 1: tap_sm" { } { { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 8 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_mux.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock_mux.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock_mux-rtl " "Info: Found design unit 1: clock_mux-rtl" { } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 21 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 clock_mux " "Info: Found entity 1: clock_mux" { } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 8 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serializer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file serializer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serializer-rtl " "Info: Found design unit 1: serializer-rtl" { } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 45 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 serializer " "Info: Found entity 1: serializer" { } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 8 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "open_jtag.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file open_jtag.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Open_JTAG " "Info: Found entity 1: Open_JTAG" { } { { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "Open_JTAG " "Info: Elaborating entity \"Open_JTAG\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tap_sm tap_sm:inst " "Info: Elaborating entity \"tap_sm\" for hierarchy \"tap_sm:inst\"" { } { { "Open_JTAG.bdf" "inst" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { -24 312 480 104 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_mux clock_mux:inst1 " "Info: Elaborating entity \"clock_mux\" for hierarchy \"clock_mux:inst1\"" { } { { "Open_JTAG.bdf" "inst1" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 536 552 672 632 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "serializer serializer:inst2 " "Info: Elaborating entity \"serializer\" for hierarchy \"serializer:inst2\"" { } { { "Open_JTAG.bdf" "inst2" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 264 288 432 488 "inst2" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1} +{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "siwu serializer.vhd(25) " "Warning (10540): VHDL Signal Declaration warning at serializer.vhd(25): used explicit default value for signal \"siwu\" because signal was never assigned a value" { } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 25 0 0 } } } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rst " "Warning (15610): No output dependent on input pin \"rst\"" { } { { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 16 48 216 32 "rst" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "286 " "Info: Implemented 286 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" { } { } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "257 " "Info: Implemented 257 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "187 " "Info: Peak virtual memory: 187 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 02 16:01:07 2010 " "Info: Processing ended: Wed Jun 02 16:01:07 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.hdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.hdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.hdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(3).cnf.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.rdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.rdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.rdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.rdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.syn_hier_info =================================================================== Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.eco.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.eco.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.eco.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.eco.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.eco.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.db_info =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.db_info (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.db_info (revision 18) @@ -0,0 +1,3 @@ +Quartus_Version = Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +Version_Index = 184638978 +Creation_Time = Wed Jun 02 15:56:20 2010 Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.smart_action.txt =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.smart_action.txt (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.smart_action.txt (revision 18) @@ -0,0 +1 @@ +DONE Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry_dsc.sci =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry_dsc.sci =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry_dsc.sci (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry_dsc.sci (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry_dsc.sci Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.hier_info =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.hier_info (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.hier_info (revision 18) @@ -0,0 +1,236 @@ +|Open_JTAG +tms <= inst4.DB_MAX_OUTPUT_PORT_TYPE +clk => clock_mux:inst1.clk +txe => serializer:inst2.txe +rxf => serializer:inst2.rxf +rst => serializer:inst2.rst +rst => tap_sm:inst.rst +tdo => serializer:inst2.tdo +db[0] <> serializer:inst2.db[0] +db[1] <> serializer:inst2.db[1] +db[2] <> serializer:inst2.db[2] +db[3] <> serializer:inst2.db[3] +db[4] <> serializer:inst2.db[4] +db[5] <> serializer:inst2.db[5] +db[6] <> serializer:inst2.db[6] +db[7] <> serializer:inst2.db[7] +tck <= inst3.DB_MAX_OUTPUT_PORT_TYPE +wrk <= tap_sm:inst.wrk +wr <= serializer:inst2.wr +rd <= serializer:inst2.rd +tdi <= serializer:inst2.tdi +trst <= serializer:inst2.trst +wcks <= clock_mux:inst1.wcks +new_state[0] <= serializer:inst2.new_state[0] +new_state[1] <= serializer:inst2.new_state[1] +new_state[2] <= serializer:inst2.new_state[2] +new_state[3] <= serializer:inst2.new_state[3] +sm[0] <= tap_sm:inst.sm[0] +sm[1] <= tap_sm:inst.sm[1] +sm[2] <= tap_sm:inst.sm[2] +sm[3] <= tap_sm:inst.sm[3] + + +|Open_JTAG|tap_sm:inst +clk => state[0].CLK +clk => state[1].CLK +clk => state[2].CLK +clk => state[3].CLK +clk => tck~reg0.CLK +clk => tms~reg0.CLK +clk => wrk~reg0.CLK +clk => sm[0]~reg0.CLK +clk => sm[1]~reg0.CLK +clk => sm[2]~reg0.CLK +clk => sm[3]~reg0.CLK +clk => astate[0].CLK +clk => astate[1].CLK +clk => astate[2].CLK +clk => astate[3].CLK +clk => rclk.CLK +rst => ~NO_FANOUT~ +new_state[0] => astate[0].DATAIN +new_state[1] => astate[1].DATAIN +new_state[2] => astate[2].DATAIN +new_state[3] => astate[3].DATAIN +tck <= tck~reg0.DB_MAX_OUTPUT_PORT_TYPE +tms <= tms~reg0.DB_MAX_OUTPUT_PORT_TYPE +wrk <= wrk~reg0.DB_MAX_OUTPUT_PORT_TYPE +sm[0] <= sm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sm[1] <= sm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sm[2] <= sm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sm[3] <= sm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|Open_JTAG|clock_mux:inst1 +clk => count[0].CLK +clk => count[1].CLK +clk => count[2].CLK +clk => count[3].CLK +clk => count[4].CLK +clk => count[5].CLK +clk => count[6].CLK +clk => cclk[0].CLK +clk => cclk[1].CLK +clk => cclk[2].CLK +clk => cclk[3].CLK +clk => cclk[4].CLK +clk => cclk[5].CLK +clk => cclk[6].CLK +clk => wcks~reg0.CLK +clk => wcks~reg0.ADATA +cks[0] => Add0.IN6 +cks[0] => Equal0.IN2 +cks[1] => Add0.IN5 +cks[1] => Equal0.IN1 +cks[2] => Add0.IN4 +cks[2] => Equal0.IN0 +wcks <= wcks~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|Open_JTAG|serializer:inst2 +clk => trst~reg0.CLK +clk => state[0].CLK +clk => state[1].CLK +clk => state[2].CLK +clk => state[3].CLK +clk => wr~reg0.CLK +clk => shift[0].CLK +clk => shift[1].CLK +clk => shift[2].CLK +clk => shift[3].CLK +clk => shift[4].CLK +clk => shift[5].CLK +clk => shift[6].CLK +clk => shift[7].CLK +clk => instr.CLK +clk => rtms.CLK +clk => sclk.CLK +clk => dir.CLK +clk => count[0].CLK +clk => count[1].CLK +clk => count[2].CLK +clk => count[3].CLK +clk => new_state[0]~reg0.CLK +clk => new_state[1]~reg0.CLK +clk => new_state[2]~reg0.CLK +clk => new_state[3]~reg0.CLK +clk => cks[0]~reg0.CLK +clk => cks[1]~reg0.CLK +clk => cks[2]~reg0.CLK +clk => db[0]~reg0.CLK +clk => db[0]~en.CLK +clk => db[1]~reg0.CLK +clk => db[1]~en.CLK +clk => db[2]~reg0.CLK +clk => db[2]~en.CLK +clk => db[3]~reg0.CLK +clk => db[3]~en.CLK +clk => db[4]~reg0.CLK +clk => db[4]~en.CLK +clk => db[5]~reg0.CLK +clk => db[5]~en.CLK +clk => db[6]~reg0.CLK +clk => db[6]~en.CLK +clk => db[7]~reg0.CLK +clk => db[7]~en.CLK +clk => rbyte[0].CLK +clk => rbyte[1].CLK +clk => rbyte[2].CLK +clk => rbyte[3].CLK +clk => rbyte[4].CLK +clk => rbyte[5].CLK +clk => rbyte[6].CLK +clk => rbyte[7].CLK +clk => ssm[0].CLK +clk => ssm[1].CLK +clk => ssm[2].CLK +clk => ssm[3].CLK +clk => rd~reg0.CLK +clk => tdi~reg0.CLK +clk => tms~reg0.CLK +clk => tck~reg0.CLK +txe => ssm.OUTPUTSELECT +txe => ssm.OUTPUTSELECT +txe => ssm.OUTPUTSELECT +txe => ssm.OUTPUTSELECT +txe => Mux78.IN15 +rxf => rd.OUTPUTSELECT +rxf => ssm.OUTPUTSELECT +rxf => ssm.OUTPUTSELECT +rxf => ssm.OUTPUTSELECT +rxf => ssm.OUTPUTSELECT +pwr => ~NO_FANOUT~ +rst => ~NO_FANOUT~ +wrk => db[7].IN1 +wrk => state[0].ENA +wrk => trst~reg0.ENA +wrk => rbyte[0].ENA +wrk => state[1].ENA +wrk => state[2].ENA +wrk => state[3].ENA +wrk => wr~reg0.ENA +wrk => shift[0].ENA +wrk => shift[1].ENA +wrk => shift[2].ENA +wrk => shift[3].ENA +wrk => shift[4].ENA +wrk => shift[5].ENA +wrk => shift[6].ENA +wrk => shift[7].ENA +wrk => instr.ENA +wrk => rtms.ENA +wrk => sclk.ENA +wrk => dir.ENA +wrk => count[0].ENA +wrk => count[1].ENA +wrk => count[2].ENA +wrk => count[3].ENA +wrk => new_state[0]~reg0.ENA +wrk => new_state[1]~reg0.ENA +wrk => new_state[2]~reg0.ENA +wrk => new_state[3]~reg0.ENA +wrk => cks[0]~reg0.ENA +wrk => cks[1]~reg0.ENA +wrk => cks[2]~reg0.ENA +wrk => rbyte[1].ENA +wrk => rbyte[2].ENA +wrk => rbyte[3].ENA +wrk => rbyte[4].ENA +wrk => rbyte[5].ENA +wrk => rbyte[6].ENA +wrk => rbyte[7].ENA +wrk => ssm[0].ENA +wrk => ssm[1].ENA +wrk => ssm[2].ENA +wrk => ssm[3].ENA +wrk => rd~reg0.ENA +wrk => tdi~reg0.ENA +wrk => tms~reg0.ENA +wrk => tck~reg0.ENA +wr <= wr~reg0.DB_MAX_OUTPUT_PORT_TYPE +rd <= rd~reg0.DB_MAX_OUTPUT_PORT_TYPE +siwu <= +db[0] <> db[0] +db[1] <> db[1] +db[2] <> db[2] +db[3] <> db[3] +db[4] <> db[4] +db[5] <> db[5] +db[6] <> db[6] +db[7] <> db[7] +tdo => shift.DATAB +tdo => shift.DATAA +tck <= tck~reg0.DB_MAX_OUTPUT_PORT_TYPE +tms <= tms~reg0.DB_MAX_OUTPUT_PORT_TYPE +tdi <= tdi~reg0.DB_MAX_OUTPUT_PORT_TYPE +trst <= trst~reg0.DB_MAX_OUTPUT_PORT_TYPE +new_state[0] <= new_state[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +new_state[1] <= new_state[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +new_state[2] <= new_state[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +new_state[3] <= new_state[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cks[0] <= cks[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cks[1] <= cks[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cks[2] <= cks[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.logdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.logdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.logdb (revision 18) @@ -0,0 +1 @@ +v1 Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.logdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.logdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.logdb (revision 18) @@ -0,0 +1 @@ +v1 Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.hdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.hdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.hdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.map.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm_labs.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm_labs.ddb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm_labs.ddb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm_labs.ddb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm_labs.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.hdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.hdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.hdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/logic_util_heursitic.dat =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/logic_util_heursitic.dat =================================================================== --- trunk/OpenJTAG/Quartus_II/db/logic_util_heursitic.dat (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/logic_util_heursitic.dat (revision 18)
trunk/OpenJTAG/Quartus_II/db/logic_util_heursitic.dat Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.hdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.hdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.hdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.pre_map.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.hdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.hdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.hdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(0).cnf.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.html =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.html (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.html (revision 18) @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
inst261111411180000
inst14000100000000
inst6010700000000
Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tmw_info =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tmw_info (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tmw_info (revision 18) @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:16 +start_analysis_synthesis:s:00:00:08-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:03-start_full_compilation +start_assembler:s:00:00:03-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv.hdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv.hdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv.hdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.hdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.hdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.hdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.(2).cnf.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.rdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.rdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.rdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.rdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm.qmsg =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm.qmsg (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm.qmsg (revision 18) @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 02 16:01:12 2010 " "Info: Processing started: Wed Jun 02 16:01:12 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "142 " "Info: Peak virtual memory: 142 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 02 16:01:13 2010 " "Info: Processing ended: Wed Jun 02 16:01:13 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm.rdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm.rdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm.rdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.asm.rdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp0.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp0.ddb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp0.ddb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp0.ddb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp0.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.tdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.tdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.tdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.tdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.cmp.tdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tis_db_list.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tis_db_list.ddb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tis_db_list.ddb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tis_db_list.ddb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tis_db_list.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.fit.qmsg =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.fit.qmsg (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.fit.qmsg (revision 18) @@ -0,0 +1,40 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 02 16:01:08 2010 " "Info: Processing started: Wed Jun 02 16:01:08 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "Open_JTAG EPM570T100C5 " "Info: Selected device EPM570T100C5 for design \"Open_JTAG\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." { } { } 0 0 "Feature %1!s! is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100C5 " "Info: Device EPM240T100C5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Info: Device EPM240T100I5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Info: Device EPM240T100A5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Info: Device EPM570T100I5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Info: Device EPM570T100A5 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "29 29 " "Critical Warning: No exact pin location assignment(s) for 29 pins of 29 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "tms " "Info: Pin tms not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { tms } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 216 680 856 232 "tms" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tms } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 299 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst " "Info: Pin rst not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { rst } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 16 48 216 32 "rst" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 304 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "tck " "Info: Pin tck not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { tck } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 168 680 856 184 "tck" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tck } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 306 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "wrk " "Info: Pin wrk not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { wrk } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 32 680 856 48 "wrk" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { wrk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 308 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "wr " "Info: Pin wr not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { wr } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 288 680 856 304 "wr" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 309 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rd " "Info: Pin rd not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { rd } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 304 680 856 320 "rd" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 310 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "tdi " "Info: Pin tdi not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { tdi } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 384 680 856 400 "tdi" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tdi } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 311 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "trst " "Info: Pin trst not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { trst } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 400 680 856 416 "trst" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { trst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 312 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "wcks " "Info: Pin wcks not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { wcks } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 712 888 576 "wcks" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { wcks } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 313 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "new_state\[3\] " "Info: Pin new_state\[3\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { new_state[3] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 416 680 856 432 "new_state\[3..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { new_state[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 291 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "new_state\[2\] " "Info: Pin new_state\[2\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { new_state[2] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 416 680 856 432 "new_state\[3..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { new_state[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 292 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "new_state\[1\] " "Info: Pin new_state\[1\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { new_state[1] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 416 680 856 432 "new_state\[3..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { new_state[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 293 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "new_state\[0\] " "Info: Pin new_state\[0\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { new_state[0] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 416 680 856 432 "new_state\[3..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { new_state[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 294 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sm\[3\] " "Info: Pin sm\[3\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { sm[3] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 48 680 856 64 "sm\[3..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sm[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 295 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sm\[2\] " "Info: Pin sm\[2\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { sm[2] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 48 680 856 64 "sm\[3..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sm[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 296 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sm\[1\] " "Info: Pin sm\[1\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { sm[1] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 48 680 856 64 "sm\[3..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sm[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 297 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sm\[0\] " "Info: Pin sm\[0\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { sm[0] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 48 680 856 64 "sm\[3..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sm[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 298 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "db\[7\] " "Info: Pin db\[7\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { db[7] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 283 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "db\[6\] " "Info: Pin db\[6\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { db[6] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 284 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "db\[5\] " "Info: Pin db\[5\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { db[5] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 285 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "db\[4\] " "Info: Pin db\[4\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { db[4] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 286 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "db\[3\] " "Info: Pin db\[3\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { db[3] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 287 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "db\[2\] " "Info: Pin db\[2\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { db[2] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 288 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "db\[1\] " "Info: Pin db\[1\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { db[1] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 289 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "db\[0\] " "Info: Pin db\[0\] not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { db[0] } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 290 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rxf " "Info: Pin rxf not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { rxf } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 320 48 216 336 "rxf" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { rxf } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 303 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { clk } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 301 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "txe " "Info: Pin txe not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { txe } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 304 48 216 320 "txe" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { txe } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 302 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "tdo " "Info: Pin tdo not assigned to an exact location on the device" { } { { "c:/altera/91sp2/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/91sp2/quartus/bin/pin_planner.ppl" { tdo } } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 384 48 216 400 "tdo" "" } } } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tdo } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/AlteraWorks/91/Open JTAG/" 0 { } { { 0 { 0 ""} 0 305 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} +{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} +{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} } { } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk Global clock in PIN 12 " "Info: Automatically promoted some destinations of signal \"clk\" to use Global clock in PIN 12" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock_mux:inst1\|wcks " "Info: Destination \"clock_mux:inst1\|wcks\" may be non-global or may not use global clock" { } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} } { { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } } } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clock_mux:inst1\|wcks Global clock " "Info: Automatically promoted some destinations of signal \"clock_mux:inst1\|wcks\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "wcks " "Info: Destination \"wcks\" may be non-global or may not use global clock" { } { { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 712 888 576 "wcks" "" } } } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" { } { } 1 0 "Moving registers into LUTs to improve timing and density" 0 0 "" 0 -1} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" { } { } 0 0 "Started processing fast register assignments" 0 0 "" 0 -1} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" { } { } 0 0 "Finished processing fast register assignments" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { } { } 0 0 "Finished register packing" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "28 unused 3.3V 4 16 8 " "Info: Number of I/O pins in group: 28 (unused VREF, 3.3V VCCIO, 4 input, 16 output, 8 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 35 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 40 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Info: Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.057 ns register pin " "Info: Estimated most critical path is register to pin delay of 6.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns serializer:inst2\|tms 1 REG LAB_X9_Y7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y7; Fanout = 3; REG Node = 'serializer:inst2\|tms'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { serializer:inst2|tms } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.620 ns) + CELL(0.740 ns) 1.360 ns inst4 2 COMB LAB_X9_Y7 1 " "Info: 2: + IC(0.620 ns) + CELL(0.740 ns) = 1.360 ns; Loc. = LAB_X9_Y7; Fanout = 1; COMB Node = 'inst4'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.360 ns" { serializer:inst2|tms inst4 } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 200 592 656 248 "inst4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.375 ns) + CELL(2.322 ns) 6.057 ns tms 3 PIN PIN_87 0 " "Info: 3: + IC(2.375 ns) + CELL(2.322 ns) = 6.057 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'tms'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.697 ns" { inst4 tms } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 216 680 856 232 "tms" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.062 ns ( 50.55 % ) " "Info: Total cell delay = 3.062 ns ( 50.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.995 ns ( 49.45 % ) " "Info: Total interconnect delay = 2.995 ns ( 49.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.057 ns" { serializer:inst2|tms inst4 tms } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "15 " "Info: Average interconnect usage is 15% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X0_Y0 X13_Y8 " "Info: Peak interconnect usage is 15% of the available device resources in the region that extends from location X0_Y0 to location X13_Y8" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "175 " "Info: Peak virtual memory: 175 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 02 16:01:11 2010 " "Info: Processing ended: Wed Jun 02 16:01:11 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tan.qmsg =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tan.qmsg (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.tan.qmsg (revision 18) @@ -0,0 +1,12 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 02 16:01:14 2010 " "Info: Processing started: Wed Jun 02 16:01:14 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} +{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock_mux:inst1\|wcks " "Info: Detected ripple clock \"clock_mux:inst1\|wcks\" as buffer" { } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock_mux:inst1\|wcks" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register serializer:inst2\|cks\[0\] register clock_mux:inst1\|wcks 78.31 MHz 12.77 ns Internal " "Info: Clock \"clk\" has Internal fmax of 78.31 MHz between source register \"serializer:inst2\|cks\[0\]\" and destination register \"clock_mux:inst1\|wcks\" (period= 12.77 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.481 ns + Longest register register " "Info: + Longest register to register delay is 6.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns serializer:inst2\|cks\[0\] 1 REG LC_X7_Y5_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y5_N5; Fanout = 5; REG Node = 'serializer:inst2\|cks\[0\]'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { serializer:inst2|cks[0] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.558 ns) + CELL(0.740 ns) 3.298 ns clock_mux:inst1\|Mux0~3 2 COMB LC_X9_Y5_N8 1 " "Info: 2: + IC(2.558 ns) + CELL(0.740 ns) = 3.298 ns; Loc. = LC_X9_Y5_N8; Fanout = 1; COMB Node = 'clock_mux:inst1\|Mux0~3'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.298 ns" { serializer:inst2|cks[0] clock_mux:inst1|Mux0~3 } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 3.803 ns clock_mux:inst1\|Mux0~4 3 COMB LC_X9_Y5_N9 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 3.803 ns; Loc. = LC_X9_Y5_N9; Fanout = 1; COMB Node = 'clock_mux:inst1\|Mux0~4'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { clock_mux:inst1|Mux0~3 clock_mux:inst1|Mux0~4 } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.200 ns) 4.732 ns clock_mux:inst1\|Mux0~2 4 COMB LC_X9_Y5_N7 1 " "Info: 4: + IC(0.729 ns) + CELL(0.200 ns) = 4.732 ns; Loc. = LC_X9_Y5_N7; Fanout = 1; COMB Node = 'clock_mux:inst1\|Mux0~2'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.929 ns" { clock_mux:inst1|Mux0~4 clock_mux:inst1|Mux0~2 } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.591 ns) 6.481 ns clock_mux:inst1\|wcks 5 REG LC_X8_Y5_N5 75 " "Info: 5: + IC(1.158 ns) + CELL(0.591 ns) = 6.481 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.749 ns" { clock_mux:inst1|Mux0~2 clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.731 ns ( 26.71 % ) " "Info: Total cell delay = 1.731 ns ( 26.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.750 ns ( 73.29 % ) " "Info: Total interconnect delay = 4.750 ns ( 73.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { serializer:inst2|cks[0] clock_mux:inst1|Mux0~3 clock_mux:inst1|Mux0~4 clock_mux:inst1|Mux0~2 clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "6.481 ns" { serializer:inst2|cks[0] {} clock_mux:inst1|Mux0~3 {} clock_mux:inst1|Mux0~4 {} clock_mux:inst1|Mux0~2 {} clock_mux:inst1|wcks {} } { 0.000ns 2.558ns 0.305ns 0.729ns 1.158ns } { 0.000ns 0.740ns 0.200ns 0.200ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.580 ns - Smallest " "Info: - Smallest clock skew is -5.580 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.261 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.918 ns) 9.261 ns serializer:inst2\|cks\[0\] 3 REG LC_X7_Y5_N5 5 " "Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X7_Y5_N5; Fanout = 5; REG Node = 'serializer:inst2\|cks\[0\]'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { clock_mux:inst1|wcks serializer:inst2|cks[0] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.44 % ) " "Info: Total cell delay = 3.375 ns ( 36.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.886 ns ( 63.56 % ) " "Info: Total interconnect delay = 5.886 ns ( 63.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|cks[0] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|cks[0] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|cks[0] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|cks[0] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { serializer:inst2|cks[0] clock_mux:inst1|Mux0~3 clock_mux:inst1|Mux0~4 clock_mux:inst1|Mux0~2 clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "6.481 ns" { serializer:inst2|cks[0] {} clock_mux:inst1|Mux0~3 {} clock_mux:inst1|Mux0~4 {} clock_mux:inst1|Mux0~2 {} clock_mux:inst1|wcks {} } { 0.000ns 2.558ns 0.305ns 0.729ns 1.158ns } { 0.000ns 0.740ns 0.200ns 0.200ns 0.591ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|cks[0] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|cks[0] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1} +{ "Info" "ITDB_TSU_RESULT" "serializer:inst2\|ssm\[2\] txe clk 1.440 ns register " "Info: tsu for register \"serializer:inst2\|ssm\[2\]\" (data pin = \"txe\", clock pin = \"clk\") is 1.440 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.368 ns + Longest pin register " "Info: + Longest pin to register delay is 10.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns txe 1 PIN PIN_38 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_38; Fanout = 3; PIN Node = 'txe'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { txe } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 304 48 216 320 "txe" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.540 ns) + CELL(0.200 ns) 5.872 ns serializer:inst2\|ssm\[2\]~0 2 COMB LC_X5_Y7_N9 1 " "Info: 2: + IC(4.540 ns) + CELL(0.200 ns) = 5.872 ns; Loc. = LC_X5_Y7_N9; Fanout = 1; COMB Node = 'serializer:inst2\|ssm\[2\]~0'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.740 ns" { txe serializer:inst2|ssm[2]~0 } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.200 ns) 6.783 ns serializer:inst2\|ssm\[2\]~1 3 COMB LC_X5_Y7_N6 1 " "Info: 3: + IC(0.711 ns) + CELL(0.200 ns) = 6.783 ns; Loc. = LC_X5_Y7_N6; Fanout = 1; COMB Node = 'serializer:inst2\|ssm\[2\]~1'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.911 ns" { serializer:inst2|ssm[2]~0 serializer:inst2|ssm[2]~1 } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.789 ns) + CELL(0.511 ns) 8.083 ns serializer:inst2\|ssm\[2\]~7 4 COMB LC_X5_Y7_N3 2 " "Info: 4: + IC(0.789 ns) + CELL(0.511 ns) = 8.083 ns; Loc. = LC_X5_Y7_N3; Fanout = 2; COMB Node = 'serializer:inst2\|ssm\[2\]~7'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { serializer:inst2|ssm[2]~1 serializer:inst2|ssm[2]~7 } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.741 ns) + CELL(0.200 ns) 9.024 ns serializer:inst2\|ssm\[0\]~9 5 COMB LC_X5_Y7_N8 2 " "Info: 5: + IC(0.741 ns) + CELL(0.200 ns) = 9.024 ns; Loc. = LC_X5_Y7_N8; Fanout = 2; COMB Node = 'serializer:inst2\|ssm\[0\]~9'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.941 ns" { serializer:inst2|ssm[2]~7 serializer:inst2|ssm[0]~9 } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.753 ns) + CELL(0.591 ns) 10.368 ns serializer:inst2\|ssm\[2\] 6 REG LC_X5_Y7_N0 20 " "Info: 6: + IC(0.753 ns) + CELL(0.591 ns) = 10.368 ns; Loc. = LC_X5_Y7_N0; Fanout = 20; REG Node = 'serializer:inst2\|ssm\[2\]'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.344 ns" { serializer:inst2|ssm[0]~9 serializer:inst2|ssm[2] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.834 ns ( 27.33 % ) " "Info: Total cell delay = 2.834 ns ( 27.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.534 ns ( 72.67 % ) " "Info: Total interconnect delay = 7.534 ns ( 72.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.368 ns" { txe serializer:inst2|ssm[2]~0 serializer:inst2|ssm[2]~1 serializer:inst2|ssm[2]~7 serializer:inst2|ssm[0]~9 serializer:inst2|ssm[2] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "10.368 ns" { txe {} txe~combout {} serializer:inst2|ssm[2]~0 {} serializer:inst2|ssm[2]~1 {} serializer:inst2|ssm[2]~7 {} serializer:inst2|ssm[0]~9 {} serializer:inst2|ssm[2] {} } { 0.000ns 0.000ns 4.540ns 0.711ns 0.789ns 0.741ns 0.753ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.511ns 0.200ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.261 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 9.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.918 ns) 9.261 ns serializer:inst2\|ssm\[2\] 3 REG LC_X5_Y7_N0 20 " "Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X5_Y7_N0; Fanout = 20; REG Node = 'serializer:inst2\|ssm\[2\]'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { clock_mux:inst1|wcks serializer:inst2|ssm[2] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.44 % ) " "Info: Total cell delay = 3.375 ns ( 36.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.886 ns ( 63.56 % ) " "Info: Total interconnect delay = 5.886 ns ( 63.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|ssm[2] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|ssm[2] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.368 ns" { txe serializer:inst2|ssm[2]~0 serializer:inst2|ssm[2]~1 serializer:inst2|ssm[2]~7 serializer:inst2|ssm[0]~9 serializer:inst2|ssm[2] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "10.368 ns" { txe {} txe~combout {} serializer:inst2|ssm[2]~0 {} serializer:inst2|ssm[2]~1 {} serializer:inst2|ssm[2]~7 {} serializer:inst2|ssm[0]~9 {} serializer:inst2|ssm[2] {} } { 0.000ns 0.000ns 4.540ns 0.711ns 0.789ns 0.741ns 0.753ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.511ns 0.200ns 0.591ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|ssm[2] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|ssm[2] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TCO_RESULT" "clk tms tap_sm:inst\|tms 15.899 ns register " "Info: tco from clock \"clk\" to destination pin \"tms\" through register \"tap_sm:inst\|tms\" is 15.899 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.261 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.918 ns) 9.261 ns tap_sm:inst\|tms 3 REG LC_X9_Y7_N7 5 " "Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X9_Y7_N7; Fanout = 5; REG Node = 'tap_sm:inst\|tms'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { clock_mux:inst1|wcks tap_sm:inst|tms } "NODE_NAME" } } { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.44 % ) " "Info: Total cell delay = 3.375 ns ( 36.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.886 ns ( 63.56 % ) " "Info: Total interconnect delay = 5.886 ns ( 63.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks tap_sm:inst|tms } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} tap_sm:inst|tms {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.262 ns + Longest register pin " "Info: + Longest register to pin delay is 6.262 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tap_sm:inst\|tms 1 REG LC_X9_Y7_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N7; Fanout = 5; REG Node = 'tap_sm:inst\|tms'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tap_sm:inst|tms } "NODE_NAME" } } { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.966 ns) + CELL(0.511 ns) 1.477 ns inst4 2 COMB LC_X9_Y7_N1 1 " "Info: 2: + IC(0.966 ns) + CELL(0.511 ns) = 1.477 ns; Loc. = LC_X9_Y7_N1; Fanout = 1; COMB Node = 'inst4'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { tap_sm:inst|tms inst4 } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 200 592 656 248 "inst4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.463 ns) + CELL(2.322 ns) 6.262 ns tms 3 PIN PIN_87 0 " "Info: 3: + IC(2.463 ns) + CELL(2.322 ns) = 6.262 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'tms'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.785 ns" { inst4 tms } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 216 680 856 232 "tms" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.833 ns ( 45.24 % ) " "Info: Total cell delay = 2.833 ns ( 45.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.429 ns ( 54.76 % ) " "Info: Total interconnect delay = 3.429 ns ( 54.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.262 ns" { tap_sm:inst|tms inst4 tms } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "6.262 ns" { tap_sm:inst|tms {} inst4 {} tms {} } { 0.000ns 0.966ns 2.463ns } { 0.000ns 0.511ns 2.322ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks tap_sm:inst|tms } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} tap_sm:inst|tms {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.262 ns" { tap_sm:inst|tms inst4 tms } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "6.262 ns" { tap_sm:inst|tms {} inst4 {} tms {} } { 0.000ns 0.966ns 2.463ns } { 0.000ns 0.511ns 2.322ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_TH_RESULT" "serializer:inst2\|rbyte\[6\] db\[6\] clk 4.193 ns register " "Info: th for register \"serializer:inst2\|rbyte\[6\]\" (data pin = \"db\[6\]\", clock pin = \"clk\") is 4.193 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.261 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.918 ns) 9.261 ns serializer:inst2\|rbyte\[6\] 3 REG LC_X7_Y7_N3 7 " "Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X7_Y7_N3; Fanout = 7; REG Node = 'serializer:inst2\|rbyte\[6\]'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { clock_mux:inst1|wcks serializer:inst2|rbyte[6] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.44 % ) " "Info: Total cell delay = 3.375 ns ( 36.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.886 ns ( 63.56 % ) " "Info: Total interconnect delay = 5.886 ns ( 63.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|rbyte[6] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|rbyte[6] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" { } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.289 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns db\[6\] 1 PIN PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_34; Fanout = 1; PIN Node = 'db\[6\]'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[6] } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns db~1 2 COMB IOC_X6_Y3_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X6_Y3_N2; Fanout = 1; COMB Node = 'db~1'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { db[6] db~1 } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.877 ns) + CELL(0.280 ns) 5.289 ns serializer:inst2\|rbyte\[6\] 3 REG LC_X7_Y7_N3 7 " "Info: 3: + IC(3.877 ns) + CELL(0.280 ns) = 5.289 ns; Loc. = LC_X7_Y7_N3; Fanout = 7; REG Node = 'serializer:inst2\|rbyte\[6\]'" { } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.157 ns" { db~1 serializer:inst2|rbyte[6] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 26.70 % ) " "Info: Total cell delay = 1.412 ns ( 26.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.877 ns ( 73.30 % ) " "Info: Total interconnect delay = 3.877 ns ( 73.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.289 ns" { db[6] db~1 serializer:inst2|rbyte[6] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "5.289 ns" { db[6] {} db~1 {} serializer:inst2|rbyte[6] {} } { 0.000ns 0.000ns 3.877ns } { 0.000ns 1.132ns 0.280ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|rbyte[6] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|rbyte[6] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.289 ns" { db[6] db~1 serializer:inst2|rbyte[6] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "5.289 ns" { db[6] {} db~1 {} serializer:inst2|rbyte[6] {} } { 0.000ns 0.000ns 3.877ns } { 0.000ns 1.132ns 0.280ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Peak virtual memory: 126 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 02 16:01:15 2010 " "Info: Processing ended: Wed Jun 02 16:01:15 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.txt =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.txt (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.lpc.txt (revision 18) @@ -0,0 +1,9 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; inst2 ; 6 ; 1 ; 1 ; 1 ; 14 ; 1 ; 1 ; 1 ; 8 ; 0 ; 0 ; 0 ; 0 ; +; inst1 ; 4 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst ; 6 ; 0 ; 1 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.hdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.hdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.hdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sgdiff.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg_swap.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg_swap.cdb =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg_swap.cdb (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg_swap.cdb (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.rtlv_sg_swap.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.hif =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.hif (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.hif (revision 18) @@ -0,0 +1,142 @@ +Quartus II +Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +45 +3403 +OFF +OFF +OFF +ON +ON +OFF +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +Open_JTAG +# storage +db|Open_JTAG.(0).cnf +db|Open_JTAG.(0).cnf +# case_insensitive +# source_file +open_jtag.bdf +335d2cdeba3af5d9b330c0837dc4823 +26 +# internal_option { +BLOCK_DESIGN_NAMING +AUTO +} +# hierarchies { +| +} +# macro_sequence + +# end +# entity +tap_sm +# storage +db|Open_JTAG.(1).cnf +db|Open_JTAG.(1).cnf +# logic_option { +AUTO_RAM_RECOGNITION +ON +} +# case_insensitive +# source_file +tap_sm.vhd +5a69bc8c7e347cdc0da8cb263363479 +5 +# internal_option { +HDL_INITIAL_FANOUT_LIMIT +OFF +AUTO_RESOURCE_SHARING +OFF +AUTO_RAM_RECOGNITION +ON +AUTO_ROM_RECOGNITION +ON +} +# hierarchies { +tap_sm:inst +} +# lmf +|altera|91sp2|quartus|lmf|maxplus2.lmf +a36c8ec425c8a2589af98b2d4daabc3 +# macro_sequence + +# end +# entity +clock_mux +# storage +db|Open_JTAG.(2).cnf +db|Open_JTAG.(2).cnf +# logic_option { +AUTO_RAM_RECOGNITION +ON +} +# case_insensitive +# source_file +clock_mux.vhd +c3c9f77b933864140a23b6a7c10222 +5 +# internal_option { +HDL_INITIAL_FANOUT_LIMIT +OFF +AUTO_RESOURCE_SHARING +OFF +AUTO_RAM_RECOGNITION +ON +AUTO_ROM_RECOGNITION +ON +} +# hierarchies { +clock_mux:inst1 +} +# lmf +|altera|91sp2|quartus|lmf|maxplus2.lmf +a36c8ec425c8a2589af98b2d4daabc3 +# macro_sequence + +# end +# entity +serializer +# storage +db|Open_JTAG.(3).cnf +db|Open_JTAG.(3).cnf +# logic_option { +AUTO_RAM_RECOGNITION +ON +} +# case_insensitive +# source_file +serializer.vhd +99fc3657b226a824e9aeff0798a7b5f +5 +# internal_option { +HDL_INITIAL_FANOUT_LIMIT +OFF +AUTO_RESOURCE_SHARING +OFF +AUTO_RAM_RECOGNITION +ON +AUTO_ROM_RECOGNITION +ON +} +# hierarchies { +serializer:inst2 +} +# lmf +|altera|91sp2|quartus|lmf|maxplus2.lmf +a36c8ec425c8a2589af98b2d4daabc3 +# macro_sequence + +# end +# complete + Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry.sci =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry.sci =================================================================== --- trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry.sci (nonexistent) +++ trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry.sci (revision 18)
trunk/OpenJTAG/Quartus_II/db/Open_JTAG.sld_design_entry.sci Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.map.rpt =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.map.rpt (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.map.rpt (revision 18) @@ -0,0 +1,293 @@ +Analysis & Synthesis report for Open_JTAG +Wed Jun 02 16:01:07 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Registers Removed During Synthesis + 9. General Register Statistics + 10. Inverted Register Statistics + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Wed Jun 02 16:01:07 2010 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; Open_JTAG ; +; Top-level Entity Name ; Open_JTAG ; +; Family ; MAX II ; +; Total logic elements ; 257 ; +; Total pins ; 29 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 0 / 1 ( 0 % ) ; ++-----------------------------+----------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EPM570T100C5 ; ; +; Top-level entity name ; Open_JTAG ; Open_JTAG ; +; Family name ; MAX II ; Stratix II ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; On ; On ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------+ +; tap_sm.vhd ; yes ; User VHDL File ; C:/AlteraWorks/91/Open JTAG/tap_sm.vhd ; +; clock_mux.vhd ; yes ; User VHDL File ; C:/AlteraWorks/91/Open JTAG/clock_mux.vhd ; +; serializer.vhd ; yes ; User VHDL File ; C:/AlteraWorks/91/Open JTAG/serializer.vhd ; +; Open_JTAG.bdf ; yes ; User Block Diagram/Schematic File ; C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------+ + + ++--------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------+ +; Total logic elements ; 257 ; +; -- Combinational with no register ; 169 ; +; -- Register only ; 32 ; +; -- Combinational with a register ; 56 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 134 ; +; -- 3 input functions ; 50 ; +; -- 2 input functions ; 30 ; +; -- 1 input functions ; 11 ; +; -- 0 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 249 ; +; -- arithmetic mode ; 8 ; +; -- qfbk mode ; 0 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 3 ; +; -- asynchronous clear/load mode ; 1 ; +; ; ; +; Total registers ; 88 ; +; Total logic cells in carry chains ; 10 ; +; I/O pins ; 29 ; +; Maximum fan-out node ; clock_mux:inst1|wcks ; +; Maximum fan-out ; 75 ; +; Total fan-out ; 973 ; +; Average fan-out ; 3.40 ; ++---------------------------------------------+----------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+ +; |Open_JTAG ; 257 (2) ; 88 ; 0 ; 29 ; 0 ; 169 (2) ; 32 (0) ; 56 (0) ; 10 (0) ; 0 (0) ; |Open_JTAG ; work ; +; |clock_mux:inst1| ; 21 (21) ; 14 ; 0 ; 0 ; 0 ; 7 (7) ; 7 (7) ; 7 (7) ; 6 (6) ; 0 (0) ; |Open_JTAG|clock_mux:inst1 ; work ; +; |serializer:inst2| ; 172 (172) ; 58 ; 0 ; 0 ; 0 ; 114 (114) ; 15 (15) ; 43 (43) ; 4 (4) ; 0 (0) ; |Open_JTAG|serializer:inst2 ; work ; +; |tap_sm:inst| ; 62 (62) ; 16 ; 0 ; 0 ; 0 ; 46 (46) ; 10 (10) ; 6 (6) ; 0 (0) ; 0 (0) ; |Open_JTAG|tap_sm:inst ; work ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------+----------------------------------------+ +; clock_mux:inst1|cclk[0] ; Merged with clock_mux:inst1|count[0] ; +; serializer:inst2|state[3] ; Stuck at GND due to stuck port data_in ; +; serializer:inst2|state[2] ; Merged with serializer:inst2|state[1] ; +; serializer:inst2|state[1] ; Stuck at GND due to stuck port data_in ; +; Total Number of Removed Registers = 4 ; ; ++---------------------------------------+----------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 88 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 3 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 1 ; +; Number of registers using Clock Enable ; 57 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; serializer:inst2|wr ; 2 ; +; serializer:inst2|rd ; 2 ; +; serializer:inst2|trst ; 2 ; +; serializer:inst2|dir ; 19 ; +; Total number of inverted registers = 4 ; ; ++----------------------------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+ +; 4:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |Open_JTAG|serializer:inst2|new_state[2] ; +; 4:1 ; 3 bits ; 6 LEs ; 0 LEs ; 6 LEs ; Yes ; |Open_JTAG|serializer:inst2|cks[2] ; +; 5:1 ; 8 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |Open_JTAG|serializer:inst2|shift[0] ; +; 5:1 ; 4 bits ; 12 LEs ; 0 LEs ; 12 LEs ; Yes ; |Open_JTAG|serializer:inst2|state[2] ; +; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |Open_JTAG|serializer:inst2|rbyte[6] ; +; 20:1 ; 4 bits ; 52 LEs ; 8 LEs ; 44 LEs ; Yes ; |Open_JTAG|serializer:inst2|rbyte[3] ; +; 37:1 ; 2 bits ; 48 LEs ; 18 LEs ; 30 LEs ; Yes ; |Open_JTAG|serializer:inst2|ssm[1] ; +; 21:1 ; 2 bits ; 28 LEs ; 4 LEs ; 24 LEs ; Yes ; |Open_JTAG|serializer:inst2|count[2] ; +; 40:1 ; 2 bits ; 52 LEs ; 22 LEs ; 30 LEs ; Yes ; |Open_JTAG|serializer:inst2|ssm[2] ; +; 1:1 ; 8 bits ; 0 LEs ; 0 LEs ; 0 LEs ; Yes ; |Open_JTAG|serializer:inst2|db[0]~reg0 ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |Open_JTAG|serializer:inst2|Add0 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Jun 02 16:01:02 2010 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Open_JTAG -c Open_JTAG +Info: Found 2 design units, including 1 entities, in source file tap_sm.vhd + Info: Found design unit 1: tap_sm-rtl + Info: Found entity 1: tap_sm +Info: Found 2 design units, including 1 entities, in source file clock_mux.vhd + Info: Found design unit 1: clock_mux-rtl + Info: Found entity 1: clock_mux +Info: Found 2 design units, including 1 entities, in source file serializer.vhd + Info: Found design unit 1: serializer-rtl + Info: Found entity 1: serializer +Info: Found 1 design units, including 1 entities, in source file open_jtag.bdf + Info: Found entity 1: Open_JTAG +Info: Elaborating entity "Open_JTAG" for the top level hierarchy +Info: Elaborating entity "tap_sm" for hierarchy "tap_sm:inst" +Info: Elaborating entity "clock_mux" for hierarchy "clock_mux:inst1" +Info: Elaborating entity "serializer" for hierarchy "serializer:inst2" +Warning (10540): VHDL Signal Declaration warning at serializer.vhd(25): used explicit default value for signal "siwu" because signal was never assigned a value +Warning: Design contains 1 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "rst" +Info: Implemented 286 device resources after synthesis - the final resource count might be different + Info: Implemented 5 input pins + Info: Implemented 16 output pins + Info: Implemented 8 bidirectional pins + Info: Implemented 257 logic cells +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 187 megabytes + Info: Processing ended: Wed Jun 02 16:01:07 2010 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:04 + + Index: trunk/OpenJTAG/Quartus_II/serializer.vhd =================================================================== --- trunk/OpenJTAG/Quartus_II/serializer.vhd (nonexistent) +++ trunk/OpenJTAG/Quartus_II/serializer.vhd (revision 18) @@ -0,0 +1,229 @@ +-- Created by Ruben H. Mileca - May-16-2010 + + +library ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.all; + +entity serializer IS + + port ( + +-- Internal + + clk: in std_logic; -- External 24 MHz oscillator + +-- FT245BM + + txe: in std_logic; -- From FT245BM TXE# pin + rxf: in std_logic; -- From FT245BM RXF pin + pwr: in std_logic; -- From FT245BM PWREN# pin + rst: in std_logic; -- From FT245BM RSTOUT# pin + wrk: in std_logic; -- From tap_sm working signal + wr: out std_logic := '1'; -- To FT245BM WR pin + rd: out std_logic := '1'; -- To FT245BM RD# pin + siwu: out std_logic := '1'; -- To FT245BM SI/WU pin + db: inout std_logic_vector(7 downto 0); -- From/To FT245BM data bus + +-- JTAG + + tdo: in std_logic; -- TDO Jtag pin + tck: out std_logic := '0'; -- TCK Jtag pin + tms: out std_logic := '0'; -- TMS Jtag pin + tdi: out std_logic := '0'; -- TDI Jtag pin + trst: out std_logic := '1'; -- TRST Jtag pin + +-- Clock and SM setting + + new_state: out std_logic_vector(3 downto 0); -- tap_sm new state + cks: out std_logic_vector(2 downto 0) -- Clock divider + + ); + +end serializer; + +architecture rtl of serializer is + + signal count: integer range 0 to 8 := 0; + signal state: integer range 0 to 15 := 0; + signal rclk: integer range 0 to 1 := 0; + signal sclk: integer range 0 to 1 := 0; + + signal instr: integer range 0 to 1 := 0; -- 0=Instruction, 1=Data, 2=Shift out, 3/4 shift in + signal ssm: integer range 0 to 15 := 0; -- Shift and data state machine + signal dir: std_logic := '1'; -- '0' = MSB, '1' = LSB + signal rtms: std_logic := '0'; -- TMS state at last shift bit + + signal shift: std_logic_vector(7 downto 0); + signal rbyte: std_logic_vector(7 downto 0); + +begin + + +changestate: process(clk, rclk, rxf, txe, pwr, rst) +begin + if (rising_edge(clk)) then + if rclk = 1 then + rclk <= 0; + else + rclk <= 1; + end if; +-- st <= std_logic_vector(to_unsigned(state, st'length)); + + if wrk = '0' then + case ssm is + when 0 => + tck <= '0'; + tms <= '0'; + tdi <= '0'; + if rxf = '0' then -- Start byte read from FT245BM + rd <= '0'; -- Send RD# to FT245BM + ssm <= 1; -- Change to next state + end if; + when 1 => + rbyte <= db; -- Read byte from FT245BM + db <= "ZZZZZZZZ"; + rd <= '1'; -- Select next byte from FT245BM + ssm <= 2; -- Change state; + when 2 => + case instr is + when 0 => -- Is an instruction byte + case rbyte(3 downto 0) is + when "0000" => -- rbyte(7 downto 4) have the new clock divisor + cks <= rbyte(7 downto 5); -- Set clock divisor + + when "0001" => -- rbyte(7 downto 4) have then new state + new_state <= rbyte(7 downto 4); + ssm <= 3; -- Reset state machine + when "0010" => -- Get current TAP state + rbyte(3 downto 0) <= std_logic_vector(to_unsigned(state, rbyte(3 downto 0)'length)); + rbyte(4) <= dir; + ssm <= 5; + when "0011" => -- Software reset TAP + count <= to_integer(unsigned(rbyte(7 downto 4))); + ssm <= 9; + tms <= '1'; + + + + when "0100" => -- Hardware reset TAP + count <= to_integer(unsigned(rbyte(7 downto 4)) - 1); + ssm <= 8; + when "0101" => -- Set MSB/LSB shift direction + dir <= rbyte(4); -- Set shift direction + sclk <= 0; + ssm <= 0; -- Reset state machine + when "0110" => -- Latch the next byte as shift data + if state = 0 or state = 4 or state = 11 then + count <= to_integer(unsigned(rbyte(7 downto 5))); + rtms <= rbyte(4); -- TMS state at last shifted bit + instr <= 1; -- Next is data to send + sclk <= 0; + ssm <= 0; -- Reset state machine + end if; + + when others => + ssm <= 0; -- Error, reset state machine + end case; + when 1 => -- There is a count bits to shift in/out +-- st <= std_logic_vector(to_unsigned(count, st'length)); + if sclk = 0 then + tck <= '0'; + if dir = '0' then + tdi <= rbyte(7); + rbyte(7 downto 1) <= rbyte(6 downto 0); + else + tdi <= rbyte(0); + rbyte(6 downto 0) <= rbyte(7 downto 1); + end if; + sclk <= 1; + if count = 0 then + tms <= rtms; + end if; + else + tck <= '1'; + +-- Read TDO + + if dir = '1' then + shift(6 downto 0) <= shift(7 downto 1); + shift(7) <= tdo; + else + shift(7 downto 1) <= shift(6 downto 0); + shift(0) <= tdo; + end if; + + if count > 0 then + count <= count - 1; + else + ssm <= 5; + instr <= 0; + end if; + sclk <= 0; + end if; + when others => + end case; + +-- Delay for SM state start to work + + when 3 => + ssm <= 4; + when 4 => + ssm <= 0; + +-- Write rbyte to data bus + + when 5 => + tck <= '0'; + tms <= '0'; + tdi <= '0'; + if txe = '0' then + ssm <= 6; + db <= shift; + end if; + when 6 => + wr <= '0'; + ssm <= 7; + when 7 => + wr <= '1'; + ssm <= 0; + db <= "ZZZZZZZZ"; + + if rtms = '1' then + if state = 4 or state = 11 then + state <= state + 1; + end if; + else + if state = 0 then + state <= state + 1; + end if; + end if; + + when 8 => + if count = 0 then + trst <= '1'; + ssm <= 0; + else + trst <= '0'; + count <= count - 1; + end if; + when 9 => + if sclk = 0 then + tck <= '1'; + else + tck <= '0'; + if count > 0 then + count <= count - 1; + else + tms <= '0'; + ssm <= 0; + end if; + end if; + when others => + + end case; + end if; + end if; + +end process changestate; +end rtl; Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.asm.rpt =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.asm.rpt (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.asm.rpt (revision 18) @@ -0,0 +1,114 @@ +Assembler report for Open_JTAG +Wed Jun 02 16:01:13 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/AlteraWorks/91/Open JTAG/Open_JTAG.pof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Wed Jun 02 16:01:13 2010 ; +; Revision Name ; Open_JTAG ; +; Top-level Entity Name ; Open_JTAG ; +; Family ; MAX II ; +; Device ; EPM570T100C5 ; ++-----------------------+---------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+-----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+-----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Security bit ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; +; In-System Programming Default Clamp State ; Tri-state ; Tri-state ; ++-----------------------------------------------------------------------------+-----------+---------------+ + + ++-------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------+ +; File Name ; ++-------------------------------------------+ +; C:/AlteraWorks/91/Open JTAG/Open_JTAG.pof ; ++-------------------------------------------+ + + ++---------------------------------------------------------------------+ +; Assembler Device Options: C:/AlteraWorks/91/Open JTAG/Open_JTAG.pof ; ++----------------+----------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------+ +; Device ; EPM570T100C5 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x00313ACA ; ++----------------+----------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Jun 02 16:01:12 2010 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 142 megabytes + Info: Processing ended: Wed Jun 02 16:01:13 2010 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.pof =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.pof =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.pof (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.pof (revision 18)
trunk/OpenJTAG/Quartus_II/Open_JTAG.pof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.done =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.done (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.done (revision 18) @@ -0,0 +1 @@ +Wed Jun 02 16:01:16 2010 Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.pin =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.pin (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.pin (revision 18) @@ -0,0 +1,167 @@ + -- Copyright (C) 1991-2010 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* + -- either individually through a 10k Ohm resistor to GND or tie all pins + -- together and connect through a single 10k Ohm resistor to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +CHIP "Open_JTAG" ASSIGNED TO AN: EPM570T100C5 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +wrk : 1 : output : 3.3-V LVTTL : : 2 : N +GND* : 2 : : : : 1 : +rd : 3 : output : 3.3-V LVTTL : : 1 : N +trst : 4 : output : 3.3-V LVTTL : : 1 : N +new_state[0] : 5 : output : 3.3-V LVTTL : : 1 : N +GND* : 6 : : : : 1 : +GND* : 7 : : : : 1 : +new_state[3] : 8 : output : 3.3-V LVTTL : : 1 : N +VCCIO1 : 9 : power : : 3.3V : 1 : +GNDIO : 10 : gnd : : : : +GNDINT : 11 : gnd : : : : +clk : 12 : input : 3.3-V LVTTL : : 1 : N +VCCINT : 13 : power : : 2.5V/3.3V : : +wr : 14 : output : 3.3-V LVTTL : : 1 : N +tdi : 15 : output : 3.3-V LVTTL : : 1 : N +GND* : 16 : : : : 1 : +sm[0] : 17 : output : 3.3-V LVTTL : : 1 : N +db[7] : 18 : bidir : 3.3-V LVTTL : : 1 : N +GND* : 19 : : : : 1 : +GND* : 20 : : : : 1 : +GND* : 21 : : : : 1 : +TMS : 22 : input : : : 1 : +TDI : 23 : input : : : 1 : +TCK : 24 : input : : : 1 : +TDO : 25 : output : : : 1 : +GND* : 26 : : : : 1 : +GND* : 27 : : : : 1 : +GND* : 28 : : : : 1 : +new_state[1] : 29 : output : 3.3-V LVTTL : : 1 : N +sm[1] : 30 : output : 3.3-V LVTTL : : 1 : N +VCCIO1 : 31 : power : : 3.3V : 1 : +GNDIO : 32 : gnd : : : : +new_state[2] : 33 : output : 3.3-V LVTTL : : 1 : N +db[6] : 34 : bidir : 3.3-V LVTTL : : 1 : N +GND* : 35 : : : : 1 : +db[5] : 36 : bidir : 3.3-V LVTTL : : 1 : N +GNDINT : 37 : gnd : : : : +txe : 38 : input : 3.3-V LVTTL : : 1 : N +VCCINT : 39 : power : : 2.5V/3.3V : : +db[2] : 40 : bidir : 3.3-V LVTTL : : 1 : N +db[1] : 41 : bidir : 3.3-V LVTTL : : 1 : N +db[4] : 42 : bidir : 3.3-V LVTTL : : 1 : N +sm[2] : 43 : output : 3.3-V LVTTL : : 1 : N +wcks : 44 : output : 3.3-V LVTTL : : 1 : N +VCCIO1 : 45 : power : : 3.3V : 1 : +GNDIO : 46 : gnd : : : : +GND* : 47 : : : : 1 : +GND* : 48 : : : : 1 : +GND* : 49 : : : : 1 : +GND* : 50 : : : : 1 : +GND* : 51 : : : : 1 : +GND* : 52 : : : : 2 : +GND* : 53 : : : : 2 : +GND* : 54 : : : : 2 : +GND* : 55 : : : : 2 : +GND* : 56 : : : : 2 : +GND* : 57 : : : : 2 : +GND* : 58 : : : : 2 : +VCCIO2 : 59 : power : : 3.3V : 2 : +GNDIO : 60 : gnd : : : : +GND* : 61 : : : : 2 : +GND* : 62 : : : : 2 : +VCCINT : 63 : power : : 2.5V/3.3V : : +db[0] : 64 : bidir : 3.3-V LVTTL : : 2 : N +GNDINT : 65 : gnd : : : : +GND* : 66 : : : : 2 : +GND* : 67 : : : : 2 : +GND* : 68 : : : : 2 : +GND* : 69 : : : : 2 : +sm[3] : 70 : output : 3.3-V LVTTL : : 2 : N +rxf : 71 : input : 3.3-V LVTTL : : 2 : N +GND* : 72 : : : : 2 : +rst : 73 : input : 3.3-V LVTTL : : 2 : N +GND* : 74 : : : : 2 : +GND* : 75 : : : : 2 : +GND* : 76 : : : : 2 : +GND* : 77 : : : : 2 : +GND* : 78 : : : : 2 : +GNDIO : 79 : gnd : : : : +VCCIO2 : 80 : power : : 3.3V : 2 : +GND* : 81 : : : : 2 : +GND* : 82 : : : : 2 : +GND* : 83 : : : : 2 : +GND* : 84 : : : : 2 : +GND* : 85 : : : : 2 : +GND* : 86 : : : : 2 : +tms : 87 : output : 3.3-V LVTTL : : 2 : N +VCCINT : 88 : power : : 2.5V/3.3V : : +GND* : 89 : : : : 2 : +GNDINT : 90 : gnd : : : : +tdo : 91 : input : 3.3-V LVTTL : : 2 : N +db[3] : 92 : bidir : 3.3-V LVTTL : : 2 : N +GNDIO : 93 : gnd : : : : +VCCIO2 : 94 : power : : 3.3V : 2 : +GND* : 95 : : : : 2 : +GND* : 96 : : : : 2 : +tck : 97 : output : 3.3-V LVTTL : : 2 : N +GND* : 98 : : : : 2 : +GND* : 99 : : : : 2 : +GND* : 100 : : : : 2 : Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.fit.rpt =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.fit.rpt (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.fit.rpt (revision 18) @@ -0,0 +1,766 @@ +Fitter report for Open_JTAG +Wed Jun 02 16:01:11 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Pin-Out File + 6. Fitter Resource Usage Summary + 7. Input Pins + 8. Output Pins + 9. Bidir Pins + 10. I/O Bank Usage + 11. All Package Pins + 12. Output Pin Default Load For Reported TCO + 13. Fitter Resource Utilization by Entity + 14. Delay Chain Summary + 15. Control Signals + 16. Global & Other Fast Signals + 17. Non-Global High Fan-Out Signals + 18. Interconnect Usage Summary + 19. LAB Logic Elements + 20. LAB-wide Signals + 21. LAB Signals Sourced + 22. LAB Signals Sourced Out + 23. LAB Distinct Inputs + 24. Fitter Device Options + 25. Estimated Delay Added for Hold Timing + 26. Fitter Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------+ +; Fitter Summary ; ++-----------------------+----------------------------------------------+ +; Fitter Status ; Successful - Wed Jun 02 16:01:11 2010 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; Open_JTAG ; +; Top-level Entity Name ; Open_JTAG ; +; Family ; MAX II ; +; Device ; EPM570T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 245 / 570 ( 43 % ) ; +; Total pins ; 29 / 76 ( 38 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 0 / 1 ( 0 % ) ; ++-----------------------+----------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EPM570T100C5 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Slow Slew Rate ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Delay Chains ; On ; On ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Use Best Effort Settings for Compilation ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/AlteraWorks/91/Open JTAG/Open_JTAG.pin. + + ++-----------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-------------------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------------------+ +; Total logic elements ; 245 / 570 ( 43 % ) ; +; -- Combinational with no register ; 157 ; +; -- Register only ; 20 ; +; -- Combinational with a register ; 68 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 134 ; +; -- 3 input functions ; 50 ; +; -- 2 input functions ; 30 ; +; -- 1 input functions ; 11 ; +; -- 0 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 237 ; +; -- arithmetic mode ; 8 ; +; -- qfbk mode ; 12 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 23 ; +; -- asynchronous clear/load mode ; 1 ; +; ; ; +; Total registers ; 88 / 570 ( 15 % ) ; +; Total LABs ; 28 / 57 ( 49 % ) ; +; Logic elements in carry chains ; 10 ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 29 / 76 ( 38 % ) ; +; -- Clock pins ; 3 / 4 ( 75 % ) ; +; Global signals ; 2 ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; Global clocks ; 2 / 4 ( 50 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 20% / 24% / 15% ; +; Peak interconnect usage (total/H/V) ; 20% / 24% / 15% ; +; Maximum fan-out node ; clock_mux:inst1|wcks ; +; Maximum fan-out ; 75 ; +; Highest non-global fan-out signal ; serializer:inst2|ssm[3] ; +; Highest non-global fan-out ; 34 ; +; Total fan-out ; 962 ; +; Average fan-out ; 3.51 ; ++---------------------------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +; clk ; 12 ; 1 ; 0 ; 5 ; 0 ; 14 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; rst ; 73 ; 2 ; 13 ; 7 ; 5 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; rxf ; 71 ; 2 ; 13 ; 6 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; tdo ; 91 ; 2 ; 6 ; 8 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; +; txe ; 38 ; 1 ; 7 ; 3 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Fitter ; ++------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++--------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++--------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; new_state[0] ; 5 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; +; new_state[1] ; 29 ; 1 ; 4 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; new_state[2] ; 33 ; 1 ; 6 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; new_state[3] ; 8 ; 1 ; 0 ; 7 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; rd ; 3 ; 1 ; 1 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; sm[0] ; 17 ; 1 ; 0 ; 5 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; sm[1] ; 30 ; 1 ; 4 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; +; sm[2] ; 43 ; 1 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; sm[3] ; 70 ; 2 ; 13 ; 6 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; tck ; 97 ; 2 ; 5 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; tdi ; 15 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; tms ; 87 ; 2 ; 7 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; trst ; 4 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; wcks ; 44 ; 1 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; wr ; 14 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; - ; - ; +; wrk ; 1 ; 2 ; 3 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; - ; - ; ++--------------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+---------------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+---------------------------+---------------------+ +; db[0] ; 64 ; 2 ; 13 ; 4 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[0]~en ; - ; +; db[1] ; 41 ; 1 ; 7 ; 3 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; serializer:inst2|db[1]~en ; - ; +; db[2] ; 40 ; 1 ; 7 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; serializer:inst2|db[2]~en ; - ; +; db[3] ; 92 ; 2 ; 6 ; 8 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[3]~en ; - ; +; db[4] ; 42 ; 1 ; 7 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[4]~en ; - ; +; db[5] ; 36 ; 1 ; 6 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[5]~en ; - ; +; db[6] ; 34 ; 1 ; 6 ; 3 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[6]~en ; - ; +; db[7] ; 18 ; 1 ; 0 ; 5 ; 5 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; Fitter ; 10 pF ; serializer:inst2|db[7]~en ; - ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+---------------------------+---------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 20 / 36 ( 56 % ) ; 3.3V ; -- ; +; 2 ; 9 / 40 ( 23 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ +; 1 ; 161 ; 2 ; wrk ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 2 ; 2 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 3 ; 4 ; 1 ; rd ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 4 ; 6 ; 1 ; trst ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 5 ; 8 ; 1 ; new_state[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 6 ; 9 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 7 ; 10 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 8 ; 11 ; 1 ; new_state[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 12 ; 20 ; 1 ; clk ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 14 ; 21 ; 1 ; wr ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 15 ; 22 ; 1 ; tdi ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 16 ; 23 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 17 ; 24 ; 1 ; sm[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 18 ; 25 ; 1 ; db[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 19 ; 32 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 20 ; 34 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 21 ; 36 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 22 ; 38 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 23 ; 39 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 24 ; 40 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 25 ; 41 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 26 ; 47 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 27 ; 48 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 28 ; 50 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 29 ; 51 ; 1 ; new_state[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 30 ; 52 ; 1 ; sm[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 33 ; 58 ; 1 ; new_state[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 34 ; 59 ; 1 ; db[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 35 ; 60 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 36 ; 61 ; 1 ; db[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 37 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 38 ; 62 ; 1 ; txe ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 39 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 40 ; 63 ; 1 ; db[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 41 ; 64 ; 1 ; db[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 42 ; 65 ; 1 ; db[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 43 ; 66 ; 1 ; sm[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 44 ; 67 ; 1 ; wcks ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 47 ; 71 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 48 ; 72 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 49 ; 73 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 50 ; 75 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 51 ; 79 ; 1 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 52 ; 83 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 53 ; 84 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 54 ; 86 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 55 ; 89 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 56 ; 91 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 57 ; 92 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 58 ; 93 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 61 ; 98 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 62 ; 101 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 64 ; 102 ; 2 ; db[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; 103 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 67 ; 104 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 68 ; 105 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 69 ; 111 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 70 ; 112 ; 2 ; sm[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 71 ; 115 ; 2 ; rxf ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 72 ; 116 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 73 ; 118 ; 2 ; rst ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; 74 ; 120 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 75 ; 122 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 76 ; 125 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 77 ; 126 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 78 ; 127 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 81 ; 135 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 82 ; 136 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 83 ; 139 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 84 ; 140 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 85 ; 141 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 86 ; 142 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 143 ; 2 ; tms ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 88 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; +; 89 ; 144 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 90 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; +; 91 ; 149 ; 2 ; tdo ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 92 ; 150 ; 2 ; db[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 95 ; 151 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 96 ; 152 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 97 ; 153 ; 2 ; tck ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; 98 ; 155 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 99 ; 156 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 100 ; 158 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------+-------+------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------+-------+------------------------+ +; 3.3-V LVTTL ; 10 pF ; Not Available ; +; 3.3-V LVCMOS ; 10 pF ; Not Available ; +; 2.5 V ; 10 pF ; Not Available ; +; 1.8 V ; 10 pF ; Not Available ; +; 1.5 V ; 10 pF ; Not Available ; +; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ; +; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ; ++----------------------------+-------+------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+ +; |Open_JTAG ; 245 (1) ; 88 ; 0 ; 29 ; 0 ; 157 (1) ; 20 (0) ; 68 (0) ; 10 (0) ; 12 (1) ; |Open_JTAG ; work ; +; |clock_mux:inst1| ; 15 (15) ; 14 ; 0 ; 0 ; 0 ; 1 (1) ; 3 (3) ; 11 (11) ; 6 (6) ; 6 (6) ; |Open_JTAG|clock_mux:inst1 ; work ; +; |serializer:inst2| ; 171 (171) ; 58 ; 0 ; 0 ; 0 ; 113 (113) ; 13 (13) ; 45 (45) ; 4 (4) ; 1 (1) ; |Open_JTAG|serializer:inst2 ; work ; +; |tap_sm:inst| ; 58 (58) ; 16 ; 0 ; 0 ; 0 ; 42 (42) ; 4 (4) ; 12 (12) ; 0 (0) ; 4 (4) ; |Open_JTAG|tap_sm:inst ; work ; ++----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------+ +; Delay Chain Summary ; ++--------------+----------+---------------+ +; Name ; Pin Type ; Pad to Core 0 ; ++--------------+----------+---------------+ +; rst ; Input ; (0) ; +; rxf ; Input ; (1) ; +; clk ; Input ; (1) ; +; txe ; Input ; (1) ; +; tdo ; Input ; (1) ; +; tms ; Output ; -- ; +; tck ; Output ; -- ; +; wrk ; Output ; -- ; +; wr ; Output ; -- ; +; rd ; Output ; -- ; +; tdi ; Output ; -- ; +; trst ; Output ; -- ; +; wcks ; Output ; -- ; +; new_state[3] ; Output ; -- ; +; new_state[2] ; Output ; -- ; +; new_state[1] ; Output ; -- ; +; new_state[0] ; Output ; -- ; +; sm[3] ; Output ; -- ; +; sm[2] ; Output ; -- ; +; sm[1] ; Output ; -- ; +; sm[0] ; Output ; -- ; +; db[7] ; Bidir ; (1) ; +; db[6] ; Bidir ; (1) ; +; db[5] ; Bidir ; (1) ; +; db[4] ; Bidir ; (1) ; +; db[3] ; Bidir ; (1) ; +; db[2] ; Bidir ; (1) ; +; db[1] ; Bidir ; (1) ; +; db[0] ; Bidir ; (1) ; ++--------------+----------+---------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++---------------------------------+-------------+---------+---------------------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++---------------------------------+-------------+---------+---------------------------+--------+----------------------+------------------+ +; clk ; PIN_12 ; 14 ; Clock ; yes ; Global Clock ; GCLK0 ; +; clock_mux:inst1|Equal0~1 ; LC_X7_Y5_N9 ; 14 ; Async. load, Clock enable ; no ; -- ; -- ; +; clock_mux:inst1|wcks ; LC_X8_Y5_N5 ; 75 ; Clock ; yes ; Global Clock ; GCLK3 ; +; serializer:inst2|cks[0]~0 ; LC_X7_Y5_N4 ; 3 ; Clock enable ; no ; -- ; -- ; +; serializer:inst2|count[1]~11 ; LC_X2_Y5_N3 ; 2 ; Clock enable ; no ; -- ; -- ; +; serializer:inst2|db[0]~en ; LC_X9_Y4_N1 ; 1 ; Output enable ; no ; -- ; -- ; +; serializer:inst2|db[1]~en ; LC_X7_Y4_N0 ; 1 ; Output enable ; no ; -- ; -- ; +; serializer:inst2|db[2]~en ; LC_X7_Y4_N9 ; 1 ; Output enable ; no ; -- ; -- ; +; serializer:inst2|db[3]~en ; LC_X6_Y5_N4 ; 1 ; Output enable ; no ; -- ; -- ; +; serializer:inst2|db[4]~en ; LC_X6_Y5_N5 ; 1 ; Output enable ; no ; -- ; -- ; +; serializer:inst2|db[5]~en ; LC_X6_Y5_N9 ; 1 ; Output enable ; no ; -- ; -- ; +; serializer:inst2|db[6]~en ; LC_X6_Y5_N6 ; 1 ; Output enable ; no ; -- ; -- ; +; serializer:inst2|db[7]~8 ; LC_X5_Y4_N0 ; 16 ; Clock enable ; no ; -- ; -- ; +; serializer:inst2|db[7]~en ; LC_X6_Y5_N1 ; 1 ; Output enable ; no ; -- ; -- ; +; serializer:inst2|instr ; LC_X5_Y4_N8 ; 30 ; Sync. load ; no ; -- ; -- ; +; serializer:inst2|new_state[3]~0 ; LC_X7_Y5_N6 ; 4 ; Clock enable ; no ; -- ; -- ; +; serializer:inst2|rbyte[1]~4 ; LC_X8_Y4_N3 ; 4 ; Clock enable ; no ; -- ; -- ; +; serializer:inst2|rbyte[6]~11 ; LC_X7_Y7_N4 ; 2 ; Clock enable ; no ; -- ; -- ; +; serializer:inst2|rtms~0 ; LC_X5_Y5_N0 ; 8 ; Clock enable ; no ; -- ; -- ; +; serializer:inst2|shift[7]~0 ; LC_X6_Y4_N6 ; 8 ; Clock enable ; no ; -- ; -- ; +; serializer:inst2|ssm[0] ; LC_X5_Y7_N5 ; 30 ; Sync. load ; no ; -- ; -- ; +; tap_sm:inst|Equal0~2 ; LC_X4_Y4_N2 ; 7 ; Clock enable ; no ; -- ; -- ; ++---------------------------------+-------------+---------+---------------------------+--------+----------------------+------------------+ + + ++----------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------------------+-------------+---------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; ++----------------------+-------------+---------+----------------------+------------------+ +; clk ; PIN_12 ; 14 ; Global Clock ; GCLK0 ; +; clock_mux:inst1|wcks ; LC_X8_Y5_N5 ; 75 ; Global Clock ; GCLK3 ; ++----------------------+-------------+---------+----------------------+------------------+ + + ++-------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++---------------------------------+---------+ +; Name ; Fan-Out ; ++---------------------------------+---------+ +; serializer:inst2|ssm[3] ; 34 ; +; serializer:inst2|ssm[1] ; 33 ; +; serializer:inst2|instr ; 30 ; +; serializer:inst2|ssm[0] ; 30 ; +; serializer:inst2|ssm[2] ; 20 ; +; serializer:inst2|dir ; 19 ; +; serializer:inst2|rbyte[2] ; 19 ; +; serializer:inst2|rbyte[0] ; 19 ; +; serializer:inst2|rbyte[1] ; 19 ; +; tap_sm:inst|state[1] ; 19 ; +; serializer:inst2|db[7]~8 ; 16 ; +; tap_sm:inst|state[2] ; 16 ; +; tap_sm:inst|wrk ; 15 ; +; serializer:inst2|sclk ; 15 ; +; clock_mux:inst1|Equal0~1 ; 14 ; +; tap_sm:inst|state[3] ; 14 ; +; tap_sm:inst|rclk ; 14 ; +; tap_sm:inst|astate[1] ; 12 ; +; tap_sm:inst|state[0] ; 12 ; +; serializer:inst2|rbyte[3] ; 11 ; +; tap_sm:inst|astate[2] ; 10 ; +; tap_sm:inst|astate[3] ; 10 ; +; serializer:inst2|rbyte[7] ; 9 ; +; serializer:inst2|LessThan0~0 ; 9 ; +; serializer:inst2|shift[7]~0 ; 8 ; +; serializer:inst2|Mux71~0 ; 8 ; +; serializer:inst2|state[0] ; 8 ; +; serializer:inst2|rtms~0 ; 8 ; +; tap_sm:inst|astate[0] ; 8 ; +; serializer:inst2|rbyte[4] ; 7 ; +; serializer:inst2|rbyte[5] ; 7 ; +; serializer:inst2|rbyte[6] ; 7 ; +; serializer:inst2|count[3] ; 7 ; +; tap_sm:inst|Equal0~2 ; 7 ; +; serializer:inst2|cks[1] ; 6 ; +; serializer:inst2|Mux27~0 ; 6 ; +; serializer:inst2|count[0] ; 6 ; +; serializer:inst2|Mux51~0 ; 5 ; +; serializer:inst2|rbyte[0]~0 ; 5 ; +; serializer:inst2|tms~3 ; 5 ; +; tap_sm:inst|Equal3~0 ; 5 ; +; tap_sm:inst|tms ; 5 ; +; serializer:inst2|Add0~16 ; 4 ; +; serializer:inst2|rbyte[1]~4 ; 4 ; +; tap_sm:inst|Equal3~1 ; 4 ; +; serializer:inst2|new_state[3]~0 ; 4 ; +; serializer:inst2|cks[0] ; 4 ; +; txe ; 3 ; +; serializer:inst2|shift[1] ; 3 ; +; serializer:inst2|shift[2] ; 3 ; ++---------------------------------+---------+ + + ++---------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+----------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+----------------------+ +; C4s ; 220 / 1,624 ( 14 % ) ; +; Direct links ; 44 / 1,930 ( 2 % ) ; +; Global clocks ; 2 / 4 ( 50 % ) ; +; LAB clocks ; 13 / 56 ( 23 % ) ; +; LUT chains ; 16 / 513 ( 3 % ) ; +; Local interconnects ; 427 / 1,930 ( 22 % ) ; +; R4s ; 288 / 1,472 ( 20 % ) ; ++----------------------------+----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 8.75) ; Number of LABs (Total = 28) ; ++--------------------------------------------+------------------------------+ +; 1 ; 2 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 23 ; ++--------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 1.54) ; Number of LABs (Total = 28) ; ++------------------------------------+------------------------------+ +; 1 Async. load ; 1 ; +; 1 Clock ; 27 ; +; 1 Clock enable ; 12 ; +; 1 Sync. load ; 2 ; +; 2 Clock enables ; 1 ; ++------------------------------------+------------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 8.96) ; Number of LABs (Total = 28) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 17 ; +; 11 ; 3 ; +; 12 ; 2 ; ++---------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 28) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 0 ; +; 3 ; 5 ; +; 4 ; 3 ; +; 5 ; 4 ; +; 6 ; 4 ; +; 7 ; 5 ; +; 8 ; 2 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 2 ; ++-------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 12.14) ; Number of LABs (Total = 28) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 2 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 4 ; +; 9 ; 3 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 4 ; +; 13 ; 2 ; +; 14 ; 3 ; +; 15 ; 2 ; +; 16 ; 2 ; +; 17 ; 1 ; +; 18 ; 2 ; +; 19 ; 1 ; +; 20 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Jun 02 16:01:08 2010 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG +Info: Selected device EPM570T100C5 for design "Open_JTAG" +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature. +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EPM240T100C5 is compatible + Info: Device EPM240T100I5 is compatible + Info: Device EPM240T100A5 is compatible + Info: Device EPM570T100I5 is compatible + Info: Device EPM570T100A5 is compatible +Critical Warning: No exact pin location assignment(s) for 29 pins of 29 total pins + Info: Pin tms not assigned to an exact location on the device + Info: Pin rst not assigned to an exact location on the device + Info: Pin tck not assigned to an exact location on the device + Info: Pin wrk not assigned to an exact location on the device + Info: Pin wr not assigned to an exact location on the device + Info: Pin rd not assigned to an exact location on the device + Info: Pin tdi not assigned to an exact location on the device + Info: Pin trst not assigned to an exact location on the device + Info: Pin wcks not assigned to an exact location on the device + Info: Pin new_state[3] not assigned to an exact location on the device + Info: Pin new_state[2] not assigned to an exact location on the device + Info: Pin new_state[1] not assigned to an exact location on the device + Info: Pin new_state[0] not assigned to an exact location on the device + Info: Pin sm[3] not assigned to an exact location on the device + Info: Pin sm[2] not assigned to an exact location on the device + Info: Pin sm[1] not assigned to an exact location on the device + Info: Pin sm[0] not assigned to an exact location on the device + Info: Pin db[7] not assigned to an exact location on the device + Info: Pin db[6] not assigned to an exact location on the device + Info: Pin db[5] not assigned to an exact location on the device + Info: Pin db[4] not assigned to an exact location on the device + Info: Pin db[3] not assigned to an exact location on the device + Info: Pin db[2] not assigned to an exact location on the device + Info: Pin db[1] not assigned to an exact location on the device + Info: Pin db[0] not assigned to an exact location on the device + Info: Pin rxf not assigned to an exact location on the device + Info: Pin clk not assigned to an exact location on the device + Info: Pin txe not assigned to an exact location on the device + Info: Pin tdo not assigned to an exact location on the device +Info: Timing-driven compilation is using the Classic Timing Analyzer +Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements + Info: Assuming a global fmax requirement of 1000 MHz + Info: Assuming a global tsu requirement of 2.0 ns + Info: Assuming a global tco requirement of 1.0 ns + Info: Assuming a global tpd requirement of 1.0 ns +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Info: Completed User Assigned Global Signals Promotion Operation +Info: Automatically promoted some destinations of signal "clk" to use Global clock in PIN 12 + Info: Destination "clock_mux:inst1|wcks" may be non-global or may not use global clock +Info: Automatically promoted some destinations of signal "clock_mux:inst1|wcks" to use Global clock + Info: Destination "wcks" may be non-global or may not use global clock +Info: Completed Auto Global Promotion Operation +Info: Starting register packing +Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option +Extra Info: Moving registers into LUTs to improve timing and density +Info: Started processing fast register assignments +Info: Finished processing fast register assignments +Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00 +Info: Finished register packing +Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info: Number of I/O pins in group: 28 (unused VREF, 3.3V VCCIO, 4 input, 16 output, 8 bidirectional) + Info: I/O standards used: 3.3-V LVTTL. +Info: I/O bank details before I/O pin placement + Info: Statistics of I/O banks + Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available + Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available +Info: Fitter preparation operations ending: elapsed time is 00:00:01 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:00 +Info: Estimated most critical path is register to pin delay of 6.057 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y7; Fanout = 3; REG Node = 'serializer:inst2|tms' + Info: 2: + IC(0.620 ns) + CELL(0.740 ns) = 1.360 ns; Loc. = LAB_X9_Y7; Fanout = 1; COMB Node = 'inst4' + Info: 3: + IC(2.375 ns) + CELL(2.322 ns) = 6.057 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'tms' + Info: Total cell delay = 3.062 ns ( 50.55 % ) + Info: Total interconnect delay = 2.995 ns ( 49.45 % ) +Info: Fitter routing operations beginning +Info: Average interconnect usage is 15% of the available device resources + Info: Peak interconnect usage is 15% of the available device resources in the region that extends from location X0_Y0 to location X13_Y8 +Info: Fitter routing operations ending: elapsed time is 00:00:00 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Quartus II Fitter was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 175 megabytes + Info: Processing ended: Wed Jun 02 16:01:11 2010 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:01 + + Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.tan.rpt =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.tan.rpt (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.tan.rpt (revision 18) @@ -0,0 +1,533 @@ +Classic Timing Analyzer report for Open_JTAG +Wed Jun 02 16:01:15 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Parallel Compilation + 6. Clock Setup: 'clk' + 7. tsu + 8. tco + 9. th + 10. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++------------------------------+-------+---------------+----------------------------------+-------------------------+---------------------------+------------+----------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++------------------------------+-------+---------------+----------------------------------+-------------------------+---------------------------+------------+----------+--------------+ +; Worst-case tsu ; N/A ; None ; 1.440 ns ; txe ; serializer:inst2|ssm[2] ; -- ; clk ; 0 ; +; Worst-case tco ; N/A ; None ; 15.899 ns ; tap_sm:inst|tms ; tms ; clk ; -- ; 0 ; +; Worst-case th ; N/A ; None ; 4.193 ns ; db[6] ; serializer:inst2|rbyte[6] ; -- ; clk ; 0 ; +; Clock Setup: 'clk' ; N/A ; None ; 78.31 MHz ( period = 12.770 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|wcks ; clk ; clk ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; ++------------------------------+-------+---------------+----------------------------------+-------------------------+---------------------------+------------+----------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ +; Device Name ; EPM570T100C5 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; Off ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ; +; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; ++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'clk' ; ++-----------------------------------------+-----------------------------------------------------+---------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+---------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; N/A ; 78.31 MHz ( period = 12.770 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|wcks ; clk ; clk ; None ; None ; 6.481 ns ; +; N/A ; 81.38 MHz ( period = 12.288 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|wcks ; clk ; clk ; None ; None ; 5.999 ns ; +; N/A ; 81.73 MHz ( period = 12.235 ns ) ; tap_sm:inst|astate[2] ; tap_sm:inst|state[1] ; clk ; clk ; None ; None ; 11.526 ns ; +; N/A ; 82.55 MHz ( period = 12.114 ns ) ; serializer:inst2|instr ; serializer:inst2|instr ; clk ; clk ; None ; None ; 11.405 ns ; +; N/A ; 83.10 MHz ( period = 12.033 ns ) ; serializer:inst2|instr ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 11.324 ns ; +; N/A ; 83.13 MHz ( period = 12.030 ns ) ; serializer:inst2|instr ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 11.321 ns ; +; N/A ; 83.79 MHz ( period = 11.935 ns ) ; serializer:inst2|instr ; serializer:inst2|tms ; clk ; clk ; None ; None ; 11.226 ns ; +; N/A ; 84.03 MHz ( period = 11.900 ns ) ; tap_sm:inst|astate[0] ; tap_sm:inst|tck ; clk ; clk ; None ; None ; 11.191 ns ; +; N/A ; 84.06 MHz ( period = 11.896 ns ) ; tap_sm:inst|astate[2] ; tap_sm:inst|tck ; clk ; clk ; None ; None ; 11.187 ns ; +; N/A ; 84.49 MHz ( period = 11.836 ns ) ; tap_sm:inst|astate[1] ; tap_sm:inst|state[1] ; clk ; clk ; None ; None ; 11.127 ns ; +; N/A ; 84.70 MHz ( period = 11.807 ns ) ; serializer:inst2|instr ; serializer:inst2|rbyte[0] ; clk ; clk ; None ; None ; 11.098 ns ; +; N/A ; 85.33 MHz ( period = 11.719 ns ) ; serializer:inst2|count[3] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 11.010 ns ; +; N/A ; 85.37 MHz ( period = 11.714 ns ) ; serializer:inst2|count[3] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 11.005 ns ; +; N/A ; 85.48 MHz ( period = 11.698 ns ) ; serializer:inst2|rbyte[1] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 10.989 ns ; +; N/A ; 85.51 MHz ( period = 11.695 ns ) ; serializer:inst2|rbyte[1] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 10.986 ns ; +; N/A ; 85.71 MHz ( period = 11.667 ns ) ; serializer:inst2|instr ; serializer:inst2|count[3] ; clk ; clk ; None ; None ; 10.958 ns ; +; N/A ; 85.76 MHz ( period = 11.661 ns ) ; tap_sm:inst|astate[3] ; tap_sm:inst|tck ; clk ; clk ; None ; None ; 10.952 ns ; +; N/A ; 85.79 MHz ( period = 11.657 ns ) ; serializer:inst2|count[1] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 10.948 ns ; +; N/A ; 85.82 MHz ( period = 11.652 ns ) ; serializer:inst2|count[1] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 10.943 ns ; +; N/A ; 85.83 MHz ( period = 11.651 ns ) ; tap_sm:inst|astate[2] ; tap_sm:inst|tms ; clk ; clk ; None ; None ; 10.942 ns ; +; N/A ; 85.88 MHz ( period = 11.644 ns ) ; tap_sm:inst|astate[1] ; tap_sm:inst|tms ; clk ; clk ; None ; None ; 10.935 ns ; +; N/A ; 85.96 MHz ( period = 11.633 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|instr ; clk ; clk ; None ; None ; 10.924 ns ; +; N/A ; 85.98 MHz ( period = 11.631 ns ) ; serializer:inst2|rbyte[2] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 10.922 ns ; +; N/A ; 86.00 MHz ( period = 11.628 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|tms ; clk ; clk ; None ; None ; 10.919 ns ; +; N/A ; 86.00 MHz ( period = 11.628 ns ) ; serializer:inst2|rbyte[2] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 10.919 ns ; +; N/A ; 86.53 MHz ( period = 11.557 ns ) ; serializer:inst2|rbyte[2] ; serializer:inst2|tms ; clk ; clk ; None ; None ; 10.848 ns ; +; N/A ; 86.57 MHz ( period = 11.552 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 10.843 ns ; +; N/A ; 86.59 MHz ( period = 11.549 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 10.840 ns ; +; N/A ; 86.84 MHz ( period = 11.516 ns ) ; tap_sm:inst|astate[3] ; tap_sm:inst|tms ; clk ; clk ; None ; None ; 10.807 ns ; +; N/A ; 87.07 MHz ( period = 11.485 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|new_state[0] ; clk ; clk ; None ; None ; 10.776 ns ; +; N/A ; 87.07 MHz ( period = 11.485 ns ) ; serializer:inst2|instr ; serializer:inst2|rtms ; clk ; clk ; None ; None ; 10.776 ns ; +; N/A ; 87.11 MHz ( period = 11.480 ns ) ; serializer:inst2|instr ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 10.771 ns ; +; N/A ; 87.15 MHz ( period = 11.475 ns ) ; serializer:inst2|instr ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 10.766 ns ; +; N/A ; 87.34 MHz ( period = 11.449 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|rbyte[0] ; clk ; clk ; None ; None ; 10.740 ns ; +; N/A ; 87.54 MHz ( period = 11.423 ns ) ; serializer:inst2|instr ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 10.714 ns ; +; N/A ; 87.62 MHz ( period = 11.413 ns ) ; tap_sm:inst|state[3] ; tap_sm:inst|tck ; clk ; clk ; None ; None ; 10.704 ns ; +; N/A ; 87.70 MHz ( period = 11.402 ns ) ; serializer:inst2|rbyte[0] ; serializer:inst2|instr ; clk ; clk ; None ; None ; 10.693 ns ; +; N/A ; 87.97 MHz ( period = 11.367 ns ) ; serializer:inst2|ssm[2] ; serializer:inst2|new_state[0] ; clk ; clk ; None ; None ; 10.658 ns ; +; N/A ; 88.33 MHz ( period = 11.321 ns ) ; serializer:inst2|rbyte[0] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 10.612 ns ; +; N/A ; 88.35 MHz ( period = 11.318 ns ) ; serializer:inst2|rbyte[0] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 10.609 ns ; +; N/A ; 88.38 MHz ( period = 11.315 ns ) ; serializer:inst2|state[0] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 10.606 ns ; +; N/A ; 88.40 MHz ( period = 11.312 ns ) ; serializer:inst2|state[0] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 10.603 ns ; +; N/A ; 88.42 MHz ( period = 11.310 ns ) ; tap_sm:inst|astate[0] ; tap_sm:inst|state[3] ; clk ; clk ; None ; None ; 10.601 ns ; +; N/A ; 88.45 MHz ( period = 11.306 ns ) ; tap_sm:inst|astate[2] ; tap_sm:inst|state[3] ; clk ; clk ; None ; None ; 10.597 ns ; +; N/A ; 88.46 MHz ( period = 11.304 ns ) ; serializer:inst2|instr ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 10.595 ns ; +; N/A ; 88.94 MHz ( period = 11.244 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|rbyte[0] ; clk ; clk ; None ; None ; 10.535 ns ; +; N/A ; 89.26 MHz ( period = 11.203 ns ) ; tap_sm:inst|astate[0] ; tap_sm:inst|state[2] ; clk ; clk ; None ; None ; 10.494 ns ; +; N/A ; 89.29 MHz ( period = 11.199 ns ) ; tap_sm:inst|astate[2] ; tap_sm:inst|state[2] ; clk ; clk ; None ; None ; 10.490 ns ; +; N/A ; 89.42 MHz ( period = 11.183 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 10.474 ns ; +; N/A ; 89.60 MHz ( period = 11.161 ns ) ; serializer:inst2|rbyte[0] ; serializer:inst2|tms ; clk ; clk ; None ; None ; 10.452 ns ; +; N/A ; 89.65 MHz ( period = 11.154 ns ) ; tap_sm:inst|astate[0] ; tap_sm:inst|tms ; clk ; clk ; None ; None ; 10.445 ns ; +; N/A ; 89.73 MHz ( period = 11.145 ns ) ; serializer:inst2|rbyte[1] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 10.436 ns ; +; N/A ; 89.77 MHz ( period = 11.140 ns ) ; serializer:inst2|rbyte[1] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 10.431 ns ; +; N/A ; 89.81 MHz ( period = 11.135 ns ) ; tap_sm:inst|astate[3] ; tap_sm:inst|state[1] ; clk ; clk ; None ; None ; 10.426 ns ; +; N/A ; 89.88 MHz ( period = 11.126 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|count[1] ; clk ; clk ; None ; None ; 4.837 ns ; +; N/A ; 89.88 MHz ( period = 11.126 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|count[0] ; clk ; clk ; None ; None ; 4.837 ns ; +; N/A ; 89.88 MHz ( period = 11.126 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|count[4] ; clk ; clk ; None ; None ; 4.837 ns ; +; N/A ; 89.88 MHz ( period = 11.126 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|count[6] ; clk ; clk ; None ; None ; 4.837 ns ; +; N/A ; 89.88 MHz ( period = 11.126 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|count[5] ; clk ; clk ; None ; None ; 4.837 ns ; +; N/A ; 89.88 MHz ( period = 11.126 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|count[3] ; clk ; clk ; None ; None ; 4.837 ns ; +; N/A ; 89.88 MHz ( period = 11.126 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|count[2] ; clk ; clk ; None ; None ; 4.837 ns ; +; N/A ; 89.88 MHz ( period = 11.126 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|cclk[3] ; clk ; clk ; None ; None ; 4.837 ns ; +; N/A ; 89.88 MHz ( period = 11.126 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|cclk[2] ; clk ; clk ; None ; None ; 4.837 ns ; +; N/A ; 89.92 MHz ( period = 11.121 ns ) ; serializer:inst2|sclk ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 10.412 ns ; +; N/A ; 89.95 MHz ( period = 11.117 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|cclk[1] ; clk ; clk ; None ; None ; 4.828 ns ; +; N/A ; 89.95 MHz ( period = 11.117 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|cclk[4] ; clk ; clk ; None ; None ; 4.828 ns ; +; N/A ; 89.95 MHz ( period = 11.117 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|cclk[6] ; clk ; clk ; None ; None ; 4.828 ns ; +; N/A ; 89.95 MHz ( period = 11.117 ns ) ; serializer:inst2|cks[0] ; clock_mux:inst1|cclk[5] ; clk ; clk ; None ; None ; 4.828 ns ; +; N/A ; 90.08 MHz ( period = 11.101 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 10.392 ns ; +; N/A ; 90.27 MHz ( period = 11.078 ns ) ; serializer:inst2|rbyte[2] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 10.369 ns ; +; N/A ; 90.31 MHz ( period = 11.073 ns ) ; serializer:inst2|rbyte[2] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 10.364 ns ; +; N/A ; 90.33 MHz ( period = 11.071 ns ) ; tap_sm:inst|astate[3] ; tap_sm:inst|state[3] ; clk ; clk ; None ; None ; 10.362 ns ; +; N/A ; 90.44 MHz ( period = 11.057 ns ) ; tap_sm:inst|state[1] ; tap_sm:inst|state[1] ; clk ; clk ; None ; None ; 10.348 ns ; +; N/A ; 90.46 MHz ( period = 11.054 ns ) ; serializer:inst2|ssm[0] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 10.345 ns ; +; N/A ; 90.59 MHz ( period = 11.039 ns ) ; serializer:inst2|sclk ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 10.330 ns ; +; N/A ; 90.60 MHz ( period = 11.038 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|count[3] ; clk ; clk ; None ; None ; 10.329 ns ; +; N/A ; 90.79 MHz ( period = 11.015 ns ) ; serializer:inst2|count[0] ; serializer:inst2|count[0] ; clk ; clk ; None ; None ; 10.306 ns ; +; N/A ; 90.88 MHz ( period = 11.004 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|rtms ; clk ; clk ; None ; None ; 10.295 ns ; +; N/A ; 90.91 MHz ( period = 11.000 ns ) ; serializer:inst2|ssm[1] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 10.291 ns ; +; N/A ; 90.92 MHz ( period = 10.999 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 10.290 ns ; +; N/A ; 90.96 MHz ( period = 10.994 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 10.285 ns ; +; N/A ; 91.14 MHz ( period = 10.972 ns ) ; serializer:inst2|ssm[0] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 10.263 ns ; +; N/A ; 91.21 MHz ( period = 10.964 ns ) ; tap_sm:inst|astate[3] ; tap_sm:inst|state[2] ; clk ; clk ; None ; None ; 10.255 ns ; +; N/A ; 91.32 MHz ( period = 10.951 ns ) ; serializer:inst2|rbyte[5] ; serializer:inst2|count[0] ; clk ; clk ; None ; None ; 10.242 ns ; +; N/A ; 91.46 MHz ( period = 10.934 ns ) ; serializer:inst2|rbyte[1] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 10.225 ns ; +; N/A ; 91.51 MHz ( period = 10.928 ns ) ; serializer:inst2|ssm[1] ; serializer:inst2|rbyte[0] ; clk ; clk ; None ; None ; 10.219 ns ; +; N/A ; 91.58 MHz ( period = 10.919 ns ) ; serializer:inst2|count[3] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 10.210 ns ; +; N/A ; 91.59 MHz ( period = 10.918 ns ) ; serializer:inst2|ssm[0] ; serializer:inst2|new_state[0] ; clk ; clk ; None ; None ; 10.209 ns ; +; N/A ; 91.59 MHz ( period = 10.918 ns ) ; serializer:inst2|ssm[1] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 10.209 ns ; +; N/A ; 91.61 MHz ( period = 10.916 ns ) ; serializer:inst2|count[3] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 10.207 ns ; +; N/A ; 91.62 MHz ( period = 10.915 ns ) ; tap_sm:inst|astate[0] ; tap_sm:inst|state[0] ; clk ; clk ; None ; None ; 10.206 ns ; +; N/A ; 91.63 MHz ( period = 10.914 ns ) ; serializer:inst2|sclk ; serializer:inst2|rbyte[0] ; clk ; clk ; None ; None ; 10.205 ns ; +; N/A ; 91.65 MHz ( period = 10.911 ns ) ; tap_sm:inst|astate[2] ; tap_sm:inst|state[0] ; clk ; clk ; None ; None ; 10.202 ns ; +; N/A ; 91.79 MHz ( period = 10.894 ns ) ; serializer:inst2|rbyte[2] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 10.185 ns ; +; N/A ; 91.94 MHz ( period = 10.877 ns ) ; tap_sm:inst|state[0] ; tap_sm:inst|tck ; clk ; clk ; None ; None ; 10.168 ns ; +; N/A ; 91.98 MHz ( period = 10.872 ns ) ; serializer:inst2|rbyte[5] ; serializer:inst2|count[3] ; clk ; clk ; None ; None ; 10.163 ns ; +; N/A ; 92.11 MHz ( period = 10.857 ns ) ; serializer:inst2|count[1] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 10.148 ns ; +; N/A ; 92.13 MHz ( period = 10.854 ns ) ; serializer:inst2|count[1] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 10.145 ns ; +; N/A ; 92.13 MHz ( period = 10.854 ns ) ; tap_sm:inst|wrk ; serializer:inst2|rbyte[0] ; clk ; clk ; None ; None ; 10.145 ns ; +; N/A ; 92.14 MHz ( period = 10.853 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 10.144 ns ; +; N/A ; 92.14 MHz ( period = 10.853 ns ) ; tap_sm:inst|astate[0] ; tap_sm:inst|state[1] ; clk ; clk ; None ; None ; 10.144 ns ; +; N/A ; 92.15 MHz ( period = 10.852 ns ) ; serializer:inst2|rbyte[1] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 10.143 ns ; +; N/A ; 92.18 MHz ( period = 10.848 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 10.139 ns ; +; N/A ; 92.26 MHz ( period = 10.839 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 10.130 ns ; +; N/A ; 92.28 MHz ( period = 10.836 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 10.127 ns ; +; N/A ; 92.33 MHz ( period = 10.831 ns ) ; serializer:inst2|count[0] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 10.122 ns ; +; N/A ; 92.37 MHz ( period = 10.826 ns ) ; serializer:inst2|count[0] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 10.117 ns ; +; N/A ; 92.40 MHz ( period = 10.823 ns ) ; tap_sm:inst|state[3] ; tap_sm:inst|state[3] ; clk ; clk ; None ; None ; 10.114 ns ; +; N/A ; 92.44 MHz ( period = 10.818 ns ) ; serializer:inst2|sclk ; serializer:inst2|tms ; clk ; clk ; None ; None ; 10.109 ns ; +; N/A ; 92.49 MHz ( period = 10.812 ns ) ; serializer:inst2|rbyte[2] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 10.103 ns ; +; N/A ; 92.82 MHz ( period = 10.773 ns ) ; serializer:inst2|rbyte[0] ; serializer:inst2|rtms ; clk ; clk ; None ; None ; 10.064 ns ; +; N/A ; 92.87 MHz ( period = 10.768 ns ) ; serializer:inst2|rbyte[0] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 10.059 ns ; +; N/A ; 92.91 MHz ( period = 10.763 ns ) ; serializer:inst2|rbyte[0] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 10.054 ns ; +; N/A ; 92.92 MHz ( period = 10.762 ns ) ; serializer:inst2|state[0] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 10.053 ns ; +; N/A ; 92.96 MHz ( period = 10.757 ns ) ; serializer:inst2|state[0] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 10.048 ns ; +; N/A ; 93.01 MHz ( period = 10.752 ns ) ; tap_sm:inst|astate[1] ; tap_sm:inst|tck ; clk ; clk ; None ; None ; 10.043 ns ; +; N/A ; 93.08 MHz ( period = 10.744 ns ) ; serializer:inst2|count[3] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 10.035 ns ; +; N/A ; 93.32 MHz ( period = 10.716 ns ) ; tap_sm:inst|state[3] ; tap_sm:inst|state[2] ; clk ; clk ; None ; None ; 10.007 ns ; +; N/A ; 93.52 MHz ( period = 10.693 ns ) ; tap_sm:inst|state[2] ; tap_sm:inst|tck ; clk ; clk ; None ; None ; 9.984 ns ; +; N/A ; 93.58 MHz ( period = 10.686 ns ) ; tap_sm:inst|state[0] ; tap_sm:inst|state[1] ; clk ; clk ; None ; None ; 9.977 ns ; +; N/A ; 93.62 MHz ( period = 10.682 ns ) ; serializer:inst2|count[1] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 9.973 ns ; +; N/A ; 93.63 MHz ( period = 10.680 ns ) ; serializer:inst2|ssm[0] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 9.971 ns ; +; N/A ; 93.66 MHz ( period = 10.677 ns ) ; serializer:inst2|ssm[0] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 9.968 ns ; +; N/A ; 93.67 MHz ( period = 10.676 ns ) ; serializer:inst2|count[3] ; serializer:inst2|tms ; clk ; clk ; None ; None ; 9.967 ns ; +; N/A ; 93.67 MHz ( period = 10.676 ns ) ; tap_sm:inst|astate[3] ; tap_sm:inst|state[0] ; clk ; clk ; None ; None ; 9.967 ns ; +; N/A ; 93.76 MHz ( period = 10.666 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|wcks ; clk ; clk ; None ; None ; 4.377 ns ; +; N/A ; 93.79 MHz ( period = 10.662 ns ) ; serializer:inst2|count[3] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 9.953 ns ; +; N/A ; 93.84 MHz ( period = 10.656 ns ) ; serializer:inst2|ssm[2] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 9.947 ns ; +; N/A ; 94.00 MHz ( period = 10.638 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|new_state[0] ; clk ; clk ; None ; None ; 9.929 ns ; +; N/A ; 94.07 MHz ( period = 10.630 ns ) ; tap_sm:inst|state[1] ; tap_sm:inst|tms ; clk ; clk ; None ; None ; 9.921 ns ; +; N/A ; 94.09 MHz ( period = 10.628 ns ) ; serializer:inst2|state[0] ; serializer:inst2|count[0] ; clk ; clk ; None ; None ; 9.919 ns ; +; N/A ; 94.09 MHz ( period = 10.628 ns ) ; serializer:inst2|rbyte[5] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 9.919 ns ; +; N/A ; 94.22 MHz ( period = 10.614 ns ) ; serializer:inst2|count[1] ; serializer:inst2|tms ; clk ; clk ; None ; None ; 9.905 ns ; +; N/A ; 94.34 MHz ( period = 10.600 ns ) ; serializer:inst2|count[1] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 9.891 ns ; +; N/A ; 94.57 MHz ( period = 10.574 ns ) ; serializer:inst2|ssm[2] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 9.865 ns ; +; N/A ; 94.73 MHz ( period = 10.556 ns ) ; serializer:inst2|ssm[2] ; serializer:inst2|rbyte[0] ; clk ; clk ; None ; None ; 9.847 ns ; +; N/A ; 95.34 MHz ( period = 10.489 ns ) ; serializer:inst2|rbyte[3] ; serializer:inst2|count[3] ; clk ; clk ; None ; None ; 9.780 ns ; +; N/A ; 95.46 MHz ( period = 10.476 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|rbyte[4] ; clk ; clk ; None ; None ; 9.767 ns ; +; N/A ; 95.46 MHz ( period = 10.476 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|rbyte[2] ; clk ; clk ; None ; None ; 9.767 ns ; +; N/A ; 95.46 MHz ( period = 10.476 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|rbyte[3] ; clk ; clk ; None ; None ; 9.767 ns ; +; N/A ; 95.61 MHz ( period = 10.459 ns ) ; serializer:inst2|rbyte[1] ; serializer:inst2|count[0] ; clk ; clk ; None ; None ; 9.750 ns ; +; N/A ; 95.66 MHz ( period = 10.454 ns ) ; serializer:inst2|count[2] ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 9.745 ns ; +; N/A ; 95.70 MHz ( period = 10.449 ns ) ; serializer:inst2|count[2] ; serializer:inst2|ssm[0] ; clk ; clk ; None ; None ; 9.740 ns ; +; N/A ; 95.85 MHz ( period = 10.433 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|count[1] ; clk ; clk ; None ; None ; 4.144 ns ; +; N/A ; 95.85 MHz ( period = 10.433 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|count[0] ; clk ; clk ; None ; None ; 4.144 ns ; +; N/A ; 95.85 MHz ( period = 10.433 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|count[4] ; clk ; clk ; None ; None ; 4.144 ns ; +; N/A ; 95.85 MHz ( period = 10.433 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|count[6] ; clk ; clk ; None ; None ; 4.144 ns ; +; N/A ; 95.85 MHz ( period = 10.433 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|count[5] ; clk ; clk ; None ; None ; 4.144 ns ; +; N/A ; 95.85 MHz ( period = 10.433 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|count[3] ; clk ; clk ; None ; None ; 4.144 ns ; +; N/A ; 95.85 MHz ( period = 10.433 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|count[2] ; clk ; clk ; None ; None ; 4.144 ns ; +; N/A ; 95.85 MHz ( period = 10.433 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|cclk[3] ; clk ; clk ; None ; None ; 4.144 ns ; +; N/A ; 95.85 MHz ( period = 10.433 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|cclk[2] ; clk ; clk ; None ; None ; 4.144 ns ; +; N/A ; 95.90 MHz ( period = 10.428 ns ) ; tap_sm:inst|state[3] ; tap_sm:inst|state[0] ; clk ; clk ; None ; None ; 9.719 ns ; +; N/A ; 95.93 MHz ( period = 10.424 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|cclk[1] ; clk ; clk ; None ; None ; 4.135 ns ; +; N/A ; 95.93 MHz ( period = 10.424 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|cclk[4] ; clk ; clk ; None ; None ; 4.135 ns ; +; N/A ; 95.93 MHz ( period = 10.424 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|cclk[6] ; clk ; clk ; None ; None ; 4.135 ns ; +; N/A ; 95.93 MHz ( period = 10.424 ns ) ; serializer:inst2|cks[1] ; clock_mux:inst1|cclk[5] ; clk ; clk ; None ; None ; 4.135 ns ; +; N/A ; 96.26 MHz ( period = 10.388 ns ) ; serializer:inst2|rbyte[0] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 9.679 ns ; +; N/A ; 96.44 MHz ( period = 10.369 ns ) ; tap_sm:inst|state[3] ; tap_sm:inst|tms ; clk ; clk ; None ; None ; 9.660 ns ; +; N/A ; 97.03 MHz ( period = 10.306 ns ) ; serializer:inst2|rbyte[0] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 9.597 ns ; +; N/A ; 97.21 MHz ( period = 10.287 ns ) ; tap_sm:inst|state[0] ; tap_sm:inst|state[3] ; clk ; clk ; None ; None ; 9.578 ns ; +; N/A ; 97.67 MHz ( period = 10.239 ns ) ; serializer:inst2|ssm[0] ; serializer:inst2|count[3] ; clk ; clk ; None ; None ; 9.530 ns ; +; N/A ; 97.84 MHz ( period = 10.221 ns ) ; serializer:inst2|state[0] ; serializer:inst2|count[2] ; clk ; clk ; None ; None ; 9.512 ns ; +; N/A ; 98.19 MHz ( period = 10.184 ns ) ; tap_sm:inst|astate[1] ; tap_sm:inst|state[3] ; clk ; clk ; None ; None ; 9.475 ns ; +; N/A ; 98.22 MHz ( period = 10.181 ns ) ; tap_sm:inst|wrk ; serializer:inst2|new_state[0] ; clk ; clk ; None ; None ; 9.472 ns ; +; N/A ; 98.23 MHz ( period = 10.180 ns ) ; tap_sm:inst|state[0] ; tap_sm:inst|state[2] ; clk ; clk ; None ; None ; 9.471 ns ; +; N/A ; 98.63 MHz ( period = 10.139 ns ) ; serializer:inst2|state[0] ; serializer:inst2|count[1] ; clk ; clk ; None ; None ; 9.430 ns ; +; N/A ; 98.76 MHz ( period = 10.126 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|count[0] ; clk ; clk ; None ; None ; 9.417 ns ; +; N/A ; 98.78 MHz ( period = 10.124 ns ) ; serializer:inst2|sclk ; serializer:inst2|rbyte[4] ; clk ; clk ; None ; None ; 9.415 ns ; +; N/A ; 98.78 MHz ( period = 10.124 ns ) ; serializer:inst2|sclk ; serializer:inst2|rbyte[2] ; clk ; clk ; None ; None ; 9.415 ns ; +; N/A ; 98.78 MHz ( period = 10.124 ns ) ; serializer:inst2|sclk ; serializer:inst2|rbyte[3] ; clk ; clk ; None ; None ; 9.415 ns ; +; N/A ; 98.79 MHz ( period = 10.122 ns ) ; serializer:inst2|ssm[1] ; serializer:inst2|count[3] ; clk ; clk ; None ; None ; 9.413 ns ; +; N/A ; 98.98 MHz ( period = 10.103 ns ) ; tap_sm:inst|state[2] ; tap_sm:inst|state[3] ; clk ; clk ; None ; None ; 9.394 ns ; +; N/A ; 99.27 MHz ( period = 10.074 ns ) ; serializer:inst2|instr ; serializer:inst2|new_state[0] ; clk ; clk ; None ; None ; 9.365 ns ; +; N/A ; 99.45 MHz ( period = 10.055 ns ) ; tap_sm:inst|astate[1] ; tap_sm:inst|state[2] ; clk ; clk ; None ; None ; 9.346 ns ; +; N/A ; 99.47 MHz ( period = 10.053 ns ) ; serializer:inst2|sclk ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 9.344 ns ; +; N/A ; 99.50 MHz ( period = 10.050 ns ) ; serializer:inst2|sclk ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 9.341 ns ; +; N/A ; 99.69 MHz ( period = 10.031 ns ) ; serializer:inst2|count[0] ; serializer:inst2|ssm[3] ; clk ; clk ; None ; None ; 9.322 ns ; +; N/A ; 99.72 MHz ( period = 10.028 ns ) ; serializer:inst2|count[0] ; serializer:inst2|ssm[1] ; clk ; clk ; None ; None ; 9.319 ns ; +; N/A ; 99.97 MHz ( period = 10.003 ns ) ; serializer:inst2|count[3] ; serializer:inst2|count[3] ; clk ; clk ; None ; None ; 9.294 ns ; +; N/A ; 100.04 MHz ( period = 9.996 ns ) ; tap_sm:inst|state[2] ; tap_sm:inst|state[2] ; clk ; clk ; None ; None ; 9.287 ns ; +; N/A ; 100.15 MHz ( period = 9.985 ns ) ; serializer:inst2|ssm[3] ; serializer:inst2|tms ; clk ; clk ; None ; None ; 9.276 ns ; +; N/A ; 100.56 MHz ( period = 9.944 ns ) ; tap_sm:inst|state[2] ; tap_sm:inst|state[1] ; clk ; clk ; None ; None ; 9.235 ns ; +; N/A ; 100.57 MHz ( period = 9.943 ns ) ; serializer:inst2|ssm[1] ; serializer:inst2|new_state[0] ; clk ; clk ; None ; None ; 9.234 ns ; +; N/A ; 100.59 MHz ( period = 9.941 ns ) ; serializer:inst2|count[1] ; serializer:inst2|count[3] ; clk ; clk ; None ; None ; 9.232 ns ; +; N/A ; 100.91 MHz ( period = 9.910 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|count[1] ; clk ; clk ; None ; None ; 3.621 ns ; +; N/A ; 100.91 MHz ( period = 9.910 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|count[0] ; clk ; clk ; None ; None ; 3.621 ns ; +; N/A ; 100.91 MHz ( period = 9.910 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|count[4] ; clk ; clk ; None ; None ; 3.621 ns ; +; N/A ; 100.91 MHz ( period = 9.910 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|count[6] ; clk ; clk ; None ; None ; 3.621 ns ; +; N/A ; 100.91 MHz ( period = 9.910 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|count[5] ; clk ; clk ; None ; None ; 3.621 ns ; +; N/A ; 100.91 MHz ( period = 9.910 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|count[3] ; clk ; clk ; None ; None ; 3.621 ns ; +; N/A ; 100.91 MHz ( period = 9.910 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|count[2] ; clk ; clk ; None ; None ; 3.621 ns ; +; N/A ; 100.91 MHz ( period = 9.910 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|cclk[3] ; clk ; clk ; None ; None ; 3.621 ns ; +; N/A ; 100.91 MHz ( period = 9.910 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|cclk[2] ; clk ; clk ; None ; None ; 3.621 ns ; +; N/A ; 100.92 MHz ( period = 9.909 ns ) ; serializer:inst2|count[2] ; serializer:inst2|count[3] ; clk ; clk ; None ; None ; 9.200 ns ; +; N/A ; 100.99 MHz ( period = 9.902 ns ) ; serializer:inst2|sclk ; serializer:inst2|ssm[2] ; clk ; clk ; None ; None ; 9.193 ns ; +; N/A ; 101.00 MHz ( period = 9.901 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|cclk[1] ; clk ; clk ; None ; None ; 3.612 ns ; +; N/A ; 101.00 MHz ( period = 9.901 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|cclk[4] ; clk ; clk ; None ; None ; 3.612 ns ; +; N/A ; 101.00 MHz ( period = 9.901 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|cclk[6] ; clk ; clk ; None ; None ; 3.612 ns ; +; N/A ; 101.00 MHz ( period = 9.901 ns ) ; serializer:inst2|cks[2] ; clock_mux:inst1|cclk[5] ; clk ; clk ; None ; None ; 3.612 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+---------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++------------------------------------------------------------------------------------+ +; tsu ; ++-------+--------------+------------+-------+-----------------------------+----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-------+--------------+------------+-------+-----------------------------+----------+ +; N/A ; None ; 1.440 ns ; txe ; serializer:inst2|ssm[2] ; clk ; +; N/A ; None ; 1.435 ns ; txe ; serializer:inst2|ssm[0] ; clk ; +; N/A ; None ; 1.052 ns ; rxf ; serializer:inst2|ssm[3] ; clk ; +; N/A ; None ; 1.049 ns ; rxf ; serializer:inst2|ssm[1] ; clk ; +; N/A ; None ; 0.499 ns ; rxf ; serializer:inst2|ssm[2] ; clk ; +; N/A ; None ; 0.494 ns ; rxf ; serializer:inst2|ssm[0] ; clk ; +; N/A ; None ; 0.403 ns ; db[4] ; serializer:inst2|rbyte[4] ; clk ; +; N/A ; None ; 0.085 ns ; txe ; serializer:inst2|db[1]~en ; clk ; +; N/A ; None ; 0.085 ns ; txe ; serializer:inst2|db[1]~reg0 ; clk ; +; N/A ; None ; 0.085 ns ; txe ; serializer:inst2|db[0]~reg0 ; clk ; +; N/A ; None ; 0.085 ns ; txe ; serializer:inst2|db[2]~en ; clk ; +; N/A ; None ; 0.085 ns ; txe ; serializer:inst2|db[2]~reg0 ; clk ; +; N/A ; None ; 0.052 ns ; txe ; serializer:inst2|ssm[3] ; clk ; +; N/A ; None ; 0.049 ns ; txe ; serializer:inst2|ssm[1] ; clk ; +; N/A ; None ; 0.024 ns ; rxf ; serializer:inst2|rd ; clk ; +; N/A ; None ; 0.017 ns ; txe ; serializer:inst2|db[0]~en ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[3]~en ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[3]~reg0 ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[6]~en ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[6]~reg0 ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[5]~en ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[5]~reg0 ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[7]~en ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[7]~reg0 ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[4]~en ; clk ; +; N/A ; None ; 0.015 ns ; txe ; serializer:inst2|db[4]~reg0 ; clk ; +; N/A ; None ; -0.024 ns ; db[7] ; serializer:inst2|rbyte[7] ; clk ; +; N/A ; None ; -0.419 ns ; db[0] ; serializer:inst2|rbyte[0] ; clk ; +; N/A ; None ; -1.527 ns ; db[2] ; serializer:inst2|rbyte[2] ; clk ; +; N/A ; None ; -2.840 ns ; tdo ; serializer:inst2|shift[0] ; clk ; +; N/A ; None ; -2.878 ns ; db[3] ; serializer:inst2|rbyte[3] ; clk ; +; N/A ; None ; -3.308 ns ; tdo ; serializer:inst2|shift[7] ; clk ; +; N/A ; None ; -3.507 ns ; db[1] ; serializer:inst2|rbyte[1] ; clk ; +; N/A ; None ; -3.548 ns ; db[5] ; serializer:inst2|rbyte[5] ; clk ; +; N/A ; None ; -3.639 ns ; db[6] ; serializer:inst2|rbyte[6] ; clk ; ++-------+--------------+------------+-------+-----------------------------+----------+ + + ++-----------------------------------------------------------------------------------------------+ +; tco ; ++-------+--------------+------------+-------------------------------+--------------+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++-------+--------------+------------+-------------------------------+--------------+------------+ +; N/A ; None ; 15.899 ns ; tap_sm:inst|tms ; tms ; clk ; +; N/A ; None ; 15.536 ns ; serializer:inst2|tms ; tms ; clk ; +; N/A ; None ; 15.296 ns ; serializer:inst2|new_state[3] ; new_state[3] ; clk ; +; N/A ; None ; 14.776 ns ; tap_sm:inst|sm[0] ; sm[0] ; clk ; +; N/A ; None ; 14.761 ns ; serializer:inst2|tck ; tck ; clk ; +; N/A ; None ; 14.634 ns ; serializer:inst2|wr ; wr ; clk ; +; N/A ; None ; 14.616 ns ; tap_sm:inst|sm[2] ; sm[2] ; clk ; +; N/A ; None ; 14.561 ns ; serializer:inst2|rd ; rd ; clk ; +; N/A ; None ; 14.494 ns ; serializer:inst2|new_state[1] ; new_state[1] ; clk ; +; N/A ; None ; 14.479 ns ; serializer:inst2|db[0]~reg0 ; db[0] ; clk ; +; N/A ; None ; 14.409 ns ; serializer:inst2|db[7]~reg0 ; db[7] ; clk ; +; N/A ; None ; 14.247 ns ; tap_sm:inst|tck ; tck ; clk ; +; N/A ; None ; 14.020 ns ; serializer:inst2|tdi ; tdi ; clk ; +; N/A ; None ; 13.981 ns ; serializer:inst2|db[3]~reg0 ; db[3] ; clk ; +; N/A ; None ; 13.927 ns ; serializer:inst2|db[4]~reg0 ; db[4] ; clk ; +; N/A ; None ; 13.923 ns ; serializer:inst2|db[5]~reg0 ; db[5] ; clk ; +; N/A ; None ; 13.911 ns ; serializer:inst2|db[6]~reg0 ; db[6] ; clk ; +; N/A ; None ; 13.911 ns ; serializer:inst2|new_state[2] ; new_state[2] ; clk ; +; N/A ; None ; 13.845 ns ; serializer:inst2|trst ; trst ; clk ; +; N/A ; None ; 13.816 ns ; tap_sm:inst|sm[3] ; sm[3] ; clk ; +; N/A ; None ; 13.307 ns ; serializer:inst2|db[7]~en ; db[7] ; clk ; +; N/A ; None ; 12.869 ns ; serializer:inst2|db[4]~en ; db[4] ; clk ; +; N/A ; None ; 12.834 ns ; serializer:inst2|db[3]~en ; db[3] ; clk ; +; N/A ; None ; 12.794 ns ; tap_sm:inst|wrk ; wrk ; clk ; +; N/A ; None ; 12.791 ns ; serializer:inst2|db[0]~en ; db[0] ; clk ; +; N/A ; None ; 12.782 ns ; serializer:inst2|db[6]~en ; db[6] ; clk ; +; N/A ; None ; 12.767 ns ; serializer:inst2|db[5]~en ; db[5] ; clk ; +; N/A ; None ; 12.747 ns ; tap_sm:inst|sm[1] ; sm[1] ; clk ; +; N/A ; None ; 12.733 ns ; serializer:inst2|db[1]~reg0 ; db[1] ; clk ; +; N/A ; None ; 12.732 ns ; serializer:inst2|new_state[0] ; new_state[0] ; clk ; +; N/A ; None ; 12.727 ns ; serializer:inst2|db[2]~reg0 ; db[2] ; clk ; +; N/A ; None ; 12.676 ns ; serializer:inst2|db[2]~en ; db[2] ; clk ; +; N/A ; None ; 12.668 ns ; serializer:inst2|db[1]~en ; db[1] ; clk ; +; N/A ; None ; 8.344 ns ; clock_mux:inst1|wcks ; wcks ; clk ; ++-------+--------------+------------+-------------------------------+--------------+------------+ + + ++------------------------------------------------------------------------------------------+ +; th ; ++---------------+-------------+-----------+-------+-----------------------------+----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++---------------+-------------+-----------+-------+-----------------------------+----------+ +; N/A ; None ; 4.193 ns ; db[6] ; serializer:inst2|rbyte[6] ; clk ; +; N/A ; None ; 4.102 ns ; db[5] ; serializer:inst2|rbyte[5] ; clk ; +; N/A ; None ; 4.061 ns ; db[1] ; serializer:inst2|rbyte[1] ; clk ; +; N/A ; None ; 3.862 ns ; tdo ; serializer:inst2|shift[7] ; clk ; +; N/A ; None ; 3.432 ns ; db[3] ; serializer:inst2|rbyte[3] ; clk ; +; N/A ; None ; 3.394 ns ; tdo ; serializer:inst2|shift[0] ; clk ; +; N/A ; None ; 2.081 ns ; db[2] ; serializer:inst2|rbyte[2] ; clk ; +; N/A ; None ; 0.973 ns ; db[0] ; serializer:inst2|rbyte[0] ; clk ; +; N/A ; None ; 0.578 ns ; db[7] ; serializer:inst2|rbyte[7] ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[3]~en ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[3]~reg0 ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[6]~en ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[6]~reg0 ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[5]~en ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[5]~reg0 ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[7]~en ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[7]~reg0 ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[4]~en ; clk ; +; N/A ; None ; 0.539 ns ; txe ; serializer:inst2|db[4]~reg0 ; clk ; +; N/A ; None ; 0.537 ns ; txe ; serializer:inst2|db[0]~en ; clk ; +; N/A ; None ; 0.530 ns ; rxf ; serializer:inst2|rd ; clk ; +; N/A ; None ; 0.505 ns ; txe ; serializer:inst2|ssm[1] ; clk ; +; N/A ; None ; 0.502 ns ; txe ; serializer:inst2|ssm[3] ; clk ; +; N/A ; None ; 0.469 ns ; txe ; serializer:inst2|db[1]~en ; clk ; +; N/A ; None ; 0.469 ns ; txe ; serializer:inst2|db[1]~reg0 ; clk ; +; N/A ; None ; 0.469 ns ; txe ; serializer:inst2|db[0]~reg0 ; clk ; +; N/A ; None ; 0.469 ns ; txe ; serializer:inst2|db[2]~en ; clk ; +; N/A ; None ; 0.469 ns ; txe ; serializer:inst2|db[2]~reg0 ; clk ; +; N/A ; None ; 0.242 ns ; rxf ; serializer:inst2|ssm[0] ; clk ; +; N/A ; None ; 0.151 ns ; db[4] ; serializer:inst2|rbyte[4] ; clk ; +; N/A ; None ; 0.055 ns ; rxf ; serializer:inst2|ssm[2] ; clk ; +; N/A ; None ; -0.495 ns ; rxf ; serializer:inst2|ssm[1] ; clk ; +; N/A ; None ; -0.498 ns ; rxf ; serializer:inst2|ssm[3] ; clk ; +; N/A ; None ; -0.699 ns ; txe ; serializer:inst2|ssm[0] ; clk ; +; N/A ; None ; -0.886 ns ; txe ; serializer:inst2|ssm[2] ; clk ; ++---------------+-------------+-----------+-------+-----------------------------+----------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Jun 02 16:01:14 2010 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG +Info: Started post-fitting delay annotation +Info: Delay annotation completed successfully +Warning: Found pins functioning as undefined clocks and/or memory enables + Info: Assuming node "clk" is an undefined clock +Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew + Info: Detected ripple clock "clock_mux:inst1|wcks" as buffer +Info: Clock "clk" has Internal fmax of 78.31 MHz between source register "serializer:inst2|cks[0]" and destination register "clock_mux:inst1|wcks" (period= 12.77 ns) + Info: + Longest register to register delay is 6.481 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y5_N5; Fanout = 5; REG Node = 'serializer:inst2|cks[0]' + Info: 2: + IC(2.558 ns) + CELL(0.740 ns) = 3.298 ns; Loc. = LC_X9_Y5_N8; Fanout = 1; COMB Node = 'clock_mux:inst1|Mux0~3' + Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 3.803 ns; Loc. = LC_X9_Y5_N9; Fanout = 1; COMB Node = 'clock_mux:inst1|Mux0~4' + Info: 4: + IC(0.729 ns) + CELL(0.200 ns) = 4.732 ns; Loc. = LC_X9_Y5_N7; Fanout = 1; COMB Node = 'clock_mux:inst1|Mux0~2' + Info: 5: + IC(1.158 ns) + CELL(0.591 ns) = 6.481 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1|wcks' + Info: Total cell delay = 1.731 ns ( 26.71 % ) + Info: Total interconnect delay = 4.750 ns ( 73.29 % ) + Info: - Smallest clock skew is -5.580 ns + Info: + Shortest clock path from clock "clk" to destination register is 3.681 ns + Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk' + Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1|wcks' + Info: Total cell delay = 2.081 ns ( 56.53 % ) + Info: Total interconnect delay = 1.600 ns ( 43.47 % ) + Info: - Longest clock path from clock "clk" to source register is 9.261 ns + Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk' + Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1|wcks' + Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X7_Y5_N5; Fanout = 5; REG Node = 'serializer:inst2|cks[0]' + Info: Total cell delay = 3.375 ns ( 36.44 % ) + Info: Total interconnect delay = 5.886 ns ( 63.56 % ) + Info: + Micro clock to output delay of source is 0.376 ns + Info: + Micro setup delay of destination is 0.333 ns +Info: tsu for register "serializer:inst2|ssm[2]" (data pin = "txe", clock pin = "clk") is 1.440 ns + Info: + Longest pin to register delay is 10.368 ns + Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_38; Fanout = 3; PIN Node = 'txe' + Info: 2: + IC(4.540 ns) + CELL(0.200 ns) = 5.872 ns; Loc. = LC_X5_Y7_N9; Fanout = 1; COMB Node = 'serializer:inst2|ssm[2]~0' + Info: 3: + IC(0.711 ns) + CELL(0.200 ns) = 6.783 ns; Loc. = LC_X5_Y7_N6; Fanout = 1; COMB Node = 'serializer:inst2|ssm[2]~1' + Info: 4: + IC(0.789 ns) + CELL(0.511 ns) = 8.083 ns; Loc. = LC_X5_Y7_N3; Fanout = 2; COMB Node = 'serializer:inst2|ssm[2]~7' + Info: 5: + IC(0.741 ns) + CELL(0.200 ns) = 9.024 ns; Loc. = LC_X5_Y7_N8; Fanout = 2; COMB Node = 'serializer:inst2|ssm[0]~9' + Info: 6: + IC(0.753 ns) + CELL(0.591 ns) = 10.368 ns; Loc. = LC_X5_Y7_N0; Fanout = 20; REG Node = 'serializer:inst2|ssm[2]' + Info: Total cell delay = 2.834 ns ( 27.33 % ) + Info: Total interconnect delay = 7.534 ns ( 72.67 % ) + Info: + Micro setup delay of destination is 0.333 ns + Info: - Shortest clock path from clock "clk" to destination register is 9.261 ns + Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk' + Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1|wcks' + Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X5_Y7_N0; Fanout = 20; REG Node = 'serializer:inst2|ssm[2]' + Info: Total cell delay = 3.375 ns ( 36.44 % ) + Info: Total interconnect delay = 5.886 ns ( 63.56 % ) +Info: tco from clock "clk" to destination pin "tms" through register "tap_sm:inst|tms" is 15.899 ns + Info: + Longest clock path from clock "clk" to source register is 9.261 ns + Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk' + Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1|wcks' + Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X9_Y7_N7; Fanout = 5; REG Node = 'tap_sm:inst|tms' + Info: Total cell delay = 3.375 ns ( 36.44 % ) + Info: Total interconnect delay = 5.886 ns ( 63.56 % ) + Info: + Micro clock to output delay of source is 0.376 ns + Info: + Longest register to pin delay is 6.262 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N7; Fanout = 5; REG Node = 'tap_sm:inst|tms' + Info: 2: + IC(0.966 ns) + CELL(0.511 ns) = 1.477 ns; Loc. = LC_X9_Y7_N1; Fanout = 1; COMB Node = 'inst4' + Info: 3: + IC(2.463 ns) + CELL(2.322 ns) = 6.262 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'tms' + Info: Total cell delay = 2.833 ns ( 45.24 % ) + Info: Total interconnect delay = 3.429 ns ( 54.76 % ) +Info: th for register "serializer:inst2|rbyte[6]" (data pin = "db[6]", clock pin = "clk") is 4.193 ns + Info: + Longest clock path from clock "clk" to destination register is 9.261 ns + Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk' + Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1|wcks' + Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X7_Y7_N3; Fanout = 7; REG Node = 'serializer:inst2|rbyte[6]' + Info: Total cell delay = 3.375 ns ( 36.44 % ) + Info: Total interconnect delay = 5.886 ns ( 63.56 % ) + Info: + Micro hold delay of destination is 0.221 ns + Info: - Shortest pin to register delay is 5.289 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_34; Fanout = 1; PIN Node = 'db[6]' + Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X6_Y3_N2; Fanout = 1; COMB Node = 'db~1' + Info: 3: + IC(3.877 ns) + CELL(0.280 ns) = 5.289 ns; Loc. = LC_X7_Y7_N3; Fanout = 7; REG Node = 'serializer:inst2|rbyte[6]' + Info: Total cell delay = 1.412 ns ( 26.70 % ) + Info: Total interconnect delay = 3.877 ns ( 73.30 % ) +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 126 megabytes + Info: Processing ended: Wed Jun 02 16:01:15 2010 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.qpf =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.qpf (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.qpf (revision 18) @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +# Date created = 15:56:20 June 02, 2010 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.1" +DATE = "15:56:20 June 02, 2010" + +# Revisions + +PROJECT_REVISION = "Open_JTAG" Index: trunk/OpenJTAG/Quartus_II/tap_sm.bsf =================================================================== --- trunk/OpenJTAG/Quartus_II/tap_sm.bsf (nonexistent) +++ trunk/OpenJTAG/Quartus_II/tap_sm.bsf (revision 18) @@ -0,0 +1,78 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2007 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 184 144) + (text "tap_sm" (rect 5 0 41 12)(font "Arial" )) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 14 12)(font "Arial" )) + (text "clk" (rect 21 27 35 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "rst" (rect 0 0 12 12)(font "Arial" )) + (text "rst" (rect 21 43 33 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "new_state[3..0]" (rect 0 0 75 12)(font "Arial" )) + (text "new_state[3..0]" (rect 21 59 96 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 168 32) + (output) + (text "tck" (rect 0 0 15 12)(font "Arial" )) + (text "tck" (rect 132 27 147 39)(font "Arial" )) + (line (pt 168 32)(pt 152 32)(line_width 1)) + ) + (port + (pt 168 48) + (output) + (text "tms" (rect 0 0 18 12)(font "Arial" )) + (text "tms" (rect 129 43 147 55)(font "Arial" )) + (line (pt 168 48)(pt 152 48)(line_width 1)) + ) + (port + (pt 168 64) + (output) + (text "wrk" (rect 0 0 16 12)(font "Arial" )) + (text "wrk" (rect 131 59 147 71)(font "Arial" )) + (line (pt 168 64)(pt 152 64)(line_width 1)) + ) + (port + (pt 168 80) + (output) + (text "sm[3..0]" (rect 0 0 41 12)(font "Arial" )) + (text "sm[3..0]" (rect 106 75 147 87)(font "Arial" )) + (line (pt 168 80)(pt 152 80)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 152 112)(line_width 1)) + ) +) Index: trunk/OpenJTAG/Quartus_II/clock_mux.bsf =================================================================== --- trunk/OpenJTAG/Quartus_II/clock_mux.bsf (nonexistent) +++ trunk/OpenJTAG/Quartus_II/clock_mux.bsf (revision 18) @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2007 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 136 112) + (text "clock_mux" (rect 5 0 58 12)(font "Arial" )) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 14 12)(font "Arial" )) + (text "clk" (rect 21 27 35 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "cks[2..0]" (rect 0 0 43 12)(font "Arial" )) + (text "cks[2..0]" (rect 21 43 64 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 120 32) + (output) + (text "wcks" (rect 0 0 24 12)(font "Arial" )) + (text "wcks" (rect 75 27 99 39)(font "Arial" )) + (line (pt 120 32)(pt 104 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 104 80)(line_width 1)) + ) +) Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.qsf =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.qsf (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.qsf (revision 18) @@ -0,0 +1,58 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +# Date created = 15:56:20 June 02, 2010 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Open_JTAG_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX II" +set_global_assignment -name DEVICE EPM570T100C5 +set_global_assignment -name TOP_LEVEL_ENTITY Open_JTAG +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:56:20 JUNE 02, 2010" +set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V +set_global_assignment -name VECTOR_WAVEFORM_FILE Open_JTAG.vwf +set_global_assignment -name VHDL_FILE tap_sm.vhd +set_global_assignment -name VHDL_FILE clock_mux.vhd +set_global_assignment -name VHDL_FILE serializer.vhd +set_global_assignment -name BDF_FILE Open_JTAG.bdf +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.bdf =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.bdf (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.bdf (revision 18) @@ -0,0 +1,778 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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64) + (input) + (text "rxf" (rect 0 0 14 12)(font "Arial" )) + (text "rxf" (rect 21 59 35 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "pwr" (rect 0 0 16 12)(font "Arial" )) + (text "pwr" (rect 21 75 37 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "rst" (rect 0 0 12 12)(font "Arial" )) + (text "rst" (rect 21 91 33 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "wrk" (rect 0 0 16 12)(font "Arial" )) + (text "wrk" (rect 21 107 37 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "tdo" (rect 0 0 15 12)(font "Arial" )) + (text "tdo" (rect 21 123 36 135)(font "Arial" )) + (line (pt 0 128)(pt 16 128)(line_width 1)) + ) + (port + (pt 144 32) + (output) + (text "wr" (rect 0 0 10 12)(font "Arial" )) + (text "wr" (rect 113 27 123 39)(font "Arial" )) + (line (pt 144 32)(pt 128 32)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "rd" (rect 0 0 9 12)(font "Arial" )) + (text "rd" (rect 114 43 123 55)(font "Arial" )) + (line (pt 144 48)(pt 128 48)(line_width 1)) + ) + (port + (pt 144 64) + (output) + (text "siwu" (rect 0 0 21 12)(font "Arial" )) + (text "siwu" (rect 102 59 123 71)(font "Arial" )) + (line (pt 144 64)(pt 128 64)(line_width 1)) + ) + (port + (pt 144 96) + (output) + (text "tck" (rect 0 0 15 12)(font "Arial" )) + (text "tck" (rect 108 91 123 103)(font "Arial" )) + (line (pt 144 96)(pt 128 96)(line_width 1)) + ) + (port + (pt 144 112) + (output) + (text "tms" (rect 0 0 18 12)(font "Arial" )) + (text "tms" (rect 105 107 123 119)(font "Arial" )) + (line (pt 144 112)(pt 128 112)(line_width 1)) + ) + (port + (pt 144 128) + (output) + (text "tdi" (rect 0 0 11 12)(font "Arial" )) + (text "tdi" (rect 112 123 123 135)(font "Arial" )) + (line (pt 144 128)(pt 128 128)(line_width 1)) + ) + (port + (pt 144 144) + (output) + (text "trst" (rect 0 0 16 12)(font "Arial" )) + (text "trst" (rect 107 139 123 151)(font "Arial" )) + (line (pt 144 144)(pt 128 144)(line_width 1)) + ) + (port + (pt 144 160) + (output) + (text "new_state[3..0]" (rect 0 0 75 12)(font "Arial" )) + (text "new_state[3..0]" (rect 48 155 123 167)(font "Arial" )) + (line (pt 144 160)(pt 128 160)(line_width 3)) + ) + (port + (pt 144 176) + (output) + (text "cks[2..0]" (rect 0 0 43 12)(font "Arial" )) + (text "cks[2..0]" (rect 80 171 123 183)(font "Arial" )) + (line (pt 144 176)(pt 128 176)(line_width 3)) + ) + (port + (pt 144 80) + (bidir) + (text "db[7..0]" (rect 0 0 37 12)(font "Arial" )) + (text "db[7..0]" (rect 86 75 123 87)(font "Arial" )) + (line (pt 144 80)(pt 128 80)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 128 208)(line_width 1)) + ) +) +(connector + (pt 656 176) + (pt 680 176) +) +(connector + (pt 656 224) + (pt 680 224) +) +(connector + (pt 480 56) + (pt 680 56) + (bus) +) +(connector + (pt 480 8) + (pt 568 8) +) +(connector + (pt 568 8) + (pt 568 168) +) +(connector + (pt 568 168) + (pt 592 168) +) +(connector + (pt 480 24) + (pt 552 24) +) +(connector + (pt 552 24) + (pt 552 232) +) +(connector + (pt 552 232) + (pt 592 232) +) +(connector + (pt 520 184) + (pt 592 184) +) +(connector + (pt 536 216) + (pt 592 216) +) +(connector + (pt 496 40) + (pt 496 224) +) +(connector + (pt 496 224) + (pt 248 224) +) +(connector + (pt 480 424) + (pt 480 176) + (bus) +) +(connector + (pt 264 8) + (pt 312 8) +) +(connector + (pt 520 184) + (pt 520 360) +) +(connector + (pt 536 216) + (pt 536 376) +) +(connector + (pt 248 224) + (pt 248 376) +) +(connector + (pt 248 376) + (pt 288 376) +) +(connector + (pt 216 312) + (pt 288 312) +) +(connector + (pt 216 392) + (pt 288 392) +) +(connector + (pt 232 360) + (pt 288 360) +) +(connector + (pt 232 24) + (pt 232 360) +) +(connector + (pt 216 328) + (pt 288 328) +) +(connector + (pt 264 296) + (pt 288 296) +) +(connector + (pt 432 296) + (pt 680 296) +) +(connector + (pt 432 312) + (pt 680 312) +) +(connector + (pt 432 360) + (pt 520 360) +) +(connector + (pt 432 376) + (pt 536 376) +) +(connector + (pt 432 392) + (pt 680 392) +) +(connector + (pt 432 408) + (pt 680 408) +) +(connector + (pt 432 344) + (pt 680 344) + (bus) +) +(connector + (pt 480 176) + (pt 288 176) + (bus) +) +(connector + (pt 288 176) + (pt 288 40) + (bus) +) +(connector + (pt 312 40) + (pt 288 40) + (bus) +) +(connector + (pt 264 656) + (pt 696 656) +) +(connector + (pt 552 584) + (pt 480 584) + (bus) +) +(connector + (pt 480 584) + (pt 480 440) + (bus) +) +(connector + (pt 432 440) + (pt 480 440) + (bus) +) +(connector + (pt 456 568) + (pt 552 568) +) +(connector + (pt 480 40) + (pt 496 40) +) +(connector + (pt 496 40) + (pt 680 40) +) +(connector + (pt 216 24) + (pt 232 24) +) +(connector + (pt 232 24) + (pt 312 24) +) +(connector + (pt 432 424) + (pt 480 424) + (bus) +) +(connector + (pt 480 424) + (pt 680 424) + (bus) +) +(connector + (pt 264 8) + (pt 264 296) +) +(connector + (pt 264 296) + (pt 264 656) +) +(connector + (pt 672 568) + (pt 696 568) +) +(connector + (pt 696 568) + (pt 712 568) +) +(connector + (pt 696 568) + (pt 696 656) +) +(junction (pt 496 40)) +(junction (pt 232 24)) +(junction (pt 480 424)) +(junction (pt 264 296)) +(junction (pt 696 568)) Index: trunk/OpenJTAG/Quartus_II/tap_sm.vhd =================================================================== --- trunk/OpenJTAG/Quartus_II/tap_sm.vhd (nonexistent) +++ trunk/OpenJTAG/Quartus_II/tap_sm.vhd (revision 18) @@ -0,0 +1,286 @@ +-- Created by Ruben H. Mileca - May-16-2010 + + +library ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.all; + +entity tap_sm IS + +-- generic ( +-- new_state: integer range 0 to 15 := 1 +-- ); + + port ( + + clk: in std_logic; -- External 48 MHz oscillator + rst: in std_logic; -- External reset, active high + new_state: in std_logic_vector(3 downto 0); -- New state + tck: out std_logic := '0'; -- TCK Jtag pin + tms: out std_logic := '0'; -- TMS Jtag pin + wrk: out std_logic := '0'; -- SM working + + sm: out std_logic_vector(3 downto 0) -- Test output + + ); + +end tap_sm; + +architecture rtl of tap_sm is + + signal state: integer range 0 to 15 := 0; + signal astate: integer range 0 to 15 := 0; + signal rclk: integer range 0 to 1 := 0; + +begin + + +changestate: process(clk, rst, state) + +begin + + if (rising_edge(clk)) then + if rclk = 1 then + rclk <= 0; + else + rclk <= 1; + end if; + + astate <= to_integer(unsigned(new_state)); + sm <= std_logic_vector(to_unsigned(state, sm'length)); + +-- TAP Change state machine + + if state /= astate then + wrk <= '1'; + if rclk = 1 then + tms <= '0'; + end if; + case state is + when 0 => -- Is in Test Logic Reset + if rclk = 1 then + tms <= '0'; + tck <= '0'; + else + tck <= '1'; + state <= 1; + end if; + when 1 => -- Is in Run Test Idle + if rclk = 1 then + tms <= '1'; + tck <= '0'; + else + tck <= '1'; + state <= 2; + end if; +-- +-- DR way +-- + when 2 => -- Is in Select DR Scan + if rclk = 1 then + if astate > 8 then -- See if go to Select IR Scan + tms <= '1'; + else + tms <= '0'; + end if; + tck <= '0'; + else + if astate > 8 then -- See if go to Select IR Scan + state <= 9; -- Go to Select IR Scan + else + state <= 3; -- Go to Capture DR + end if; + tck <= '1'; + end if; + when 3 => -- Is in Capture DR + if rclk = 1 then + if astate > 4 then -- See if go to Exit-1 DR + tms <= '1'; + else + tms <= '0'; + end if; + tck <= '0'; + else + tck <= '1'; + if astate > 4 then -- See if go to Exit-1 DR + state <= 5; -- Go to Exit-1 DR + else + state <= 4; -- Go to Capture DR + end if; + end if; + when 4 => -- Is in Capture DR + if rclk = 1 then + tms <= '1'; + tck <= '0'; + else + tck <= '1'; + state <= 5; + end if; + when 5 => -- Is in Exit-1 DR + if rclk = 1 then + if astate = 6 then -- See if go to Pause DR + tms <= '0'; + else + tms <= '1'; + end if; + tck <= '0'; + else + tck <= '1'; + if astate = 6 then -- See if go to Pause DR + state <= 6; -- Go to Exit-1 DR + else + state <= 8; -- Go to Capture DR + end if; + end if; + when 6 => -- Is in Pause DR + if rclk = 1 then + tms <= '1'; + tck <= '0'; + else + tck <= '1'; + state <= 7; + end if; + when 7 => -- Is in Exit-2 DR + if rclk = 1 then + if astate = 4 then -- See if go to Shift DR + tms <= '0'; + else + tms <= '1'; + end if; + tck <= '0'; + else + tck <= '1'; + if astate = 4 then -- See if go to Pause DR + state <= 4; -- Go to Pause DR + else + state <= 8; -- Go to Update DR + end if; + end if; + when 8 => -- Is in Exit-2 DR + if rclk = 1 then + if astate > 1 then -- See if go to Select DR Scan + tms <= '1'; + else + tms <= '0'; + end if; + tck <= '0'; + else + tck <= '1'; + if astate > 1 then -- See if go to Select DR Scan + state <= 2; -- Go to Select DR Scan + else + state <= 1; -- Go to Run Test Idle + end if; + end if; +-- +-- IR way +-- + when 9 => -- Is in Select IR Scan + if rclk = 1 then + if astate = 1 then -- See if go to Test Logic Reset + tms <= '1'; + else + tms <= '0'; + end if; + tck <= '0'; + else + tck <= '1'; + if astate = 1 then -- See if go to Test Logic Reset + state <= 1; -- Go to Test Logic Reset + else + state <= 10; -- Go to Capture IR + end if; + end if; + when 10 => -- Is in Capture IR + if rclk = 1 then + if astate = 11 then -- See if go to Shift-IR + tms <= '0'; + else + tms <= '1'; + end if; + tck <= '0'; + else + tck <= '1'; + if astate = 11 then -- See if go to Shift-IR + state <= 11; -- Go to Shift-IR + else + state <= 12; -- Go to Exit 1-IR + end if; + end if; + when 11 => -- Is in Shift-IR + if rclk = 1 then + tms <= '1'; + tck <= '0'; + else + tck <= '1'; + state <= 12; + end if; + when 12 => -- Is in Exit 1-IR + if rclk = 1 then + if astate > 13 then -- See if go to Update-IR + tms <= '1'; + else + tms <= '0'; + end if; + tck <= '0'; + else + tck <= '1'; + if astate > 13 then -- See if go to Update-IR + state <= 15; -- Go to Update-IR + else + state <= 13; -- Go to Pause-IR + end if; + end if; + when 13 => -- Is in Pause-IR + if rclk = 1 then + tms <= '1'; + tck <= '0'; + else + tck <= '1'; + state <= 14; + end if; + when 14 => -- Is in Exit 2-IR + if rclk = 1 then + if astate = 11 then -- See if go to Shift-IR + tms <= '0'; + else + tms <= '0'; + end if; + tck <= '0'; + else + tck <= '1'; + if astate = 11 then -- See if go to Shift-IR + state <= 11; -- Go to Shift-IR + else + state <= 15; -- Go to Update-IR + end if; + end if; + when 15 => -- Is in Update-IR + if rclk = 1 then + if astate > 1 then -- See if go to Select DR-Scan + tms <= '1'; + else + tms <= '0'; + end if; + tck <= '0'; + else + tck <= '1'; + if astate > 1 then -- See if go to Select DR-Scan + state <= 2; -- Go to Update-IR + else + state <= 1; -- Go to Run Test-Idle + end if; + end if; + when others => + tck <= '0'; + tms <= '0'; + end case; + else + astate <= to_integer(unsigned(new_state)); + tck <= '0'; + tms <= '0'; + wrk <= '0'; + end if; + end if; +end process changestate; +end rtl; Index: trunk/OpenJTAG/Quartus_II/clock_mux.vhd =================================================================== --- trunk/OpenJTAG/Quartus_II/clock_mux.vhd (nonexistent) +++ trunk/OpenJTAG/Quartus_II/clock_mux.vhd (revision 18) @@ -0,0 +1,43 @@ +-- Created by Ruben H. Mileca - May-16-2010 + + +library ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.all; + +entity clock_mux IS + + port ( + +-- Internal + + clk: in std_logic; -- External 48 MHz oscillator + cks: in std_logic_vector(2 downto 0) := "000"; -- Clock divider + wcks: out std_logic -- Clock output + ); + +end clock_mux; + +architecture rtl of clock_mux is + + signal count: integer range 0 to 127 := 0; + signal cclk: std_logic_vector(6 downto 0); +begin + + +clock_gen: process(clk, cks) + +begin + + if cks = "000" then + wcks <= clk; + else + if (rising_edge(clk)) then + cclk <= std_logic_vector(to_unsigned(count, cclk'length)); + wcks <= cclk(to_integer(unsigned(cks)) - 1); + count <= count + 1; + end if; + end if; + +end process clock_gen; +end rtl; Index: trunk/OpenJTAG/Quartus_II/incremental_db/compiled_partitions/Open_JTAG.root_partition.map.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Quartus_II/incremental_db/compiled_partitions/Open_JTAG.root_partition.map.kpt =================================================================== --- trunk/OpenJTAG/Quartus_II/incremental_db/compiled_partitions/Open_JTAG.root_partition.map.kpt (nonexistent) +++ trunk/OpenJTAG/Quartus_II/incremental_db/compiled_partitions/Open_JTAG.root_partition.map.kpt (revision 18)
trunk/OpenJTAG/Quartus_II/incremental_db/compiled_partitions/Open_JTAG.root_partition.map.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/OpenJTAG/Quartus_II/incremental_db/README =================================================================== --- trunk/OpenJTAG/Quartus_II/incremental_db/README (nonexistent) +++ trunk/OpenJTAG/Quartus_II/incremental_db/README (revision 18) @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.vwf =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.vwf (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.vwf (revision 18) @@ -0,0 +1,129 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 4000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 100.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("tck") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("tms") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 200; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("tck") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 4000.0; + } +} + +TRANSITION_LIST("tms") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 4000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "tck"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "tms"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; Index: trunk/OpenJTAG/Quartus_II/serializer.vwf =================================================================== --- trunk/OpenJTAG/Quartus_II/serializer.vwf (nonexistent) +++ trunk/OpenJTAG/Quartus_II/serializer.vwf (revision 18) @@ -0,0 +1,851 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2007 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 4000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 100.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("tck") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("tms") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("new_state") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("new_state[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "new_state"; +} + +SIGNAL("new_state[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "new_state"; +} + +SIGNAL("new_state[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "new_state"; +} + +SIGNAL("new_state[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "new_state"; +} + +SIGNAL("sm") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("sm[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sm"; +} + +SIGNAL("sm[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sm"; +} + +SIGNAL("sm[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sm"; +} + +SIGNAL("sm[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sm"; +} + +SIGNAL("db") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = BIDIR; + PARENT = ""; +} + +SIGNAL("db[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "db"; +} + +SIGNAL("db[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "db"; +} + +SIGNAL("db[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "db"; +} + +SIGNAL("db[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "db"; +} + +SIGNAL("db[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "db"; +} + +SIGNAL("db[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "db"; +} + +SIGNAL("db[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "db"; +} + +SIGNAL("db[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = BIDIR; + PARENT = "db"; +} + +SIGNAL("rxf") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("rd") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("tdi") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("tdo") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("txe") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("wr") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 200; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("tck") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 4000.0; + } +} + +TRANSITION_LIST("tms") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 4000.0; + } +} + +TRANSITION_LIST("new_state[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 4000.0; + } +} + +TRANSITION_LIST("new_state[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 4000.0; + } +} + +TRANSITION_LIST("new_state[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 4000.0; + } +} + +TRANSITION_LIST("new_state[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 4000.0; + } +} + +TRANSITION_LIST("sm[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 4000.0; + } +} + +TRANSITION_LIST("sm[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 4000.0; + } +} + +TRANSITION_LIST("sm[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 4000.0; + } +} + +TRANSITION_LIST("sm[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 4000.0; + } +} + +TRANSITION_LIST("db[7]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 73.431; + LEVEL 1 FOR 138.043; + LEVEL Z FOR 3788.526; + } +} + +TRANSITION_LIST("db[6]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 73.431; + LEVEL 1 FOR 138.043; + LEVEL Z FOR 3788.526; + } +} + +TRANSITION_LIST("db[5]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 73.431; + LEVEL 1 FOR 138.043; + LEVEL Z FOR 3788.526; + } +} + +TRANSITION_LIST("db[4]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 73.431; + LEVEL 1 FOR 138.043; + LEVEL Z FOR 3788.526; + } +} + +TRANSITION_LIST("db[3]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 73.431; + LEVEL 0 FOR 81.244; + LEVEL 1 FOR 56.799; + LEVEL Z FOR 3788.526; + } +} + +TRANSITION_LIST("db[2]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 73.431; + LEVEL 0 FOR 81.244; + LEVEL 1 FOR 56.799; + LEVEL Z FOR 3788.526; + } +} + +TRANSITION_LIST("db[1]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 73.431; + LEVEL 1 FOR 138.043; + LEVEL Z FOR 3788.526; + } +} + +TRANSITION_LIST("db[0]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 73.431; + LEVEL 0 FOR 138.043; + LEVEL Z FOR 3788.526; + } +} + +TRANSITION_LIST("rxf") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 74.92; + LEVEL 0 FOR 134.981; + LEVEL 1 FOR 3790.099; + } +} + +TRANSITION_LIST("rd") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 4000.0; + } +} + +TRANSITION_LIST("tdi") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 4000.0; + } +} + +TRANSITION_LIST("tdo") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 239.939; + LEVEL 1 FOR 78.973; + LEVEL 0 FOR 45.272; + LEVEL 1 FOR 38.733; + LEVEL 0 FOR 3597.083; + } + } +} + +TRANSITION_LIST("txe") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 549.295; + LEVEL 0 FOR 69.416; + LEVEL 1 FOR 3381.289; + } +} + +TRANSITION_LIST("wr") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 4000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "tck"; + EXPAND_STATUS = COLLAPSED; + RADIX = ASCII; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "tms"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "tdi"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "tdo"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "rxf"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "rd"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "txe"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "wr"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "new_state"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 9; + TREE_LEVEL = 0; + CHILDREN = 10, 11, 12, 13; +} + +DISPLAY_LINE +{ + CHANNEL = "new_state[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "new_state[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "new_state[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "new_state[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "sm"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 14; + TREE_LEVEL = 0; + CHILDREN = 15, 16, 17, 18; +} + +DISPLAY_LINE +{ + CHANNEL = "sm[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 14; +} + +DISPLAY_LINE +{ + CHANNEL = "sm[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 14; +} + +DISPLAY_LINE +{ + CHANNEL = "sm[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 14; +} + +DISPLAY_LINE +{ + CHANNEL = "sm[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 14; +} + +DISPLAY_LINE +{ + CHANNEL = "db"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 19; + TREE_LEVEL = 0; + CHILDREN = 20, 21, 22, 23, 24, 25, 26, 27; +} + +DISPLAY_LINE +{ + CHANNEL = "db[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "db[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "db[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 22; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "db[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "db[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 24; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "db[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 25; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "db[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 19; +} + +DISPLAY_LINE +{ + CHANNEL = "db[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Hexadecimal; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 19; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; Index: trunk/OpenJTAG/Quartus_II/Open_JTAG.map.summary =================================================================== --- trunk/OpenJTAG/Quartus_II/Open_JTAG.map.summary (nonexistent) +++ trunk/OpenJTAG/Quartus_II/Open_JTAG.map.summary (revision 18) @@ -0,0 +1,9 @@ +Analysis & Synthesis Status : Successful - Wed Jun 02 16:01:07 2010 +Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +Revision Name : Open_JTAG +Top-level Entity Name : Open_JTAG +Family : MAX II +Total logic elements : 257 +Total pins : 29 +Total virtual pins : 0 +UFM blocks : 0 / 1 ( 0 % ) Index: trunk/OpenJTAG/Docs/pcb_bottom.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/OpenJTAG/Docs/pcb_bottom.pdf =================================================================== --- trunk/OpenJTAG/Docs/pcb_bottom.pdf (nonexistent) +++ trunk/OpenJTAG/Docs/pcb_bottom.pdf (revision 18)
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