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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

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  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/core/bench
    from Rev 151 to Rev 154
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Rev 151 → Rev 154

/verilog/dbg_uart_tasks.v
61,6 → 61,7
parameter BRK3_STAT = (8'h40 | 8'h15);
parameter BRK3_ADDR0 = (8'h00 | 8'h16);
parameter BRK3_ADDR1 = (8'h00 | 8'h17);
parameter CPU_NR = (8'h00 | 8'h18);
 
// Read / Write commands
parameter DBG_WR = 8'h80;
/verilog/tb_openMSP430.v
155,7 → 155,7
reg scan_enable;
reg scan_mode;
 
// Debug interface
// Debug interface: UART
reg dbg_en;
wire dbg_freeze;
wire dbg_uart_txd;
168,6 → 168,26
reg dbg_uart_rx_busy;
reg dbg_uart_tx_busy;
 
// Debug interface: I2C
wire dbg_scl;
wire dbg_sda;
wire dbg_scl_slave;
wire dbg_scl_master;
reg dbg_scl_master_sel;
reg dbg_scl_master_dly;
reg dbg_scl_master_pre;
reg dbg_scl_master_meta;
wire dbg_sda_slave_out;
wire dbg_sda_slave_in;
wire dbg_sda_master_out;
reg dbg_sda_master_out_sel;
reg dbg_sda_master_out_dly;
reg dbg_sda_master_out_pre;
reg dbg_sda_master_out_meta;
wire dbg_sda_master_in;
reg [15:0] dbg_i2c_buf;
reg [8*32-1:0] dbg_i2c_string;
 
// Core testbench debuging signals
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
191,6 → 211,7
 
// Debug interface tasks
`include "dbg_uart_tasks.v"
`include "dbg_i2c_tasks.v"
 
// Simple uart tasks
//`include "uart_tasks.v"
247,37 → 268,46
 
initial
begin
error = 0;
stimulus_done = 1;
irq = 14'h0000;
nmi = 1'b0;
wkup = 14'h0000;
cpu_en = 1'b1;
dbg_en = 1'b0;
dbg_uart_rxd_sel = 1'b0;
dbg_uart_rxd_dly = 1'b1;
dbg_uart_rxd_pre = 1'b1;
dbg_uart_rxd_meta= 1'b0;
dbg_uart_buf = 16'h0000;
dbg_uart_rx_busy = 1'b0;
dbg_uart_tx_busy = 1'b0;
p1_din = 8'h00;
p2_din = 8'h00;
p3_din = 8'h00;
p4_din = 8'h00;
p5_din = 8'h00;
p6_din = 8'h00;
inclk = 1'b0;
taclk = 1'b0;
ta_cci0a = 1'b0;
ta_cci0b = 1'b0;
ta_cci1a = 1'b0;
ta_cci1b = 1'b0;
ta_cci2a = 1'b0;
ta_cci2b = 1'b0;
uart_rxd = 1'b1;
scan_enable = 1'b0;
scan_mode = 1'b0;
error = 0;
stimulus_done = 1;
irq = 14'h0000;
nmi = 1'b0;
wkup = 14'h0000;
cpu_en = 1'b1;
dbg_en = 1'b0;
dbg_uart_rxd_sel = 1'b0;
dbg_uart_rxd_dly = 1'b1;
dbg_uart_rxd_pre = 1'b1;
dbg_uart_rxd_meta = 1'b0;
dbg_uart_buf = 16'h0000;
dbg_uart_rx_busy = 1'b0;
dbg_uart_tx_busy = 1'b0;
dbg_scl_master_sel = 1'b0;
dbg_scl_master_dly = 1'b1;
dbg_scl_master_pre = 1'b1;
dbg_scl_master_meta = 1'b0;
dbg_sda_master_out_sel = 1'b0;
dbg_sda_master_out_dly = 1'b1;
dbg_sda_master_out_pre = 1'b1;
dbg_sda_master_out_meta = 1'b0;
dbg_i2c_string = "";
p1_din = 8'h00;
p2_din = 8'h00;
p3_din = 8'h00;
p4_din = 8'h00;
p5_din = 8'h00;
p6_din = 8'h00;
inclk = 1'b0;
taclk = 1'b0;
ta_cci0a = 1'b0;
ta_cci0b = 1'b0;
ta_cci1a = 1'b0;
ta_cci1b = 1'b0;
ta_cci2a = 1'b0;
ta_cci2b = 1'b0;
uart_rxd = 1'b1;
scan_enable = 1'b0;
scan_mode = 1'b0;
end
 
324,47 → 354,52
openMSP430 dut (
 
// OUTPUTs
.aclk (aclk), // ASIC ONLY: ACLK
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dco_enable (dco_enable), // ASIC ONLY: Fast oscillator enable
.dco_wkup (dco_wkup), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.lfxt_enable (lfxt_enable), // ASIC ONLY: Low frequency oscillator enable
.lfxt_wkup (lfxt_wkup), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc_rst (puc_rst), // Main system reset
.smclk (smclk), // ASIC ONLY: SMCLK
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
.aclk (aclk), // ASIC ONLY: ACLK
.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_i2c_sda_out (dbg_sda_slave_out), // Debug interface: I2C SDA OUT
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dco_enable (dco_enable), // ASIC ONLY: Fast oscillator enable
.dco_wkup (dco_wkup), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.lfxt_enable (lfxt_enable), // ASIC ONLY: Low frequency oscillator enable
.lfxt_wkup (lfxt_wkup), // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc_rst (puc_rst), // Main system reset
.smclk (smclk), // ASIC ONLY: SMCLK
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
 
// INPUTs
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq_in), // Maskable interrupts
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
.scan_enable (scan_enable), // ASIC ONLY: Scan enable (active during scan shifting)
.scan_mode (scan_mode), // ASIC ONLY: Scan mode
.wkup (|wkup_in) // ASIC ONLY: System Wake-up (asynchronous)
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
.dbg_i2c_addr (I2C_ADDR), // Debug interface: I2C Address
.dbg_i2c_broadcast (I2C_BROADCAST), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_scl_slave), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_sda_slave_in), // Debug interface: I2C SDA IN
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq_in), // Maskable interrupts
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
.scan_enable (scan_enable), // ASIC ONLY: Scan enable (active during scan shifting)
.scan_mode (scan_mode), // ASIC ONLY: Scan mode
.wkup (|wkup_in) // ASIC ONLY: System Wake-up (asynchronous)
);
 
//
575,6 → 610,48
 
 
//
// I2C serial debug interface
//----------------------------------
 
// I2C Bus
//.........................
pullup dbg_scl_inst (dbg_scl);
pullup dbg_sda_inst (dbg_sda);
 
// I2C Slave (openMSP430)
//.........................
io_cell scl_slave_inst (
.pad (dbg_scl), // I/O pad
.data_in (dbg_scl_slave), // Input
.data_out_en (1'b0), // Output enable
.data_out (1'b0) // Output
);
io_cell sda_slave_inst (
.pad (dbg_sda), // I/O pad
.data_in (dbg_sda_slave_in), // Input
.data_out_en (!dbg_sda_slave_out), // Output enable
.data_out (1'b0) // Output
);
 
// I2C Master (Debugger)
//.........................
io_cell scl_master_inst (
.pad (dbg_scl), // I/O pad
.data_in (), // Input
.data_out_en (!dbg_scl_master), // Output enable
.data_out (1'b0) // Output
);
io_cell sda_master_inst (
.pad (dbg_sda), // I/O pad
.data_in (dbg_sda_master_in), // Input
.data_out_en (!dbg_sda_master_out), // Output enable
.data_out (1'b0) // Output
);
 
 
//
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_0 (
/verilog/dbg_i2c_tasks.v
0,0 → 1,355
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: dbg_i2c_tasks.v
//
// *Module Description:
// openMSP430 debug interface I2C tasks
//
// *Author(s):
// - Olivier Girard, olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 17 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
// I2C COMMUNICATION CONFIGURATION
//----------------------------------------------------------------------------
 
// Data rate
parameter I2C_FREQ = 2000000;
integer I2C_PERIOD = 1000000000/I2C_FREQ;
 
// Address
parameter I2C_ADDR = 7'h45;
parameter I2C_BROADCAST = 7'h67;
 
 
//----------------------------------------------------------------------------
// Generate START / STOP conditions
//----------------------------------------------------------------------------
task dbg_i2c_start;
begin
dbg_i2c_string = "Start";
dbg_sda_master_out_pre = 1'b0;
#(I2C_PERIOD/2);
dbg_scl_master_pre = 1'b0;
#(I2C_PERIOD/4);
dbg_i2c_string = "";
end
endtask
 
task dbg_i2c_stop;
begin
dbg_i2c_string = "Stop";
dbg_sda_master_out_pre = 1'b0;
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1'b1;
#(I2C_PERIOD/4);
dbg_sda_master_out_pre = 1'b1;
#(I2C_PERIOD/2);
dbg_i2c_string = "";
end
endtask
 
//----------------------------------------------------------------------------
// Send a byte on the I2C bus
//----------------------------------------------------------------------------
task dbg_i2c_send;
input [7:0] txbuf;
reg [9:0] txbuf_full;
integer txcnt;
begin
#(1);
txbuf_full = txbuf;
for (txcnt = 0; txcnt < 8; txcnt = txcnt + 1)
begin
$sformat(dbg_i2c_string, "TX_%-d", txcnt);
dbg_sda_master_out_pre = txbuf_full[7-txcnt];
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1'b1;
#(I2C_PERIOD/2);
dbg_scl_master_pre = 1'b0;
#(I2C_PERIOD/4);
end
dbg_sda_master_out_pre = 1'b1;
dbg_i2c_string = "";
end
endtask
 
//----------------------------------------------------------------------------
// Read ACK / NACK
//----------------------------------------------------------------------------
task dbg_i2c_ack_rd;
begin
dbg_i2c_string = "ACK (rd)";
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1'b1;
#(I2C_PERIOD/2);
dbg_scl_master_pre = 1'b0;
#(I2C_PERIOD/4);
dbg_i2c_string = "";
end
endtask
 
 
//----------------------------------------------------------------------------
// Read a byte from the I2C bus
//----------------------------------------------------------------------------
task dbg_i2c_receive;
output [7:0] rxbuf;
reg [9:0] rxbuf_full;
integer rxcnt;
begin
#(1);
rxbuf_full = 0;
for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
begin
$sformat(dbg_i2c_string, "RX_%-d", rxcnt);
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1'b1;
#(I2C_PERIOD/4);
rxbuf_full[7-rxcnt] = dbg_sda;
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1'b0;
#(I2C_PERIOD/4);
end
dbg_i2c_string = "";
rxbuf = rxbuf_full;
end
endtask
 
 
//----------------------------------------------------------------------------
// Write ACK
//----------------------------------------------------------------------------
task dbg_i2c_ack_wr;
begin
dbg_i2c_string = "ACK (wr)";
dbg_sda_master_out_pre = 1'b0;
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1'b1;
#(I2C_PERIOD/2);
dbg_scl_master_pre = 1'b0;
#(I2C_PERIOD/4);
dbg_sda_master_out_pre = 1'b1;
dbg_i2c_string = "";
end
endtask
//----------------------------------------------------------------------------
// Write NACK
//----------------------------------------------------------------------------
task dbg_i2c_nack_wr;
begin
dbg_i2c_string = "NACK (wr)";
dbg_sda_master_out_pre = 1'b1;
#(I2C_PERIOD/4);
dbg_scl_master_pre = 1'b1;
#(I2C_PERIOD/2);
dbg_scl_master_pre = 1'b0;
#(I2C_PERIOD/4);
dbg_sda_master_out_pre = 1'b1;
dbg_i2c_string = "";
end
endtask
 
//----------------------------------------------------------------------------
// Start Burst
//----------------------------------------------------------------------------
task dbg_i2c_burst_start;
input read;
begin
dbg_i2c_start; // START
dbg_i2c_send({I2C_ADDR, read}); // Device Address + Write access
dbg_i2c_ack_rd;
end
endtask
 
 
//----------------------------------------------------------------------------
// Read 16 bits
//----------------------------------------------------------------------------
task dbg_i2c_rx16;
input is_last;
reg [7:0] rxbuf_lo;
reg [7:0] rxbuf_hi;
begin
rxbuf_lo = 8'h00;
rxbuf_hi = 8'h00;
 
dbg_i2c_receive(rxbuf_lo); // Data (low)
dbg_i2c_ack_wr;
dbg_i2c_receive(rxbuf_hi); // Data (high)
if (is_last)
begin
dbg_i2c_nack_wr;
dbg_i2c_stop; // STOP
end
else
begin
dbg_i2c_ack_wr;
end
 
dbg_i2c_buf = {rxbuf_hi, rxbuf_lo};
end
endtask
 
//----------------------------------------------------------------------------
// Transmit 16 bits
//----------------------------------------------------------------------------
task dbg_i2c_tx16;
input [15:0] dbg_data;
input is_last;
begin
dbg_i2c_send(dbg_data[7:0]); // write LSB
dbg_i2c_ack_rd;
dbg_i2c_send(dbg_data[15:8]); // write MSB
dbg_i2c_ack_rd;
if (is_last)
dbg_i2c_stop; // STOP CONDITION
end
endtask
 
//----------------------------------------------------------------------------
// Read 8 bits
//----------------------------------------------------------------------------
task dbg_i2c_rx8;
input is_last;
reg [7:0] rxbuf;
begin
rxbuf = 8'h00;
 
dbg_i2c_receive(rxbuf); // Data (low)
if (is_last)
begin
dbg_i2c_nack_wr;
dbg_i2c_stop; // STOP
end
else
begin
dbg_i2c_ack_wr;
end
 
dbg_i2c_buf = {8'h00, rxbuf};
end
endtask
 
//----------------------------------------------------------------------------
// Transmit 8 bits
//----------------------------------------------------------------------------
task dbg_i2c_tx8;
input [7:0] dbg_data;
input is_last;
begin
dbg_i2c_send(dbg_data); // write LSB
dbg_i2c_ack_rd;
if (is_last)
dbg_i2c_stop; // STOP CONDITION
end
endtask
 
//----------------------------------------------------------------------------
// Write to Debug register
//----------------------------------------------------------------------------
task dbg_i2c_wr;
input [7:0] dbg_reg;
input [15:0] dbg_data;
begin
dbg_i2c_start; // START
dbg_i2c_tx8({I2C_ADDR, 1'b0}, 0); // Device Address + Write access
dbg_i2c_tx8(DBG_WR | dbg_reg, 0); // Command
 
if (~dbg_reg[6])
dbg_i2c_tx16(dbg_data, 1);
else
dbg_i2c_tx8 (dbg_data[7:0], 1);
end
endtask
 
//----------------------------------------------------------------------------
// Read Debug register
//----------------------------------------------------------------------------
task dbg_i2c_rd;
input [7:0] dbg_reg;
reg [7:0] rxbuf_lo;
reg [7:0] rxbuf_hi;
begin
rxbuf_lo = 8'h00;
rxbuf_hi = 8'h00;
 
dbg_i2c_start; // START
dbg_i2c_tx8({I2C_ADDR, 1'b0}, 0); // Device Address + Write access
dbg_i2c_tx8(DBG_RD | dbg_reg, 1); // Command
 
dbg_i2c_start; // START
dbg_i2c_tx8({I2C_ADDR, 1'b1}, 0); // Device Address + Read access
 
if (~dbg_reg[6])
dbg_i2c_rx16(1);
else
dbg_i2c_rx8(1);
end
endtask
 
//----------------------------------------------------------------------------
// Build random delay insertion on SCL_MASTER and SDA_MASTER_OUT in order to
// simulate synchronization mechanism
//----------------------------------------------------------------------------
 
always @(posedge mclk or posedge dbg_rst)
if (dbg_rst)
begin
dbg_sda_master_out_sel <= 1'b0;
dbg_sda_master_out_dly <= 1'b1;
 
dbg_scl_master_sel <= 1'b0;
dbg_scl_master_dly <= 1'b1;
end
else if (dbg_en)
begin
dbg_sda_master_out_sel <= dbg_sda_master_out_meta ? $random : 1'b0;
dbg_sda_master_out_dly <= dbg_sda_master_out_pre;
 
dbg_scl_master_sel <= dbg_scl_master_meta ? $random : 1'b0;
dbg_scl_master_dly <= dbg_scl_master_pre;
end
 
assign dbg_sda_master_out = dbg_sda_master_out_sel ? dbg_sda_master_out_dly : dbg_sda_master_out_pre;
 
assign dbg_scl_master = dbg_scl_master_sel ? dbg_scl_master_dly : dbg_scl_master_pre;
 
verilog/dbg_i2c_tasks.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: verilog/io_cell.v =================================================================== --- verilog/io_cell.v (nonexistent) +++ verilog/io_cell.v (revision 154) @@ -0,0 +1,79 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2009 , Olivier Girard +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// * Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// * Neither the name of the authors nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +// THE POSSIBILITY OF SUCH DAMAGE +// +//---------------------------------------------------------------------------- +// +// *File Name: io_cell.v +// +// *Module Description: +// I/O cell model +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 103 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $ +//---------------------------------------------------------------------------- + +module io_cell ( + +// INOUTs + pad, // I/O Pad + +// OUTPUTs + data_in, // Input value + +// INPUTs + data_out_en, // Output enable + data_out // Output value +); + +// INOUTs +//========= +inout pad; // I/O Pad + +// OUTPUTs +//========= +output data_in; // Input value + +// INPUTs +//========= +input data_out_en; // Output enable +input data_out; // Output value + + +//============================================================================= +// 1) I/O CELL +//============================================================================= + +assign data_in = pad; +assign pad = data_out_en ? data_out : 1'bz; + + +endmodule // io_cell
verilog/io_cell.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property

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