OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

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  • This comparison shows the changes necessary to convert path
    /openmsp430/trunk/core/sim/rtl_sim/bin
    from Rev 76 to Rev 94
    Reverse comparison

Rev 76 → Rev 94

/rtlsim.sh
27,6 → 27,7
#
# Author(s):
# - Olivier Girard, olgirard@gmail.com
# - Mihai M., mmihai@delajii.net
#
#------------------------------------------------------------------------------
# $Rev$
42,6 → 43,7
echo "ERROR : wrong number of arguments"
echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>"
echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f"
echo "MYVLOG env keeps simulator name iverilog/cver/verilog/ncverilog"
exit 1
fi
 
68,14 → 70,42
# Start verilog simulation #
###############################################################################
 
rm -rf simv
if [ "${MYVLOG:-iverilog}" = iverilog ]; then
 
NODUMP=${OMSP_NODUMP-0}
if [ $NODUMP -eq 1 ]
then
iverilog -o simv -c $3 -D NODUMP
else
iverilog -o simv -c $3
rm -rf simv
NODUMP=${OMSP_NODUMP-0}
if [ $NODUMP -eq 1 ]
then
iverilog -o simv -c $3 -D NODUMP
else
iverilog -o simv -c $3
fi
./simv
else
 
NODUMP=${OMSP_NODUMP-0}
if [ $NODUMP -eq 1 ] ; then
vargs="+define+NODUMP"
else
vargs=""
fi
 
case $MYVLOG in
cver* )
vargs="$vargs +define+VXL" ;;
verilog* )
vargs="$vargs +define+VXL" ;;
ncverilog* )
vargs="$vargs +access+r" ;;
vsim )
# Modelsim
if [ -d work ]; then vdel -all; fi
vlib work
exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all"
esac
echo "Running: $MYVLOG -f $3 $vargs"
exec $MYVLOG -f $3 $vargs
fi
 
./simv

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