OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/core/sim/rtl_sim/run
    from Rev 128 to Rev 134
    ↔ Reverse comparison
  •

Rev 128 → Rev 134

/run_all_mpy
4,7 → 4,20
OMSP_NODUMP=1
export OMSP_NODUMP
 
rm -rf *.log
# Choose simulator:
# - iverilog : Icarus Verilog (default)
# - cver : CVer
# - verilog : Verilog-XL
# - ncverilog : NC-Verilog
# - vcs : VCS
# - vsim : Modelsim
# - isim : Xilinx simulator
OMSP_SIMULATOR=iverilog
export OMSP_SIMULATOR
 
rm -rf ./log/*.log
mkdir ./log
 
echo ""
echo " ===================================================="
echo "| WARNING: Complete Hardware Multiplier verification |"
13,22 → 26,25
echo ""
 
# Hardware multiplier test patterns
../bin/msp430sim mpy_basic | tee mpy_basic.log
../bin/msp430sim mpy_mpy | tee mpy_mpy.log
../bin/msp430sim mpy_mpys | tee mpy_mpys.log
../bin/msp430sim mpy_mac | tee mpy_mac.log
../bin/msp430sim mpy_macs | tee mpy_macs.log
../bin/msp430sim mpy_basic | tee ./log/mpy_basic.log
../bin/msp430sim mpy_mpy | tee ./log/mpy_mpy.log
../bin/msp430sim mpy_mpys | tee ./log/mpy_mpys.log
../bin/msp430sim mpy_mac | tee ./log/mpy_mac.log
../bin/msp430sim mpy_macs | tee ./log/mpy_macs.log
 
grep FAILED *.log
grep SKIPPED ./log/*.log
grep FAILED ./log/*.log
echo ""
echo " ================================"
echo -n "| Number of passed patterns: "
cat *.log | grep -c PASSED
echo -n "| Number of failed patterns: "
cat *.log | grep -c FAILED
echo -n "| Number of passed patterns : "
cat ./log/*.log | grep -c PASSED
echo -n "| Number of failed patterns : "
cat ./log/*.log | grep -c FAILED
echo -n "| Number of skipped patterns: "
cat ./log/*.log | grep -c SKIPPED
echo "|--------------------------------"
echo -n "| Number of patterns: "
ls -1 *.log | wc -l
ls -1 ./log/*.log | wc -l
echo " ================================"
echo " Make sure passed == total"
echo ""
/run_coverage_analysis
6,10 → 6,10
# WAS RUN USING "ncverilog" SIMULATOR
 
# Remove old merged report
rm -rf cov_work/design/merged_coverage
rm -rf cov_work/scope/merged_coverage
 
# Merge all available coverage reports
iccr ../bin/cov_iccr_merge.cf
imc -batch ../bin/cov_iccr_merge.cf
 
# Launch GUI
iccr -test cov_work/design/merged_coverage -GUI
imc -gui -load cov_work/scope/merged_coverage
/run
15,4 → 15,6
OMSP_SIMULATOR=iverilog
export OMSP_SIMULATOR
 
../bin/msp430sim two-op_mov
rm -rf cov_work
 
../bin/msp430sim sing-op_reti
/run_c
1,4 → 1,19
#!/bin/csh -f
 
# Enable/Disable waveform dumping
OMSP_NODUMP=0
export OMSP_NODUMP
 
# Choose simulator:
# - iverilog : Icarus Verilog (default)
# - cver : CVer
# - verilog : Verilog-XL
# - ncverilog : NC-Verilog
# - vcs : VCS
# - vsim : Modelsim
OMSP_SIMULATOR=ncverilog
export OMSP_SIMULATOR
 
 
../bin/msp430sim_c sandbox
 
/run_all
15,89 → 15,114
OMSP_SIMULATOR=iverilog
export OMSP_SIMULATOR
 
rm -rf ./cov_work
rm -rf ./log/*.log
mkdir ./log
 
# Two-Operand Arithmetic test patterns
../bin/msp430sim two-op_mov | tee ./log/two-op_mov.log
../bin/msp430sim two-op_mov-b | tee ./log/two-op_mov-b.log
../bin/msp430sim two-op_add | tee ./log/two-op_add.log
../bin/msp430sim two-op_add-b | tee ./log/two-op_add-b.log
../bin/msp430sim two-op_addc | tee ./log/two-op_addc.log
../bin/msp430sim two-op_sub | tee ./log/two-op_sub.log
../bin/msp430sim two-op_subc | tee ./log/two-op_subc.log
../bin/msp430sim two-op_cmp | tee ./log/two-op_cmp.log
../bin/msp430sim two-op_bit | tee ./log/two-op_bit.log
../bin/msp430sim two-op_bic | tee ./log/two-op_bic.log
../bin/msp430sim two-op_bis | tee ./log/two-op_bis.log
../bin/msp430sim two-op_xor | tee ./log/two-op_xor.log
../bin/msp430sim two-op_and | tee ./log/two-op_and.log
../bin/msp430sim two-op_dadd | tee ./log/two-op_dadd.log
../bin/msp430sim two-op_mov | tee ./log/two-op_mov.log
../bin/msp430sim two-op_mov-b | tee ./log/two-op_mov-b.log
../bin/msp430sim two-op_add | tee ./log/two-op_add.log
../bin/msp430sim two-op_add-b | tee ./log/two-op_add-b.log
../bin/msp430sim two-op_addc | tee ./log/two-op_addc.log
../bin/msp430sim two-op_sub | tee ./log/two-op_sub.log
../bin/msp430sim two-op_subc | tee ./log/two-op_subc.log
../bin/msp430sim two-op_cmp | tee ./log/two-op_cmp.log
../bin/msp430sim two-op_bit | tee ./log/two-op_bit.log
../bin/msp430sim two-op_bic | tee ./log/two-op_bic.log
../bin/msp430sim two-op_bis | tee ./log/two-op_bis.log
../bin/msp430sim two-op_xor | tee ./log/two-op_xor.log
../bin/msp430sim two-op_and | tee ./log/two-op_and.log
../bin/msp430sim two-op_dadd | tee ./log/two-op_dadd.log
../bin/msp430sim two-op_autoincr | tee ./log/two-op_autoincr.log
../bin/msp430sim two-op_autoincr-b | tee ./log/two-op_autoincr-b.log
 
# Conditional Jump test patterns
../bin/msp430sim c-jump_jeq | tee ./log/c-jump_jeq.log
../bin/msp430sim c-jump_jne | tee ./log/c-jump_jne.log
../bin/msp430sim c-jump_jc | tee ./log/c-jump_jc.log
../bin/msp430sim c-jump_jnc | tee ./log/c-jump_jnc.log
../bin/msp430sim c-jump_jn | tee ./log/c-jump_jn.log
../bin/msp430sim c-jump_jge | tee ./log/c-jump_jge.log
../bin/msp430sim c-jump_jl | tee ./log/c-jump_jl.log
../bin/msp430sim c-jump_jmp | tee ./log/c-jump_jmp.log
../bin/msp430sim c-jump_jeq | tee ./log/c-jump_jeq.log
../bin/msp430sim c-jump_jne | tee ./log/c-jump_jne.log
../bin/msp430sim c-jump_jc | tee ./log/c-jump_jc.log
../bin/msp430sim c-jump_jnc | tee ./log/c-jump_jnc.log
../bin/msp430sim c-jump_jn | tee ./log/c-jump_jn.log
../bin/msp430sim c-jump_jge | tee ./log/c-jump_jge.log
../bin/msp430sim c-jump_jl | tee ./log/c-jump_jl.log
../bin/msp430sim c-jump_jmp | tee ./log/c-jump_jmp.log
 
# Single-Operand Arithmetic test patterns
../bin/msp430sim sing-op_rrc | tee ./log/sing-op_rrc.log
../bin/msp430sim sing-op_rra | tee ./log/sing-op_rra.log
../bin/msp430sim sing-op_swpb | tee ./log/sing-op_swpb.log
../bin/msp430sim sing-op_sxt | tee ./log/sing-op_sxt.log
../bin/msp430sim sing-op_push | tee ./log/sing-op_push.log
../bin/msp430sim sing-op_call | tee ./log/sing-op_call.log
../bin/msp430sim sing-op_reti | tee ./log/sing-op_reti.log
../bin/msp430sim sing-op_rrc | tee ./log/sing-op_rrc.log
../bin/msp430sim sing-op_rra | tee ./log/sing-op_rra.log
../bin/msp430sim sing-op_swpb | tee ./log/sing-op_swpb.log
../bin/msp430sim sing-op_sxt | tee ./log/sing-op_sxt.log
../bin/msp430sim sing-op_push | tee ./log/sing-op_push.log
../bin/msp430sim sing-op_call | tee ./log/sing-op_call.log
 
# Interrupts & NMI
../bin/msp430sim sing-op_reti | tee ./log/sing-op_reti.log
../bin/msp430sim nmi | tee ./log/nmi.log
 
# ROM Data Read access
../bin/msp430sim two-op_add_rom-rd | tee ./log/two-op_add_rom-rd.log
../bin/msp430sim sing-op_push_rom-rd | tee ./log/sing-op_push_rom-rd.log
../bin/msp430sim sing-op_call_rom-rd | tee ./log/sing-op_call_rom-rd.log
../bin/msp430sim two-op_add_rom-rd | tee ./log/two-op_add_rom-rd.log
../bin/msp430sim sing-op_push_rom-rd | tee ./log/sing-op_push_rom-rd.log
../bin/msp430sim sing-op_call_rom-rd | tee ./log/sing-op_call_rom-rd.log
 
# Power saving modes (CPUOFF, OSCOFF, SCG1)
../bin/msp430sim op_modes | tee ./log/op_modes.log
# Power saving modes (CPUOFF, OSCOFF, SCG0, SCG1)
../bin/msp430sim op_modes | tee ./log/op_modes.log
../bin/msp430sim op_modes_asic | tee ./log/op_modes_asic.log
../bin/msp430sim lp_modes_asic | tee ./log/lp_modes_asic.log
../bin/msp430sim lp_modes_dbg_asic | tee ./log/lp_modes_dbg_asic.log
 
# CPU startup conditions
../bin/msp430sim cpu_startup_asic | tee ./log/cpu_startup_asic.log
 
# Basic clock module
../bin/msp430sim clock_module | tee ./log/clock_module.log
../bin/msp430sim clock_module | tee ./log/clock_module.log
../bin/msp430sim clock_module_asic | tee ./log/clock_module_asic.log
../bin/msp430sim clock_module_asic_mclk | tee ./log/clock_module_asic_mclk.log
../bin/msp430sim clock_module_asic_smclk | tee ./log/clock_module_asic_smclk.log
../bin/msp430sim clock_module_asic_lfxt | tee ./log/clock_module_asic_lfxt.log
 
# Serial Debug Interface
../bin/msp430sim dbg_uart | tee ./log/dbg_uart.log
../bin/msp430sim dbg_cpu | tee ./log/dbg_cpu.log
../bin/msp430sim dbg_mem | tee ./log/dbg_mem.log
../bin/msp430sim dbg_hwbrk0 | tee ./log/dbg_hwbrk0.log
../bin/msp430sim dbg_hwbrk1 | tee ./log/dbg_hwbrk1.log
../bin/msp430sim dbg_hwbrk2 | tee ./log/dbg_hwbrk2.log
../bin/msp430sim dbg_hwbrk3 | tee ./log/dbg_hwbrk3.log
../bin/msp430sim dbg_halt_irq | tee ./log/dbg_halt_irq.log
../bin/msp430sim dbg_onoff | tee ./log/dbg_onoff.log
../bin/msp430sim dbg_uart | tee ./log/dbg_uart.log
../bin/msp430sim dbg_uart_sync | tee ./log/dbg_uart_sync.log
../bin/msp430sim dbg_cpu | tee ./log/dbg_cpu.log
../bin/msp430sim dbg_mem | tee ./log/dbg_mem.log
../bin/msp430sim dbg_hwbrk0 | tee ./log/dbg_hwbrk0.log
../bin/msp430sim dbg_hwbrk1 | tee ./log/dbg_hwbrk1.log
../bin/msp430sim dbg_hwbrk2 | tee ./log/dbg_hwbrk2.log
../bin/msp430sim dbg_hwbrk3 | tee ./log/dbg_hwbrk3.log
../bin/msp430sim dbg_rdwr | tee ./log/dbg_rdwr.log
../bin/msp430sim dbg_halt_irq | tee ./log/dbg_halt_irq.log
../bin/msp430sim dbg_onoff | tee ./log/dbg_onoff.log
../bin/msp430sim dbg_onoff_asic | tee ./log/dbg_onoff_asic.log
 
# SFR test patterns
../bin/msp430sim sfr | tee ./log/sfr.log
 
# SCAN test patterns (only to increase coverage)
../bin/msp430sim scan | tee ./log/scan.log
 
# Watchdog test patterns
../bin/msp430sim wdt_interval | tee ./log/wdt_interval.log
../bin/msp430sim wdt_watchdog | tee ./log/wdt_watchdog.log
../bin/msp430sim wdt_clkmux | tee ./log/wdt_clkmux.log
../bin/msp430sim wdt_interval | tee ./log/wdt_interval.log
../bin/msp430sim wdt_watchdog | tee ./log/wdt_watchdog.log
../bin/msp430sim wdt_clkmux | tee ./log/wdt_clkmux.log
../bin/msp430sim wdt_wkup | tee ./log/wdt_wkup.log
 
# GPIO test patterns
../bin/msp430sim gpio_rdwr | tee ./log/gpio_rdwr.log
../bin/msp430sim gpio_irq | tee ./log/gpio_irq.log
../bin/msp430sim gpio_rdwr | tee ./log/gpio_rdwr.log
../bin/msp430sim gpio_irq | tee ./log/gpio_irq.log
 
# Peripheral templates test patterns
../bin/msp430sim template_periph_8b | tee ./log/template_periph_8b.log
../bin/msp430sim template_periph_16b | tee ./log/template_periph_16b.log
../bin/msp430sim template_periph_8b | tee ./log/template_periph_8b.log
../bin/msp430sim template_periph_16b | tee ./log/template_periph_16b.log
 
# Timer A patterns
../bin/msp430sim tA_modes | tee ./log/tA_modes.log
../bin/msp430sim tA_compare | tee ./log/tA_compare.log
../bin/msp430sim tA_output | tee ./log/tA_output.log
../bin/msp430sim tA_capture | tee ./log/tA_capture.log
../bin/msp430sim tA_clkmux | tee ./log/tA_clkmux.log
../bin/msp430sim tA_modes | tee ./log/tA_modes.log
../bin/msp430sim tA_compare | tee ./log/tA_compare.log
../bin/msp430sim tA_output | tee ./log/tA_output.log
../bin/msp430sim tA_capture | tee ./log/tA_capture.log
../bin/msp430sim tA_clkmux | tee ./log/tA_clkmux.log
 
 
# Hardware multiplier test patterns
../bin/msp430sim mpy_basic | tee ./log/mpy_basic.log
../bin/msp430sim mpy_basic | tee ./log/mpy_basic.log
 
 
grep SKIPPED ./log/*.log
/load_waveform.sav
1,11 → 1,13
[timestart] 0
[size] 1680 991
[pos] -1 -1
*-21.526770 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[timestart] 2700000
[size] 1680 990
[pos] -678 -4
*-23.404364 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_openMSP430.
[treeopen] tb_openMSP430.dut.
@22
tb_openMSP430.r15[15:0]
tb_openMSP430.error[31:0]
tb_openMSP430.dut.pmem_dout[15:0]
@820
tb_openMSP430.inst_full[255:0]
@22
19,3 → 21,44
tb_openMSP430.r6[15:0]
tb_openMSP430.mem250[15:0]
tb_openMSP430.mem24E[15:0]
@200
-
@28
(10)tb_openMSP430.wkup[13:0]
(10)tb_openMSP430.irq[13:0]
(11)tb_openMSP430.wkup[13:0]
(11)tb_openMSP430.irq[13:0]
@200
-
@28
tb_openMSP430.dco_wkup
tb_openMSP430.dco_enable
tb_openMSP430.dco_clk
@200
-
@28
tb_openMSP430.lfxt_wkup
tb_openMSP430.lfxt_enable
tb_openMSP430.lfxt_clk
@200
-
@28
tb_openMSP430.dut.clock_module_0.cpu_en
@29
tb_openMSP430.dut.clock_module_0.dbg_en
@28
tb_openMSP430.dut.frontend_0.cpuoff
tb_openMSP430.dut.clock_module_0.oscoff
tb_openMSP430.dut.clock_module_0.scg0
tb_openMSP430.dut.clock_module_0.scg1
@200
-
@28
tb_openMSP430.mclk
tb_openMSP430.smclk
tb_openMSP430.aclk
tb_openMSP430.dbg_clk
tb_openMSP430.dut.clock_module_0.mclk_enable
tb_openMSP430.dut.clock_module_0.mclk_wkup
[pattern_trace] 1
[pattern_trace] 0

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