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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

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Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/core/sim/rtl_sim/src
    from Rev 105 to Rev 106
    ↔ Reverse comparison
  •

Rev 105 → Rev 106

/dbg_hwbrk3.v
42,6 → 42,7
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
#1 dbg_en = 1;
repeat(30) @(posedge mclk);
stimulus_done = 0;
 
48,7 → 49,11
// SEND UART SYNCHRONIZATION FRAME
dbg_uart_tx(DBG_SYNC);
 
`ifdef DBG_RST_BRK_EN
dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
`endif
 
// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES
//----------------------------------------------------------------------
 
/dbg_halt_irq.v
42,14 → 42,22
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
#1 dbg_en = 1;
repeat(30) @(posedge mclk);
stimulus_done = 0;
 
// Initialize the debug interface and send the CPU in halt mode
dbg_uart_tx(DBG_SYNC);
 
`ifdef DBG_RST_BRK_EN
dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
`endif
 
// Wait until software initialization is done
@(r15==16'h0200);
if (r15!==16'h0200)
@(r15==16'h0200);
 
// Initialize the debug interface and send the CPU in halt mode
dbg_uart_tx(DBG_SYNC);
 
dbg_uart_wr(CPU_CTL, 16'h0001); // HALT
repeat(150) @(posedge mclk);
r13_bkup = r13;
/dbg_onoff.v
0,0 → 1,189
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DEBUG INTERFACE */
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - CPU Control features. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
 
 
integer my_test;
integer test_var;
 
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
#1 dbg_en = 0;
repeat(30) @(posedge mclk);
stimulus_done = 0;
 
// Make sure the CPU always starts executing when the
// debug interface is disabled during POR.
//--------------------------------------------------------
dbg_en = 0;
 
repeat(300) @(posedge mclk);
if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
test_var = r14;
// Make sure that enabling the debug interface after the POR
// don't stop the cpu
//--------------------------------------------------------
dbg_en = 1;
repeat(300) @(posedge mclk);
if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 2 =====");
 
// Create POR with debug enable and observe the
// behavior depending on the DBG_RST_BRK_EN define
//--------------------------------------------------------
dbg_en = 1;
@(posedge mclk); // Generate POR
reset_n = 1'b0;
@(posedge mclk);
reset_n = 1'b1;
repeat(300) @(posedge mclk);
`ifdef DBG_RST_BRK_EN
if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
`else
if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
`endif
 
// Send uart synchronization frame
dbg_uart_tx(DBG_SYNC);
 
// Check CPU_CTL reset value
dbg_uart_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_uart_buf !== 16'h0020) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`else
if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`endif
 
 
// Make sure that DBG_EN resets the debug interface
//--------------------------------------------------------
 
// Let the CPU run
dbg_uart_wr(CPU_CTL, 16'h0002);
 
repeat(300) @(posedge mclk);
dbg_uart_wr(CPU_CTL, 16'h0000);
dbg_uart_wr(MEM_DATA, 16'haa55);
dbg_uart_rd(CPU_CTL);
if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 =====");
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 =====");
 
test_var = r14; // Backup the current register value
 
@(posedge mclk); // Resets the debug interface
dbg_en = 1'b0;
repeat(2) @(posedge mclk);
dbg_en = 1'b1;
 
// Make sure that the register was not reseted
if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 =====");
repeat(2) @(posedge mclk);
// Send uart synchronization frame
dbg_uart_tx(DBG_SYNC);
 
// Check CPU_CTL reset value
dbg_uart_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_uart_buf !== 16'h0020) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
 
 
// Make sure that RESET_N resets the debug interface
//--------------------------------------------------------
 
// Let the CPU run
dbg_uart_wr(CPU_CTL, 16'h0002);
 
repeat(300) @(posedge mclk);
dbg_uart_wr(CPU_CTL, 16'h0000);
dbg_uart_wr(MEM_DATA, 16'haa55);
dbg_uart_rd(CPU_CTL);
if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 =====");
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 =====");
 
 
@(posedge mclk); // Generates POR
reset_n = 1'b0;
repeat(2) @(posedge mclk);
reset_n = 1'b1;
 
// Make sure that the register was reseted
if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 =====");
repeat(2) @(posedge mclk);
// Send uart synchronization frame
dbg_uart_tx(DBG_SYNC);
 
// Check CPU_CTL reset value
dbg_uart_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_uart_buf !== 16'h0020) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_uart_buf !== 16'h0000) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_uart_rd(MEM_DATA);
if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
 
// Let the CPU run
dbg_uart_wr(CPU_CTL, 16'h0002);
 
// Generate IRQ to terminate the test pattern
irq[1] = 1'b1;
@(r13);
irq[1] = 1'b0;
stimulus_done = 1;
end
 
dbg_onoff.v Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: dbg_mem.v =================================================================== --- dbg_mem.v (revision 105) +++ dbg_mem.v (revision 106) @@ -45,6 +45,7 @@ $display(" ==============================================="); $display("| START SIMULATION |"); $display(" ==============================================="); + #1 dbg_en = 1; repeat(30) @(posedge mclk); stimulus_done = 0; @@ -51,7 +52,10 @@ // SEND UART SYNCHRONIZATION FRAME dbg_uart_tx(DBG_SYNC); - + `ifdef DBG_RST_BRK_EN + dbg_uart_wr(CPU_CTL, 16'h0002); // RUN + `endif + // RD/WR ACCESS: CPU REGISTERS (16b) //--------------------------------------------------------
/clock_module.s43
125,6 → 125,14
 
mov #0x3000, r15
 
 
/* -------------- CPU ENABLE - CPU_EN INPUT ----------------- */
 
mov #0x0800, r14
call #WAIT_FUNC
 
mov #0x4000, r15
/* ---------------------- END OF TEST --------------- */
end_of_test:
/dbg_hwbrk0.v
42,6 → 42,7
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
#1 dbg_en = 1;
repeat(30) @(posedge mclk);
stimulus_done = 0;
 
48,6 → 49,10
// SEND UART SYNCHRONIZATION FRAME
dbg_uart_tx(DBG_SYNC);
 
`ifdef DBG_RST_BRK_EN
dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
`endif
 
// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES
//----------------------------------------------------------------------
/dbg_hwbrk2.v
42,6 → 42,7
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
#1 dbg_en = 1;
repeat(30) @(posedge mclk);
stimulus_done = 0;
 
48,6 → 49,10
// SEND UART SYNCHRONIZATION FRAME
dbg_uart_tx(DBG_SYNC);
 
`ifdef DBG_RST_BRK_EN
dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
`endif
 
// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES
//----------------------------------------------------------------------
/dbg_onoff.s43
0,0 → 1,86
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DEBUG INTERFACE */
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - CPU Control features. */
/* */
/* Author(s): */
/* - Olivier Girard, olgirard@gmail.com */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
 
.global main
 
main:
mov #0x0250, r1 ; Initialize stack
mov #0x0000, r15
mov #0x0000, r14
mov #0x0000, r13
nop
eint
test_loop:
add #0x0001, r14
cmp #0xffff, r13
jne test_loop
 
mov #0x1000, r15
 
 
/* ---------------------- END OF TEST --------------- */
end_of_test:
nop
br #0xffff
 
isr_1:
mov #0xffff, r13
reti
/* ---------------------- INTERRUPT VECTORS --------------- */
 
.section .vectors, "a"
.word end_of_test ; Interrupt 0 (lowest priority) <unused>
.word isr_1 ; Interrupt 1 <unused>
.word end_of_test ; Interrupt 2 <unused>
.word end_of_test ; Interrupt 3 <unused>
.word end_of_test ; Interrupt 4 <unused>
.word end_of_test ; Interrupt 5 <unused>
.word end_of_test ; Interrupt 6 <unused>
.word end_of_test ; Interrupt 7 <unused>
.word end_of_test ; Interrupt 8 <unused>
.word end_of_test ; Interrupt 9 <unused>
.word end_of_test ; Interrupt 10 Watchdog timer
.word end_of_test ; Interrupt 11 <unused>
.word end_of_test ; Interrupt 12 <unused>
.word end_of_test ; Interrupt 13 <unused>
.word end_of_test ; Interrupt 14 NMI
.word main ; Interrupt 15 (highest priority) RESET
dbg_onoff.s43 Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: clock_module.v =================================================================== --- clock_module.v (revision 105) +++ clock_module.v (revision 106) @@ -49,7 +49,8 @@ always @ (negedge mclk) if (smclk_en) smclk_counter <= smclk_counter+1; - +reg [15:0] reg_val; + initial begin $display(" ==============================================="); @@ -185,7 +186,34 @@ if (mclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) ====="); if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) ====="); - + + // SMCLK GENERATION - DCO_CLK INPUT + //-------------------------------------------------------- + + @(r15 === 16'h3000); + repeat(50) @(posedge mclk); + if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) ====="); + cpu_en = 1'b0; + repeat(3) @(posedge mclk); + reg_val = r14; // Read R14 register & initialize aclk/smclk counters + aclk_counter = 0; + smclk_counter = 0; + if (dbg_freeze !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 2) ====="); + + repeat(500) @(posedge mclk); // Make sure that the CPU is stopped + if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) ====="); + if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 4) ====="); + if (smclk_counter !== 0) tb_error("====== SMCLK is not stopped (test 5) ====="); + if (dbg_freeze !== 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 6) ====="); + cpu_en = 1'b1; + + repeat(500) @(posedge mclk); // Make sure that the CPU runs again + if (reg_val == r14) tb_error("====== CPU is not running (test 7) ====="); + if (aclk_counter == 0) tb_error("====== ACLK is not running (test 8) ====="); + if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 9) ====="); + if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) ====="); + + stimulus_done = 1; end
/dbg_cpu.v
45,6 → 45,7
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
#1 dbg_en = 1;
repeat(30) @(posedge mclk);
stimulus_done = 0;
 
51,6 → 52,11
// SEND UART SYNCHRONIZATION FRAME
dbg_uart_tx(DBG_SYNC);
 
`ifdef DBG_RST_BRK_EN
dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
`endif
 
 
// STOP, FREEZE, ISTEP, RUN
//--------------------------------------------------------
 
/submit.f
47,6 → 47,7
// Module specific modules
//=============================================================================
+incdir+../../../rtl/verilog/
+incdir+../../../rtl/verilog/periph/
../../../rtl/verilog/openMSP430_defines.v
../../../rtl/verilog/openMSP430.v
../../../rtl/verilog/omsp_frontend.v
/dbg_uart.v
48,6 → 48,7
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
#1 dbg_en = 1;
repeat(30) @(posedge mclk);
stimulus_done = 0;
 
54,6 → 55,10
// SEND UART SYNCHRONIZATION FRAME
dbg_uart_tx(DBG_SYNC);
 
`ifdef DBG_RST_BRK_EN
dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
`endif
 
// TEST CPU REGISTERS
//--------------------------------------------------------
dbg_id_pmem = `PMEM_SIZE;
/dbg_hwbrk1.v
42,6 → 42,7
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
#1 dbg_en = 1;
repeat(30) @(posedge mclk);
stimulus_done = 0;
 
48,6 → 49,10
// SEND UART SYNCHRONIZATION FRAME
dbg_uart_tx(DBG_SYNC);
 
`ifdef DBG_RST_BRK_EN
dbg_uart_wr(CPU_CTL, 16'h0002); // RUN
`endif
 
// HARDWARE BREAKPOINTS: INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES
//----------------------------------------------------------------------

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