OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/core/sim/rtl_sim/src
    from Rev 154 to Rev 175
    ↔ Reverse comparison
  •

Rev 154 → Rev 175

/dbg_i2c_hwbrk3.v
161,8 → 161,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
dbg_i2c_rd(BRK3_STAT);
176,7 → 176,7
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
192,7 → 192,7
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
dbg_i2c_rd(BRK3_STAT);
344,8 → 344,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
dbg_i2c_rd(BRK3_STAT);
if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK3_STAT, 16'h0002);
if (dbg_i2c_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK3_STAT, 16'h0003);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
359,8 → 359,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
dbg_i2c_rd(BRK3_STAT);
if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK3_STAT, 16'h0008);
if (dbg_i2c_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK3_STAT, 16'h000C);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
415,8 → 415,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
dbg_i2c_rd(BRK3_STAT);
430,8 → 430,8
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
dbg_i2c_rd(BRK3_STAT);
589,8 → 589,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
dbg_i2c_rd(BRK3_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK3_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK3_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
604,8 → 604,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
dbg_i2c_rd(BRK3_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK3_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK3_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
634,8 → 634,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
dbg_i2c_rd(BRK3_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_i2c_wr(BRK3_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_i2c_wr(BRK3_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
/dbg_uart_hwbrk0.v
164,8 → 164,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
dbg_uart_rd(BRK0_STAT);
179,7 → 179,7
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
195,7 → 195,7
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
dbg_uart_rd(BRK0_STAT);
347,8 → 347,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK0_STAT, 16'h0002);
if (dbg_uart_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK0_STAT, 16'h0003);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
362,8 → 362,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK0_STAT, 16'h0008);
if (dbg_uart_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK0_STAT, 16'h000C);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
418,8 → 418,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
dbg_uart_rd(BRK0_STAT);
433,8 → 433,8
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
dbg_uart_rd(BRK0_STAT);
592,8 → 592,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK0_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK0_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
607,8 → 607,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK0_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK0_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
637,8 → 637,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
dbg_uart_rd(BRK0_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_uart_wr(BRK0_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_uart_wr(BRK0_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
/dbg_i2c_rdwr.v
135,11 → 135,10
`ifdef DBG_HWBRK_0
`ifdef DBG_HWBRK_RANGE
8 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK0_CTL)");
9 : if (dbg_i2c_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK0_STAT)");
`else
8 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK0_CTL)");
9 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK0_STAT)");
`endif
9 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK0_STAT)");
10 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR0)");
11 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR1)");
`endif
146,11 → 145,10
`ifdef DBG_HWBRK_1
`ifdef DBG_HWBRK_RANGE
12 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK1_CTL)");
13 : if (dbg_i2c_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK1_STAT)");
`else
12 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK1_CTL)");
13 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK1_STAT)");
`endif
13 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK1_STAT)");
14 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR0)");
15 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR1)");
`endif
157,11 → 155,10
`ifdef DBG_HWBRK_2
`ifdef DBG_HWBRK_RANGE
16 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK2_CTL)");
17 : if (dbg_i2c_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK2_STAT)");
`else
16 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK2_CTL)");
17 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK2_STAT)");
`endif
17 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK2_STAT)");
18 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR0)");
19 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR1)");
`endif
168,11 → 165,10
`ifdef DBG_HWBRK_3
`ifdef DBG_HWBRK_RANGE
20 : if (dbg_i2c_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK3_CTL)");
21 : if (dbg_i2c_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK3_STAT)");
`else
20 : if (dbg_i2c_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK3_CTL)");
21 : if (dbg_i2c_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK3_STAT)");
`endif
21 : if (dbg_i2c_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK3_STAT)");
22 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR0)");
23 : if (dbg_i2c_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR1)");
`endif
/dbg_i2c_hwbrk0.v
161,8 → 161,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
dbg_i2c_rd(BRK0_STAT);
176,7 → 176,7
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
192,7 → 192,7
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
dbg_i2c_rd(BRK0_STAT);
344,8 → 344,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
dbg_i2c_rd(BRK0_STAT);
if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK0_STAT, 16'h0002);
if (dbg_i2c_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK0_STAT, 16'h0003);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
359,8 → 359,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
dbg_i2c_rd(BRK0_STAT);
if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK0_STAT, 16'h0008);
if (dbg_i2c_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK0_STAT, 16'h000C);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
415,8 → 415,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
dbg_i2c_rd(BRK0_STAT);
430,8 → 430,8
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
dbg_i2c_rd(BRK0_STAT);
589,8 → 589,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
dbg_i2c_rd(BRK0_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK0_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK0_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
604,8 → 604,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
dbg_i2c_rd(BRK0_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK0_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK0_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
634,8 → 634,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0011) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
dbg_i2c_rd(BRK0_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_i2c_wr(BRK0_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_i2c_wr(BRK0_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
/dbg_uart_hwbrk1.v
164,8 → 164,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
dbg_uart_rd(BRK1_STAT);
179,7 → 179,7
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
195,7 → 195,7
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
dbg_uart_rd(BRK1_STAT);
347,8 → 347,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK1_STAT, 16'h0002);
if (dbg_uart_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK1_STAT, 16'h0003);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
362,8 → 362,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK1_STAT, 16'h0008);
if (dbg_uart_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK1_STAT, 16'h000C);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
418,8 → 418,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
dbg_uart_rd(BRK1_STAT);
433,8 → 433,8
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
dbg_uart_rd(BRK1_STAT);
591,8 → 591,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK1_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK1_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
606,8 → 606,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK1_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK1_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
636,8 → 636,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
dbg_uart_rd(BRK1_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_uart_wr(BRK1_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_uart_wr(BRK1_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
/dbg_i2c_hwbrk1.v
161,8 → 161,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
dbg_i2c_rd(BRK1_STAT);
176,7 → 176,7
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
192,7 → 192,7
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
dbg_i2c_rd(BRK1_STAT);
344,8 → 344,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
dbg_i2c_rd(BRK1_STAT);
if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK1_STAT, 16'h0002);
if (dbg_i2c_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK1_STAT, 16'h0003);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
359,8 → 359,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
dbg_i2c_rd(BRK1_STAT);
if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK1_STAT, 16'h0008);
if (dbg_i2c_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK1_STAT, 16'h000C);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
415,8 → 415,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
dbg_i2c_rd(BRK1_STAT);
430,8 → 430,8
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
dbg_i2c_rd(BRK1_STAT);
588,8 → 588,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
dbg_i2c_rd(BRK1_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK1_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK1_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
603,8 → 603,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
dbg_i2c_rd(BRK1_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK1_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK1_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
633,8 → 633,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0021) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
dbg_i2c_rd(BRK1_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_i2c_wr(BRK1_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_i2c_wr(BRK1_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
/dbg_uart_rdwr.v
138,11 → 138,10
`ifdef DBG_HWBRK_0
`ifdef DBG_HWBRK_RANGE
8 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK0_CTL)");
9 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK0_STAT)");
`else
8 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK0_CTL)");
9 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK0_STAT)");
`endif
9 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK0_STAT)");
10 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR0)");
11 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK0_ADDR1)");
`endif
149,11 → 148,10
`ifdef DBG_HWBRK_1
`ifdef DBG_HWBRK_RANGE
12 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK1_CTL)");
13 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK1_STAT)");
`else
12 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK1_CTL)");
13 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK1_STAT)");
`endif
13 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK1_STAT)");
14 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR0)");
15 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK1_ADDR1)");
`endif
160,11 → 158,10
`ifdef DBG_HWBRK_2
`ifdef DBG_HWBRK_RANGE
16 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK2_CTL)");
17 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK2_STAT)");
`else
16 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK2_CTL)");
17 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK2_STAT)");
`endif
17 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK2_STAT)");
18 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR0)");
19 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK2_ADDR1)");
`endif
171,11 → 168,10
`ifdef DBG_HWBRK_3
`ifdef DBG_HWBRK_RANGE
20 : if (dbg_uart_buf !== 16'h001F) tb_error("READ 2 ERROR (BRK3_CTL)");
21 : if (dbg_uart_buf !== 16'h0010) tb_error("READ 2 ERROR (BRK3_STAT)");
`else
20 : if (dbg_uart_buf !== 16'h000F) tb_error("READ 2 ERROR (BRK3_CTL)");
21 : if (dbg_uart_buf !== 16'h0005) tb_error("READ 2 ERROR (BRK3_STAT)");
`endif
21 : if (dbg_uart_buf !== 16'h0000) tb_error("READ 2 ERROR (BRK3_STAT)");
22 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR0)");
23 : if (dbg_uart_buf !== 16'hFFFF) tb_error("READ 2 ERROR (BRK3_ADDR1)");
`endif
/dbg_uart_hwbrk2.v
164,8 → 164,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0c)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
dbg_uart_rd(BRK2_STAT);
179,7 → 179,7
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
195,7 → 195,7
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
dbg_uart_rd(BRK2_STAT);
347,8 → 347,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK2_STAT, 16'h0002);
if (dbg_uart_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK2_STAT, 16'h0003);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
362,8 → 362,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK2_STAT, 16'h0008);
if (dbg_uart_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK2_STAT, 16'h000C);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
418,8 → 418,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
dbg_uart_rd(BRK2_STAT);
433,8 → 433,8
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
dbg_uart_rd(BRK2_STAT);
593,8 → 593,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK2_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK2_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
608,8 → 608,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK2_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK2_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
638,8 → 638,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
dbg_uart_rd(BRK2_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_uart_wr(BRK2_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_uart_wr(BRK2_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
/dbg_i2c_hwbrk2.v
161,8 → 161,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
dbg_i2c_rd(BRK2_STAT);
176,7 → 176,7
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
192,7 → 192,7
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
dbg_i2c_rd(BRK2_STAT);
344,8 → 344,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
dbg_i2c_rd(BRK2_STAT);
if (dbg_i2c_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK2_STAT, 16'h0002);
if (dbg_i2c_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK2_STAT, 16'h0003);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
359,8 → 359,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
dbg_i2c_rd(BRK2_STAT);
if (dbg_i2c_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK2_STAT, 16'h0008);
if (dbg_i2c_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK2_STAT, 16'h000C);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
415,8 → 415,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
dbg_i2c_rd(BRK2_STAT);
430,8 → 430,8
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
dbg_i2c_rd(BRK2_STAT);
590,8 → 590,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
dbg_i2c_rd(BRK2_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK2_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_i2c_wr(BRK2_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
605,8 → 605,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
dbg_i2c_rd(BRK2_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK2_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_i2c_wr(BRK2_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
635,8 → 635,8
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0041) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
dbg_i2c_rd(BRK2_STAT);
if (dbg_i2c_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_i2c_wr(BRK2_STAT, 16'h0020);
if (dbg_i2c_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_i2c_wr(BRK2_STAT, 16'h0030);
dbg_i2c_rd(CPU_STAT);
if (dbg_i2c_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 
/dbg_uart_hwbrk3.v
164,8 → 164,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 3 =====");
dbg_uart_rd(BRK3_STAT);
179,7 → 179,7
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h1C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h14)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 6 =====");
if (mem200 !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ: test 8 =====");
195,7 → 195,7
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 11 =====");
if (mem200 !== 16'h0002) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 12 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - SINGLE ADDRESSES - READ: test 13 =====");
dbg_uart_rd(BRK3_STAT);
347,8 → 347,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 13 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK3_STAT, 16'h0002);
if (dbg_uart_buf !== 16'h0003) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK3_STAT, 16'h0003);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 15 =====");
 
362,8 → 362,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 18 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0008) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK3_STAT, 16'h0008);
if (dbg_uart_buf !== 16'h000C) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK3_STAT, 16'h000C);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - SINGLE ADDRESSES - READ/WRITE: test 20 =====");
 
418,8 → 418,8
repeat(100) @(posedge mclk);
 
// CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0001) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h08)) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 1 =====");
if (mem200 !== 16'h0000) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 2 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== DATA FLOW (EXECUTION-UNIT) - ADDRESS RANGE - READ: test 3 =====");
dbg_uart_rd(BRK3_STAT);
433,8 → 433,8
repeat(100) @(posedge mclk);
 
// RE-CHECK
if (r0 !== ('h10000-`PMEM_SIZE+'h18)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0002) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
if (r0 !== ('h10000-`PMEM_SIZE+'h0C)) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 6 =====");
if (mem200 !== 16'h0000) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 7 =====");
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ: test 8 =====");
dbg_uart_rd(BRK3_STAT);
592,8 → 592,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 13 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK3_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 14 =====");
dbg_uart_wr(BRK3_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 15 =====");
 
607,8 → 607,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 18 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK3_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 19 =====");
dbg_uart_wr(BRK3_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 20 =====");
 
637,8 → 637,8
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0081) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 28 =====");
dbg_uart_rd(BRK3_STAT);
if (dbg_uart_buf !== 16'h0020) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_uart_wr(BRK3_STAT, 16'h0020);
if (dbg_uart_buf !== 16'h0030) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 29 =====");
dbg_uart_wr(BRK3_STAT, 16'h0030);
dbg_uart_rd(CPU_STAT);
if (dbg_uart_buf !== 16'h0001) tb_error("====== INSTRUCTION FLOW (FRONTEND) - ADDRESS RANGE - READ/WRITE: test 30 =====");
 

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