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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

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  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/core/sim/rtl_sim
    from Rev 115 to Rev 122
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  •

Rev 115 → Rev 122

/run/run_coverage_analysis
0,0 → 1,15
#!/bin/bash
 
# NOTE:
# COVERAGE ANALYSIS IS ONLY AVAILABLE
# IF THE SIMULATION REGRESSION (i.e. run_all script)
# WAS RUN USING "ncverilog" SIMULATOR
 
# Remove old merged report
rm -rf cov_work/design/merged_coverage
 
# Merge all available coverage reports
iccr ../bin/cov_iccr_merge.cf
 
# Launch GUI
iccr -test cov_work/design/merged_coverage -GUI
run/run_coverage_analysis Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: run/run =================================================================== --- run/run (revision 115) +++ run/run (revision 122) @@ -4,4 +4,15 @@ OMSP_NODUMP=0 export OMSP_NODUMP +# Choose simulator: +# - iverilog : Icarus Verilog (default) +# - cver : CVer +# - verilog : Verilog-XL +# - ncverilog : NC-Verilog +# - vcs : VCS +# - vsim : Modelsim +# - isim : Xilinx simulator +OMSP_SIMULATOR=iverilog +export OMSP_SIMULATOR + ../bin/msp430sim two-op_mov
/run/run_all
4,103 → 4,115
OMSP_NODUMP=1
export OMSP_NODUMP
 
rm -rf *.log
# Choose simulator:
# - iverilog : Icarus Verilog (default)
# - cver : CVer
# - verilog : Verilog-XL
# - ncverilog : NC-Verilog
# - vcs : VCS
# - vsim : Modelsim
# - isim : Xilinx simulator
OMSP_SIMULATOR=iverilog
export OMSP_SIMULATOR
 
rm -rf ./log/*.log
mkdir ./log
 
# Two-Operand Arithmetic test patterns
../bin/msp430sim two-op_mov | tee two-op_mov.log
../bin/msp430sim two-op_mov-b | tee two-op_mov-b.log
../bin/msp430sim two-op_add | tee two-op_add.log
../bin/msp430sim two-op_add-b | tee two-op_add-b.log
../bin/msp430sim two-op_addc | tee two-op_addc.log
../bin/msp430sim two-op_sub | tee two-op_sub.log
../bin/msp430sim two-op_subc | tee two-op_subc.log
../bin/msp430sim two-op_cmp | tee two-op_cmp.log
../bin/msp430sim two-op_bit | tee two-op_bit.log
../bin/msp430sim two-op_bic | tee two-op_bic.log
../bin/msp430sim two-op_bis | tee two-op_bis.log
../bin/msp430sim two-op_xor | tee two-op_xor.log
../bin/msp430sim two-op_and | tee two-op_and.log
../bin/msp430sim two-op_dadd | tee two-op_dadd.log
../bin/msp430sim two-op_mov | tee ./log/two-op_mov.log
../bin/msp430sim two-op_mov-b | tee ./log/two-op_mov-b.log
../bin/msp430sim two-op_add | tee ./log/two-op_add.log
../bin/msp430sim two-op_add-b | tee ./log/two-op_add-b.log
../bin/msp430sim two-op_addc | tee ./log/two-op_addc.log
../bin/msp430sim two-op_sub | tee ./log/two-op_sub.log
../bin/msp430sim two-op_subc | tee ./log/two-op_subc.log
../bin/msp430sim two-op_cmp | tee ./log/two-op_cmp.log
../bin/msp430sim two-op_bit | tee ./log/two-op_bit.log
../bin/msp430sim two-op_bic | tee ./log/two-op_bic.log
../bin/msp430sim two-op_bis | tee ./log/two-op_bis.log
../bin/msp430sim two-op_xor | tee ./log/two-op_xor.log
../bin/msp430sim two-op_and | tee ./log/two-op_and.log
../bin/msp430sim two-op_dadd | tee ./log/two-op_dadd.log
 
# Conditional Jump test patterns
../bin/msp430sim c-jump_jeq | tee c-jump_jeq.log
../bin/msp430sim c-jump_jne | tee c-jump_jne.log
../bin/msp430sim c-jump_jc | tee c-jump_jc.log
../bin/msp430sim c-jump_jnc | tee c-jump_jnc.log
../bin/msp430sim c-jump_jn | tee c-jump_jn.log
../bin/msp430sim c-jump_jge | tee c-jump_jge.log
../bin/msp430sim c-jump_jl | tee c-jump_jl.log
../bin/msp430sim c-jump_jmp | tee c-jump_jmp.log
../bin/msp430sim c-jump_jeq | tee ./log/c-jump_jeq.log
../bin/msp430sim c-jump_jne | tee ./log/c-jump_jne.log
../bin/msp430sim c-jump_jc | tee ./log/c-jump_jc.log
../bin/msp430sim c-jump_jnc | tee ./log/c-jump_jnc.log
../bin/msp430sim c-jump_jn | tee ./log/c-jump_jn.log
../bin/msp430sim c-jump_jge | tee ./log/c-jump_jge.log
../bin/msp430sim c-jump_jl | tee ./log/c-jump_jl.log
../bin/msp430sim c-jump_jmp | tee ./log/c-jump_jmp.log
 
# Single-Operand Arithmetic test patterns
../bin/msp430sim sing-op_rrc | tee sing-op_rrc.log
../bin/msp430sim sing-op_rra | tee sing-op_rra.log
../bin/msp430sim sing-op_swpb | tee sing-op_swpb.log
../bin/msp430sim sing-op_sxt | tee sing-op_sxt.log
../bin/msp430sim sing-op_push | tee sing-op_push.log
../bin/msp430sim sing-op_call | tee sing-op_call.log
../bin/msp430sim sing-op_reti | tee sing-op_reti.log
../bin/msp430sim sing-op_rrc | tee ./log/sing-op_rrc.log
../bin/msp430sim sing-op_rra | tee ./log/sing-op_rra.log
../bin/msp430sim sing-op_swpb | tee ./log/sing-op_swpb.log
../bin/msp430sim sing-op_sxt | tee ./log/sing-op_sxt.log
../bin/msp430sim sing-op_push | tee ./log/sing-op_push.log
../bin/msp430sim sing-op_call | tee ./log/sing-op_call.log
../bin/msp430sim sing-op_reti | tee ./log/sing-op_reti.log
 
# ROM Data Read access
../bin/msp430sim two-op_add_rom-rd | tee two-op_add_rom-rd.log
../bin/msp430sim sing-op_push_rom-rd | tee sing-op_push_rom-rd.log
../bin/msp430sim sing-op_call_rom-rd | tee sing-op_call_rom-rd.log
../bin/msp430sim two-op_add_rom-rd | tee ./log/two-op_add_rom-rd.log
../bin/msp430sim sing-op_push_rom-rd | tee ./log/sing-op_push_rom-rd.log
../bin/msp430sim sing-op_call_rom-rd | tee ./log/sing-op_call_rom-rd.log
 
# Power saving modes (CPUOFF, OSCOFF, SCG1)
../bin/msp430sim op_modes | tee op_modes.log
../bin/msp430sim op_modes | tee ./log/op_modes.log
 
# Basic clock module
../bin/msp430sim clock_module | tee clock_module.log
../bin/msp430sim clock_module | tee ./log/clock_module.log
 
# Serial Debug Interface
../bin/msp430sim dbg_uart | tee dbg_uart.log
../bin/msp430sim dbg_cpu | tee dbg_cpu.log
../bin/msp430sim dbg_mem | tee dbg_mem.log
../bin/msp430sim dbg_hwbrk0 | tee dbg_hwbrk0.log
../bin/msp430sim dbg_hwbrk1 | tee dbg_hwbrk1.log
../bin/msp430sim dbg_hwbrk2 | tee dbg_hwbrk2.log
../bin/msp430sim dbg_hwbrk3 | tee dbg_hwbrk3.log
../bin/msp430sim dbg_halt_irq | tee dbg_halt_irq.log
../bin/msp430sim dbg_onoff | tee dbg_onoff.log
../bin/msp430sim dbg_uart | tee ./log/dbg_uart.log
../bin/msp430sim dbg_cpu | tee ./log/dbg_cpu.log
../bin/msp430sim dbg_mem | tee ./log/dbg_mem.log
../bin/msp430sim dbg_hwbrk0 | tee ./log/dbg_hwbrk0.log
../bin/msp430sim dbg_hwbrk1 | tee ./log/dbg_hwbrk1.log
../bin/msp430sim dbg_hwbrk2 | tee ./log/dbg_hwbrk2.log
../bin/msp430sim dbg_hwbrk3 | tee ./log/dbg_hwbrk3.log
../bin/msp430sim dbg_halt_irq | tee ./log/dbg_halt_irq.log
../bin/msp430sim dbg_onoff | tee ./log/dbg_onoff.log
 
# Watchdog test patterns
../bin/msp430sim wdt_interval | tee wdt_interval.log
../bin/msp430sim wdt_watchdog | tee wdt_watchdog.log
../bin/msp430sim wdt_clkmux | tee wdt_clkmux.log
../bin/msp430sim wdt_interval | tee ./log/wdt_interval.log
../bin/msp430sim wdt_watchdog | tee ./log/wdt_watchdog.log
../bin/msp430sim wdt_clkmux | tee ./log/wdt_clkmux.log
 
# GPIO test patterns
../bin/msp430sim gpio_rdwr | tee gpio_rdwr.log
../bin/msp430sim gpio_irq | tee gpio_irq.log
../bin/msp430sim gpio_rdwr | tee ./log/gpio_rdwr.log
../bin/msp430sim gpio_irq | tee ./log/gpio_irq.log
 
# Peripheral templates test patterns
../bin/msp430sim template_periph_8b | tee template_periph_8b.log
../bin/msp430sim template_periph_16b | tee template_periph_16b.log
../bin/msp430sim template_periph_8b | tee ./log/template_periph_8b.log
../bin/msp430sim template_periph_16b | tee ./log/template_periph_16b.log
 
# Timer A patterns
../bin/msp430sim tA_modes | tee tA_modes.log
../bin/msp430sim tA_compare | tee tA_compare.log
../bin/msp430sim tA_output | tee tA_output.log
../bin/msp430sim tA_capture | tee tA_capture.log
../bin/msp430sim tA_clkmux | tee tA_clkmux.log
../bin/msp430sim tA_modes | tee ./log/tA_modes.log
../bin/msp430sim tA_compare | tee ./log/tA_compare.log
../bin/msp430sim tA_output | tee ./log/tA_output.log
../bin/msp430sim tA_capture | tee ./log/tA_capture.log
../bin/msp430sim tA_clkmux | tee ./log/tA_clkmux.log
 
 
# Hardware multiplier test patterns
../bin/msp430sim mpy_basic | tee mpy_basic.log
../bin/msp430sim mpy_basic | tee ./log/mpy_basic.log
 
 
grep SKIPPED *.log
grep FAILED *.log
grep SKIPPED ./log/*.log
grep FAILED ./log/*.log
echo ""
echo " ================================"
echo -n "| Number of passed patterns : "
cat *.log | grep -c PASSED
cat ./log/*.log | grep -c PASSED
echo -n "| Number of failed patterns : "
cat *.log | grep -c FAILED
cat ./log/*.log | grep -c FAILED
echo -n "| Number of skipped patterns: "
cat *.log | grep -c SKIPPED
cat ./log/*.log | grep -c SKIPPED
echo "|--------------------------------"
echo -n "| Number of patterns: "
ls -1 *.log | wc -l
ls -1 ./log/*.log | wc -l
echo " ================================"
echo " Make sure passed == total"
echo ""
/bin/msp430sim
43,7 → 43,7
echo "USAGE : msp430sim <test name>"
echo "Example : msp430sim c-jump_jge"
echo ""
echo "In order to switch the verilog simulator, the MYVLOG environment"
echo "In order to switch the verilog simulator, the OMSP_SIMULATOR environment"
echo "variable can be set to the following values:"
echo ""
echo " - iverilog : Icarus Verilog (default)"
52,6 → 52,7
echo " - ncverilog : NC-Verilog"
echo " - vcs : VCS"
echo " - vsim : Modelsim"
echo " - isim : Xilinx simulator"
echo ""
exit 1
fi
62,9 → 63,12
###############################################################################
asmfile=../src/$1.s43;
verfile=../src/$1.v;
submitfile=../src/submit.f;
incfile=../../../rtl/verilog/openMSP430_defines.v;
deffile=../bin/template.def;
submitfile=../src/submit.f;
if [ $OMSP_SIMULATOR == "isim" ]; then
submitfile=../src/submit.prj;
fi
 
if [ ! -e $asmfile ]; then
echo "Assembler file $asmfile doesn't exist: $asmfile"
/bin/cov_ncverilog.tcl
0,0 → 1,8
set mytest [file link stimulus.v]
set mytest [file rootname [file tail $mytest]]
 
coverage -setup -testname $mytest -dut tb_openMSP430.dut
 
run
quit
 
bin/cov_ncverilog.tcl Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: bin/msp430sim_c =================================================================== --- bin/msp430sim_c (revision 115) +++ bin/msp430sim_c (revision 122) @@ -43,7 +43,7 @@ echo "USAGE : msp430sim_c " echo "Example : msp430sim_c sandbox" echo "" - echo "In order to switch the verilog simulator, the MYVLOG environment" + echo "In order to switch the verilog simulator, the OMSP_SIMULATOR environment" echo "variable can be set to the following values:" echo "" echo " - iverilog : Icarus Verilog (default)" @@ -52,6 +52,7 @@ echo " - ncverilog : NC-Verilog" echo " - vcs : VCS" echo " - vsim : Modelsim" + echo " - isim : Xilinx simulator" echo "" exit 1 fi @@ -63,8 +64,11 @@ softdir=../src-c/$1; elffile=../src-c/$1/$1.elf; verfile=../src-c/$1/$1.v; +incfile=../../../rtl/verilog/openMSP430_defines.v; submitfile=../src/submit.f; -incfile=../../../rtl/verilog/openMSP430_defines.v; +if [ $OMSP_SIMULATOR == "isim" ]; then + submitfile=../src/submit.prj; +fi if [ ! -e $softdir ]; then echo "Software directory doesn't exist: $softdir"
/bin/rtlsim.sh
43,7 → 43,7
echo "ERROR : wrong number of arguments"
echo "USAGE : rtlsim.sh <verilog stimulus file> <memory file> <submit file>"
echo "Example : rtlsim.sh ./stimulus.v pmem.mem ../src/submit.f"
echo "MYVLOG env keeps simulator name iverilog/cver/verilog/ncverilog/vsim/vcs"
echo "OMSP_SIMULATOR env keeps simulator name iverilog/cver/verilog/ncverilog/vsim/vcs"
exit 1
fi
 
70,7 → 70,7
# Start verilog simulation #
###############################################################################
 
if [ "${MYVLOG:-iverilog}" = iverilog ]; then
if [ "${OMSP_SIMULATOR:-iverilog}" = iverilog ]; then
 
rm -rf simv
92,7 → 92,7
vargs=""
fi
 
case $MYVLOG in
case $OMSP_SIMULATOR in
cver* )
vargs="$vargs +define+VXL +define+CVER" ;;
verilog* )
99,17 → 99,24
vargs="$vargs +define+VXL" ;;
ncverilog* )
rm -rf INCA_libs
vargs="$vargs +access+r +define+TRN_FILE" ;;
vargs="$vargs +access+r +ncinput+../bin/cov_ncverilog.tcl -covfile ../bin/cov_ncverilog.ccf -coverage all +define+TRN_FILE" ;;
vcs* )
rm -rf csrc simv*
vargs="$vargs -R -debug_pp +vcs+lic+wait +v2k +define+VPD_FILE" ;;
vsim )
vsim* )
# Modelsim
if [ -d work ]; then vdel -all; fi
vlib work
exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all"
exec vlog +acc=prn -f $3 $vargs -R -c -do "run -all" ;;
isim )
# Xilinx simulator
rm -rf fuse* isim*
fuse tb_openMSP430 -prj $3 -o isim.exe -i ../../../bench/verilog/ -i ../../../rtl/verilog/ -i ../../../rtl/verilog/periph/
echo "run all" > isim.tcl
./isim.exe -tclbatch isim.tcl
exit
esac
echo "Running: $MYVLOG -f $3 $vargs"
exec $MYVLOG -f $3 $vargs
echo "Running: $OMSP_SIMULATOR -f $3 $vargs"
exec $OMSP_SIMULATOR -f $3 $vargs
fi
/bin/cov_exclude.dat
0,0 → 1,3
 
module openMSP430.scan_enable
module openMSP430.scan_mode
bin/cov_exclude.dat Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: bin/cov_exclude_bits.dat =================================================================== --- bin/cov_exclude_bits.dat (nonexistent) +++ bin/cov_exclude_bits.dat (revision 122) @@ -0,0 +1,69 @@ +#============================================ +# FRONTENT +#============================================ + +# Exclude pc[0] as these are constant signals + -ere instance tb_openMSP430\.dut\.frontend_0\.pc\[0\] + -ere instance tb_openMSP430\.dut\.frontend_0\.pc_incr\[0\] + +# Exclude irq_addr[15:5] and irq_addr[0] as these are constant signals + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[15\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[14\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[13\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[12\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[11\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[10\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[9\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[8\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[7\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[6\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[5\] + -ere instance tb_openMSP430\.dut\.frontend_0\.irq_addr\[0\] + +# Exclude inst_ad[7/5/3/2] as these are constant signals + -ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[7\] + -ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[5\] + -ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[3\] + -ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad\[2\] + -ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad_nxt\[7\] + -ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad_nxt\[5\] + -ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad_nxt\[3\] + -ere instance tb_openMSP430\.dut\.frontend_0\.inst_ad_nxt\[2\] + +# Diverse remaining constants + -ere instance tb_openMSP430\.dut\.frontend_0\.ext_incr\[0\] + + +#============================================ +# EXECUTION UNIT +#============================================ + +# Exclude pc[0] as these are constant signals + -ere instance tb_openMSP430\.dut\.execution_unit_0\.pc\[0\] + +# Exclude inst_ad[7/5/3/2] as these are constant signals + -ere instance tb_openMSP430\.dut\.execution_unit_0\.inst_ad\[7\] + -ere instance tb_openMSP430\.dut\.execution_unit_0\.inst_ad\[5\] + -ere instance tb_openMSP430\.dut\.execution_unit_0\.inst_ad\[3\] + -ere instance tb_openMSP430\.dut\.execution_unit_0\.inst_ad\[2\] + + +#============================================ +# MEMORY BACKBONE +#============================================ + +# Higher peripheral address bits might be constants depending on the configuration + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[13\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[12\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[11\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[10\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[9\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr\[8\] + + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[14\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[13\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[12\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[11\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[10\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[9\] + -ere instance tb_openMSP430\.dut\.mem_backbone_0\.per_addr_ful\[8\]
bin/cov_exclude_bits.dat Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: bin/cov_ncverilog.ccf =================================================================== --- bin/cov_ncverilog.ccf (nonexistent) +++ bin/cov_ncverilog.ccf (revision 122) @@ -0,0 +1,4 @@ + +#set_expr_scoring -all +set_toggle_excludefile ../bin/cov_exclude.dat +set_toggle_excludefile -bitexclude ../bin/cov_exclude_bits.dat
bin/cov_ncverilog.ccf Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Index: bin/cov_iccr_merge.cf =================================================================== --- bin/cov_iccr_merge.cf (nonexistent) +++ bin/cov_iccr_merge.cf (revision 122) @@ -0,0 +1,10 @@ +set mytests_ucd [glob cov_work/design/*/icc.ucd] + +set mytests "" +foreach ucd_file $mytests_ucd { + lappend mytests [file dirname $ucd_file] +} + +eval load_test $mytests +eval merge $mytests -output merged_coverage +quit
bin/cov_iccr_merge.cf Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property

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