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URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

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  • This comparison shows the changes necessary to convert path 
    /openmsp430/trunk/core/synthesis
    from Rev 2 to Rev 56
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  •

Rev 2 → Rev 56

/synopsys/library.tcl
19,10 → 19,11
# Define wire-load model
set LIB_WIRE_LOAD "<YOUR WIRE LOAD MODEL>"
 
# Define nand2 gate name for aera size calculation
set NAND2_NAME "<YOUR LIBRARY NAND2 GATE NAME>"
 
 
# Set library
set target_library $LIB_WC_FILE
set link_library $LIB_WC_FILE
set_min_library $LIB_WC_FILE -min_version $LIB_BC_FILE
 
 
/synopsys/constraints.tcl
4,10 → 4,8
# #
##############################################################################
 
#set CLOCK_PERIOD 50.0; # 20 MHz
#set CLOCK_PERIOD 40.0; # 25 MHz
#set CLOCK_PERIOD 30.0; # 33 MHz
#set CLOCK_PERIOD 25.0; # 40 MHz
set CLOCK_PERIOD 20.0; # 50 MHz
#set CLOCK_PERIOD 15.0; # 66 MHz
#set CLOCK_PERIOD 10.0; # 100 MHz
14,10 → 12,10
#set CLOCK_PERIOD 8.0; # 125 MHz
 
 
create_clock -name "clock" \
create_clock -name "dco_clk" \
-period "$CLOCK_PERIOD" \
-waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \
[get_ports clock]
[get_ports dco_clk]
 
 
##############################################################################
27,8 → 25,8
##############################################################################
 
group_path -name REGOUT -to [all_outputs]
group_path -name REGIN -from [remove_from_collection [all_inputs] [get_ports clock]]
group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] [get_ports clock]] -to [all_outputs]
group_path -name REGIN -from [remove_from_collection [all_inputs] [get_ports dco_clk]]
group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] [get_ports dco_clk]] -to [all_outputs]
 
 
##############################################################################
36,106 → 34,149
# BOUNDARY TIMINGS #
# #
##############################################################################
# NOTE: There are some path through between RAM and ROM signals.
# If required you might want to relax the constrains a bit.
# NOTE: There are some path through between Program/Data memory signals
# which are limiting the maximum frequency achievable by the core.
# The memory constraints set on these interfaces are therefore quite
# critical regarding the achievable performance of the core.
# As a consequence, the constrains on the pmem_*/dmem_* signals must
# be set with some absolute values as they are specified by the targeted
# process RAM/ROM generator.
 
#===============#
# INPUT PORTS #
#===============#
#================#
# PROGRAM MEMORY #
#================#
 
set IRQ_DLY [expr ($CLOCK_PERIOD/100) * 30]
set NMI_DLY [expr ($CLOCK_PERIOD/100) * 10]
set PMEM_DOUT_DLY 2.25
 
set PER_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]
set RAM_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]
set ROM_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]
set PMEM_ADDR_DLY 0.64
set PMEM_CEN_DLY 0.63
set PMEM_DIN_DLY 0.39
set PMEM_WEN_DLY 0.44
 
set RESET_N_DLY [expr ($CLOCK_PERIOD/100) * 75]
set_input_delay $PMEM_DOUT_DLY -max -clock "dco_clk" [get_ports pmem_dout]
set_input_delay 0 -min -clock "dco_clk" [get_ports pmem_dout]
 
set_output_delay $PMEM_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_addr]
set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_addr]
 
set_input_delay $IRQ_DLY -max -clock "clock" [get_ports irq]
set_input_delay 0 -min -clock "clock" [get_ports irq]
set_output_delay $PMEM_CEN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_cen]
set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_cen]
 
set_input_delay $NMI_DLY -max -clock "clock" [get_ports nmi]
set_input_delay 0 -min -clock "clock" [get_ports nmi]
set_output_delay $PMEM_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_din]
set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_din]
 
set_input_delay $PER_DOUT_DLY -max -clock "clock" [get_ports per_dout]
set_input_delay 0 -min -clock "clock" [get_ports per_dout]
set_output_delay $PMEM_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_wen]
set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_wen]
 
set_input_delay $RAM_DOUT_DLY -max -clock "clock" [get_ports ram_dout]
set_input_delay 0 -min -clock "clock" [get_ports ram_dout]
 
set_input_delay $ROM_DOUT_DLY -max -clock "clock" [get_ports rom_dout]
set_input_delay 0 -min -clock "clock" [get_ports rom_dout]
#================#
# DATA MEMORY #
#================#
 
set_input_delay $RESET_N_DLY -max -clock "clock" -clock_fall [get_ports reset_n]
set_input_delay 0 -min -clock "clock" -clock_fall [get_ports reset_n]
set DMEM_DOUT_DLY 2.25
 
set DMEM_ADDR_DLY 0.64
set DMEM_CEN_DLY 0.63
set DMEM_DIN_DLY 0.39
set DMEM_WEN_DLY 0.44
 
#===============#
# OUTPUT PORTS #
#===============#
 
set PER_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 25]
set PER_DIN_DLY [expr ($CLOCK_PERIOD/100) * 25]
set PER_WEN_DLY [expr ($CLOCK_PERIOD/100) * 25]
set PER_8B_CEN_DLY [expr ($CLOCK_PERIOD/100) * 25]
set PER_16B_CEN_DLY [expr ($CLOCK_PERIOD/100) * 25]
set_input_delay $DMEM_DOUT_DLY -max -clock "dco_clk" [get_ports dmem_dout]
set_input_delay 0 -min -clock "dco_clk" [get_ports dmem_dout]
 
set RAM_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 20]
set RAM_CEN_DLY [expr ($CLOCK_PERIOD/100) * 20]
set RAM_DIN_DLY [expr ($CLOCK_PERIOD/100) * 20]
set RAM_WEN_DLY [expr ($CLOCK_PERIOD/100) * 20]
set_output_delay $DMEM_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_addr]
set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_addr]
 
set ROM_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 20]
set ROM_CEN_DLY [expr ($CLOCK_PERIOD/100) * 20]
set_output_delay $DMEM_CEN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_cen]
set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_cen]
 
set MRST_DLY [expr ($CLOCK_PERIOD/100) * 75]
set_output_delay $DMEM_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_din]
set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_din]
 
set_output_delay $DMEM_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_wen]
set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_wen]
 
set_output_delay $PER_ADDR_DLY -add_delay -max -clock "clock" [get_ports per_addr]
set_output_delay 0 -min -clock "clock" [get_ports per_addr]
 
set_output_delay $PER_DIN_DLY -add_delay -max -clock "clock" [get_ports per_din]
set_output_delay 0 -min -clock "clock" [get_ports per_din]
#==========================#
# REMAINING INPUT PORTS #
#==========================#
 
set_output_delay $PER_WEN_DLY -add_delay -max -clock "clock" [get_ports per_wen]
set_output_delay 0 -min -clock "clock" [get_ports per_wen]
set IRQ_DLY [expr ($CLOCK_PERIOD/100) * 30]
set PER_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]
 
set_output_delay $PER_8B_CEN_DLY -add_delay -max -clock "clock" [get_ports per_8b_cen]
set_output_delay 0 -min -clock "clock" [get_ports per_8b_cen]
 
set_output_delay $PER_16B_CEN_DLY -add_delay -max -clock "clock" [get_ports per_16b_cen]
set_output_delay 0 -min -clock "clock" [get_ports per_16b_cen]
set_input_delay $IRQ_DLY -max -clock "dco_clk" [get_ports irq]
set_input_delay 0 -min -clock "dco_clk" [get_ports irq]
 
set_output_delay $RAM_ADDR_DLY -add_delay -max -clock "clock" [get_ports ram_addr]
set_output_delay 0 -min -clock "clock" [get_ports ram_addr]
set_input_delay $PER_DOUT_DLY -max -clock "dco_clk" [get_ports per_dout]
set_input_delay 0 -min -clock "dco_clk" [get_ports per_dout]
 
set_output_delay $RAM_CEN_DLY -add_delay -max -clock "clock" [get_ports ram_cen]
set_output_delay 0 -min -clock "clock" [get_ports ram_cen]
 
set_output_delay $RAM_DIN_DLY -add_delay -max -clock "clock" [get_ports ram_din]
set_output_delay 0 -min -clock "clock" [get_ports ram_din]
#=========================#
# REMAINING OUTPUT PORTS #
#=========================#
 
set_output_delay $RAM_WEN_DLY -add_delay -max -clock "clock" [get_ports ram_wen]
set_output_delay 0 -min -clock "clock" [get_ports ram_wen]
set ACLK_EN_DLY [expr ($CLOCK_PERIOD/100) * 85]
set SMCLK_EN_DLY [expr ($CLOCK_PERIOD/100) * 85]
set DBG_FREEZE_DLY [expr ($CLOCK_PERIOD/100) * 85]
set IRQ_ACC_DLY [expr ($CLOCK_PERIOD/100) * 60]
 
set_output_delay $ROM_ADDR_DLY -add_delay -max -clock "clock" [get_ports rom_addr]
set_output_delay 0 -min -clock "clock" [get_ports rom_addr]
set PER_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 25]
set PER_DIN_DLY [expr ($CLOCK_PERIOD/100) * 25]
set PER_WEN_DLY [expr ($CLOCK_PERIOD/100) * 25]
set PER_EN_DLY [expr ($CLOCK_PERIOD/100) * 25]
 
set_output_delay $ROM_CEN_DLY -add_delay -max -clock "clock" [get_ports rom_cen]
set_output_delay 0 -min -clock "clock" [get_ports rom_cen]
set PUC_DLY [expr ($CLOCK_PERIOD/100) * 75]
 
set_output_delay $MRST_DLY -add_delay -max -clock "clock" -clock_fall [get_ports mrst]
set_output_delay 0 -min -clock "clock" -clock_fall [get_ports mrst]
 
set_output_delay $ACLK_EN_DLY -add_delay -max -clock "dco_clk" [get_ports aclk_en]
set_output_delay 0 -min -clock "dco_clk" [get_ports aclk_en]
 
set_output_delay $SMCLK_EN_DLY -add_delay -max -clock "dco_clk" [get_ports smclk_en]
set_output_delay 0 -min -clock "dco_clk" [get_ports smclk_en]
 
set_output_delay $DBG_FREEZE_DLY -add_delay -max -clock "dco_clk" [get_ports dbg_freeze]
set_output_delay 0 -min -clock "dco_clk" [get_ports dbg_freeze]
 
set_output_delay $IRQ_ACC_DLY -add_delay -max -clock "dco_clk" [get_ports irq_acc]
set_output_delay 0 -min -clock "dco_clk" [get_ports irq_acc]
 
 
set_output_delay $PER_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports per_addr]
set_output_delay 0 -min -clock "dco_clk" [get_ports per_addr]
 
set_output_delay $PER_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports per_din]
set_output_delay 0 -min -clock "dco_clk" [get_ports per_din]
 
set_output_delay $PER_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports per_wen]
set_output_delay 0 -min -clock "dco_clk" [get_ports per_wen]
 
set_output_delay $PER_EN_DLY -add_delay -max -clock "dco_clk" [get_ports per_en]
set_output_delay 0 -min -clock "dco_clk" [get_ports per_en]
 
set_output_delay $PUC_DLY -add_delay -max -clock "dco_clk" -clock_fall [get_ports puc]
set_output_delay 0 -min -clock "dco_clk" -clock_fall [get_ports puc]
 
 
#========================#
# FEEDTHROUGH EXCEPTIONS #
#========================#
 
#set_max_delay [expr 2.0 + $RAM_DOUT_DLY + $RAM_ADDR_DLY] \
# -from [get_ports ram_dout] \
# -to [get_ports ram_addr] \
#set_max_delay [expr 2.0 + $DMEM_DOUT_DLY + $DMEM_ADDR_DLY] \
# -from [get_ports dmem_dout] \
# -to [get_ports dmem_addr] \
# -group_path FEEDTHROUGH
 
 
#===============#
# FALSE PATHS #
#===============#
# The following signals are internaly synchronized to
# the dco_clk domain and can be set as false path.
 
set_false_path -from dbg_uart_rxd
set_false_path -to dbg_uart_txd
 
set_false_path -from nmi
set_false_path -from lfxt_clk
set_false_path -from reset_n
/synopsys/synthesis.tcl
1,5 → 1,4
 
 
#=============================================================================#
# Read technology library #
#=============================================================================#
60,9 → 59,20
redirect ./results/report.full_paths.max {report_timing -path full -delay max -max_paths 5 -nworst 2}
redirect ./results/report.paths.min {report_timing -path end -delay min -max_paths 200 -nworst 2}
redirect ./results/report.full_paths.min {report_timing -path full -delay min -max_paths 5 -nworst 2}
redirect ./results/report.refs {report_reference}
redirect ./results/report.area {report_area}
redirect ./results/report.refs {report_reference}
 
# Add NAND2 size equivalent report to the area report file
if {[info exists NAND2_NAME]} {
set nand2_area [get_attribute [get_lib_cell $LIB_WC_NAME/$NAND2_NAME] area]
redirect -variable area {report_area}
regexp {Total cell area:\s+([^\n]+)\n} $area whole_match area
set nand2_eq [expr $area/$nand2_area]
set fp [open "./results/report.area" a]
puts $fp ""
puts $fp "NAND2 equivalent cell area: $nand2_eq"
close $fp
}
 
#=============================================================================#
# Dump gate level netlist & final DDC file #
/synopsys/read.tcl
5,17 → 5,21
##############################################################################
 
set DESIGN_NAME "openMSP430"
set RTL_SOURCE_FILES {../../rtl/verilog/openMSP430.inc
../../rtl/verilog/openMSP430.v
../../rtl/verilog/cpu_frontend.v
../../rtl/verilog/cpu_execution_unit.v
../../rtl/verilog/cpu_register_file.v
../../rtl/verilog/cpu_alu.v
../../rtl/verilog/mem_backbone.v
../../rtl/verilog/sfr.v
../../rtl/verilog/watchdog.v
set RTL_SOURCE_FILES {../../rtl/verilog/openMSP430.v
../../rtl/verilog/omsp_frontend.v
../../rtl/verilog/omsp_execution_unit.v
../../rtl/verilog/omsp_register_file.v
../../rtl/verilog/omsp_alu.v
../../rtl/verilog/omsp_sfr.v
../../rtl/verilog/omsp_clock_module.v
../../rtl/verilog/omsp_mem_backbone.v
../../rtl/verilog/omsp_watchdog.v
../../rtl/verilog/omsp_dbg.v
../../rtl/verilog/omsp_dbg_uart.v
../../rtl/verilog/omsp_dbg_hwbrk.v
}
 
 
set_svf ./results/$DESIGN_NAME.svf
define_design_lib WORK -path ./WORK
analyze -format verilog $RTL_SOURCE_FILES

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