URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/openmsp430/trunk
- from Rev 115 to Rev 116
- ↔ Reverse comparison
Rev 115 → Rev 116
/ChangeLog_tools.txt
1,3 → 1,7
2011-05-26 [r114] |
|
* Improved the VerifyCPU_ID procedure. |
|
2011-05-19 [r110] |
|
* Rework of the GUI for the software development tools. Added |
/doc/openMSP430.pdf
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/doc/html/software_development_tools.html
6,10 → 6,11
<li><a href="#2.%20openmsp430-loader"> 2. openmsp430-loader</a></li> |
<li><a href="#3.%20openmsp430-minidebug"> 3. openmsp430-minidebug</a></li> |
<li><a href="#4.%20openmsp430-gdbproxy"> 4. openmsp430-gdbproxy</a></li> |
<li><a href="#5.%20MSPGCC%20Toolchain"> 5. MSPGCC Toolchain</a> |
<li><a href="#5.%20MSPGCC(4)%20Toolchain"> 5. MSPGCC(4) Toolchain</a> |
<ul> |
<li><a href="#5.1%20Some%20notes%20regarding%20msp430-gdb"> 5.1 Some notes regarding msp430-gdb</a></li> |
<li><a href="#5.2%20CPU%20selection%20for%20msp430-gcc"> 5.2 CPU selection for msp430-gcc</a></li> |
<li><a href="#5.1%20Compiler%20options"> 5.1 Compiler options</a></li> |
<li><a href="#5.2%20MCU%20selection"> 5.2 MCU selection</a></li> |
<li><a href="#5.3%20Custom%20linker%20script"> 5.3 Custom linker script</a></li> |
</ul> |
</li> |
</ul> |
24,12 → 25,11
<li><b>openmsp430-gdbproxy:</b> GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends.</li> |
</ul> |
|
All these software development tools have been developed in TCL/TK and were successfully tested on both Linux and Windows XP. |
All these software development tools have been developed in TCL/TK and were successfully tested on both Linux and Windows (XP/Vista/7). |
<br><br> |
<b>Note:</b> in order to be able to directly execute the scripts, <a href="http://www.tcl.tk/software/tcltk/">TCL/TK</a> |
needs to be installed on your system. Optionally for Windows users, the |
scripts have been turned into single-file binary executable programs |
using <a href="http://freewrap.sourceforge.net/">freeWrap</a>. |
needs to be installed on your system. Optionally for Windows users, the scripts can be turned into single-file binary executable programs |
using <a href="http://freewrap.sourceforge.net/">freeWrap</a> by running/clicking the <i>"tools/freewrap642/generate_exec.bat"</i> file provided in the project repository. |
|
|
<a name="2. openmsp430-loader"></a> |
58,27 → 58,26
<br> |
These screenshots show the script in action under Linux and Windows: |
<br><br> |
<img src="getimg.php?1248897300" alt="openmsp430-loader Linux" title="openmsp430-loader Linux" width="75%"> |
<img src="usercontent,img,1306525377" alt="openmsp430-loader Linux" title="openmsp430-loader Linux" width="75%"/> |
<br><br> |
<img src="getimg.php?1249244501" alt="openmsp430-loader Windows" title="openmsp430-loader Windows" width="75%"> |
<img src="getimg.php?1249244501" alt="openmsp430-loader Windows" title="openmsp430-loader Windows" width="75%"/> |
<br> |
<a name="3. openmsp430-minidebug"></a> |
<h1>3. openmsp430-minidebug</h1> |
This small program provides a minimalistic graphical interface enabling simple interaction with the openMSP430: |
<br><br> |
<img src="usercontent,img,1297506385" alt="openmsp430-minidebug" title="openmsp430-minidebug" width="75%"> |
<img src="usercontent,img,1306665243" alt="openmsp430-minidebug" title="openmsp430-minidebug" width="75%"/> |
<br><br> |
As you can see from the screenshot, it allows the following actions: |
<ul> |
<li><b><font color="#ff0000">(1)</font></b> Connect to the openMSP430 Serial Debug Interface</li> |
<li><b><font color="#ff0000">(1)</font></b> Connect to the openMSP430 Serial Debug Interface.</li> |
<li><b><font color="#ff0000">(2)</font></b> Load the program memory with an ELF or Intel-HEX file</li> |
<li><b><font color="#ff0000">(3)</font></b> Control the CPU: Reset, Stop, Start and Single-Step</li> |
<li><b><font color="#ff0000">(4)</font></b> Read/Write individual status bits</li> |
<li><b><font color="#ff0000">(5)</font></b> Read/Write access of the CPU registers</li> |
<li><b><font color="#ff0000">(6)</font></b> Read/Write access of the whole memory range (program, data, peripherals)</li> |
<li><b><font color="#ff0000">(7)</font></b> Source a custom external TCL script</li> |
<li><b><font color="#ff0000">(8)</font></b> Basic disassembled view of the loaded program (current PC location is highlighted in yellow)</li> |
<li><b><font color="#ff0000">(9)</font></b> Choose the disassembled view type</li> |
<li><b><font color="#ff0000">(3)</font></b> Control the CPU: Reset, Stop, Start, Single-Step and Software breakpoints</li> |
<li><b><font color="#ff0000">(4)</font></b> Read/Write access of the CPU registers</li> |
<li><b><font color="#ff0000">(5)</font></b> Read/Write access of the whole memory range (program, data, peripherals)</li> |
<li><b><font color="#ff0000">(6)</font></b> Basic disassembled view of the loaded program (current PC location is highlighted in green, software breakpoints in yellow, pink and violet)</li> |
<li><b><font color="#ff0000">(7)</font></b> Choose the disassembled view type</li> |
<li><b><font color="#ff0000">(8)</font></b> Source a custom external TCL script</li> |
</ul> |
|
<a name="4. openmsp430-gdbproxy"></a> |
90,41 → 89,59
the serial debug interface from the openMSP430.<br> |
Schematically the communication flow looks as following: |
<br><br> |
<img src="getimg.php?1248897690" alt="GDB Proxy flow" title="GDB Proxy flow" width="40%"> |
<img src="getimg.php?1248897690" alt="GDB Proxy flow" title="GDB Proxy flow" width="40%"/> |
<br><br> |
Like the original '<b><i>msp430-gdbproxy</i></b>' program, '<b><i>openmsp430-gdbproxy</i></b>' can be controlled from the command line. However, it also provides a small graphical interface: |
<br><br> |
<img src="getimg.php?1248897753" alt="openmsp430-gdbproxy" title="openmsp430-gdbproxy" width="60%"> |
<img src="usercontent,img,1306525816" alt="gdbproxy" title="gdbproxy" width="60%"/> |
<br><br> |
These two additional screenshots show the script in action together with the Eclipse and DDD graphical frontends: |
<br><br> |
<img src="getimg.php?1248897844" alt="openmsp430-gdbproxy and Eclipse" title="openmsp430-gdbproxy and Eclipse" width="100%"> |
<img src="usercontent,img,1306525935" alt="gdbproxy-Eclipse" title="gdbproxy-Eclipse" width="100%"/> |
<br><br> |
<img src="getimg.php?1248897887" alt="openmsp430-gdbproxy and DDD" title="openmsp430-gdbproxy and DDD" width="100%"> |
<img src="usercontent,img,1306526049" alt="gdbproxy-DDD" title="gdbproxy-DDD" width="100%"/> |
<br><br> |
<b>Tip:</b> There are several tutorials on Internet explaining how to |
configure Eclipse for the MSP430. As an Eclipse newbie, I found the |
followings quite helpful: |
followings quite helpful (the <b><i>msp430-gdbproxy</b></i> sections should of course be ignored as we are using our own <b><i>openmsp430-gdbproxy</b></i> program :-) ): |
<ul> |
<li><a href="http://matthias-hartmann.blogspot.com/2009/02/use-eclipse-and-mspgcc-easy-way.html">Use Eclipse and mspgcc - The easy way</a> (English)</li> |
<li><a href="http://msp430.ms.funpic.de/doku.php?id=msp430:entwicklungumgebung">MSP430 - Entwicklungumgebung</a> (German)</li> |
<li><a href="http://www.43oh.com/2010/11/a-step-by-step-guide-msp430-programming-under-linux/">A Step By Step Guide To MSP430 Programming Under Linux</a> (English)</li> |
<li><a href="http://www.mikrocontroller.net/articles/MSP430_eclipse_helios_mspgcc4_gdb-proxy">MSP430 eclipse helios mspgcc4</a> (German)</li> |
</ul> |
|
<a name="5. MSPGCC Toolchain"></a> |
<h1>5. MSPGCC Toolchain</h1> |
<a name="5. MSPGCC(4) Toolchain"></a> |
<h1>5. MSPGCC(4) Toolchain</h1> |
|
<a name="5.1 Some notes regarding msp430-gdb"></a> |
<h2>5.1 Some notes regarding msp430-gdb</h2> |
<a name="5.1 Compiler options"></a> |
<h2>5.1 Compiler options</h2> |
|
As of today (July 2009), the GDB port for the MSP430 has some problems (<a href="http://www.nabble.com/Help-with-gdb-commands-td21942613.html">here</a>).<br> |
The stepping over function is not available and the backtrace and finish commands don't work properly.<br> |
There is fortunately a <a href="http://www.nabble.com/Useful-new-GDB-fixes-td19554922.html">patch</a> |
existing, and until it is included into GDB, I can only recommend to |
recompile GDB with it (I didn't try it for Windows but it is quite |
straight forward to do for Linux). <a name="5.2 CPU selection for msp430-gcc"></a> |
<h2>5.2 CPU selection for msp430-gcc</h2> |
The <b>msp430-gcc</b> compiler accepts the following MSP430 specific command line parameters (copied from the MSPGCC <a href="http://mspgcc.sourceforge.net/manual/c745.html">manual page</a>): |
<br><br> |
<table align="center" border="1"> |
<tbody> |
<tr><td>-mmcu= </td><td>Specify the MCU name </td></tr> |
<tr><td>-mno-volatile-workaround</td><td>Do not perform a volatile workaround for bitwise operations. </td></tr> |
<tr><td>-mno-stack-init </td><td>Do not initialize the stack as <i>main()</i>starts. </td></tr> |
<tr><td>-minit-stack= </td><td>Specify the initial stack address. </td></tr> |
<tr><td>-mendup-at= </td><td>Jump to the specified routine at the end of <i>main()</i>. </td></tr> |
<tr><td>-mforce-hwmul </td><td>Force use of a hardware multiplier. </td></tr> |
<tr><td>-mdisable-hwmul </td><td>Do not use the hardware multiplier. </td></tr> |
<tr><td>-minline-hwmul </td><td>Issue inline code for 32-bit integer operations for devices with a hardware multiplier. </td></tr> |
<tr><td>-mnoint-hwmul </td><td>Do not disable and enable interrupts around hardware multiplier operations. This makes |
multiplication faster when you are certain no hardware multiplier operations will occur |
at deeper interrupt levels. </td></tr> |
<tr><td>-mcall-shifts </td><td>Use subroutine calls for shift operations. This may save some space for shift intensive |
applications. </td></tr> |
</tbody> |
</table> |
<br> |
|
The following table aims to help selecting the proper <b>-mmcu</b> <a href="http://mspgcc.sourceforge.net/manual/c745.html">option</a> for the <b>msp430-gcc</b> call:<br><br> |
|
<a name="5.2 MCU selection"></a> |
<h2>5.2 MCU selection</h2> |
|
The following table aims to help selecting the proper MCU name for the <b>-mmcu</b> <a href="http://mspgcc.sourceforge.net/manual/c745.html">option</a> during the <b>msp430-gcc</b> call: |
<br><br> |
<table align="center" border="1"> |
<tbody><tr align="center"><td><b>-mmcu option</b></td><td><b> Program <br>Memory</b></td><td><b>Data<br> Memory </b></td><td style="vertical-align: top; text-align: center;"><span style="font-weight: bold;">Hardware<br> |
Multiplier </span><br> |
818,14 → 835,28
</tr> |
|
</tbody></table><br> |
<span style="text-decoration: underline;">Note 1:</span> the program memory size should imperatively match the openMSP430 configuration.<br> |
<span style="text-decoration: underline;">Note:</span> the program memory size should imperatively match the openMSP430 configuration.<br> |
|
<span style="text-decoration: underline;">Note 2:</span> the <span style="font-weight: bold;">-mforce-hwmul</span> parameter will force <b>msp430-gcc </b>to use the hardware multiplier.<br> |
|
<span style="text-decoration: underline;">Note 3:</span> the <span style="font-weight: bold;">-mdisable-hwmul</span> parameter will force <b>msp430-gcc </b>not to use the hardware multiplier.<br> |
<br> |
<a name="5.3 Custom linker script"></a> |
<h2>5.3 Custom linker script</h2> |
The use of the <b>-mmcu</b> switch is of course <b>NOT</b> mandatory. It is simply a convenient way to use the pre-existing linker scripts provided with the MSPGCC4 toolchain.<br> |
<br> |
However, if the peripheral address space is larger than the standard 512B of the original MSP430 (see the <a href="http://opencores.org/project,openmsp430,core#2.1.3.2 Advanced System Configuration)">Advanced System Configuration</a> section), a customized linker script <b>MUST</b> be provided.<br> |
<br> |
To create a custom linker script, the simplest way is to start from an existing one: |
<ul> |
<li>the MSPGCC(4) toolchain provides a wide range of examples for all supported MSP430 models (see "<b><i>msp430/lib/ldscripts/</i></b>" sub-directory, in the MSPGCC(4) installation directory).</li> |
<li>the openMSP430 project also provide a simple linker script example: <a href="http://opencores.org/websvn,filedetails?repname=openmsp430&path=/openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x">ldscript_example.x</a></li> |
</ul> |
<br> |
From there, the script can be modified to match <b>YOUR</b> openMSP430 configuration: |
<ul> |
<li>In the <b><i>text (rx)</i></b> section definition, update the <b><i>ORIGIN</i></b> and <b><i>LENGTH</b></i> fields to match the <b>PROGRAM MEMORY</b> configuration.</li> |
<li>In the <b><i>data (rwx)</i></b> section definition, update the <b><i>ORIGIN</i></b> field to match the <b>PERIPHERAL SPACE</b> configuration and the <b><i>LENGTH</b></i> field to match the <b>DATA MEMORY</b> configuration.</li> |
<li>At last, update the stack pointer initialization value (look for the "<b><i>PROVIDE (__stack =</i></b>" section) and make sure that it falls in the data memory space (the stack size should also matches your application requirements, i.e. not to small... and not to big :-P ).</li> |
</ul> |
<br><br> |
|
|
|
|
</body></html> |
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+++ doc/html/integration.html (revision 116)
@@ -23,7 +23,7 @@
This chapter aims to give a comprehensive description of all openMSP430 core interfaces in order to facilitates its integration within an ASIC or FPGA.
The following diagram shows an overview of the openMSP430 core connectivity:
-
+
The full pinout of the core is summarized in the following table.
@@ -31,6 +31,12 @@ Port Name Direction Width Description
Clocks
+
+ cpu_en
+ Input
+ 1
+ Enable CPU code execution (asynchronous)
+
dco_clk
Input
@@ -64,7 +70,7 @@
Resets
- puc
+ puc_rst
Output
1
Main system reset
@@ -73,7 +79,7 @@
reset_n
Input
1
- Reset Pin (low active)
+ Reset Pin (low active, asynchronous)
@@ -106,7 +112,7 @@
pmem_wen
Output
2
- Program Memory write enable (low active)
+ Program Memory write byte enable (low active)
Data Memory interface
@@ -138,7 +144,7 @@
dmem_wen
Output
2
- Data Memory write enable (low active)
+ Data Memory write byte enable (low active)
External Peripherals interface
@@ -145,7 +151,7 @@
per_addr
Output
- 8
+ 14
Peripheral address
@@ -167,10 +173,10 @@
Peripheral enable (high active)
- per_wen
+ per_we
Output
2
- Peripheral write enable (high active)
+ Peripheral write byte enable (high active)
Interrupts
@@ -195,6 +201,12 @@
Serial Debug interface
+ dbg_en
+ Input
+ 1
+ Debug interface enable (asynchronous)
+
+
dbg_freeze
Output
1
@@ -210,7 +222,7 @@
dbg_uart_rxd
Input
1
- Debug interface: UART RXD
+ Debug interface: UART RXD (asynchronous)
@@ -227,20 +239,25 @@
- PER_ADDR: peripheral register address of the 16 bit word which is going to be accessed.
+ PER_ADDR: peripheral register address of the 16 bit word which is currently accessed. It is to be noted that a 14 bit address will always be provided from the openMSP430 to the peripheral in order to accommodate the biggest possible PER_SIZE Verilog configuration option (i.e. 32kB as opposed to 512B by default).
Note: in order to calculate the core logical address from the peripheral register physical address, the formula goes as following: LOGICAL@=2*PHYSICAL@
@@ -361,7 +378,7 @@
- PER_WE: this signal selects which byte should be written during a valid access. PER_WEN[0] will activate a write on the lower byte, PER_WEN[1] a write on the upper byte. Note that these signals are HIGH ACTIVE.
+ PER_WE: this signal selects which byte should be written during a valid access. PER_WE[0] will activate a write on the lower byte, PER_WE[1] a write on the upper byte. Note that these signals are HIGH ACTIVE.
@@ -500,6 +517,10 @@
The following diagram shows an overview of the openMSP430 core connectivity:
-
The full pinout of the core is summarized in the following table.
@@ -31,6 +31,12 @@
@@ -227,20 +239,25 @@
-
-
- DCO_CLK: this input port is typically connected to a PLL, RC oscillator or any clock resource the target FPGA might provide.
+ -
+ CPU_EN: this input port provide a hardware mean to stop or resume CPU execution. When unused, this port should be set to 1.
+
+
+ -
+ DCO_CLK: this input port is typically connected to a PLL, RC oscillator or any clock resource the target FPGA might provide.
From a synthesis tool perspective (ISE, Quartus, Libero, Design Compiler...), this the only port where a clock needs to be declared.
-
- LFXT_CLK: if ACLK_EN or SMCLK_EN are going to be used in the project (for example through the Watchdog or TimerA peripherals), then this port needs to be connected to a clock running at least two time slower as DCO_CLK (typically 32kHz). It can be connected to 0 or 1 otherwise.
+ LFXT_CLK: if ACLK_EN or SMCLK_EN are going to be used in the project (for example through the Watchdog or TimerA peripherals), then this port needs to be connected to a clock running at least two time slower as DCO_CLK (typically 32kHz). It can be connected to 0 or 1 otherwise.
-
- MCLK: the main system clock drives the complete openMSP430 clock domain, including program/data memories and the peripheral interfaces.
+ MCLK: the main system clock drives the complete openMSP430 clock domain, including program/data memories and the peripheral interfaces.
-
- ACLK_EN / SMCLK_EN: these two clock enable signals can be used in order to emulate the original ACLK and SMCLK from the MSP430 specification.
+ ACLK_EN / SMCLK_EN: these two clock enable signals can be used in order to emulate the original ACLK and SMCLK from the MSP430 specification.
An example of this can be found in the Watchdog and TimerA modules, where it is implemented as following:
@@ -260,7 +277,7 @@
-
- PUC: the Power-Up-Clear signal is asynchronously set with the reset pin (RESET_N), the watchdog reset or the serial debug interface reset. In order to get clean timings, it is synchronously cleared with MCLK's falling edge. As a general rule, this signal should be used as the reset of the MCLK clock domain.
+ PUC_RST: the Power-Up-Clear signal is asynchronously set with the reset pin (RESET_N), the watchdog reset or the serial debug interface reset. In order to get clean timings, it is synchronously cleared with MCLK's falling edge. As a general rule, this signal should be used as the reset of the MCLK clock domain.
+ PER_ADDR: peripheral register address of the 16 bit word which is currently accessed. It is to be noted that a 14 bit address will always be provided from the openMSP430 to the peripheral in order to accommodate the biggest possible PER_SIZE Verilog configuration option (i.e. 32kB as opposed to 512B by default).
Note: in order to calculate the core logical address from the peripheral register physical address, the formula goes as following: LOGICAL@=2*PHYSICAL@
-
+ DBG_EN: this signal allows the user to enable or disable the serial debug interface without interfering with the CPU execution. It is to be noted that when disabled (i.e. DBG_EN=0), the debug interface is held into reset.
+
+
+ -
DBG_FREEZE: this signal will be set whenever the debug interface stops the CPU (and if the FRZ_BRK_EN field of the CPU_CTL debug register is set). As its name implies, the purpose of DBG_FREEZE is to freeze a peripheral whenever the CPU is stopped by the software debugger.
For example, it is used by the Watchdog timer in order to stop its free-running counter. This prevents the CPU from being reseted by the watchdog every times the user stops the CPU during a debugging session.
/doc/html/serial_debug_interface.html
92,12 → 92,17
<tr align="center"> |
<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_LO</a></font></td> |
<td><font size="-1">0x00</font></td> |
<td colspan="16"><font size="-5">DMEM_AWIDTH</font></td> |
<td colspan="7"><font size="-5">PER_SPACE</font></td> |
<td colspan="5"><font size="-5">USER_VERSION</font></td> |
<td colspan="1"><font size="-5">ASIC</font></td> |
<td colspan="3"><font size="-5">CPU_VERSION</font></td> |
</tr> |
<tr align="center"> |
<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_HI</a></font></td> |
<td><font size="-1">0x01</font></td> |
<td colspan="16"><font size="-5">PMEM_AWIDTH</font></td> |
<td colspan="6"><font size="-5">PMEM_SIZE</font></td> |
<td colspan="9"><font size="-5">DMEM_SIZE</font></td> |
<td colspan="1"><font size="-5">MPY</font></td> |
</tr> |
<tr align="center"> |
<td><font size="-1"><a href="#2.2.2 CPU_CTL">CPU_CTL</a></font></td> |
297,24 → 302,49
<tr align="center"> |
<td><font size="-1">CPU_ID_LO</font></td> |
<td><font size="-1">0x00</font></td> |
<td colspan="16"><font size="-5">DMEM_AWIDTH</font></td> |
<td colspan="7"><font size="-5">PER_SPACE</font></td> |
<td colspan="5"><font size="-5">USER_VERSION</font></td> |
<td colspan="1"><font size="-5">ASIC</font></td> |
<td colspan="3"><font size="-5">CPU_VERSION</font></td> |
</tr> |
<tr align="center"> |
<td><font size="-1">CPU_ID_HI</font></td> |
<td><font size="-1">0x01</font></td> |
<td colspan="16"><font size="-5">PMEM_AWIDTH</font></td> |
<td colspan="6"><font size="-5">PMEM_SIZE</font></td> |
<td colspan="9"><font size="-5">DMEM_SIZE</font></td> |
<td colspan="1"><font size="-5">MPY</font></td> |
</tr> |
</table> |
<br /> |
<table border="0"> |
<tr> |
<td> </td><td valign="top"><li><b>PMEM_AWIDTH</b></li></td> |
<td>: Program memory size in byte for the current implementation</td> |
<td> </td><td valign="top"><li><b>CPU_VERSION</b></li></td> |
<td>: Current CPU version (currently 1)</td> |
</tr> |
<tr> |
<td> </td><td valign="top"><li><b>DMEM_AWIDTH</b></li></td> |
<td>: Data memory size in byte for the current implementation.</td> |
<td> </td><td valign="top"><li><b>ASIC</b></li></td> |
<td>: Defines if the ASIC specific features are enabled in the current openMSP430 implementation.</td> |
</tr> |
<tr> |
<td> </td><td valign="top"><li><b>USER_VERSION</b></li></td> |
<td>: Reflects the value defined in the <b>openMSP430_defines.v</b> file.</td> |
</tr> |
<tr> |
<td> </td><td valign="top"><li><b>PER_SPACE</b></li></td> |
<td>: Peripheral address space for the current implementation (byte size = PER_SPACE*512)</td> |
</tr> |
<tr> |
<td> </td><td valign="top"><li><b>MPY</b></li></td> |
<td>: This bit is set if the hardware multiplier is included in the current implementation</td> |
</tr> |
<tr> |
<td> </td><td valign="top"><li><b>DMEM_SIZE</b></li></td> |
<td>: Data memory size for the current implementation (byte size = DMEM_SIZE*128)</td> |
</tr> |
<tr> |
<td> </td><td valign="top"><li><b>PMEM_SIZE</b></li></td> |
<td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td> |
</tr> |
</table> |
|
<a name="2.2.2 CPU_CTL"></a> |
692,7 → 722,7
<tr> |
<td> </td><td> </td> |
<td> 1 - Address match on BRK_ADDR0→BRK_ADDR1 range (range mode) |
<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td> |
<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td> |
</td> |
</tr> |
<tr> |
764,7 → 794,7
<tr> |
<td> </td><td valign="top"><li><b>RANGE_RD</b></li></td> |
<td>: This bit is set whenever the CPU performs a read access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[0]=1). |
<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td> |
<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td> |
</tr> |
<tr> |
<td> </td><td valign="top"><li><b>ADDR1_WR</b></li></td> |
/doc/html/overview.html
4,13 → 4,13
<title>openMSP430 Overview</title> |
</head> |
<body> |
|
<br /> |
<h1>Introduction</h1> |
|
The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by an MSP430 toolchain in a cycle accurate way. |
The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430 microcontroller family</a></b> and can execute the code generated by an MSP430 toolchain in a cycle accurate way. |
<br /><br /> |
The core comes with some peripherals (16x16 Hardware Multiplier, GPIO, TimerA, generic templates) and a Serial Debug Interface for in-system software development. |
|
The core comes with some peripherals (<b>16x16 Hardware Multiplier</b>, GPIO, TimerA, generic templates) and most notably with a <b>Serial Debug Interface</b> supporting <b>the MSPGCC(4) GNU Debugger</b> (GDB) for in-system software debugging. |
<br /><br /> |
<h1>Download</h1> |
<h3>Design</h3> |
The complete tar archive of the project can be downloaded <a href="http://www.opencores.org/download,openmsp430">here</a> (OpenCores account required).<br /> |
27,22 → 27,28
</td> |
</tr> |
</table> |
<br /> |
<h3>ChangeLog</h3> |
<ul> |
<li>The <a href="http://opencores.org/websvn,filedetails?repname=openmsp430&path=/openmsp430/trunk/ChangeLog_core.txt">Core's ChangeLog</a> lists the CPU updates.</li> |
<li>The <a href="http://opencores.org/websvn,filedetails?repname=openmsp430&path=/openmsp430/trunk/ChangeLog_tools.txt">Tools' ChangeLog</a> lists the Software development tools updates.</li> |
<li>Subscribe to the following <a href="http://opencores.org/websvn,rss?repname=openmsp430&path=/openmsp430/&isdir=1">RSS</a> feed to keep yourself informed about ALL updates.</i> |
</ul> |
<br /> |
<h3>Documentation</h3> |
The online documentation is available as <a href="usercontent,doc,1307395772" title="openMSP430 PDF Doc. R1.9">pdf</a>. |
<br /><br /> |
To keep yourself informed about project updates, you can subscribe to the following <a href="http://opencores.org/websvn,rss?repname=openmsp430&path=/openmsp430/&isdir=1">RSS</a> feed. |
<br /><br /> |
<h3>Documentation</h3> |
The online documentation is available as <a href="usercontent,doc,1299010945" title="openMSP430 PDF Doc. R1.8">pdf</a>. |
<h1>Features & Limitations</h1> |
<h2>Features</h2> |
<ul> |
<li><b>Core:</b> |
<ul> |
<li>Full instruction set support.</li> |
<li>All addressing modes are supported.</li> |
<li>IRQ and NMI support.</li> |
<li>Power saving modes functionality is supported.</li> |
<li>Full instruction set.</li> |
<li>Interrupts: IRQs (x14), NMI (x1).</li> |
<li>Power saving modes functionality.</li> |
<li>Configurable memory size for both program and data.</li> |
<li>Serial Debug Interface (Nexus class 3).</li> |
<li>Scalable peripheral address space.</li> |
<li>Serial Debug Interface (Nexus class 3, w/o trace) with GDB support.</li> |
<li>FPGA friendly (single clock domain, no clock gate).</li> |
<li>Small size (Xilinx: 1650 LUTs / Altera: 1550 LEs / ASIC: 8k gates).</li> |
</ul> |
73,7 → 79,7
</ul> |
</li> |
</ul> |
|
<br /><br /> |
<h1>Links</h1> |
Development has been performed using the following freely available (excellent) tools: |
<ul> |
111,7 → 117,7
<li><a href="http://www.ti.com/litv/pdf/slau049f">TI: MSP430x1xx Family User's Guide</a></li> |
<li><a href="http://processors.wiki.ti.com/index.php/Open_Source_Projects_-_MSP430">TI: a list of available MSP430 Open Source projects out there on the web today.</a></li> |
</ul> |
|
<br /><br /> |
<h1>Legal information</h1> |
MSP430 is a trademark of Texas Instruments, Inc. This project is not affiliated in any way with Texas Instruments. All other product names are trademarks or registered trademarks of their respective owners. |
|
/doc/html/area_speed.html
35,7 → 35,7
applied timing constraints and exact configuration of the openMSP430 core. |
The FPGA results were obtained using the free tool versions provided by |
the vendors (i.e ISE 11.1, QuartusII 9.1 & Libero 8.5). The ASIC synthesis was |
run with Synopsys Design Compiler 2007.12 (without dc_ultra or any special feature).</span> |
run with Synopsys Design Compiler 2007.12 (<b>without dc_ultra or any special feature</b>).</span> |
<h1>1. Overview</h1> |
|
<a name="1.1 FPGAs"></a> |
/doc/html/core.html
14,9 → 14,15
<li><a href="#2.1.1 Design structure"> 2.1.1 Design structure</a></li> |
<li><a href="#2.1.2 Limitations"> 2.1.2 Limitations</a></li> |
<li><a href="#2.1.3 Configuration"> 2.1.3 Configuration</a></li> |
<li><a href="#2.1.4 Pinout"> 2.1.4 Pinout</a></li> |
<li><a href="#2.1.5 Instruction Cycles and Lengths">2.1.5 Instruction Cycles and Lengths</a></li> |
<li><a href="#2.1.6 Serial Debug Interface"> 2.1.6 Serial Debug Interface</a></li> |
<ul> |
<li><a href="#2.1.3.1 Basic System Configuration"> 2.1.3.1 Basic System Configuration</a></li> |
<li><a href="#2.1.3.2 Advanced System Configuration"> 2.1.3.2 Advanced System Configuration</a></li> |
<li><a href="#2.1.3.3 Expert System Configuration"> 2.1.3.3 Expert System Configuration</a></li> |
</ul> |
<li><a href="#2.1.4 Memory mapping"> 2.1.4 Memory mapping</a></li> |
<li><a href="#2.1.5 Pinout"> 2.1.5 Pinout</a></li> |
<li><a href="#2.1.6 Instruction Cycles and Lengths">2.1.6 Instruction Cycles and Lengths</a></li> |
<li><a href="#2.1.7 Serial Debug Interface"> 2.1.7 Serial Debug Interface</a></li> |
</ul> |
</li> |
<li><a href="#2.2 Peripherals"> 2.2 Peripherals</a> |
35,11 → 41,11
<a name="1. Introduction"></a> |
<h1>1. Introduction</h1> |
|
The openMSP430 is a 16-bit microcontroller core compatible with TI's MSP430 family (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data. |
The openMSP430 is a 16-bit microcontroller core compatible with <b><a href="http://www.ti.com/litv/pdf/slau049f">TI's MSP430 family</a></b> (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data. |
<br /><br /> |
This design has been implemented to be FPGA friendly. Therefore, the core doesn't contain any clock gate and has only a single clock domain. As a consequence, the clock management block has a few limitations. |
<br /><br /> |
This IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration). |
It is to be noted that this IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration). |
However the core is fully configurable in regard to the supported RAM and/or ROM sizes. |
<br /><br /> |
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration. |
66,6 → 72,7
<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li> |
<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li> |
<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li> |
<li><b>16x16 Multiplier</b>: The hardware multiplier peripheral is transparently supported by the GCC compiler and is also located in the core. It can be included or excluded at will through a Verilog define.</li> |
</ul> |
|
<a name="2.1.2 Limitations"></a> |
82,8 → 89,13
<a name="2.1.3 Configuration"></a> |
<h3>2.1.3 Configuration</h3> |
|
It is possible to configure the openMSP430 core through the "openMSP430_defines.v" file located in the "rtl" directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br /> |
Two sets of parameters can be adjusted by the user in order to define the program and data memory sizes: |
It is possible to configure the openMSP430 core through the <b><i>openMSP430_defines.v</i></b> file located in the <b><i>rtl</i></b> directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br /> |
Three sets of parameters can be adjusted by the user in order to fully customize the core. |
|
<a name="2.1.3.1 Basic System Configuration"></a> |
<h4>2.1.3.1 Basic System Configuration</h4> |
|
The basic system can be adjusted with the following set of defines in order to match the target system requirements. |
<br /><br /> |
<table border="0" cellspacing="4" cellpadding="0"> |
<tr> |
92,7 → 104,17
<td width="15"></td> |
<td> |
<code> |
// Program Memory Size: |
//============================================================================ |
<br />//============================================================================ |
<br />// BASIC SYSTEM CONFIGURATION |
<br />//============================================================================ |
<br />//============================================================================ |
<br />// |
<br />// Note: the sum of program, data and peripheral memory spaces must not |
<br />// exceed 64 kB |
<br />// |
<br /> |
<br />// Program Memory Size: |
<br />// Uncomment the required memory size |
<br />//------------------------------------------------------- |
<br />//`define PMEM_SIZE_59_KB |
126,15 → 148,28
<br />//`define DMEM_SIZE_512_B |
<br />//`define DMEM_SIZE_256_B |
<br />`define DMEM_SIZE_128_B |
<br /> |
<br />// Include/Exclude Hardware Multiplier |
<br />`define MULTIPLIER |
<br /> |
<br />// Include/Exclude Serial Debug interface |
<br />`define DBG_EN |
</code> |
</td> |
</tr> |
</table> |
<br /><br /> |
<b>Note:</b> The sum of both program and data memories <b>SHOULD NOT</b> exceed 63.5 kB. |
<br /><br /><br /> |
The following parameters define if the debug interface should be included or not and how many hardware breakpoint units should be included. |
The only design considerations at this stage are: |
<ul> |
<li>Make sure that the program and data memories have the correct size :-P</li> |
<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li> |
</ul> |
<br /> |
|
<a name="2.1.3.2 Advanced System Configuration"></a> |
<h4>2.1.3.2 Advanced System Configuration</h4> |
|
In this section, some additional features are available in order to match the needs of more experienced users. |
<br /><br /> |
<table border="0" cellspacing="4" cellpadding="0"> |
<tr> |
143,38 → 178,69
<td width="15"></td> |
<td> |
<code> |
//---------------------------------------------------------------------------- |
<br />// REMOTE DEBUGGING INTERFACE CONFIGURATION |
<br />//---------------------------------------------------------------------------- |
//============================================================================ |
<br />//============================================================================ |
<br />// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS) |
<br />//============================================================================ |
<br />//============================================================================ |
<br /> |
<br />// Include Debug interface |
<br />`define DBG_EN |
<br />//------------------------------------------------------- |
<br />// Peripheral Memory Space: |
<br />//------------------------------------------------------- |
<br />// The original MSP430 architecture map the peripherals |
<br />// from 0x0000 to 0x01FF (i.e. 512B of the memory space). |
<br />// The following defines allow you to expand this space |
<br />// up to 32 kB (i.e. from 0x0000 to 0x7fff). |
<br />// As a consequence, the data memory mapping will be |
<br />// shifted up and a custom linker script will therefore |
<br />// be required by the GCC compiler. |
<br />//------------------------------------------------------- |
<br />//`define PER_SIZE_32_KB |
<br />//`define PER_SIZE_16_KB |
<br />//`define PER_SIZE_8_KB |
<br />//`define PER_SIZE_4_KB |
<br />//`define PER_SIZE_2_KB |
<br />//`define PER_SIZE_1_KB |
<br />`define PER_SIZE_512_B |
<br /> |
<br />// Debug interface selection |
<br />// `define DBG_UART -> Enable UART (8N1) debug interface |
<br />// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED |
<br />// |
<br />`define DBG_UART |
<br />//`define DBG_JTAG |
<br /> |
<br />// Number of hardware breakpoints (each unit contains 2 hw address breakpoints) |
<br />// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0 |
<br />// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1 |
<br />// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2 |
<br />// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3 |
<br />// |
<br />`define DBG_HWBRK_0 |
<br />`define DBG_HWBRK_1 |
<br />`define DBG_HWBRK_2 |
<br />`define DBG_HWBRK_3 |
<br />//------------------------------------------------------- |
<br />// Defines the debugger CPU_CTL.RST_BRK_EN reset value |
<br />// (CPU break on PUC reset) |
<br />//------------------------------------------------------- |
<br />// When defined, the CPU will automatically break after |
<br />// a PUC occurrence by default. This is typically usefull |
<br />// when the program memory can only be initialized through |
<br />// the serial debug interface. |
<br />//------------------------------------------------------- |
<br />//`define DBG_RST_BRK_EN |
<br /> |
<br /> |
<br />//------------------------------------------------------- |
<br />// Custom user version number |
<br />//------------------------------------------------------- |
<br />// This 5 bit field can be freely used in order to allow |
<br />// custom identification of the system through the debug |
<br />// interface. |
<br />// (see CPU_ID.USER_VERSION field in the documentation) |
<br />//------------------------------------------------------- |
<br />`define USER_VERSION 5'b00000 |
<br /> |
</code> |
</td> |
</tr> |
</table> |
<br /><br /> |
<b>Note:</b> Since the hardware breakpoint units are relatively big, it is recommended to include as many as you plan to use. These units are particularly useful if your instruction memory is a ROM (i.e. when you can't use software breakpoints) or if you want to be able to stop the CPU whenever some particular data addresses are accessed. |
<br /><br /><br /> |
At last, this parameter controls if the hardware multiplier is included or not. |
Design consideration at this stage are: |
<ul> |
<li>Setting a peripheral memory space to something else than 512B will shift the data memory mapping up, which in turn will require the use of a custom linker script. If you don't know what a linker script is and if you don't want to know what it is, you should probably not modify this section.</li> |
<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li> |
</ul> |
<br /> |
<a name="2.1.3.3 Expert System Configuration"></a> |
<h4>2.1.3.3 Expert System Configuration</h4> |
|
In this section, you will find configuration options which will be relevant for roughly 0.01% of the users (according to an highly reliable market analysis ;-) ). |
<br /><br /> |
<table border="0" cellspacing="4" cellpadding="0"> |
<tr> |
183,18 → 249,95
<td width="15"></td> |
<td> |
<code> |
// Include/Exclude Hardware Multiplier |
<br />`define MULTIPLIER |
//============================================================================ |
<br />//============================================================================ |
<br />// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! ) |
<br />//============================================================================ |
<br />//============================================================================ |
<br />// |
<br />// IMPORTANT NOTE: Please update following configuration options ONLY if |
<br />// you have a good reason to do so... and if you know what |
<br />// you are doing :-P |
<br />// |
<br />//============================================================================ |
<br /> |
<br />//------------------------------------------------------- |
<br />// Number of hardware breakpoint units (each unit contains |
<br />// two hardware address breakpoints): |
<br />// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0 |
<br />// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1 |
<br />// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2 |
<br />// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3 |
<br />//------------------------------------------------------- |
<br />// Please keep in mind that hardware breakpoints only |
<br />// make sense whenever the program memory is not an SRAM |
<br />// (i.e. Flash/OTP/ROM/...) or when you are interested |
<br />// in data breakpoints (btw. not supported by GDB). |
<br />//------------------------------------------------------- |
<br />//`define DBG_HWBRK_0 |
<br />//`define DBG_HWBRK_1 |
<br />//`define DBG_HWBRK_2 |
<br />//`define DBG_HWBRK_3 |
<br /> |
<br />//------------------------------------------------------- |
<br />// Enable/Disable the hardware breakpoint RANGE mode |
<br />//------------------------------------------------------- |
<br />// When enabled this feature allows the hardware breakpoint |
<br />// units to stop the cpu whenever an instruction or data |
<br />// access lays within an address range. |
<br />// Note that this feature is not supported by GDB. |
<br />//------------------------------------------------------- |
<br />//`define DBG_HWBRK_RANGE |
<br /> |
<br />//------------------------------------------------------- |
<br />// Input synchronizers |
<br />//------------------------------------------------------- |
<br />// In some cases, the asynchronous input ports might |
<br />// already be synchronized externally. |
<br />// If an extensive CDC design review showed that this |
<br />// is really the case, the individual synchronizers |
<br />// can be disabled with the following defines. |
<br />// |
<br />// Notes: |
<br />// - the dbg_en signal will reset the debug interface |
<br />// when 0. Therefore make sure it is glitch free. |
<br />// |
<br />// - the dbg_uart_rxd synchronizer must be set to 1 |
<br />// when its reset is active. |
<br />//------------------------------------------------------- |
<br />`define SYNC_CPU_EN |
<br />`define SYNC_DBG_EN |
<br />`define SYNC_DBG_UART_RXD |
<br />`define SYNC_NMI |
<br /> |
</code> |
</td> |
</tr> |
</table> |
<br /><br /><br /> |
All remaining defines located in this file are system constants and should not be edited. |
<br /><br /> |
Design consideration at this stage are: |
<ul> |
<li>This is the expert section... so you know what your are doing anyway right ;-)</li> |
</ul> |
<br /> |
All remaining defines located in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited. |
<br /><br /> |
|
<a name="2.1.4 Pinout"></a> |
<h3>2.1.4 Pinout</h3> |
<a name="2.1.4 Memory mapping"></a> |
<h3>2.1.4 Memory mapping</h3> |
|
As discussed in the earlier section, the openMSP430 memory mapping is fully configurable.<br /> |
The basic system configuration section allows to adjust program and data memory sizes while keeping 100% compatibility with the pre-existing linker scripts provided by MSPGCC4 (or any other toolchain for that matter).<br /> |
However, an increasing number of users saw the 512B space available for peripherals in the standard MSP430 architecture as a limitation. Therefore, the advanced system configuration section give the possibility to up-scale the reserved peripheral address space anywhere between 512B and 32kB. As a consequence, the data memory space will be shifted up, which means that the linker script of your favorite toolchain will have to be modified accordingly.<br /> |
The following schematic should hopefully summarize this:<br /> |
<br /><br /> |
<img src="usercontent,img,1306066277" width="100%" alt="Memory mapping" title="Memory mapping" /> |
<br /> |
|
<br /><br /> |
<a name="2.1.5 Pinout"></a> |
<h3>2.1.5 Pinout</h3> |
|
The full pinout of the openMSP430 core is provided in the following table: |
<br /><br /> |
<table border="1"> |
202,6 → 345,12
|
<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr> |
<tr> |
<td> cpu_en </td> |
<td> Input </td> |
<td> 1 </td> |
<td> Enable CPU code execution (asynchronous) - set to 1 if unused </td> |
</tr> |
<tr> |
<td> dco_clk </td> |
<td> Input </td> |
<td> 1 </td> |
234,7 → 383,7
|
<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr> |
<tr> |
<td> puc </td> |
<td> puc_rst </td> |
<td> Output </td> |
<td> 1 </td> |
<td> Main system reset </td> |
243,7 → 392,7
<td> reset_n </td> |
<td> Input </td> |
<td> 1 </td> |
<td> Reset Pin (low active) </td> |
<td> Reset Pin (active low, asynchronous) </td> |
</tr> |
|
|
251,7 → 400,7
<tr> |
<td> pmem_addr </td> |
<td> Output </td> |
<td> `PMEM_AWIDTH<sup>1</sup> </td> |
<td> `PMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b> </td> |
<td> Program Memory address </td> |
</tr> |
<tr> |
264,7 → 413,7
<td> pmem_din </td> |
<td> Output </td> |
<td> 16 </td> |
<td> Program Memory data input (optional<sup>2</sup>) </td> |
<td> Program Memory data input (optional <b><sup><font color="#FF0000">2</font></sup></b>)</td> |
</tr> |
<tr> |
<td> pmem_dout </td> |
276,7 → 425,7
<td> pmem_wen </td> |
<td> Output </td> |
<td> 2 </td> |
<td> Program Memory write enable (low active) (optional<sup>2</sup>) </td> |
<td> Program Memory write byte enable (low active) (optional <b><sup><font color="#FF0000">2</font></sup></b>) </td> |
</tr> |
|
<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr> |
283,7 → 432,7
<tr> |
<td> dmem_addr </td> |
<td> Output </td> |
<td> `DMEM_AWIDTH<sup>1</sup> </td> |
<td> `DMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b></td> |
<td> Data Memory address </td> |
</tr> |
<tr> |
308,7 → 457,7
<td> dmem_wen </td> |
<td> Output </td> |
<td> 2 </td> |
<td> Data Memory write enable (low active) </td> |
<td> Data Memory write byte enable (low active) </td> |
</tr> |
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr> |
315,7 → 464,7
<tr> |
<td> per_addr </td> |
<td> Output </td> |
<td> 8 </td> |
<td> 14 </td> |
<td> Peripheral address </td> |
</tr> |
<tr> |
337,7 → 486,7
<td> Peripheral enable (high active) </td> |
</tr> |
<tr> |
<td> per_wen </td> |
<td> per_we </td> |
<td> Output </td> |
<td> 2 </td> |
<td> Peripheral write enable (high active) </td> |
365,6 → 514,12
|
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr> |
<tr> |
<td> dbg_en </td> |
<td> Input </td> |
<td> 1 </td> |
<td> Debug interface enable (asynchronous) <b><sup><font color="#FF0000">3</font></sup></b> </td> |
</tr> |
<tr> |
<td> dbg_freeze </td> |
<td> Output </td> |
<td> 1 </td> |
380,19 → 535,21
<td> dbg_uart_rxd </td> |
<td> Input </td> |
<td> 1 </td> |
<td> Debug interface: UART RXD </td> |
<td> Debug interface: UART RXD (asynchronous) </td> |
</tr> |
</table> |
<br /> |
<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br /> |
<sup>2</sup>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints. |
<br /><br /> |
<b><sup><font color="#FF0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br /> |
<b><sup><font color="#FF0000">2</font></sup></b>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.<br /> |
<b><sup><font color="#FF0000">3</font></sup></b>: When disabled, the debug interface is hold into reset. As a consequence, the <b><i>dbg_en</i></b> port can be used to reset the debug interface without disrupting the CPU execution.<br /> |
<br /> |
|
<a name="2.1.5 Instruction Cycles and Lengths"></a> |
<h3>2.1.5 Instruction Cycles and Lengths</h3> |
<a name="2.1.6 Instruction Cycles and Lengths"></a> |
<h3>2.1.6 Instruction Cycles and Lengths</h3> |
|
The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself. |
<br />In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>). |
Please note that a detailed description of the instruction and addressing modes can be found in the <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a></b> (Chapter 3).<br /><br /> |
The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.<br /> |
In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>). |
Differences with the original MSP430 are highlighted in green (the original value being red). |
<ul> |
<li><b>Interrupt and Reset Cycles</b></li> |
470,8 → 627,8
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr> |
</table> |
|
<a name="2.1.6 Serial Debug Interface"></a> |
<h3>2.1.6 Serial Debug Interface</h3> |
<a name="2.1.7 Serial Debug Interface"></a> |
<h3>2.1.7 Serial Debug Interface</h3> |
|
All the details about the Serial Debug Interface are located <a href="http://www.opencores.org/project/openmsp430/serial%20debug%20interface">here</a>. |
<a name="2.2 Peripherals"></a> |
506,8 → 663,8
<code> |
reg [7:0] test_cnt; |
<br /> |
<br />always @ (posedge mclk or posedge puc) |
<br /> if (puc) test_cnt <= 8'h00; |
<br />always @ (posedge mclk or posedge puc_rst) |
<br /> if (puc_rst) test_cnt <= 8'h00; |
<br /> else if (smclk_en) test_cnt <= test_cnt + 8'h01; |
</code> |
</td> |
590,7 → 747,7
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr> |
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr> |
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr> |
<tr> <td> puc </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr> |
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr> |
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr> |
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr> |
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr> |
647,7 → 804,7
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr> |
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr> |
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr> |
<tr> <td> puc </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr> |
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr> |
<tr> <td> dbg_freeze </td> <td> Input </td> <td> 1 </td> <td> Freeze Timer A counter </td> </tr> |
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr> |
<tr> <td> irq_ta0 </td> <td> Output </td> <td> 1 </td> <td> Timer A interrupt: TACCR0 </td> </tr> |
/doc/html/files_directory_description.html
26,20 → 26,24
|
<table border="1"> |
<tbody><tr><td colspan="5"><b>core</b></td> <td><i><b>openMSP430 Core top level directory</b></i></td></tr> |
<tr><td rowspan="80" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr> |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br> |
<tr><td rowspan="87" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr> |
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br> |
</td></tr> |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">tb_openMSP430.v</td> <td><i>Testbench top level module</i></td></tr> |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">tb_openMSP430.v</td> <td><i>Testbench top level module</i></td></tr> |
<tr><td colspan="2">ram.v</td> <td><i>RAM verilog model</i></td></tr> |
<tr><td colspan="2">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr> |
<tr><td colspan="2">dbg_uart_tasks.v</td> <td><i>UART tasks for the serial debug interface</i></td></tr> |
<tr><td colspan="2">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr> |
<tr> |
<td colspan="2" rowspan="1" style="vertical-align: top;">msp_debug.v</td> |
<td style="vertical-align: top;"><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td> |
</tr> |
<tr><td colspan="2">timescale.v</td> <td><i>Global time scale definition for simulation.</i></td></tr> |
<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr> |
<tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td> <td><i>MSP430x1xx Family User's Guide</i></td></tr> |
<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr> |
<tr><td rowspan="22" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i><br> |
<tr><td rowspan="24" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i><br> |
</td></tr> |
<tr><td rowspan="21" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration)</i></td></tr> |
<tr><td rowspan="23" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration, ...)</i></td></tr> |
<tr><td colspan="2">openMSP430_undefines.v</td> <td><i>openMSP430 Verilog `undef file</i></td></tr> |
<tr><td colspan="2">openMSP430.v</td> <td><i>openMSP430 top level</i></td></tr> |
<tr><td colspan="2">omsp_frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr> |
54,28 → 58,61
<tr><td colspan="2">omsp_dbg.v</td> <td><i>Serial Debug Interface main block</i></td></tr> |
<tr><td colspan="2">omsp_dbg_hwbrk.v</td> <td><i>Serial Debug Interface hardware breakpoint unit</i></td></tr> |
<tr><td colspan="2">omsp_dbg_uart.v</td> <td><i>Serial Debug Interface UART communication block</i></td></tr> |
<tr><td colspan="2">timescale.v</td> <td><i>Global time scale definition for simulation.</i></td></tr> |
<tr><td colspan="2">omsp_sync_cell.v<br> |
</td> <td><i>Simple synchronization module (double flip-flop).</i></td></tr> |
<tr><td colspan="2"><b>periph</b></td> <td><i><b>Peripherals directory</b></i></td></tr> |
<tr><td rowspan="4"><font color="white">abcd</font></td> <td>omsp_gpio.v</td> <td><i>Digital I/O (Port 1 to 6)</i></td></tr> |
<tr><td colspan="1">omsp_timerA.v</td> <td><i>Timer A</i></td></tr> |
<tr><td rowspan="6"><font color="white">abcd</font></td> <td>omsp_gpio.v</td> <td><i>Digital I/O (Port 1 to 6)</i></td></tr> |
<tr> |
<td style="vertical-align: top;">omsp_timerA_defines.v<br> |
</td> |
<td style="vertical-align: top;"><i>Timer A configuration file</i></td> |
</tr> |
<tr> |
<td style="vertical-align: top;">omsp_timerA_undefines.v<br> |
</td> |
<td style="vertical-align: top;"><i>Timer A Verilog `undef file</i></td> |
</tr> |
<tr><td colspan="1">omsp_timerA.v</td> <td><i>Timer A</i></td></tr> |
<tr><td colspan="1">template_periph_16b.v</td> <td><i>Verilog template for 16 bit peripherals</i></td></tr> |
<tr><td colspan="1">template_periph_8b.v</td> <td><i>Verilog template for 8 bit peripherals</i></td></tr> |
<tr><td colspan="4"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr> |
<tr><td rowspan="36" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr> |
<tr><td rowspan="35" valign="bottom"><font color="white">abcd</font></td> <td colspan="2"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr> |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">msp430sim</td> <td><i>Main simulation script</i></td></tr> |
<tr><td colspan="1">asm2ihex.sh</td> <td><i>Assembly file compilation (Intel HEX file generation)</i></td></tr> |
<tr><td rowspan="40" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr> |
<tr><td rowspan="39" valign="bottom"><font color="white">abcd</font></td> <td colspan="2"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr> |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">msp430sim</td> <td><i>Main simulation script for assembler vector sources (located in the <span style="font-weight: bold;">src</span> directory)<br> |
</i></td></tr> |
<tr> |
<td style="vertical-align: top;">msp430sim_c<br> |
</td> |
<td style="vertical-align: top;"><i>Main simulation script for C vector sources</i><i> (located in the <span style="font-weight: bold;">src-c</span> directory)</i></td> |
</tr> |
<tr><td colspan="1">asm2ihex.sh</td> <td><i>Assembly file compilation (Intel HEX file generation)</i></td></tr> |
<tr><td colspan="1">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr> |
<tr><td colspan="1">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr> |
<tr><td colspan="1">template.def</td> <td><i>ASM linker definition file template</i></td></tr> |
<tr><td colspan="2"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">run</td> <td><i>Run single simulation of a given vector</i></td></tr> |
<tr><td colspan="1">run_all</td> <td><i>Run regression of all vectors</i></td></tr> |
<tr><td colspan="1">run_disassemble</td> <td><i>Disassemble the program memory content of the latest simulation</i></td></tr> |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">run</td> <td><i>Run single simulation of a given assembler vector</i></td></tr> |
<tr> |
<td style="vertical-align: top;">run_c<br> |
</td> |
<td style="vertical-align: top;"><i>Run single simulation of a given C vector</i></td> |
</tr> |
<tr><td colspan="1">run_all</td> <td><i>Run regression of all vectors</i></td></tr> |
<tr> |
<td style="vertical-align: top;">run_all_mpy<br> |
</td> |
<td style="vertical-align: top;"><span style="font-style: italic;">Run regression of all hardware multiplier vectors (!!! very long simulation time !!!)</span><br> |
</td> |
</tr> |
<tr><td colspan="1">run_disassemble</td> <td><i>Disassemble the program memory content of the latest simulation</i></td></tr> |
<tr><td colspan="1">load_waveform.sav</td> <td><i>SAV file for gtkWave</i></td></tr> |
<tr><td colspan="2"><b>src</b></td> <td><i><b>RTL simulation vectors sources</b></i></td></tr> |
<tr><td rowspan="23" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">submit.f</td> <td><i>Verilog simulator command file</i></td></tr> |
<tr><td colspan="1">sing-op_*.s43</td> <td><i>Single-operand assembler vector files</i></td></tr> |
<tr><td rowspan="24" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">ldscript_example.x<br> |
</td> <td><i>MSPGCC toolchain linker script example</i></td></tr> |
<tr> |
<td style="vertical-align: top;">submit.f</td> |
<td style="vertical-align: top;"><i>Verilog simulator command file</i></td> |
</tr> |
<tr><td colspan="1">sing-op_*.s43</td> <td><i>Single-operand assembler vector files</i></td></tr> |
<tr><td colspan="1">sing-op_*.v</td> <td><i>Single-operand verilog stimulus vector files</i></td></tr> |
<tr><td colspan="1">two-op_*.s43</td> <td><i>Two-operand assembler vector files</i></td></tr> |
<tr><td colspan="1">two-op_*.v</td> <td><i>Two-operand verilog stimulus vector files</i></td></tr> |
119,20 → 156,24
|
<table border="1"> |
<tbody><tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr> |
<tr><td rowspan="52" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>xilinx_diligent_s3_board</b></td> <td><i><b>Xilinx FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr> |
<tr><td rowspan="51" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr> |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br> |
<tr><td rowspan="53" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>xilinx_diligent_s3_board</b></td> <td><i><b>Xilinx FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr> |
<tr><td rowspan="52" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr> |
<tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br> |
</td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr> |
<tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr> |
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr> |
<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr> |
<tr><td colspan="3">glbl.v</td> <td><i>Xilinx "glbl.v" file</i></td></tr> |
<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr> |
<tr> |
<td colspan="3">timescale.v<br> |
</td> <td> <i>Global time scale definition for simulation.</i> </td> |
</tr> |
<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr> |
<tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">board_user_guide.pdf</td> <td><i>Spartan-3 FPGA Starter Kit Board User Guide</i></td></tr> |
<tr><td colspan="4">msp430f1121a.pdf</td> <td><i>msp430f1121a Specification</i></td></tr> |
<tr><td colspan="4">xapp462.pdf</td> <td><i>Xilinx Digital Clock Managers (DCMs) user guide</i></td></tr> |
<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr> |
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i><br> |
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><br> |
</td></tr> |
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr> |
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr> |
189,21 → 230,27
|
<table border="1"> |
<tbody><tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr> |
<tr><td rowspan="49" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>altera_de1_board</b></td> <td><i><b>Altera FPGA Project based on Cyclone II Starter Development Board</b></i></td></tr> |
<tr><td rowspan="48" valign="bottom"><font color="white">abcd</font></td> <td colspan="5">README</td> <td><i>README file</i></td></tr> |
<tr><td rowspan="50" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>altera_de1_board</b></td> <td><i><b>Altera FPGA Project based on Cyclone II Starter Development Board</b></i></td></tr> |
<tr><td rowspan="49" valign="bottom"><font color="white">abcd</font></td> <td colspan="5">README</td> <td><i>README file</i></td></tr> |
<tr><td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr> |
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br> |
<tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br> |
</td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr> |
<tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr> |
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr> |
<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr> |
<tr><td colspan="3">altsyncram.v</td> <td><i>Altera verilog model of the altsyncram module.</i></td></tr> |
<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr> |
<tr> |
<td colspan="3" rowspan="1" style="vertical-align: top;">timescale.v<br> |
</td> |
<td style="vertical-align: top;"><i>Global time scale definition for simulation.</i> |
</td> |
</tr> |
<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr> |
<tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">DE1_Board_Schematic.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Schematics</i></td></tr> |
<tr><td colspan="4">DE1_Reference_Manual.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Reference Manual</i></td></tr> |
<tr><td colspan="4">DE1_User_Guide.pdf</td> <td><i>Cyclone II FPGA Starter Development Board User Guide</i></td></tr> |
<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr> |
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i><br> |
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><br> |
</td></tr> |
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">OpenMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr> |
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr> |
249,20 → 296,30
|
<table border="1"> |
<tbody><tr><td colspan="6"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr> |
<tr><td rowspan="43" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>actel_m1a3pl_dev_kit</b></td> <td><i><b>Actel FPGA Project based on the ProASIC3 M1A3PL development kit<br> |
<tr><td rowspan="45" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>actel_m1a3pl_dev_kit</b></td> <td><i><b>Actel FPGA Project based on the ProASIC3 M1A3PL development kit<br> |
</b></i></td></tr> |
|
<tr><td rowspan="42" style="vertical-align: top;"><font color="white">abcd</font></td> |
<tr><td rowspan="44" style="vertical-align: top;"><font color="white">abcd</font></td> |
<td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr> |
<tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br> |
<tr><td colspan="1" rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br> |
</td></tr> |
<tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">tb_openMSP430_fpga.v</td> |
<tr><td colspan="1" rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">tb_openMSP430_fpga.v</td> |
<td><i>FPGA testbench top level module</i></td></tr> |
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">registers.v</td> |
<td><i>Connections to Core internals for easy debugging</i></td></tr> |
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">msp_debug.v</td> |
<td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr> |
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">proasic3l.v</td> |
<tr> |
<td colspan="2" rowspan="1" style="vertical-align: top;">dbg_uart_tasks.v<br> |
</td> |
<td style="vertical-align: top;"><i>UART tasks for the serial debug interface.</i></td> |
</tr> |
<tr> |
<td colspan="2" rowspan="1" style="vertical-align: top;">timescale.v<br> |
</td> |
<td style="vertical-align: top;"><i>Global time scale definition for simulation.</i></td> |
</tr> |
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">proasic3l.v</td> |
<td><i>Actel ProASIC3L library file.<br> |
</i></td></tr> |
<tr> |
367,7 → 424,7
<tr> |
<td style="vertical-align: top;"><br> |
</td> |
<td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><img src="usercontent,img,1299013492" alt="Spacewar" title="Spacewar" width="25%"/><br> |
<td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><img src="usercontent,img,1299013492" alt="Spacewar" title="Spacewar" width="25%"><br> |
</td> |
</tr> |
<tr><td colspan="4"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr> |
415,31 → 472,58
<h1>4. Directory structure: Software Development Tools</h1> |
|
<table border="1"> |
<tbody><tr><td colspan="5"><b>tools</b></td> <td><i><b>openMSP430 Software Development Tools top level directory</b></i></td></tr> |
<tr><td rowspan="72" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bin</b></td> <td><i><b>Contains the executable files</b></i></td></tr> |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openmsp430-loader.tcl</td> <td><i>Simple command line boot loader: TCL Script</i></td></tr> |
<tr><td colspan="3">openmsp430-loader.exe</td> <td><i>Simple command line boot loader: Windows executable</i></td></tr> |
<tr><td colspan="3">openmsp430-minidebug.tcl</td> <td><i>Minimalistic debugger with simple GUI: TCL Script</i></td></tr> |
<tr><td colspan="3">openmsp430-minidebug.exe</td> <td><i>Minimalistic debugger with simple GUI: Windows executable</i></td></tr> |
<tr><td colspan="3">openmsp430-gdbproxy.tcl</td> <td><i>GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends: TCL Script</i></td></tr> |
<tr><td colspan="3">openmsp430-gdbproxy.exe</td> <td><i>GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends: Windows executable</i></td></tr> |
<tr><td colspan="4"><b>lib</b></td> <td><i><b>Common library</b></i></td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>tcl-lib</b></td> <td><i><b>Common TCL library</b></i></td></tr> |
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">dbg_uart.tcl</td> <td><i>Low level UART communication functions</i></td></tr> |
<tr><td colspan="2">dbg_functions.tcl</td> <td><i>Main utility functions for the openMSP430 serial debug interface</i></td></tr> |
<tr><td colspan="2">combobox.tcl</td> <td><i>A combobox listbox widget written in pure tcl (from Bryan Oakley)</i></td></tr> |
<tr><td colspan="4"><b>openmsp430-gdbproxy</b></td> <td><i><b>GDB Proxy server main project directory</b></i></td></tr> |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openmsp430-gdbproxy.tcl</td> <td><i>GDB Proxy server main TCL Script (symbolic link with the script in the <b>bin</b> directory)</i></td></tr> |
<tr><td colspan="3">server.tcl</td> <td><i>TCP/IP Server utility functions. Send/Receive RSP packets from GDB.</i></td></tr> |
<tr><td colspan="3">commands.tcl</td> <td><i>RSP command execution functions.</i></td></tr> |
<tr><td colspan="3"><b>doc</b></td> <td><i><b>Some documentation regarding GDB and the RSP protocol.</b></i></td></tr> |
<tr><td rowspan="2"><font color="white">abcd</font></td> <td colspan="2">ew_GDB_RSP.pdf</td> <td><i>Document from Bill Gatliff: Embedding with GNU: the gdb Remote Serial Protocol</i></td></tr> |
<tr><td colspan="2">Howto-GDB_Remote_Serial_Protocol.pdf</td> <td><i>Document from Jeremy Bennett (Embecosm): Howto: GDB Remote Serial Protocol - Writing a RSP Server</i></td></tr> |
<tr><td colspan="4"><b>freewrap642</b></td> <td><i><b>The freeWrap program turns TCL/TK scripts into single-file binary executable programs for Windows.</b></i></td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">freewrap.exe</td> <td><i>freeWrap executable to run on TCL/TK scripts (i.e. with GUI)</i></td></tr> |
<tr><td colspan="3">freewrapTCLSH.exe</td> <td><i>freeWrap executable to run on pure TCL scripts (i.e. command line)</i></td></tr> |
<tr><td colspan="3">tclpip85s.dll</td> <td><i>freeWrap mandatory DLL</i></td></tr> |
<tr><td colspan="3">generate_exec.bat</td> <td><i>Simple Batch file for auto generation of the tools' windows executables</i></td></tr> |
<tbody><tr><td colspan="4"><b>tools</b></td> <td><i><b>openMSP430 Software Development Tools top level directory</b></i></td></tr> |
<tr> |
<td colspan="1" rowspan="24" style="vertical-align: top;"><font color="white">abcd</font></td> |
<td colspan="3" rowspan="1" style="vertical-align: top;">omsp_alias.xml<br> |
</td> |
<td style="vertical-align: top;"><span style="font-style: italic;">This |
XML file allows the software development tools to identify a openMSP430 |
implementation, and add customized extra information (Alias, URL, ...).</span><br> |
</td> |
</tr> |
<tr> <td colspan="3"><b>bin</b></td> <td><i><b>Contains the main TCL scripts (and the windows executable files if generated)<br> |
</b></i></td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openmsp430-loader.tcl</td> <td><i>Simple command line boot loader</i></td></tr> |
|
<tr><td colspan="2">openmsp430-minidebug.tcl</td> <td><i>Minimalistic debugger with simple GUI</i></td></tr> |
|
<tr><td colspan="2">openmsp430-gdbproxy.tcl</td> <td><i>GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends<br> |
</i></td></tr> |
<tr><td colspan="2">README.TXT</td> <td><i>README file regarding the use of TCL scripts in a Windows environment.</i></td></tr> |
|
<tr><td colspan="3"><b>lib</b></td> <td><i><b>Common library</b></i></td></tr> |
<tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="2"><b>tcl-lib</b></td> <td><i><b>Common TCL library</b></i></td></tr> |
<tr><td colspan="1" rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td rowspan="1" colspan="1">dbg_uart.tcl<i><br> |
</i></td> <td style="vertical-align: top;"><i>Low level UART communication functions</i></td> |
</tr> |
<tr><td rowspan="1" colspan="1">dbg_functions.tcl<i><br> |
</i></td> <td style="vertical-align: top;"><i>Main utility functions for the openMSP430 serial debug interface</i></td> |
</tr> |
<tr><td rowspan="1" colspan="1">combobox.tcl<i><br> |
</i></td> <td style="vertical-align: top;"><i>A combobox listbox widget written in pure tcl (from Bryan Oakley)</i></td> |
</tr> |
<tr><td colspan="1">xml.tcl</td> <td style="vertical-align: top;"><i>Simple XML parser (from Keith Vetter)</i></td> |
</tr> |
<tr><td colspan="3"><b>openmsp430-gdbproxy</b></td> <td><i><b>GDB Proxy server main project directory</b></i></td></tr> |
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openmsp430-gdbproxy.tcl</td> <td><i>GDB Proxy server main TCL Script (symbolic link with the script in the <b>bin</b> directory)</i></td></tr> |
<tr><td colspan="2">server.tcl</td> <td><i>TCP/IP Server utility functions. Send/Receive RSP packets from GDB.</i></td></tr> |
<tr><td colspan="2">commands.tcl</td> <td><i>RSP command execution functions.</i></td></tr> |
<tr><td colspan="2"><b>doc</b></td> <td><i><b>Some documentation regarding GDB and the RSP protocol.</b></i></td></tr> |
<tr><td rowspan="2"><font color="white">abcd</font></td> <td rowspan="1" colspan="1">ew_GDB_RSP.pdf<i><br> |
</i></td> <td style="vertical-align: top;"><i>Document from Bill Gatliff: Embedding with GNU: the gdb Remote Serial Protocol</i></td> |
</tr> |
<tr><td rowspan="1" colspan="1">Howto-GDB_Remote_Serial_Protocol.pdf<i><br> |
</i></td> <td style="vertical-align: top;"><i>Document from Jeremy Bennett (Embecosm): Howto: GDB Remote Serial Protocol - Writing a RSP Server</i></td> |
</tr> |
<tr><td colspan="3"><b>freewrap642</b></td> <td><i><b>The freeWrap program turns TCL/TK scripts into single-file binary executable programs for Windows.</b></i></td></tr> |
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">freewrap.exe</td> <td><i>freeWrap executable to run on TCL/TK scripts (i.e. with GUI)</i></td></tr> |
<tr><td colspan="2">freewrapTCLSH.exe</td> <td><i>freeWrap executable to run on pure TCL scripts (i.e. command line)</i></td></tr> |
<tr><td colspan="2">tclpip85s.dll</td> <td><i>freeWrap mandatory DLL</i></td></tr> |
<tr><td rowspan="1" colspan="2" style="vertical-align: top;">generate_exec.bat<i><br> |
</i></td> |
<td style="vertical-align: top;"><i>Simple Batch file for auto generation of the tools' windows executables</i></td> |
</tr> |
</tbody></table> |
<br> |
<div style="text-align: right;"><a href="#TOC">Top</a></div> |
/doc/openMSP430.odt
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/ChangeLog_core.txt
1,3 → 1,7
2011-05-29 [r115] |
|
* Add linker script example. |
|
2011-05-21 [r112] |
|
* Modified comment. |