URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/openmsp430
- from Rev 222 to Rev 223
- ↔ Reverse comparison
Rev 222 → Rev 223
/trunk/fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_reg.v
897,11 → 897,11
else if (frame_select_wr) |
begin |
refresh_frame_select <= per_din_i[1:0]; |
vid_ram0_frame_select <= per_din_i[5:4]; |
vid_ram1_frame_select <= per_din_i[7:6]; |
vid_ram0_frame_select <= per_din_i[9:8]; |
vid_ram1_frame_select <= per_din_i[13:12]; |
end |
|
wire [15:0] frame_select = {8'h00, vid_ram1_frame_select, vid_ram0_frame_select, 2'h0, refresh_frame_select}; |
wire [15:0] frame_select = {2'h0, vid_ram1_frame_select, 2'h0, vid_ram0_frame_select, 6'h00, refresh_frame_select}; |
`else |
reg refresh_frame_select; |
reg vid_ram0_frame_select; |
917,11 → 917,11
else if (frame_select_wr) |
begin |
refresh_frame_select <= per_din_i[0]; |
vid_ram0_frame_select <= per_din_i[4]; |
vid_ram1_frame_select <= per_din_i[6]; |
vid_ram0_frame_select <= per_din_i[8]; |
vid_ram1_frame_select <= per_din_i[12]; |
end |
|
wire [15:0] frame_select = {8'h00, 1'h0, vid_ram1_frame_select, 1'h0, vid_ram0_frame_select, 2'h0, 1'h0, refresh_frame_select}; |
wire [15:0] frame_select = {3'h0, vid_ram1_frame_select, 3'h0, vid_ram0_frame_select, 7'h00, refresh_frame_select}; |
`endif |
`else |
wire [15:0] frame_select = 16'h0000; |
/trunk/fpga/altera_de0_nano_soc/software/libs/gfx/gfx_controller.h
249,16 → 249,16
#define REFRESH_FRAME_MASK 0x0003 |
|
#define VID_RAM0_FRAME0_SELECT 0x0000 |
#define VID_RAM0_FRAME1_SELECT 0x0010 |
#define VID_RAM0_FRAME2_SELECT 0x0020 |
#define VID_RAM0_FRAME3_SELECT 0x0030 |
#define VID_RAM0_FRAME_MASK 0x0030 |
#define VID_RAM0_FRAME1_SELECT 0x0100 |
#define VID_RAM0_FRAME2_SELECT 0x0200 |
#define VID_RAM0_FRAME3_SELECT 0x0300 |
#define VID_RAM0_FRAME_MASK 0x0300 |
|
#define VID_RAM1_FRAME0_SELECT 0x0000 |
#define VID_RAM1_FRAME1_SELECT 0x0040 |
#define VID_RAM1_FRAME2_SELECT 0x0080 |
#define VID_RAM1_FRAME3_SELECT 0x00C0 |
#define VID_RAM1_FRAME_MASK 0x00C0 |
#define VID_RAM1_FRAME1_SELECT 0x1000 |
#define VID_RAM1_FRAME2_SELECT 0x2000 |
#define VID_RAM1_FRAME3_SELECT 0x3000 |
#define VID_RAM1_FRAME_MASK 0x3000 |
|
// VID_RAMx_CFG Register |
#define VID_RAM_RMW_MODE 0x0010 |