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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/boards
    from Rev 568 to Rev 563
    ↔ Reverse comparison
  •

Rev 568 → Rev 563

/xilinx/s3adsp1800/sw/board/include/board.h File deleted
/xilinx/s3adsp1800/sw/bootrom/Makefile File deleted
/xilinx/s3adsp1800/sw/bootrom/bootrom.v File deleted
/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/Makefile File deleted
/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/ddr2cache-1.S File deleted
/xilinx/s3adsp1800/sw/tests/ddr2cache/sim/ddr2cache-2.S File deleted
/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-tx.c File deleted
/xilinx/s3adsp1800/sw/tests/ethmac/sim/Makefile File deleted
/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c File deleted
/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rxtx.c File deleted
/xilinx/s3adsp1800/sw/tests/ethmac/sim/ethmac-rx.c File deleted
/xilinx/s3adsp1800/sw/Makefile.inc File deleted
/xilinx/s3adsp1800/syn/xst/run/Makefile File deleted
/xilinx/s3adsp1800/syn/xst/bin/Makefile File deleted
/xilinx/s3adsp1800/README File deleted
/xilinx/s3adsp1800/bench/verilog/include/eth_stim.v File deleted \ No newline at end of file
/xilinx/s3adsp1800/bench/verilog/include/eth_phy_defines.v File deleted
/xilinx/s3adsp1800/bench/verilog/include/ddr2_model_parameters.v File deleted
/xilinx/s3adsp1800/bench/verilog/include/ddr2_model_preload.v File deleted
/xilinx/s3adsp1800/bench/verilog/include/synthesis-defines.v File deleted
/xilinx/s3adsp1800/bench/verilog/include/timescale.v File deleted \ No newline at end of file
/xilinx/s3adsp1800/bench/verilog/orpsoc_testbench.v File deleted
/xilinx/s3adsp1800/bench/verilog/ddr2_model.v File deleted
/xilinx/s3adsp1800/rtl/verilog/orpsoc_top/orpsoc_top.v File deleted
/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_dbus.v File deleted
/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_bytebus.v File deleted
/xilinx/s3adsp1800/rtl/verilog/arbiter/arbiter_ibus.v File deleted
/xilinx/s3adsp1800/rtl/verilog/gpio/README File deleted
/xilinx/s3adsp1800/rtl/verilog/gpio/gpio.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_path_iobs_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_top_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cal_top.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_read_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dqs_iob.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_read_controller_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2_if.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_ram8d_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_clk_dcm.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_tap_dly.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dm_iob.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_wr_gray_cntr.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cal_ctl.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_s3_dq_iob.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure_top.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_controller_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_write_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_cache.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_data_path_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_dqs_delay.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_infrastructure_iobs_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_fifo_0_wr_en_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_iobs_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/xilinx_s3adsp_ddr2.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_fifo_1_wr_en_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_rd_gray_cntr.v File deleted
/xilinx/s3adsp1800/rtl/verilog/xilinx_s3adsp_ddr2/s3adsp_ddr2_controller_iobs_0.v File deleted
/xilinx/s3adsp1800/rtl/verilog/include/orpsoc-params.v File deleted
/xilinx/s3adsp1800/rtl/verilog/include/uart_defines.v File deleted
/xilinx/s3adsp1800/rtl/verilog/include/dbg_defines.v File deleted
/xilinx/s3adsp1800/rtl/verilog/include/s3adsp_ddr2_parameters_0.v File deleted \ No newline at end of file
/xilinx/s3adsp1800/rtl/verilog/include/ethmac_defines.v File deleted \ No newline at end of file
/xilinx/s3adsp1800/rtl/verilog/include/i2c_master_slave_defines.v File deleted
/xilinx/s3adsp1800/rtl/verilog/include/orpsoc-defines.v File deleted
/xilinx/s3adsp1800/rtl/verilog/include/dbg_cpu_defines.v File deleted
/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v File deleted
/xilinx/s3adsp1800/rtl/verilog/include/tap_defines.v File deleted
/xilinx/s3adsp1800/rtl/verilog/include/dbg_wb_defines.v File deleted
/xilinx/s3adsp1800/rtl/verilog/clkgen/clkgen.v File deleted
/xilinx/s3adsp1800/Makefile.inc File deleted
/xilinx/s3adsp1800/backend/par/run/Makefile File deleted
/xilinx/s3adsp1800/backend/par/bin/Makefile File deleted
/xilinx/s3adsp1800/backend/par/bin/s3adsp1800.ucf File deleted
/xilinx/s3adsp1800/backend/bin/s3adsp_ddr2_cache.ngc File deleted \ No newline at end of file
/xilinx/s3adsp1800/sim/run/Makefile File deleted
/xilinx/s3adsp1800/sim/bin/Makefile File deleted

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