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/openrisc/trunk/or1200/rtl/verilog
- from Rev 151 to Rev 185
- ↔ Reverse comparison
Rev 151 → Rev 185
/or1200_defines.v
3,10 → 3,10
//// OR1200's definitions //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// Parameters of the OR1200 core //// |
//// Defines for the OR1200 core //// |
//// //// |
//// To Do: //// |
//// - add parameters that are missing //// |
41,218 → 41,10
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: or1200_defines.v,v $ |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// Minor update: |
// Defines added, bugs fixed. |
// |
// Revision 1.45 2006/04/09 01:32:29 lampret |
// See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts. |
// |
// Revision 1.44 2005/10/19 11:37:56 jcastillo |
// Added support for RAMB16 Xilinx4/Spartan3 primitives |
// |
// Revision 1.43 2005/01/07 09:23:39 andreje |
// l.ff1 and l.cmov instructions added |
// |
// Revision 1.42 2004/06/08 18:17:36 lampret |
// Non-functional changes. Coding style fixes. |
// |
// Revision 1.41 2004/05/09 20:03:20 lampret |
// By default l.cust5 insns are disabled |
// |
// Revision 1.40 2004/05/09 19:49:04 lampret |
// Added some l.cust5 custom instructions as example |
// |
// Revision 1.39 2004/04/08 11:00:46 simont |
// Add support for 512B instruction cache. |
// |
// Revision 1.38 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.35.4.6 2004/02/11 01:40:11 lampret |
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. |
// |
// Revision 1.35.4.5 2004/01/15 06:46:38 markom |
// interface to debug changed; no more opselect; stb-ack protocol |
// |
// Revision 1.35.4.4 2004/01/11 22:45:46 andreje |
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added |
// |
// Revision 1.35.4.3 2003/12/17 13:43:38 simons |
// Exception prefix configuration changed. |
// |
// Revision 1.35.4.2 2003/12/05 00:05:03 lampret |
// Static exception prefix. |
// |
// Revision 1.35.4.1 2003/07/08 15:36:37 lampret |
// Added embedded memory QMEM. |
// |
// Revision 1.35 2003/04/24 00:16:07 lampret |
// No functional changes. Added defines to disable implementation of multiplier/MAC |
// |
// Revision 1.34 2003/04/20 22:23:57 lampret |
// No functional change. Only added customization for exception vectors. |
// |
// Revision 1.33 2003/04/07 20:56:07 lampret |
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. |
// |
// Revision 1.32 2003/04/07 01:26:57 lampret |
// RFRAM defines comments updated. Altera LPM option added. |
// |
// Revision 1.31 2002/12/08 08:57:56 lampret |
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. |
// |
// Revision 1.30 2002/10/28 15:09:22 mohor |
// Previous check-in was done by mistake. |
// |
// Revision 1.29 2002/10/28 15:03:50 mohor |
// Signal scanb_sen renamed to scanb_en. |
// |
// Revision 1.28 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
// Revision 1.27 2002/09/16 03:13:23 lampret |
// Removed obsolete comment. |
// |
// Revision 1.26 2002/09/08 05:52:16 lampret |
// Added optional l.div/l.divu insns. By default they are disabled. |
// |
// Revision 1.25 2002/09/07 19:16:10 lampret |
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. |
// |
// Revision 1.24 2002/09/07 05:42:02 lampret |
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. |
// |
// Revision 1.23 2002/09/04 00:50:34 lampret |
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. |
// |
// Revision 1.22 2002/09/03 22:28:21 lampret |
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. |
// |
// Revision 1.21 2002/08/22 02:18:55 lampret |
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. |
// |
// Revision 1.20 2002/08/18 21:59:45 lampret |
// Disable SB until it is tested |
// |
// Revision 1.19 2002/08/18 19:53:08 lampret |
// Added store buffer. |
// |
// Revision 1.18 2002/08/15 06:04:11 lampret |
// Fixed Xilinx trace buffer address. REported by Taylor Su. |
// |
// Revision 1.17 2002/08/12 05:31:44 lampret |
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. |
// |
// Revision 1.16 2002/07/14 22:17:17 lampret |
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. |
// |
// Revision 1.15 2002/06/08 16:20:21 lampret |
// Added defines for enabling generic FF based memory macro for register file. |
// |
// Revision 1.14 2002/03/29 16:24:06 lampret |
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives |
// |
// Revision 1.13 2002/03/29 15:16:55 lampret |
// Some of the warnings fixed. |
// |
// Revision 1.12 2002/03/28 19:25:42 lampret |
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. |
// |
// Revision 1.11 2002/03/28 19:13:17 lampret |
// Updated defines. |
// |
// Revision 1.10 2002/03/14 00:30:24 lampret |
// Added alternative for critical path in DU. |
// |
// Revision 1.9 2002/03/11 01:26:26 lampret |
// Fixed async loop. Changed multiplier type for ASIC. |
// |
// Revision 1.8 2002/02/11 04:33:17 lampret |
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. |
// |
// Revision 1.7 2002/02/01 19:56:54 lampret |
// Fixed combinational loops. |
// |
// Revision 1.6 2002/01/19 14:10:22 lampret |
// Fixed OR1200_XILINX_RAM32X1D. |
// |
// Revision 1.5 2002/01/18 07:56:00 lampret |
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. |
// |
// Revision 1.4 2002/01/14 09:44:12 lampret |
// Default ASIC configuration does not sample WB inputs. |
// |
// Revision 1.3 2002/01/08 00:51:08 lampret |
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. |
// |
// Revision 1.2 2002/01/03 21:23:03 lampret |
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.20 2001/12/04 05:02:36 lampret |
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 |
// |
// Revision 1.19 2001/11/27 19:46:57 lampret |
// Now FPGA and ASIC target are separate. |
// |
// Revision 1.18 2001/11/23 21:42:31 simons |
// Program counter divided to PPC and NPC. |
// |
// Revision 1.17 2001/11/23 08:38:51 lampret |
// Changed DSR/DRR behavior and exception detection. |
// |
// Revision 1.16 2001/11/20 21:30:38 lampret |
// Added OR1200_REGISTERED_INPUTS. |
// |
// Revision 1.15 2001/11/19 14:29:48 simons |
// Cashes disabled. |
// |
// Revision 1.14 2001/11/13 10:02:21 lampret |
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) |
// |
// Revision 1.13 2001/11/12 01:45:40 lampret |
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. |
// |
// Revision 1.12 2001/11/10 03:43:57 lampret |
// Fixed exceptions. |
// |
// Revision 1.11 2001/11/02 18:57:14 lampret |
// Modified virtual silicon instantiations. |
// |
// Revision 1.10 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.9 2001/10/19 23:28:46 lampret |
// Fixed some synthesis warnings. Configured with caches and MMUs. |
// |
// Revision 1.8 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm |
// no message |
// |
// Revision 1.3 2001/08/17 08:01:19 lampret |
// IC enable/disable. |
// |
// Revision 1.2 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/22 03:31:54 lampret |
// Fixed RAM's oen bug. Cache bypass under development. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// |
// Dump VCD |
584,6 → 376,11
//`define OR1200_LOWPWR_MULT |
|
// |
// Implement HW Single Precision FPU |
// |
//`define OR1200_FPU_IMPLEMENTED |
|
// |
// Clock ratio RISC clock versus WB clock |
// |
// If you plan to run WB:RISC clock fixed to 1:1, disable |
670,9 → 467,9
`define OR1200_SHROTOP_ROR 2'd3 |
|
// Execution cycles per instruction |
`define OR1200_MULTICYCLE_WIDTH 2 |
`define OR1200_ONE_CYCLE 2'd0 |
`define OR1200_TWO_CYCLES 2'd1 |
`define OR1200_MULTICYCLE_WIDTH 3 |
`define OR1200_ONE_CYCLE 3'd0 |
`define OR1200_TWO_CYCLES 3'd1 |
|
// Operand MUX selects |
`define OR1200_SEL_WIDTH 2 |
728,13 → 525,15
// Register File Write-Back OPs |
// |
// Bit 0: register file write enable |
// Bits 2-1: write-back mux selects |
`define OR1200_RFWBOP_WIDTH 3 |
`define OR1200_RFWBOP_NOP 3'b000 |
`define OR1200_RFWBOP_ALU 3'b001 |
`define OR1200_RFWBOP_LSU 3'b011 |
`define OR1200_RFWBOP_SPRS 3'b101 |
`define OR1200_RFWBOP_LR 3'b111 |
// Bits 3-1: write-back mux selects |
// |
`define OR1200_RFWBOP_WIDTH 4 |
`define OR1200_RFWBOP_NOP 4'b0000 |
`define OR1200_RFWBOP_ALU 3'b000 |
`define OR1200_RFWBOP_LSU 3'b001 |
`define OR1200_RFWBOP_SPRS 3'b010 |
`define OR1200_RFWBOP_LR 3'b011 |
`define OR1200_RFWBOP_FPU 3'b100 |
|
// Compare instructions |
`define OR1200_COP_SFEQ 3'b000 |
748,6 → 547,33
`define OR1200_COMPOP_WIDTH 4 |
|
// |
// FP OPs |
// |
// MSbit indicates FPU operation valid |
// |
`define OR1200_FPUOP_WIDTH 8 |
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles |
`define OR1200_FPUOP_CYCLES 3'd4 |
// FP instruction is double precision if bit 4 is set. We're a 32-bit |
// implementation thus do not support double precision FP |
`define OR1200_FPUOP_DOUBLE_BIT 4 |
`define OR1200_FPUOP_ADD 8'b0000_0000 |
`define OR1200_FPUOP_SUB 8'b0000_0001 |
`define OR1200_FPUOP_MUL 8'b0000_0010 |
`define OR1200_FPUOP_DIV 8'b0000_0011 |
`define OR1200_FPUOP_ITOF 8'b0000_0100 |
`define OR1200_FPUOP_FTOI 8'b0000_0101 |
`define OR1200_FPUOP_REM 8'b0000_0110 |
`define OR1200_FPUOP_RESERVED 8'b0000_0111 |
// FP Compare instructions |
`define OR1200_FPCOP_SFEQ 8'b0000_1000 |
`define OR1200_FPCOP_SFNE 8'b0000_1001 |
`define OR1200_FPCOP_SFGT 8'b0000_1010 |
`define OR1200_FPCOP_SFGE 8'b0000_1011 |
`define OR1200_FPCOP_SFLT 8'b0000_1100 |
`define OR1200_FPCOP_SFLE 8'b0000_1101 |
|
// |
// TAGs for instruction bus |
// |
`define OR1200_ITAG_IDLE 4'h0 // idle bus |
811,6 → 637,7
/* */ |
`define OR1200_OR32_MTSPR 6'b110000 |
`define OR1200_OR32_MACMSB 6'b110001 |
`define OR1200_OR32_FLOAT 6'b110010 |
/* */ |
`define OR1200_OR32_SW 6'b110101 |
`define OR1200_OR32_SB 6'b110110 |
864,7 → 691,7
// |
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf |
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he |
`define OR1200_EXCEPT_BREAK `OR1200_EXCEPT_WIDTH'hd |
`define OR1200_EXCEPT_FLOAT `OR1200_EXCEPT_WIDTH'hd |
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc |
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb |
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha |
905,8 → 732,8
`define OR1200_SPR_GROUP_PM 5'd08 |
`define OR1200_SPR_GROUP_PIC 5'd09 |
`define OR1200_SPR_GROUP_TT 5'd10 |
`define OR1200_SPR_GROUP_FPU 5'd11 |
|
|
///////////////////////////////////////////////////// |
// |
// System group |
920,6 → 747,7
`define OR1200_SPR_NPC 11'd16 |
`define OR1200_SPR_SR 11'd17 |
`define OR1200_SPR_PPC 11'd18 |
`define OR1200_SPR_FPCSR 11'd20 |
`define OR1200_SPR_EPCR 11'd32 |
`define OR1200_SPR_EEAR 11'd48 |
`define OR1200_SPR_ESR 11'd64 |
960,6 → 788,24
// |
`define OR1200_SR_EPH_DEF 1'b0 |
|
|
// |
// FPCSR bits |
// |
`define OR1200_FPCSR_WIDTH 12 |
`define OR1200_FPCSR_FPEE 0 |
`define OR1200_FPCSR_RM 2:1 |
`define OR1200_FPCSR_OVF 3 |
`define OR1200_FPCSR_UNF 4 |
`define OR1200_FPCSR_SNF 5 |
`define OR1200_FPCSR_QNF 6 |
`define OR1200_FPCSR_ZF 7 |
`define OR1200_FPCSR_IXF 8 |
`define OR1200_FPCSR_IVF 9 |
`define OR1200_FPCSR_INF 10 |
`define OR1200_FPCSR_DZF 11 |
`define OR1200_FPCSR_RES 31:12 |
|
///////////////////////////////////////////////////// |
// |
// Power Management (PM) |
1108,7 → 954,7
`define OR1200_DU_DSR_IME 9 |
`define OR1200_DU_DSR_RE 10 |
`define OR1200_DU_DSR_SCE 11 |
`define OR1200_DU_DSR_BE 12 |
`define OR1200_DU_DSR_FPE 12 |
`define OR1200_DU_DSR_TE 13 |
|
// DRR bits |
1124,7 → 970,7
`define OR1200_DU_DRR_IME 9 |
`define OR1200_DU_DRR_RE 10 |
`define OR1200_DU_DRR_SCE 11 |
`define OR1200_DU_DRR_BE 12 |
`define OR1200_DU_DRR_FPE 12 |
`define OR1200_DU_DRR_TE 13 |
|
// Define if reading DU regs is allowed |
1800,8 → 1646,10
|
/////////////////////////////////////////////////////////////////////////////// |
// Boot Address Selection // |
// This only changes where the initial reset occurs. EPH setting is still // |
// used to determine where vectors are located. // |
/////////////////////////////////////////////////////////////////////////////// |
// Boot from ROM at 0xf0000100 |
// Boot from 0xf0000100 |
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f |
`define OR1200_BOOT_ADR 32'hf0000100 |
// Boot from 0x100 |
/or1200_alu.v
3,7 → 3,7
//// OR1200's ALU //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://www.opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// ALU //// |
41,80 → 41,10
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: or1200_alu.v,v $ |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// Minor update: |
// Defines added, flags are corrected. |
// |
// Revision 1.15 2005/01/07 09:23:39 andreje |
// l.ff1 and l.cmov instructions added |
// |
// Revision 1.14 2004/06/08 18:17:36 lampret |
// Non-functional changes. Coding style fixes. |
// |
// Revision 1.13 2004/05/09 19:49:03 lampret |
// Added some l.cust5 custom instructions as example |
// |
// Revision 1.12 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.11 2003/04/24 00:16:07 lampret |
// No functional changes. Added defines to disable implementation of multiplier/MAC |
// |
// Revision 1.10 2002/09/08 05:52:16 lampret |
// Added optional l.div/l.divu insns. By default they are disabled. |
// |
// Revision 1.9 2002/09/07 19:16:10 lampret |
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. |
// |
// Revision 1.8 2002/09/07 05:42:02 lampret |
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. |
// |
// Revision 1.7 2002/09/03 22:28:21 lampret |
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. |
// |
// Revision 1.6 2002/03/29 16:40:10 lampret |
// Added a directive to ignore signed division variables that are only used in simulation. |
// |
// Revision 1.5 2002/03/29 16:33:59 lampret |
// Added again just recently removed full_case directive |
// |
// Revision 1.4 2002/03/29 15:16:53 lampret |
// Some of the warnings fixed. |
// |
// Revision 1.3 2002/01/28 01:15:59 lampret |
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. |
// |
// Revision 1.2 2002/01/14 06:18:22 lampret |
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.10 2001/11/12 01:45:40 lampret |
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. |
// |
// Revision 1.9 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.8 2001/10/19 23:28:45 lampret |
// Fixed some synthesis warnings. Configured with caches and MMUs. |
// |
// Revision 1.7 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm |
// no message |
// |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
/or1200_cfgr.v
3,7 → 3,7
//// OR1200's VR, UPR and Configuration Registers //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://www.opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// According to OR1K architectural and OR1200 specifications. //// |
41,40 → 41,10
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: or1200_cfgr.v,v $ |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// No update |
// |
// Revision 1.4 2004/06/08 18:17:36 lampret |
// Non-functional changes. Coding style fixes. |
// |
// Revision 1.3 2002/03/29 15:16:54 lampret |
// Some of the warnings fixed. |
// |
// Revision 1.2 2002/01/14 06:18:22 lampret |
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.7 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.6 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm |
// no message |
// |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:21 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
/or1200_cpu.v
3,7 → 3,7
//// OR1200's CPU //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://www.opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, //// |
42,113 → 42,10
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: or1200_cpu.v,v $ |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// Major update: |
// Structure reordered and bugs fixed. |
// |
// Revision 1.16 2005/01/07 09:28:37 andreje |
// flag for l.cmov instruction added |
// |
// Revision 1.15 2004/05/09 19:49:04 lampret |
// Added some l.cust5 custom instructions as example |
// |
// Revision 1.14 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.12.4.2 2004/02/11 01:40:11 lampret |
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. |
// |
// Revision 1.12.4.1 2003/12/09 11:46:48 simons |
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. |
// |
// Revision 1.12 2002/09/07 05:42:02 lampret |
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. |
// |
// Revision 1.11 2002/08/28 01:44:25 lampret |
// Removed some commented RTL. Fixed SR/ESR flag bug. |
// |
// Revision 1.10 2002/07/14 22:17:17 lampret |
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. |
// |
// Revision 1.9 2002/03/29 16:29:37 lampret |
// Fixed some ports in instnatiations that were removed from the modules |
// |
// Revision 1.8 2002/03/29 15:16:54 lampret |
// Some of the warnings fixed. |
// |
// Revision 1.7 2002/02/11 04:33:17 lampret |
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. |
// |
// Revision 1.6 2002/02/01 19:56:54 lampret |
// Fixed combinational loops. |
// |
// Revision 1.5 2002/01/28 01:15:59 lampret |
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. |
// |
// Revision 1.4 2002/01/18 14:21:43 lampret |
// Fixed 'the NPC single-step fix'. |
// |
// Revision 1.3 2002/01/18 07:56:00 lampret |
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. |
// |
// Revision 1.2 2002/01/14 06:18:22 lampret |
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.19 2001/11/30 18:59:47 simons |
// *** empty log message *** |
// |
// Revision 1.18 2001/11/23 21:42:31 simons |
// Program counter divided to PPC and NPC. |
// |
// Revision 1.17 2001/11/23 08:38:51 lampret |
// Changed DSR/DRR behavior and exception detection. |
// |
// Revision 1.16 2001/11/20 00:57:22 lampret |
// Fixed width of du_except. |
// |
// Revision 1.15 2001/11/18 09:58:28 lampret |
// Fixed some l.trap typos. |
// |
// Revision 1.14 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
// Revision 1.13 2001/11/13 10:02:21 lampret |
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) |
// |
// Revision 1.12 2001/11/12 01:45:40 lampret |
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. |
// |
// Revision 1.11 2001/11/10 03:43:57 lampret |
// Fixed exceptions. |
// |
// Revision 1.10 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.9 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm |
// no message |
// |
// Revision 1.4 2001/08/17 08:01:19 lampret |
// IC enable/disable. |
// |
// Revision 1.3 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
248,8 → 145,8
input [24:0] du_dmr1; |
input du_hwbkpt; |
input du_hwbkpt_ls_r; |
output [12:0] du_except_trig; |
output [12:0] du_except_stop; |
output [13:0] du_except_trig; |
output [13:0] du_except_stop; |
output [dw-1:0] du_dat_cpu; |
output [dw-1:0] rf_dataw; |
output [dw-1:0] du_lsu_store_dat; |
334,6 → 231,7
wire [`OR1200_SEL_WIDTH-1:0] sel_a; |
wire [`OR1200_SEL_WIDTH-1:0] sel_b; |
wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; |
wire [`OR1200_FPUOP_WIDTH-1:0] fpu_op; |
wire [dw-1:0] rf_dataw; |
wire [dw-1:0] rf_dataa; |
wire [dw-1:0] rf_datab; |
346,6 → 244,7
wire [dw-1:0] alu_dataout; |
wire [dw-1:0] lsu_dataout; |
wire [dw-1:0] sprs_dataout; |
wire [dw-1:0] fpu_dataout; |
wire [31:0] ex_simm; |
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle; |
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type; |
360,7 → 259,10
wire flag; |
wire flagforw; |
wire flag_we; |
wire flagforw_alu; |
wire flag_we_alu; |
wire flagforw_fpu; |
wire flag_we_fpu; |
wire carry; |
wire cyforw; |
wire cy_we_alu; |
373,6 → 275,8
wire [31:0] epcr; |
wire [31:0] eear; |
wire [`OR1200_SR_WIDTH-1:0] esr; |
wire [`OR1200_FPCSR_WIDTH-1:0] fpcsr; |
wire fpcsr_we; |
wire sr_we; |
wire [`OR1200_SR_WIDTH-1:0] to_sr; |
wire [`OR1200_SR_WIDTH-1:0] sr; |
379,14 → 283,17
wire except_flushpipe; |
wire except_start; |
wire except_started; |
wire fpu_except_started; |
wire [31:0] wb_insn; |
wire sig_syscall; |
wire sig_trap; |
wire sig_fp; |
wire [31:0] spr_dat_cfgr; |
wire [31:0] spr_dat_rf; |
wire [31:0] spr_dat_npc; |
wire [31:0] spr_dat_ppc; |
wire [31:0] spr_dat_mac; |
wire [31:0] spr_dat_fpu; |
wire force_dslot_fetch; |
wire no_more_dslot; |
wire ex_void; |
399,8 → 306,8
wire [`OR1200_MACOP_WIDTH-1:0] mac_op; |
wire [31:0] mult_mac_result; |
wire mac_stall; |
wire [12:0] except_trig; |
wire [12:0] except_stop; |
wire [13:0] except_trig; |
wire [13:0] except_stop; |
wire genpc_refetch; |
wire rfe; |
wire lsu_unstall; |
476,7 → 383,8
// |
// FLAG write enable |
// |
assign flag_we = flag_we_alu && ~abort_mvspr; |
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu); |
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr; |
|
// |
// Instantiation of instruction fetch block |
569,6 → 477,7
.comp_op(comp_op), |
.rf_addrw(rf_addrw), |
.rfwb_op(rfwb_op), |
.fpu_op(fpu_op), |
.pc_we(pc_we), |
.wb_insn(wb_insn), |
.id_simm(id_simm), |
663,7 → 572,7
.cust5_op(cust5_op), |
.cust5_limm(cust5_limm), |
.result(alu_dataout), |
.flagforw(flagforw), |
.flagforw(flagforw_alu), |
.flag_we(flag_we_alu), |
.cyforw(cyforw), |
.cy_we(cy_we_alu), |
671,9 → 580,46
.carry(carry) |
); |
|
|
`ifdef OR1200_FPU_IMPLEMENTED |
|
// |
// Instantiation of CPU's ALU |
// FPU's exception is being dealt with |
// |
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT); |
|
// |
// Instantiation of FPU |
// |
or1200_fpu or1200_fpu( |
.clk(clk), |
.rst(rst), |
.ex_freeze(ex_freeze), |
.a(operand_a), |
.b(operand_b), |
.fpu_op(fpu_op), |
.result(fpu_dataout), |
.flagforw(flagforw_fpu), |
.flag_we(flag_we_fpu), |
.sig_fp(sig_fp), |
.except_started(fpu_except_started), |
.fpcsr_we(fpcsr_we), |
.fpcsr(fpcsr), |
.spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]), |
.spr_write(spr_we), |
.spr_addr(spr_addr), |
.spr_dat_i(spr_dat_cpu), |
.spr_dat_o(spr_dat_fpu) |
); |
`else |
assign sig_fp = 0; |
assign fpcsr = 0; |
`endif |
|
|
// |
// Instantiation of CPU's multiply unit |
// |
or1200_mult_mac or1200_mult_mac( |
.clk(clk), |
.rst(rst), |
743,6 → 689,10
.esr(esr), |
.except_started(except_started), |
|
.fpcsr(fpcsr), |
.fpcsr_we(fpcsr_we), |
.spr_dat_fpu(spr_dat_fpu), |
|
.sr_we(sr_we), |
.to_sr(to_sr), |
.sr(sr), |
798,6 → 748,7
.muxin_b(lsu_dataout), |
.muxin_c(sprs_dataout), |
.muxin_d(ex_pc), |
.muxin_e(fpu_dataout), |
.muxout(rf_dataw), |
.muxreg(wb_forw), |
.muxreg_valid(wbforw_valid) |
848,6 → 799,8
.sig_itlbmiss(except_itlbmiss), |
.sig_immufault(except_immufault), |
.sig_tick(sig_tick), |
.sig_fp(sig_fp), |
.fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]), |
.ex_branch_taken(ex_branch_taken), |
.icpu_ack_i(icpu_ack_i), |
.icpu_err_i(icpu_err_i), |
/or1200_sprs.v
3,7 → 3,7
//// OR1200's interface to SPRs //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://www.opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// Decoding of SPR addresses and access to SPRs //// |
41,74 → 41,10
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: or1200_sprs.v,v $ |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// Major update: |
// Structure reordered and bugs fixed. |
// |
// Revision 1.11 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.9.4.1 2003/12/17 13:43:38 simons |
// Exception prefix configuration changed. |
// |
// Revision 1.9 2002/09/07 05:42:02 lampret |
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. |
// |
// Revision 1.8 2002/08/28 01:44:25 lampret |
// Removed some commented RTL. Fixed SR/ESR flag bug. |
// |
// Revision 1.7 2002/03/29 15:16:56 lampret |
// Some of the warnings fixed. |
// |
// Revision 1.6 2002/03/11 01:26:57 lampret |
// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. |
// |
// Revision 1.5 2002/02/01 19:56:54 lampret |
// Fixed combinational loops. |
// |
// Revision 1.4 2002/01/23 07:52:36 lampret |
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. |
// |
// Revision 1.3 2002/01/19 09:27:49 lampret |
// SR[TEE] should be zero after reset. |
// |
// Revision 1.2 2002/01/18 07:56:00 lampret |
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.12 2001/11/23 21:42:31 simons |
// Program counter divided to PPC and NPC. |
// |
// Revision 1.11 2001/11/23 08:38:51 lampret |
// Changed DSR/DRR behavior and exception detection. |
// |
// Revision 1.10 2001/11/12 01:45:41 lampret |
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. |
// |
// Revision 1.9 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.8 2001/10/14 13:12:10 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm |
// no message |
// |
// Revision 1.3 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:21 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
126,6 → 62,9
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr, |
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac, |
boot_adr_sel_i, |
|
// Floating point control register and SPR input |
fpcsr, fpcsr_we, spr_dat_fpu |
|
// From/to other RISC units |
spr_dat_pic, spr_dat_tt, spr_dat_pm, |
179,6 → 118,10
input [31:0] spr_dat_mac; // Data from MAC |
input boot_adr_sel_i; |
|
input [`OR1200_FPCSR_WIDTH-1:0] fpcsr; // FPCSR |
output fpcsr_we; // Write enable FPCSR |
input [31:0] spr_dat_fpu; // Data from FPU |
|
// |
// To/from other RISC units |
// |
219,6 → 162,7
wire epcr_sel; // Select for EPCR0 |
wire eear_sel; // Select for EEAR0 |
wire esr_sel; // Select for ESR0 |
wire fpcsr_sel; // Select for FPCSR |
wire [31:0] sys_data; // Read data from system SPRs |
wire du_access; // Debug unit access |
reg [31:0] unqualified_cs; // Unqualified chip selects |
344,6 → 288,12
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR)); |
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR)); |
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR)); |
`ifdef OR1200_FPU_IMPLEMENTED |
assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_FPCSR)); |
`else |
assign fpcsr_sel = 0; |
`endif |
|
|
// |
// Write enables for system SPRs |
353,6 → 303,11
assign epcr_we = (spr_we && epcr_sel); |
assign eear_we = (spr_we && eear_sel); |
assign esr_we = (spr_we && esr_sel); |
`ifdef OR1200_FPU_IMPLEMENTED |
assign fpcsr_we = (spr_we && fpcsr_sel); |
`else |
assign fpcsr_we = 0; |
`endif |
|
// |
// Output from system SPRs |
364,6 → 319,10
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) | |
(epcr & {32{epcr_sel}}) | |
(eear & {32{eear_sel}}) | |
`ifdef OR1200_FPU_IMPLEMENTED |
({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} & |
{32{read_spr & fpcsr_sel}}) | |
`endif |
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}}); |
|
// |
414,6 → 373,9
// MTSPR/MFSPR interface |
// |
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or |
`ifdef OR1200_FPU_IMPLEMENTED |
spr_dat_fpu or |
`endif |
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin |
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case |
`OR1200_SPR_GROUP_SYS: |
430,6 → 392,10
to_wbmux = spr_dat_immu; |
`OR1200_SPR_GROUP_MAC: |
to_wbmux = spr_dat_mac; |
`ifdef OR1200_FPU_IMPLEMENTED |
`OR1200_SPR_GROUP_FPU: |
to_wbmux = spr_dat_fpu; |
`endif |
default: //`OR1200_SPR_GROUP_DU: |
to_wbmux = spr_dat_du; |
endcase |
/or1200_fpu.v
0,0 → 1,281
////////////////////////////////////////////////////////////////////// |
//// //// |
//// OR1200's FPU Wrapper //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// Wrapper for floating point unit. //// |
//// Interface based on MULT/MAC unit. //// |
//// //// |
//// To Do: //// |
//// - remainder instruction implementation //// |
//// - registering in/around compare unit //// |
//// //// |
//// Author(s): //// |
//// - Julius Baxter, julius@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "or1200_defines.v" |
|
module or1200_fpu( |
// Clock and reset |
clk, rst, |
|
// FPU interface |
ex_freeze, a, b, fpu_op, result, |
|
// Flag controls |
flagforw, flag_we, |
|
// Exception signal |
sig_fp, except_started, |
|
// SPR interface |
fpcsr_we, fpcsr, |
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o |
); |
|
parameter width = `OR1200_OPERAND_WIDTH; |
|
// |
// I/O |
// |
|
// |
// Clock and reset |
// |
input clk; |
input rst; |
|
// |
// FPU interface |
// |
input ex_freeze; |
input [width-1:0] a; |
input [width-1:0] b; |
input [`OR1200_FPUOP_WIDTH-1:0] fpu_op; |
output [width-1:0] result; |
|
// |
// Flag signals |
// |
output flagforw; |
output flag_we; |
|
|
// |
// FPCSR interface |
// |
input fpcsr_we; |
output [`OR1200_FPCSR_WIDTH-1:0] fpcsr; |
|
// |
// Exception signal |
// |
output sig_fp; |
input except_started; |
|
|
// |
// SPR interface |
// |
input spr_cs; |
input spr_write; |
input [31:0] spr_addr; |
input [31:0] spr_dat_i; |
output [31:0] spr_dat_o; |
|
// |
// Internals |
// |
reg [2:0] fpu_op_count; |
reg [`OR1200_FPUOP_WIDTH:0] fpu_op_r; |
reg [`OR1200_FPCSR_WIDTH-1:0] fpcsr_r; |
reg fpu_latch_operand; |
wire fpu_check_op; |
wire fpu_latch_op; |
wire inf, snan, qnan, ine, overflow, |
underflow, zero, div_by_zero; |
wire fpu_op_is_comp, fpu_op_r_is_comp; |
wire altb, blta, aeqb, cmp_inf, cmp_zero, |
unordered ; |
reg flag; |
|
assign fpcsr = fpcsr_r; |
|
assign sig_fp = fpcsr_r[`OR1200_FPCSR_FPEE] |
& (|fpcsr_r[`OR1200_FPCSR_WIDTH-1:`OR1200_FPCSR_OVF]); |
|
// Generate signals to latch fpu_op from decode instruction, then latch |
// operands when they appear during execute stage |
|
assign fpu_check_op = (!ex_freeze & fpu_op[`OR1200_FPUOP_WIDTH-1]); |
|
assign fpu_op_is_comp = fpu_op[3]; |
|
assign fpu_op_r_is_comp = fpu_op_r[3]; |
|
assign fpu_latch_op = fpu_check_op & !fpu_op_is_comp; |
|
always @(posedge clk) |
fpu_latch_operand <= fpu_check_op & !fpu_op_is_comp; |
|
// Register fpu_op on comparisons, clear otherwise, remove top bit |
always @(posedge clk) |
fpu_op_r <= (fpu_check_op & fpu_op_is_comp) ? |
{1'b0,fpu_op[`OR1200_FPUOP_WIDTH-2:0]} : !ex_freeze ? |
0 : fpu_op_r; |
|
// |
// Counter for each FPU operation |
// Loaded at start, counts down |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
fpu_op_count <= 0; |
else |
if (|fpu_op_count) |
fpu_op_count <= fpu_op_count - 1; |
else if(fpu_check_op) |
fpu_op_count <= 5; |
end |
|
// |
// FPCSR register |
// |
always @(posedge clk or posedge rst) begin |
if (rst) |
fpcsr_r <= 0; |
else |
begin |
if (fpcsr_we) |
fpcsr_r <= b[`OR1200_FPCSR_WIDTH-1:0]; |
else if (fpu_op_count == 1) |
begin |
fpcsr_r[`OR1200_FPCSR_OVF] <= overflow; |
fpcsr_r[`OR1200_FPCSR_UNF] <= underflow; |
fpcsr_r[`OR1200_FPCSR_SNF] <= snan; |
fpcsr_r[`OR1200_FPCSR_QNF] <= qnan; |
fpcsr_r[`OR1200_FPCSR_ZF] <= zero | |
(cmp_zero & fpu_op_r_is_comp); |
fpcsr_r[`OR1200_FPCSR_IXF] <= ine; |
fpcsr_r[`OR1200_FPCSR_IVF] <= 0; // Not used by this FPU |
fpcsr_r[`OR1200_FPCSR_INF] <= inf | |
(cmp_inf & fpu_op_r_is_comp); |
fpcsr_r[`OR1200_FPCSR_DZF] <= div_by_zero; |
end // if (fpu_op_count == 1) |
if (except_started) |
fpcsr_r[`OR1200_FPCSR_FPEE] <= 0; |
end // else: !if(rst) |
end // always @ (posedge clk or posedge rst) |
|
// |
// Comparison flag generation |
// |
always@(posedge clk) |
begin |
if (fpu_op_r_is_comp) |
begin |
case(fpu_op_r) |
`OR1200_FPCOP_SFEQ: begin |
flag <= aeqb; |
end |
`OR1200_FPCOP_SFNE: begin |
flag <= !aeqb; |
end |
`OR1200_FPCOP_SFGT: begin |
flag <= blta & !aeqb; |
end |
`OR1200_FPCOP_SFGE: begin |
flag <= blta | aeqb; |
end |
`OR1200_FPCOP_SFLT: begin |
flag <= altb & !aeqb; |
end |
`OR1200_FPCOP_SFLE: begin |
flag <= altb | aeqb; |
end |
default: begin |
flag <= 0; |
end |
endcase // case (fpu_op_r) |
end // if (fpu_op_r_is_comp) |
else |
flag <= 0; |
end // always@ (posedge clk) |
|
assign flagforw = flag; |
|
// Determine here where we do the write, ie how much we pipeline the |
// comparison |
assign flag_we = fpu_op_r_is_comp & (fpu_op_count == 2); |
|
// FP arithmetic module |
fpu fpu0 |
( |
.clk(clk), |
.rmode(fpcsr_r[`OR1200_FPCSR_RM]), |
.fpu_op(fpu_op[2:0]), |
.opa(a), |
.opb(b), |
.out(result), |
.latch_operand(fpu_latch_operand), |
.latch_op(fpu_latch_op), |
.inf(inf), |
.snan(snan), |
.qnan(qnan), |
.ine(ine), |
.overflow(overflow), |
.underflow(underflow), |
.zero(zero), |
.div_by_zero(div_by_zero) |
); |
|
// FP comparator |
fcmp fcmp0 |
( |
.opa(a), |
.opb(b), |
.unordered(unordered), |
// I am convinced the comparison logic is wrong way around in this |
// module, simplest to swap them on output -- julius |
|
.altb(blta), |
.blta(altb), |
.aeqb(aeqb), |
.inf(cmp_inf), |
.zero(cmp_zero)); |
|
|
endmodule // or1200_fpu |
/or1200_ctrl.v
3,7 → 3,7
//// OR1200's Instruction decode //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://www.opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// Majority of instruction decoding is performed here. //// |
41,89 → 41,11
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: or1200_ctrl.v,v $ |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// Major update: |
// Structure reordered and bugs fixed. |
// |
// Revision 1.13 2005/01/13 11:03:43 phoenix |
// revert to the old l.sfxxi behavior |
// |
// Revision 1.12 2005/01/07 09:31:07 andreje |
// sign/zero extension for l.sfxxi instructions corrected |
// |
// Revision 1.11 2004/06/08 18:17:36 lampret |
// Non-functional changes. Coding style fixes. |
// |
// Revision 1.10 2004/05/09 19:49:04 lampret |
// Added some l.cust5 custom instructions as example |
// |
// Revision 1.9 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.8.4.1 2004/02/11 01:40:11 lampret |
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. |
// |
// Revision 1.8 2003/04/24 00:16:07 lampret |
// No functional changes. Added defines to disable implementation of multiplier/MAC |
// |
// Revision 1.7 2002/09/07 05:42:02 lampret |
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. |
// |
// Revision 1.6 2002/03/29 15:16:54 lampret |
// Some of the warnings fixed. |
// |
// Revision 1.5 2002/02/01 19:56:54 lampret |
// Fixed combinational loops. |
// |
// Revision 1.4 2002/01/28 01:15:59 lampret |
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. |
// |
// Revision 1.3 2002/01/18 14:21:43 lampret |
// Fixed 'the NPC single-step fix'. |
// |
// Revision 1.2 2002/01/14 06:18:22 lampret |
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.14 2001/11/30 18:59:17 simons |
// force_dslot_fetch does not work - allways zero. |
// |
// Revision 1.13 2001/11/20 18:46:15 simons |
// Break point bug fixed |
// |
// Revision 1.12 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
// Revision 1.11 2001/11/13 10:02:21 lampret |
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) |
// |
// Revision 1.10 2001/11/12 01:45:40 lampret |
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports. |
// |
// Revision 1.9 2001/11/10 03:43:57 lampret |
// Fixed exceptions. |
// |
// Revision 1.8 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.7 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm |
// no message |
// |
// Revision 1.2 2001/08/13 03:36:20 lampret |
// Added cfg regs. Moved all defines into one defines.v file. More cleanup. |
// |
// Revision 1.1 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
130,22 → 52,27
// synopsys translate_on |
`include "or1200_defines.v" |
|
module or1200_ctrl( |
// Clock and reset |
clk, rst, |
module or1200_ctrl |
( |
// Clock and reset |
clk, rst, |
|
// Internal i/f |
except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe, |
wb_flushpipe, |
id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr, |
id_branch_op, ex_branch_op, ex_branch_taken, pc_we, |
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, |
rf_addrw, rfwb_op, fpu_op, |
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a, |
sel_b, id_lsu_op, |
cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt, |
multicycle, wbforw_valid, sig_syscall, sig_trap, |
force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read, |
ex_spr_write, |
id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal |
); |
|
// Internal i/f |
except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe, wb_flushpipe, |
id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr, |
id_branch_op, ex_branch_op, ex_branch_taken, pc_we, |
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op, |
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a, sel_b, id_lsu_op, |
cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt, |
multicycle, wbforw_valid, sig_syscall, sig_trap, |
force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read, ex_spr_write, |
id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal |
); |
|
// |
// I/O |
// |
176,6 → 103,7
output [`OR1200_MACOP_WIDTH-1:0] mac_op; |
output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; |
output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; |
output [`OR1200_FPUOP_WIDTH-1:0] fpu_op; |
input pc_we; |
output [31:0] wb_insn; |
output [31:2] id_branch_addrtarget; |
516,6 → 444,12
|
`OR1200_OR32_MULI: |
multicycle = 2'h3; |
|
`ifdef OR1200_FPU_IMPLEMENTED |
`OR1200_OR32_FLOAT: |
multicycle = `OR1200_FPUOP_CYCLES; |
`endif |
|
|
// Single cycle instructions |
default: begin |
666,7 → 600,11
`OR1200_OR32_CUST5: |
sel_imm <= #1 1'b0; |
`endif |
|
`ifdef OR1200_FPU_IMPLEMENTED |
// FPU instructions |
`OR1200_OR32_FLOAT: |
sel_imm <= #1 1'b0; |
`endif |
// l.nop |
`OR1200_OR32_NOP: |
sel_imm <= #1 1'b0; |
733,6 → 671,11
`endif |
`OR1200_OR32_NOP: |
except_illegal <= #1 1'b0; |
`ifdef OR1200_FPU_IMPLEMENTED |
`OR1200_OR32_FLOAT: |
// Check it's not a double precision instruction |
except_illegal <= #1 id_insn[`OR1200_FPUOP_DOUBLE_BIT]; |
`endif |
|
`OR1200_OR32_ALU: |
except_illegal <= #1 1'b0 |
1020,7 → 963,11
`OR1200_OR32_CUST5: |
rfwb_op <= #1 `OR1200_RFWBOP_ALU; |
`endif |
|
`ifdef OR1200_FPU_IMPLEMENTED |
// FPU instructions, lf.XXX.s, except sfxx |
`OR1200_OR32_FLOAT: |
rfwb_op <= #1 {`OR1200_RFWBOP_FPU,!id_insn[3]}; |
`endif |
// Instructions w/o register-file write-back |
default: |
rfwb_op <= #1 `OR1200_RFWBOP_NOP; |
1145,7 → 1092,17
comp_op <= #1 id_insn[24:21]; |
end |
|
`ifdef OR1200_FPU_IMPLEMENTED |
// |
// Decode of FPU ops |
// |
assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT), id_insn[`OR1200_FPUOP_WIDTH-2:0]}; |
`else |
assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}}; |
`endif |
|
|
// |
// Decode of l.sys |
// |
always @(posedge clk or posedge rst) begin |
/or1200_du.v
3,7 → 3,7
//// OR1200's Debug Unit //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://www.opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// Basic OR1200 debug unit. //// |
41,83 → 41,11
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: or1200_du.v,v $ |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// Minor update: |
// Bugs fixed. |
// |
// Revision 1.12 2005/10/19 11:37:56 jcastillo |
// Added support for RAMB16 Xilinx4/Spartan3 primitives |
// |
// Revision 1.11 2005/01/07 09:35:08 andreje |
// du_hwbkpt disabled when debug unit not implemented |
// |
// Revision 1.10 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.9.4.4 2004/02/11 01:40:11 lampret |
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. |
// |
// Revision 1.9.4.3 2004/01/18 10:08:00 simons |
// Error fixed. |
// |
// Revision 1.9.4.2 2004/01/17 21:14:14 simons |
// Errors fixed. |
// |
// Revision 1.9.4.1 2004/01/15 06:46:38 markom |
// interface to debug changed; no more opselect; stb-ack protocol |
// |
// Revision 1.9 2003/01/22 03:23:47 lampret |
// Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs] |
// |
// Revision 1.8 2002/09/08 19:31:52 lampret |
// Fixed a typo, reported by Taylor Su. |
// |
// Revision 1.7 2002/07/14 22:17:17 lampret |
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. |
// |
// Revision 1.6 2002/03/14 00:30:24 lampret |
// Added alternative for critical path in DU. |
// |
// Revision 1.5 2002/02/11 04:33:17 lampret |
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. |
// |
// Revision 1.4 2002/01/28 01:16:00 lampret |
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. |
// |
// Revision 1.3 2002/01/18 07:56:00 lampret |
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. |
// |
// Revision 1.2 2002/01/14 06:18:22 lampret |
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.12 2001/11/30 18:58:00 simons |
// Trap insn couses break after exits ex_insn. |
// |
// Revision 1.11 2001/11/23 08:38:51 lampret |
// Changed DSR/DRR behavior and exception detection. |
// |
// Revision 1.10 2001/11/20 21:25:44 lampret |
// Fixed dbg_is_o assignment width. |
// |
// Revision 1.9 2001/11/20 18:46:14 simons |
// Break point bug fixed |
// |
// Revision 1.8 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
// Revision 1.7 2001/10/21 18:09:53 lampret |
// Fixed sensitivity list. |
// |
// Revision 1.6 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
176,7 → 104,7
output [dw-1:0] du_dat_o; // Debug Unit Data Out |
output du_read; // Debug Unit Read Enable |
output du_write; // Debug Unit Write Enable |
input [12:0] du_except_stop; // Exception masked by DSR |
input [13:0] du_except_stop; // Exception masked by DSR |
output du_hwbkpt; // Cause trap exception (HW Breakpoints) |
input spr_cs; // SPR Chip Select |
input spr_write; // SPR Read/Write |
604,50 → 532,49
// |
// Decode started exception |
// |
// du_except_stop comes from or1200_except |
// |
always @(du_except_stop) begin |
except_stop = 14'b0000_0000_0000; |
except_stop = 14'b00_0000_0000_0000; |
casex (du_except_stop) |
13'b1_xxxx_xxxx_xxxx: begin |
14'b1x_xxxx_xxxx_xxxx: |
except_stop[`OR1200_DU_DRR_TTE] = 1'b1; |
end |
13'b0_1xxx_xxxx_xxxx: begin |
14'b01_xxxx_xxxx_xxxx: begin |
except_stop[`OR1200_DU_DRR_IE] = 1'b1; |
end |
13'b0_01xx_xxxx_xxxx: begin |
14'b00_1xxx_xxxx_xxxx: begin |
except_stop[`OR1200_DU_DRR_IME] = 1'b1; |
end |
13'b0_001x_xxxx_xxxx: begin |
14'b00_01xx_xxxx_xxxx: |
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1; |
end |
13'b0_0001_xxxx_xxxx: begin |
14'b00_001x_xxxx_xxxx: begin |
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1; |
end |
13'b0_0000_1xxx_xxxx: begin |
14'b00_0001_xxxx_xxxx: |
except_stop[`OR1200_DU_DRR_IIE] = 1'b1; |
end |
13'b0_0000_01xx_xxxx: begin |
14'b00_0000_1xxx_xxxx: begin |
except_stop[`OR1200_DU_DRR_AE] = 1'b1; |
end |
13'b0_0000_001x_xxxx: begin |
14'b00_0000_01xx_xxxx: begin |
except_stop[`OR1200_DU_DRR_DME] = 1'b1; |
end |
13'b0_0000_0001_xxxx: begin |
14'b00_0000_001x_xxxx: |
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1; |
end |
13'b0_0000_0000_1xxx: begin |
14'b00_0000_0001_xxxx: |
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1; |
end |
13'b0_0000_0000_01xx: begin |
14'b00_0000_0000_1xxx: begin |
except_stop[`OR1200_DU_DRR_RE] = 1'b1; |
end |
13'b0_0000_0000_001x: begin |
14'b00_0000_0000_01xx: begin |
except_stop[`OR1200_DU_DRR_TE] = 1'b1; |
end |
13'b0_0000_0000_0001: begin |
14'b00_0000_0000_001x: begin |
except_stop[`OR1200_DU_DRR_FPE] = 1'b1; |
end |
14'b00_0000_0000_0001: |
except_stop[`OR1200_DU_DRR_SCE] = 1'b1; |
end |
default: |
except_stop = 14'b0000_0000_0000; |
except_stop = 14'b00_0000_0000_0000; |
endcase |
end |
|
/or1200_amultp2_32x32.v
3,7 → 3,7
//// OR1200's 32x32 multiply for ASIC //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://www.opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// 32x32 multiply for ASIC //// |
41,37 → 41,9
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: or1200_amultp2_32x32.v,v $ |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// No update |
// |
// Revision 1.2 2003/04/07 01:23:31 lampret |
// Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.9 2001/12/04 05:02:35 lampret |
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 |
// |
// Revision 1.8 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.7 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm |
// no message |
// |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
/or1200_wbmux.v
3,7 → 3,7
//// OR1200's Write-back Mux //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://www.opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// CPU's write-back stage of the pipeline //// |
41,37 → 41,10
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: or1200_wbmux.v,v $ |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// No update |
// |
// Revision 1.3 2004/06/08 18:17:36 lampret |
// Non-functional changes. Coding style fixes. |
// |
// Revision 1.2 2002/03/29 15:16:56 lampret |
// Some of the warnings fixed. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.8 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.7 2001/10/14 13:12:10 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm |
// no message |
// |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:23 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
84,7 → 57,7
|
// Internal i/f |
wb_freeze, rfwb_op, |
muxin_a, muxin_b, muxin_c, muxin_d, |
muxin_a, muxin_b, muxin_c, muxin_d, muxin_e, |
muxout, muxreg, muxreg_valid |
); |
|
109,6 → 82,7
input [width-1:0] muxin_b; |
input [width-1:0] muxin_c; |
input [width-1:0] muxin_d; |
input [width-1:0] muxin_e; |
output [width-1:0] muxout; |
output [width-1:0] muxreg; |
output muxreg_valid; |
137,14 → 111,14
// |
// Write-back multiplexer |
// |
always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin |
always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin |
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES |
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux |
`else |
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case |
`endif |
2'b00: muxout = muxin_a; |
2'b01: begin |
`OR1200_RFWBOP_ALU: muxout = muxin_a; |
`OR1200_RFWBOP_LSU: begin |
muxout = muxin_b; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
152,7 → 126,7
// synopsys translate_on |
`endif |
end |
2'b10: begin |
`OR1200_RFWBOP_SPRS: begin |
muxout = muxin_c; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
160,7 → 134,7
// synopsys translate_on |
`endif |
end |
2'b11: begin |
`OR1200_RFWBOP_LR: begin |
muxout = muxin_d + 32'h8; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
168,6 → 142,16
// synopsys translate_on |
`endif |
end |
`ifdef OR1200_FPU_IMPLEMENTED |
`OR1200_RFWBOP_FPU : begin |
muxout = muxin_e; |
`ifdef OR1200_VERBOSE |
// synopsys translate_off |
$display(" WBMUX: muxin_e %h", muxin_e); |
// synopsys translate_on |
`endif |
end |
`endif |
endcase |
end |
|
/or1200_except.v
3,7 → 3,7
//// OR1200's Exception logic //// |
//// //// |
//// This file is part of the OpenRISC 1200 project //// |
//// http://www.opencores.org/cores/or1k/ //// |
//// http://www.opencores.org/project,or1k //// |
//// //// |
//// Description //// |
//// Handles all OR1K exceptions inside CPU block. //// |
41,104 → 41,11
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// $Log: or1200_except.v,v $ |
// |
// Revision 2.0 2010/06/30 11:00:00 ORSoC |
// Major update: |
// Structure reordered and bugs fixed. |
// |
// Revision 1.17 2004/06/08 18:17:36 lampret |
// Non-functional changes. Coding style fixes. |
// |
// Revision 1.16 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.15.4.1 2004/02/11 01:40:11 lampret |
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. |
// |
// Revision 1.15 2003/04/20 22:23:57 lampret |
// No functional change. Only added customization for exception vectors. |
// |
// Revision 1.14 2002/09/03 22:28:21 lampret |
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. |
// |
// Revision 1.13 2002/08/28 01:44:25 lampret |
// Removed some commented RTL. Fixed SR/ESR flag bug. |
// |
// Revision 1.12 2002/08/22 02:16:45 lampret |
// Fixed IMMU bug. |
// |
// Revision 1.11 2002/08/18 19:54:28 lampret |
// Added store buffer. |
// |
// Revision 1.10 2002/07/14 22:17:17 lampret |
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. |
// |
// Revision 1.9 2002/02/11 04:33:17 lampret |
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. |
// |
// Revision 1.8 2002/01/28 01:16:00 lampret |
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. |
// |
// Revision 1.7 2002/01/23 07:52:36 lampret |
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. |
// |
// Revision 1.6 2002/01/18 14:21:43 lampret |
// Fixed 'the NPC single-step fix'. |
// |
// Revision 1.5 2002/01/18 07:56:00 lampret |
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. |
// |
// Revision 1.4 2002/01/14 21:11:50 lampret |
// Changed alignment exception EPCR. Not tested yet. |
// |
// Revision 1.3 2002/01/14 19:09:57 lampret |
// Fixed order of syscall and range exceptions. |
// |
// Revision 1.2 2002/01/14 06:18:22 lampret |
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.15 2001/11/27 23:13:11 lampret |
// Fixed except_stop width and fixed EX PC for 1400444f no-ops. |
// |
// Revision 1.14 2001/11/23 08:38:51 lampret |
// Changed DSR/DRR behavior and exception detection. |
// |
// Revision 1.13 2001/11/20 18:46:15 simons |
// Break point bug fixed |
// |
// Revision 1.12 2001/11/18 09:58:28 lampret |
// Fixed some l.trap typos. |
// |
// Revision 1.11 2001/11/18 08:36:28 lampret |
// For GDB changed single stepping and disabled trap exception. |
// |
// Revision 1.10 2001/11/13 10:02:21 lampret |
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc) |
// |
// Revision 1.9 2001/11/10 03:43:57 lampret |
// Fixed exceptions. |
// |
// Revision 1.8 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.7 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm |
// no message |
// |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
157,21 → 64,22
// Exception recognition and sequencing |
// |
|
module or1200_except( |
// Clock and reset |
clk, rst, |
|
// Internal i/f |
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault, |
sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick, |
ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall, |
if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe, extend_flush, except_flushpipe, except_type, except_start, |
except_started, except_stop, except_trig, ex_void, abort_mvspr, branch_op, |
spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear, |
du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, |
esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i |
|
|
module or1200_except |
( |
// Clock and reset |
clk, rst, |
|
// Internal i/f |
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, |
sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, |
sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, |
if_stall, if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe, |
extend_flush, except_flushpipe, except_type, except_start, except_started, |
except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc, |
spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear, |
du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr, |
abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee |
|
); |
|
// |
192,6 → 100,8
input sig_itlbmiss; |
input sig_immufault; |
input sig_tick; |
input sig_fp; |
input fpcsr_fpee; |
input ex_branch_taken; |
input genpc_freeze; |
input id_freeze; |
225,8 → 135,8
output [`OR1200_EXCEPT_WIDTH-1:0] except_type; |
output except_start; |
output except_started; |
output [12:0] except_stop; |
output [12:0] except_trig; |
output [13:0] except_stop; |
output [13:0] except_trig; |
input ex_void; |
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; |
output [31:0] spr_dat_ppc; |
264,6 → 174,8
reg [2:0] delayed_tee; |
wire int_pending; |
wire tick_pending; |
wire fp_pending; |
|
reg trace_trap ; |
reg ex_freeze_prev; |
reg sr_ted_prev; |
279,12 → 191,32
// Simple combinatorial logic |
// |
assign except_started = extend_flush & except_start; |
|
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush; |
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] | (sr_we & to_sr[`OR1200_SR_IEE])) & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]); |
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] | (sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val & delayed_tee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]); |
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te); // Abort write into RF by load & other instructions |
assign abort_mvspr = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te) ; // abort spr read/writes |
|
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] | |
(sr_we & to_sr[`OR1200_SR_IEE])) |
& id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken |
& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]); |
|
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] | |
(sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val |
& delayed_tee[2] & ~ex_freeze & ~ex_branch_taken |
& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]); |
|
assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken |
& ~ex_dslot; |
|
// Abort write into RF by load & other instructions |
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | |
sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val |
& !sr_ted & !dsr_te); |
|
// abort spr read/writes |
assign abort_mvspr = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val |
& !sr_ted & !dsr_te) ; |
assign spr_dat_ppc = wb_pc; |
|
assign spr_dat_npc = ex_void ? id_pc : ex_pc; |
|
// |
294,17 → 226,19
ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME], |
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE], |
ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE], |
sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE], |
sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE], |
sig_align & ~du_dsr[`OR1200_DU_DSR_AE], |
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME], |
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME], |
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE], |
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze, |
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE], |
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE], |
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze, |
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE], |
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE], |
sig_range & ~du_dsr[`OR1200_DU_DSR_RE], |
int_pending & ~du_dsr[`OR1200_DU_DSR_IE], |
tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE] |
fp_pending & ~du_dsr[`OR1200_DU_DSR_FPE], |
int_pending & ~du_dsr[`OR1200_DU_DSR_IE], |
tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE] |
}; |
|
wire trace_cond = !ex_freeze && !ex_void && (1'b0 |
`ifdef OR1200_DU_DMR1_ST |
|| dmr1_st |
327,6 → 261,7
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE], |
sig_range & du_dsr[`OR1200_DU_DSR_RE], |
sig_trap & du_dsr[`OR1200_DU_DSR_TE], |
fp_pending & du_dsr[`OR1200_DU_DSR_FPE], |
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze |
}; |
|
417,7 → 352,7
if (rst) begin |
ex_dslot <= #1 1'b0; |
ex_pc <= #1 32'd0; |
ex_pc_val <= #1 1'b0 ; |
ex_pc_val <= #1 1'b0 ; |
ex_exceptflags <= #1 3'b000; |
delayed1_ex_dslot <= #1 1'b0; |
delayed2_ex_dslot <= #1 1'b0; |
424,7 → 359,7
end |
else if (ex_flushpipe) begin |
ex_dslot <= #1 1'b0; |
ex_pc_val <= #1 1'b0 ; |
ex_pc_val <= #1 1'b0 ; |
ex_exceptflags <= #1 3'b000; |
delayed1_ex_dslot <= #1 1'b0; |
delayed2_ex_dslot <= #1 1'b0; |
432,7 → 367,7
else if (!ex_freeze & id_freeze) begin |
ex_dslot <= #1 1'b0; |
ex_pc <= #1 id_pc; |
ex_pc_val <= #1 id_pc_val ; |
ex_pc_val <= #1 id_pc_val ; |
ex_exceptflags <= #1 3'b000; |
delayed1_ex_dslot <= #1 ex_dslot; |
delayed2_ex_dslot <= #1 delayed1_ex_dslot; |
440,7 → 375,7
else if (!ex_freeze) begin |
ex_dslot <= #1 ex_branch_taken; |
ex_pc <= #1 id_pc; |
ex_pc_val <= #1 id_pc_val ; |
ex_pc_val <= #1 id_pc_val ; |
ex_exceptflags <= #1 id_exceptflags; |
delayed1_ex_dslot <= #1 ex_dslot; |
delayed2_ex_dslot <= #1 delayed1_ex_dslot; |
474,168 → 409,198
// except_type signals which exception handler we start fetching in: |
// 1. Asserted in next clock cycle after exception is recognized |
// |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
state <= #1 `OR1200_EXCEPTFSM_IDLE; |
except_type <= #1 `OR1200_EXCEPT_NONE; |
extend_flush <= #1 1'b0; |
epcr <= #1 32'b0; |
eear <= #1 32'b0; |
esr <= #1 {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1}; |
extend_flush_last <= #1 1'b0; |
end |
else begin |
always @(posedge clk or posedge rst) begin |
if (rst) begin |
state <= #1 `OR1200_EXCEPTFSM_IDLE; |
except_type <= #1 `OR1200_EXCEPT_NONE; |
extend_flush <= #1 1'b0; |
epcr <= #1 32'b0; |
eear <= #1 32'b0; |
esr <= #1 {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1}; |
extend_flush_last <= #1 1'b0; |
end |
else begin |
`ifdef OR1200_CASE_DEFAULT |
case (state) // synopsys parallel_case |
case (state) // synopsys parallel_case |
`else |
case (state) // synopsys full_case parallel_case |
case (state) // synopsys full_case parallel_case |
`endif |
`OR1200_EXCEPTFSM_IDLE: |
if (except_flushpipe) begin |
state <= #1 `OR1200_EXCEPTFSM_FLU1; |
extend_flush <= #1 1'b1; |
esr <= #1 sr_we ? to_sr : sr; |
casex (except_trig) |
`OR1200_EXCEPTFSM_IDLE: |
if (except_flushpipe) begin |
state <= #1 `OR1200_EXCEPTFSM_FLU1; |
extend_flush <= #1 1'b1; |
esr <= #1 sr_we ? to_sr : sr; |
casex (except_trig) |
`ifdef OR1200_EXCEPT_ITLBMISS |
13'b1_xxxx_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_ITLBMISS; |
eear <= #1 ex_dslot ? ex_pc : ex_pc; |
epcr <= #1 ex_dslot ? wb_pc : ex_pc; |
end |
14'b1x_xxxx_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_ITLBMISS; |
eear <= #1 ex_dslot ? |
ex_pc : ex_pc; |
epcr <= #1 ex_dslot ? |
wb_pc : ex_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_IPF |
13'b0_1xxx_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_IPF; |
eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; |
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; |
end |
14'b01_xxxx_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_IPF; |
eear <= #1 ex_dslot ? |
ex_pc : delayed1_ex_dslot ? |
id_pc : delayed2_ex_dslot ? |
id_pc : id_pc; |
epcr <= #1 ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
id_pc : delayed2_ex_dslot ? |
id_pc : id_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_BUSERR |
13'b0_01xx_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_BUSERR; |
eear <= #1 ex_dslot ? wb_pc : ex_pc; |
epcr <= #1 ex_dslot ? wb_pc : ex_pc; |
end |
14'b00_1xxx_xxxx_xxxx: begin // Insn. Bus Error |
except_type <= #1 `OR1200_EXCEPT_BUSERR; |
eear <= #1 ex_dslot ? |
wb_pc : ex_pc; |
epcr <= #1 ex_dslot ? |
wb_pc : ex_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_ILLEGAL |
13'b0_001x_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_ILLEGAL; |
eear <= #1 ex_pc; |
epcr <= #1 ex_dslot ? wb_pc : ex_pc; |
end |
14'b00_01xx_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_ILLEGAL; |
eear <= #1 ex_pc; |
epcr <= #1 ex_dslot ? |
wb_pc : ex_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_ALIGN |
13'b0_0001_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_ALIGN; |
eear <= #1 lsu_addr; |
epcr <= #1 ex_dslot ? wb_pc : ex_pc; |
end |
14'b00_001x_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_ALIGN; |
eear <= #1 lsu_addr; |
epcr <= #1 ex_dslot ? |
wb_pc : ex_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_DTLBMISS |
13'b0_0000_1xxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_DTLBMISS; |
eear <= #1 lsu_addr; |
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc; |
end |
14'b00_0001_xxxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_DTLBMISS; |
eear <= #1 lsu_addr; |
epcr <= #1 ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
dl_pc : ex_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_01xx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_TRAP; |
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : ex_pc; |
end |
`ifdef OR1200_EXCEPT_TRAP |
14'b00_0000_1xxx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_TRAP; |
epcr <= #1 ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
id_pc : ex_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_SYSCALL |
13'b0_0000_001x_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_SYSCALL; |
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; |
end |
14'b00_0000_01xx_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_SYSCALL; |
epcr <= #1 ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
id_pc : delayed2_ex_dslot ? |
id_pc : id_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_DPF |
13'b0_0000_0001_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_DPF; |
eear <= #1 lsu_addr; |
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc; |
end |
14'b00_0000_001x_xxxx: begin |
except_type <= #1 `OR1200_EXCEPT_DPF; |
eear <= #1 lsu_addr; |
epcr <= #1 ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
dl_pc : ex_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_BUSERR |
13'b0_0000_0000_1xxx: begin // Data Bus Error |
except_type <= #1 `OR1200_EXCEPT_BUSERR; |
eear <= #1 lsu_addr; |
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc; |
end |
14'b00_0000_0001_xxxx: begin // Data Bus Error |
except_type <= #1 `OR1200_EXCEPT_BUSERR; |
eear <= #1 lsu_addr; |
epcr <= #1 ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
dl_pc : ex_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_RANGE |
13'b0_0000_0000_01xx: begin |
except_type <= #1 `OR1200_EXCEPT_RANGE; |
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; |
end |
14'b00_0000_0000_1xxx: begin |
except_type <= #1 `OR1200_EXCEPT_RANGE; |
epcr <= #1 ex_dslot ? |
wb_pc : delayed1_ex_dslot ? |
id_pc : delayed2_ex_dslot ? |
id_pc : id_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_FLOAT |
14'b00_0000_0000_01xx: begin |
except_type <= #1 `OR1200_EXCEPT_FLOAT; |
epcr <= #1 id_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_INT |
13'b0_0000_0000_001x: begin |
except_type <= #1 `OR1200_EXCEPT_INT; |
epcr <= #1 id_pc; |
//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; |
end |
14'b00_0000_0000_001x: begin |
except_type <= #1 `OR1200_EXCEPT_INT; |
epcr <= #1 id_pc; |
end |
`endif |
`ifdef OR1200_EXCEPT_TICK |
13'b0_0000_0000_0001: begin |
except_type <= #1 `OR1200_EXCEPT_TICK; |
epcr <= #1 id_pc; |
//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc; |
end |
14'b00_0000_0000_0001: begin |
except_type <= #1 `OR1200_EXCEPT_TICK; |
epcr <= #1 id_pc; |
end |
`endif |
|
default: |
except_type <= #1 `OR1200_EXCEPT_NONE; |
endcase |
end |
else if (pc_we) begin |
state <= #1 `OR1200_EXCEPTFSM_FLU1; |
extend_flush <= #1 1'b1; |
end |
else begin |
if (epcr_we) |
epcr <= #1 datain; |
if (eear_we) |
eear <= #1 datain; |
if (esr_we) |
esr <= #1 {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]}; |
end |
`OR1200_EXCEPTFSM_FLU1: |
if (icpu_ack_i | icpu_err_i | genpc_freeze) |
state <= #1 `OR1200_EXCEPTFSM_FLU2; |
`OR1200_EXCEPTFSM_FLU2: |
default: |
except_type <= #1 `OR1200_EXCEPT_NONE; |
endcase |
end |
else if (pc_we) begin |
state <= #1 `OR1200_EXCEPTFSM_FLU1; |
extend_flush <= #1 1'b1; |
end |
else begin |
if (epcr_we) |
epcr <= #1 datain; |
if (eear_we) |
eear <= #1 datain; |
if (esr_we) |
esr <= #1 {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]}; |
end |
`OR1200_EXCEPTFSM_FLU1: |
if (icpu_ack_i | icpu_err_i | genpc_freeze) |
state <= #1 `OR1200_EXCEPTFSM_FLU2; |
`OR1200_EXCEPTFSM_FLU2: |
`ifdef OR1200_EXCEPT_TRAP |
if (except_type == `OR1200_EXCEPT_TRAP) begin |
state <= #1 `OR1200_EXCEPTFSM_IDLE; |
extend_flush <= #1 1'b0; |
extend_flush_last <= #1 1'b0; |
except_type <= #1 `OR1200_EXCEPT_NONE; |
end |
else |
if (except_type == `OR1200_EXCEPT_TRAP) begin |
state <= #1 `OR1200_EXCEPTFSM_IDLE; |
extend_flush <= #1 1'b0; |
extend_flush_last <= #1 1'b0; |
except_type <= #1 `OR1200_EXCEPT_NONE; |
end |
else |
`endif |
state <= #1 `OR1200_EXCEPTFSM_FLU3; |
`OR1200_EXCEPTFSM_FLU3: |
begin |
state <= #1 `OR1200_EXCEPTFSM_FLU4; |
end |
`OR1200_EXCEPTFSM_FLU4: begin |
state <= #1 `OR1200_EXCEPTFSM_FLU5; |
extend_flush <= #1 1'b0; |
extend_flush_last <= #1 1'b0; // damjan |
end |
state <= #1 `OR1200_EXCEPTFSM_FLU3; |
`OR1200_EXCEPTFSM_FLU3: |
begin |
state <= #1 `OR1200_EXCEPTFSM_FLU4; |
end |
`OR1200_EXCEPTFSM_FLU4: begin |
state <= #1 `OR1200_EXCEPTFSM_FLU5; |
extend_flush <= #1 1'b0; |
extend_flush_last <= #1 1'b0; // damjan |
end |
`ifdef OR1200_CASE_DEFAULT |
default: begin |
default: begin |
`else |
`OR1200_EXCEPTFSM_FLU5: begin |
`OR1200_EXCEPTFSM_FLU5: begin |
`endif |
if (!if_stall && !id_freeze) begin |
state <= #1 `OR1200_EXCEPTFSM_IDLE; |
except_type <= #1 `OR1200_EXCEPT_NONE; |
extend_flush_last <= #1 1'b0; |
end |
end |
endcase |
end |
end |
if (!if_stall && !id_freeze) begin |
state <= #1 `OR1200_EXCEPTFSM_IDLE; |
except_type <= #1 `OR1200_EXCEPT_NONE; |
extend_flush_last <= #1 1'b0; |
end |
end |
endcase |
end |
end |
|
endmodule |
/or1200_top.v
474,8 → 474,8
wire [dw-1:0] du_dat_du; |
wire du_read; |
wire du_write; |
wire [12:0] du_except_trig; |
wire [12:0] du_except_stop; |
wire [13:0] du_except_trig; |
wire [13:0] du_except_stop; |
wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; |
wire [24:0] du_dmr1; |
wire [dw-1:0] du_dat_cpu; |