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    /openrisc/trunk/or1200/rtl/verilog
    from Rev 358 to Rev 364
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  •

Rev 358 → Rev 364

/or1200_defines.v
922,10 → 922,10
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1xx
`define OR1200_DU_TBIM 11'h2xx
`define OR1200_DU_TBAR 11'h3xx
`define OR1200_DU_TBTS 11'h4xx
`define OR1200_DU_TBIA 11'h1??
`define OR1200_DU_TBIM 11'h2??
`define OR1200_DU_TBAR 11'h3??
`define OR1200_DU_TBTS 11'h4??
`endif
 
// Position of offset bits inside SPR address
1075,10 → 1075,11
// Shift {MACHI,MACLO} into destination register when executing l.macrc
//
// According to architecture manual there is no shift, so default value is 0.
//
// However the implementation has deviated in this from the arch manual and had hard coded shift by 28 bits which
// is a useful optimization for MP3 decoding (if using libmad fixed point library). Shifts are no longer
// default setup, but if you need to remain backward compatible, define your shift bits, which were normally
// However the implementation has deviated in this from the arch manual and had
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding
// (if using libmad fixed point library). Shifts are no longer default setup,
// but if you need to remain backward compatible, define your shift bits, which
// were normally
// dest_GPR = {MACHI,MACLO}[59:28]
`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility
 
1630,7 → 1631,7
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
`ifdef OR1200_DC_WRITETHROUGH
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`else
1678,7 → 1679,7
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1 // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
1706,7 → 1707,7
`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 28'h0000000
`define OR1200_DCFGR_RES1 27'd0
 
///////////////////////////////////////////////////////////////////////////////
// Boot Address Selection //
/or1200_freeze.v
158,9 → 158,9
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
multicycle_cnt <= 2'b00;
multicycle_cnt <= `OR1200_MULTICYCLE_WIDTH'd0;
else if (|multicycle_cnt)
multicycle_cnt <= multicycle_cnt - 2'd1;
multicycle_cnt <= multicycle_cnt - `OR1200_MULTICYCLE_WIDTH'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= multicycle;
 
/or1200_alu.v
148,9 → 148,9
`endif
) begin
`ifdef OR1200_CASE_DEFAULT
casex (alu_op) // synopsys parallel_case
casez (alu_op) // synopsys parallel_case
`else
casex (alu_op) // synopsys full_case parallel_case
casez (alu_op) // synopsys full_case parallel_case
`endif
`OR1200_ALUOP_FF1: begin
result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
220,9 → 220,9
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
casex (cust5_op) // synopsys parallel_case
casez (cust5_op) // synopsys parallel_case
5'h1 : begin
casex (cust5_limm[1:0])
casez (cust5_limm[1:0])
2'h0: result_cust5 = {a[31:8], b[7:0]};
2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
250,7 → 250,7
or result_csum
`endif
) begin
casex (alu_op) // synopsys parallel_case
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`OR1200_ALUOP_ADD : begin
flagforw = (result_sum == 32'h0000_0000);
291,7 → 291,7
`endif
`endif
) begin
casex (alu_op) // synopsys parallel_case
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`OR1200_ALUOP_ADD : begin
cyforw = cy_sum;
/or1200_sprs.v
365,7 → 365,7
 
function [31:0] get_sr;
// verilator public
get_sr = sr;
get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
endfunction // get_sr
 
function [31:0] get_epcr;
380,7 → 380,7
 
function [31:0] get_esr;
// verilator public
get_esr = esr;
get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
endfunction // get_esr
 
`endif
392,7 → 392,7
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
spr_dat_fpu or
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
casez (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_SYS:
to_wbmux = sys_data;
`OR1200_SPR_GROUP_TT:
/or1200_fpu.v
143,7 → 143,7
fpu_comp_done;
wire [width-1:0] result_arith, result_conv;
reg [`OR1200_FPUOP_WIDTH:0] fpu_op_r;
reg [`OR1200_FPUOP_WIDTH-1:0] fpu_op_r;
reg [`OR1200_FPCSR_WIDTH-1:0] fpcsr_r;
wire fpu_op_valid;
reg fpu_op_valid_re;
/or1200_dc_fsm.v
366,7 → 366,7
hitmiss_eval <= 1'b0;
store <= 1'b0;
load <= 1'b0;
cnt <= 3'b000;
cnt <= 3'd0;
cache_miss <= 1'b0;
cache_dirty_needs_writeback <= 1'b0;
cache_inhibit <= 1'b0;
453,10 → 453,10
state <= `OR1200_DCFSM_IDLE;
load <= 1'b0;
store <= 1'b0;
cnt <= 1'b0;
cnt <= 3'd0;
end
if (biudata_valid & (|cnt)) begin
cnt <= cnt - 1'b1;
cnt <= cnt - 3'd1;
addr_r[3:2] <= addr_r[3:2] + 1'b1;
end
else if (biudata_valid & !(|cnt)) begin
/or1200_fpu_pre_norm_div.v
109,62 → 109,62
// count leading zeros
//s_dvd_zeros <= count_l_zeros( s_fracta_24 );
always @(s_fracta_24)
casex(s_fracta_24) // synopsys full_case parallel_case
24'b1???????????????????????: s_dvd_zeros <= 0;
24'b01??????????????????????: s_dvd_zeros <= 1;
24'b001?????????????????????: s_dvd_zeros <= 2;
24'b0001????????????????????: s_dvd_zeros <= 3;
24'b00001???????????????????: s_dvd_zeros <= 4;
24'b000001??????????????????: s_dvd_zeros <= 5;
24'b0000001?????????????????: s_dvd_zeros <= 6;
24'b00000001????????????????: s_dvd_zeros <= 7;
24'b000000001???????????????: s_dvd_zeros <= 8;
24'b0000000001??????????????: s_dvd_zeros <= 9;
24'b00000000001?????????????: s_dvd_zeros <= 10;
24'b000000000001????????????: s_dvd_zeros <= 11;
24'b0000000000001???????????: s_dvd_zeros <= 12;
24'b00000000000001??????????: s_dvd_zeros <= 13;
24'b000000000000001?????????: s_dvd_zeros <= 14;
24'b0000000000000001????????: s_dvd_zeros <= 15;
24'b00000000000000001???????: s_dvd_zeros <= 16;
24'b000000000000000001??????: s_dvd_zeros <= 17;
24'b0000000000000000001?????: s_dvd_zeros <= 18;
24'b00000000000000000001????: s_dvd_zeros <= 19;
24'b000000000000000000001???: s_dvd_zeros <= 20;
24'b0000000000000000000001??: s_dvd_zeros <= 21;
24'b00000000000000000000001?: s_dvd_zeros <= 22;
24'b000000000000000000000001: s_dvd_zeros <= 23;
24'b000000000000000000000000: s_dvd_zeros <= 24;
casez(s_fracta_24) // synopsys full_case parallel_case
24'b1???????????????????????: s_dvd_zeros = 0;
24'b01??????????????????????: s_dvd_zeros = 1;
24'b001?????????????????????: s_dvd_zeros = 2;
24'b0001????????????????????: s_dvd_zeros = 3;
24'b00001???????????????????: s_dvd_zeros = 4;
24'b000001??????????????????: s_dvd_zeros = 5;
24'b0000001?????????????????: s_dvd_zeros = 6;
24'b00000001????????????????: s_dvd_zeros = 7;
24'b000000001???????????????: s_dvd_zeros = 8;
24'b0000000001??????????????: s_dvd_zeros = 9;
24'b00000000001?????????????: s_dvd_zeros = 10;
24'b000000000001????????????: s_dvd_zeros = 11;
24'b0000000000001???????????: s_dvd_zeros = 12;
24'b00000000000001??????????: s_dvd_zeros = 13;
24'b000000000000001?????????: s_dvd_zeros = 14;
24'b0000000000000001????????: s_dvd_zeros = 15;
24'b00000000000000001???????: s_dvd_zeros = 16;
24'b000000000000000001??????: s_dvd_zeros = 17;
24'b0000000000000000001?????: s_dvd_zeros = 18;
24'b00000000000000000001????: s_dvd_zeros = 19;
24'b000000000000000000001???: s_dvd_zeros = 20;
24'b0000000000000000000001??: s_dvd_zeros = 21;
24'b00000000000000000000001?: s_dvd_zeros = 22;
24'b000000000000000000000001: s_dvd_zeros = 23;
24'b000000000000000000000000: s_dvd_zeros = 24;
endcase
 
//s_div_zeros <= count_l_zeros( s_fractb_24 );
always @(s_fractb_24)
casex(s_fractb_24) // synopsys full_case parallel_case
24'b1???????????????????????: s_div_zeros <= 0;
24'b01??????????????????????: s_div_zeros <= 1;
24'b001?????????????????????: s_div_zeros <= 2;
24'b0001????????????????????: s_div_zeros <= 3;
24'b00001???????????????????: s_div_zeros <= 4;
24'b000001??????????????????: s_div_zeros <= 5;
24'b0000001?????????????????: s_div_zeros <= 6;
24'b00000001????????????????: s_div_zeros <= 7;
24'b000000001???????????????: s_div_zeros <= 8;
24'b0000000001??????????????: s_div_zeros <= 9;
24'b00000000001?????????????: s_div_zeros <= 10;
24'b000000000001????????????: s_div_zeros <= 11;
24'b0000000000001???????????: s_div_zeros <= 12;
24'b00000000000001??????????: s_div_zeros <= 13;
24'b000000000000001?????????: s_div_zeros <= 14;
24'b0000000000000001????????: s_div_zeros <= 15;
24'b00000000000000001???????: s_div_zeros <= 16;
24'b000000000000000001??????: s_div_zeros <= 17;
24'b0000000000000000001?????: s_div_zeros <= 18;
24'b00000000000000000001????: s_div_zeros <= 19;
24'b000000000000000000001???: s_div_zeros <= 20;
24'b0000000000000000000001??: s_div_zeros <= 21;
24'b00000000000000000000001?: s_div_zeros <= 22;
24'b000000000000000000000001: s_div_zeros <= 23;
24'b000000000000000000000000: s_div_zeros <= 24;
casez(s_fractb_24) // synopsys full_case parallel_case
24'b1???????????????????????: s_div_zeros = 0;
24'b01??????????????????????: s_div_zeros = 1;
24'b001?????????????????????: s_div_zeros = 2;
24'b0001????????????????????: s_div_zeros = 3;
24'b00001???????????????????: s_div_zeros = 4;
24'b000001??????????????????: s_div_zeros = 5;
24'b0000001?????????????????: s_div_zeros = 6;
24'b00000001????????????????: s_div_zeros = 7;
24'b000000001???????????????: s_div_zeros = 8;
24'b0000000001??????????????: s_div_zeros = 9;
24'b00000000001?????????????: s_div_zeros = 10;
24'b000000000001????????????: s_div_zeros = 11;
24'b0000000000001???????????: s_div_zeros = 12;
24'b00000000000001??????????: s_div_zeros = 13;
24'b000000000000001?????????: s_div_zeros = 14;
24'b0000000000000001????????: s_div_zeros = 15;
24'b00000000000000001???????: s_div_zeros = 16;
24'b000000000000000001??????: s_div_zeros = 17;
24'b0000000000000000001?????: s_div_zeros = 18;
24'b00000000000000000001????: s_div_zeros = 19;
24'b000000000000000000001???: s_div_zeros = 20;
24'b0000000000000000000001??: s_div_zeros = 21;
24'b00000000000000000000001?: s_div_zeros = 22;
24'b000000000000000000000001: s_div_zeros = 23;
24'b000000000000000000000000: s_div_zeros = 24;
endcase
 
// left-shift the dividend and divisor
/or1200_fpu_post_norm_addsub.v
132,35 → 132,35
reg [5:0] lzeroes;
always @(s_fract_28_i)
casex(s_fract_28_i[26:0]) // synopsys full_case parallel_case
27'b1??????????????????????????: lzeroes <= 0;
27'b01?????????????????????????: lzeroes <= 1;
27'b001????????????????????????: lzeroes <= 2;
27'b0001???????????????????????: lzeroes <= 3;
27'b00001??????????????????????: lzeroes <= 4;
27'b000001?????????????????????: lzeroes <= 5;
27'b0000001????????????????????: lzeroes <= 6;
27'b00000001???????????????????: lzeroes <= 7;
27'b000000001??????????????????: lzeroes <= 8;
27'b0000000001?????????????????: lzeroes <= 9;
27'b00000000001????????????????: lzeroes <= 10;
27'b000000000001???????????????: lzeroes <= 11;
27'b0000000000001??????????????: lzeroes <= 12;
27'b00000000000001?????????????: lzeroes <= 13;
27'b000000000000001????????????: lzeroes <= 14;
27'b0000000000000001???????????: lzeroes <= 15;
27'b00000000000000001??????????: lzeroes <= 16;
27'b000000000000000001?????????: lzeroes <= 17;
27'b0000000000000000001????????: lzeroes <= 18;
27'b00000000000000000001???????: lzeroes <= 19;
27'b000000000000000000001??????: lzeroes <= 20;
27'b0000000000000000000001?????: lzeroes <= 21;
27'b00000000000000000000001????: lzeroes <= 22;
27'b000000000000000000000001???: lzeroes <= 23;
27'b0000000000000000000000001??: lzeroes <= 24;
27'b00000000000000000000000001?: lzeroes <= 25;
27'b000000000000000000000000001: lzeroes <= 26;
27'b000000000000000000000000000: lzeroes <= 27;
casez(s_fract_28_i[26:0]) // synopsys full_case parallel_case
27'b1??????????????????????????: lzeroes = 0;
27'b01?????????????????????????: lzeroes = 1;
27'b001????????????????????????: lzeroes = 2;
27'b0001???????????????????????: lzeroes = 3;
27'b00001??????????????????????: lzeroes = 4;
27'b000001?????????????????????: lzeroes = 5;
27'b0000001????????????????????: lzeroes = 6;
27'b00000001???????????????????: lzeroes = 7;
27'b000000001??????????????????: lzeroes = 8;
27'b0000000001?????????????????: lzeroes = 9;
27'b00000000001????????????????: lzeroes = 10;
27'b000000000001???????????????: lzeroes = 11;
27'b0000000000001??????????????: lzeroes = 12;
27'b00000000000001?????????????: lzeroes = 13;
27'b000000000000001????????????: lzeroes = 14;
27'b0000000000000001???????????: lzeroes = 15;
27'b00000000000000001??????????: lzeroes = 16;
27'b000000000000000001?????????: lzeroes = 17;
27'b0000000000000000001????????: lzeroes = 18;
27'b00000000000000000001???????: lzeroes = 19;
27'b000000000000000000001??????: lzeroes = 20;
27'b0000000000000000000001?????: lzeroes = 21;
27'b00000000000000000000001????: lzeroes = 22;
27'b000000000000000000000001???: lzeroes = 23;
27'b0000000000000000000000001??: lzeroes = 24;
27'b00000000000000000000000001?: lzeroes = 25;
27'b000000000000000000000000001: lzeroes = 26;
27'b000000000000000000000000000: lzeroes = 27;
endcase
 
assign s_zeros = s_fract_28_i[27] ? 0 : lzeroes;
/or1200_fpu_arith.v
396,27 → 396,27
begin
if (s_rmode_i==2'd0 | s_div_zero_o | s_infa | s_infb | s_qnan_o |
s_qnan_o) // Round to nearest even
s_output_o <= s_output1;
s_output_o = s_output1;
else if (s_rmode_i==2'd1 & (&s_output1[30:23]))
// In round-to-zero: the sum of two non-infinity operands is never
// infinity,even if an overflow occures
s_output_o <= {s_output1[31], 31'b1111111_01111111_11111111_11111111};
s_output_o = {s_output1[31], 31'b1111111_01111111_11111111_11111111};
else if (s_rmode_i==2'd2 & (&s_output1[31:23]))
// In round-up: the sum of two non-infinity operands is never
// negative infinity,even if an overflow occures
s_output_o <= {32'b11111111_01111111_11111111_11111111};
s_output_o = {32'b11111111_01111111_11111111_11111111};
else if (s_rmode_i==2'd3) begin
if (((s_fpu_op_i==3'd0) | (s_fpu_op_i==3'd1)) & s_zero_o &
(s_opa_i[31] | (s_fpu_op_i[0] ^ s_opb_i[31])))
// In round-down: a-a= -0
s_output_o <= {1'b1,s_output1[30:0]};
s_output_o = {1'b1,s_output1[30:0]};
else if (s_output1[31:23]==9'b0_11111111)
s_output_o <= 32'b01111111011111111111111111111111;
s_output_o = 32'b01111111011111111111111111111111;
else
s_output_o <= s_output1;
s_output_o = s_output1;
end
else
s_output_o <= s_output1;
s_output_o = s_output1;
end // always @ *
 
// Exception generation
423,7 → 423,7
assign s_underflow_o = (s_output1[30:23]==8'h00) & s_ine_o;
assign s_overflow_o = (s_output1[30:23]==8'hff) & s_ine_o;
assign s_div_zero_o = serial_div_div_zero & fpu_op_i==3'd3;
assign s_inf_o = s_output1[31:23]==8'hff & !(s_qnan_o | s_snan_o);
assign s_inf_o = s_output1[30:23]==8'hff & !(s_qnan_o | s_snan_o);
assign s_zero_o = !(|s_output1[30:0]);
assign s_qnan_o = s_output1[30:0]==QNAN;
assign s_snan_o = s_output1[30:0]==SNAN;
/or1200_fpu_post_norm_div.v
150,7 → 150,7
wire [9:0] v_shl;
assign v_shr = (s_exp_10b[9] | !(|s_exp_10b)) ?
(10'd1 - s_exp_10b) - s_qutdn : 0;
(10'd1 - s_exp_10b) - {9'd0,s_qutdn} : 0;
assign v_shl = (s_exp_10b[9] | !(|s_exp_10b)) ?
0 :
183,35 → 183,35
//s_r_zeros <= count_r_zeros(s_qutnt_i);
always @(s_qutnt_i)
casex(s_qutnt_i) // synopsys full_case parallel_case
27'b??????????????????????????1: s_r_zeros <= 0;
27'b?????????????????????????10: s_r_zeros <= 1;
27'b????????????????????????100: s_r_zeros <= 2;
27'b???????????????????????1000: s_r_zeros <= 3;
27'b??????????????????????10000: s_r_zeros <= 4;
27'b?????????????????????100000: s_r_zeros <= 5;
27'b????????????????????1000000: s_r_zeros <= 6;
27'b???????????????????10000000: s_r_zeros <= 7;
27'b??????????????????100000000: s_r_zeros <= 8;
27'b?????????????????1000000000: s_r_zeros <= 9;
27'b????????????????10000000000: s_r_zeros <= 10;
27'b???????????????100000000000: s_r_zeros <= 11;
27'b??????????????1000000000000: s_r_zeros <= 12;
27'b?????????????10000000000000: s_r_zeros <= 13;
27'b????????????100000000000000: s_r_zeros <= 14;
27'b???????????1000000000000000: s_r_zeros <= 15;
27'b??????????10000000000000000: s_r_zeros <= 16;
27'b?????????100000000000000000: s_r_zeros <= 17;
27'b????????1000000000000000000: s_r_zeros <= 18;
27'b???????10000000000000000000: s_r_zeros <= 19;
27'b??????100000000000000000000: s_r_zeros <= 20;
27'b?????1000000000000000000000: s_r_zeros <= 21;
27'b????10000000000000000000000: s_r_zeros <= 22;
27'b???100000000000000000000000: s_r_zeros <= 23;
27'b??1000000000000000000000000: s_r_zeros <= 24;
27'b?10000000000000000000000000: s_r_zeros <= 25;
27'b100000000000000000000000000: s_r_zeros <= 26;
27'b000000000000000000000000000: s_r_zeros <= 27;
casez(s_qutnt_i) // synopsys full_case parallel_case
27'b??????????????????????????1: s_r_zeros = 0;
27'b?????????????????????????10: s_r_zeros = 1;
27'b????????????????????????100: s_r_zeros = 2;
27'b???????????????????????1000: s_r_zeros = 3;
27'b??????????????????????10000: s_r_zeros = 4;
27'b?????????????????????100000: s_r_zeros = 5;
27'b????????????????????1000000: s_r_zeros = 6;
27'b???????????????????10000000: s_r_zeros = 7;
27'b??????????????????100000000: s_r_zeros = 8;
27'b?????????????????1000000000: s_r_zeros = 9;
27'b????????????????10000000000: s_r_zeros = 10;
27'b???????????????100000000000: s_r_zeros = 11;
27'b??????????????1000000000000: s_r_zeros = 12;
27'b?????????????10000000000000: s_r_zeros = 13;
27'b????????????100000000000000: s_r_zeros = 14;
27'b???????????1000000000000000: s_r_zeros = 15;
27'b??????????10000000000000000: s_r_zeros = 16;
27'b?????????100000000000000000: s_r_zeros = 17;
27'b????????1000000000000000000: s_r_zeros = 18;
27'b???????10000000000000000000: s_r_zeros = 19;
27'b??????100000000000000000000: s_r_zeros = 20;
27'b?????1000000000000000000000: s_r_zeros = 21;
27'b????10000000000000000000000: s_r_zeros = 22;
27'b???100000000000000000000000: s_r_zeros = 23;
27'b??1000000000000000000000000: s_r_zeros = 24;
27'b?10000000000000000000000000: s_r_zeros = 25;
27'b100000000000000000000000000: s_r_zeros = 26;
27'b000000000000000000000000000: s_r_zeros = 27;
endcase // casex (s_qutnt_i)
assign s_lost = (s_shr1+{5'd0,s_shr2}) > s_r_zeros;
/or1200_reg2mem.v
104,7 → 104,7
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
casez({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
default : memdata_hh = regdata[31:24];
115,7 → 115,7
// Mux to memdata[23:16]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
casez({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
default : memdata_hl = regdata[7:0];
endcase
125,7 → 125,7
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
casez({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
default : memdata_lh = regdata[15:8];
endcase
/or1200_fpu_fcmp.v
120,7 → 120,7
always @( qnan or snan or opa_inf or opb_inf or signa or signb or exp_eq or exp_gt or
exp_lt or fract_eq or fract_gt or fract_lt or all_zero)
 
casex( {qnan, snan, opa_inf, opb_inf, signa, signb, exp_eq, exp_gt, exp_lt, fract_eq, fract_gt, fract_lt, all_zero})
casez( {qnan, snan, opa_inf, opb_inf, signa, signb, exp_eq, exp_gt, exp_lt, fract_eq, fract_gt, fract_lt, all_zero})
//13'b??_??_??_???_???_?: {altb, blta, aeqb} = 3'b000;
 
13'b1?_??_??_???_???_?: {altb, blta, aeqb} = 3'b000; // qnan
/or1200_lsu.v
147,7 → 147,7
 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
dcpu_adr_r <= {`OR1200_LSUEA_PRECALC{1'b0}};
dcpu_adr_r <= {`OR1200_LSUEA_PRECALC+1{1'b0}};
else if (!ex_freeze)
dcpu_adr_r <= id_precalc_sum;
end
181,7 → 181,12
//
// External I/F assignments
//
assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] = ex_addrbase[31:`OR1200_LSUEA_PRECALC] + ex_addrofs[31:`OR1200_LSUEA_PRECALC] + dcpu_adr_r[`OR1200_LSUEA_PRECALC]; // carry
assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] =
ex_addrbase[31:`OR1200_LSUEA_PRECALC] +
(ex_addrofs[31:`OR1200_LSUEA_PRECALC] +
// carry from precalc, pad to 30-bits
{{(32-`OR1200_LSUEA_PRECALC)-1{1'b0}},
dcpu_adr_r[`OR1200_LSUEA_PRECALC]});
assign dcpu_adr_o[`OR1200_LSUEA_PRECALC-1:0] = dcpu_adr_r[`OR1200_LSUEA_PRECALC-1:0];
assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ?
1'b0 : |ex_lsu_op;
188,7 → 193,7
assign dcpu_we_o = ex_lsu_op[3];
assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
always @(ex_lsu_op or dcpu_adr_o)
casex({ex_lsu_op, dcpu_adr_o[1:0]})
casez({ex_lsu_op, dcpu_adr_o[1:0]})
{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
/or1200_ctrl.v
321,7 → 321,7
// pipeline ID and EX branch target address
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
ex_branch_addrtarget <= 32'h00000000;
ex_branch_addrtarget <= 0;
else if (!ex_freeze)
ex_branch_addrtarget <= id_branch_addrtarget;
end
471,15 → 471,14
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
case (id_insn[3:0]) // synopsys parallel_case
4'h6: multicycle = 2'b11; // l.mul
4'h9: multicycle = 2'b10; // l.div
4'hA: multicycle = 2'b10; // l.divu
4'hB: multicycle = 2'b11; // l.mulu
default: multicycle = 2'b00;
endcase
4'h6: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mul
4'h9: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.div
4'hA: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.divu
4'hB: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mulu
default: multicycle = `OR1200_MULTICYCLE_WIDTH'd0;
endcase
`OR1200_OR32_MULI:
multicycle = 2'h3;
multicycle = `OR1200_MULTICYCLE_WIDTH'd3;
// Single cycle instructions
default: begin
724,52 → 723,53
`OR1200_OR32_CUST5,
`endif
`OR1200_OR32_NOP:
except_illegal <= 1'b0;
except_illegal <= 1'b0;
`ifdef OR1200_FPU_IMPLEMENTED
`OR1200_OR32_FLOAT:
// Check it's not a double precision instruction
except_illegal <= id_insn[`OR1200_FPUOP_DOUBLE_BIT];
// Check it's not a double precision instruction
except_illegal <= id_insn[`OR1200_FPUOP_DOUBLE_BIT];
`endif
 
`OR1200_OR32_ALU:
except_illegal <= 1'b0
except_illegal <= 1'b0
 
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
`else
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
| (id_insn[3:0] == `OR1200_ALUOP_DIV)
| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
`endif
`else
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_MUL)
| (id_insn[3:0] == `OR1200_ALUOP_DIV)
| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
| (id_insn[3:0] == `OR1200_ALUOP_MUL)
`endif
 
`ifdef OR1200_IMPL_ADDC
`else
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_ADDC)
| (id_insn[3:0] == `OR1200_ALUOP_ADDC)
`endif
 
`ifdef OR1200_IMPL_ALU_ROTATE
`else
| (({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SHROT) && (id_insn[7:6] == `OR1200_SHROTOP_ROR))
| ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
(id_insn[7:6] == `OR1200_SHROTOP_ROR))
`endif
 
`ifdef OR1200_IMPL_SUB
`else
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SUB)
| (id_insn[3:0] == `OR1200_ALUOP_SUB)
`endif
;
;
 
// Illegal and OR1200 unsupported instructions
default:
except_illegal <= 1'b1;
default:
except_illegal <= 1'b1;
 
endcase
end
endcase
end // if (!ex_freeze)
end
 
//
// Decode of alu_op
/or1200_wb_biu.v
337,17 → 337,17
end
else begin
// WB ack toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
wb_ack_cnt <= 1'b0;
else if (wb_stb_o & wb_ack)
wb_ack_cnt <= !wb_ack_cnt;
// WB err toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
wb_err_cnt <= 1'b0;
else if (wb_stb_o & wb_err_i)
wb_err_cnt <= !wb_err_cnt;
// WB rty toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
wb_rty_cnt <= 1'b0;
else if (wb_stb_o & wb_rty_i)
wb_rty_cnt <= !wb_rty_cnt;
371,17 → 371,17
else
biu_stb_reg <= biu_stb_i;
// BIU ack toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
biu_ack_cnt <= 1'b0 ;
else if (biu_ack_o)
biu_ack_cnt <= !biu_ack_cnt ;
// BIU err toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
biu_err_cnt <= 1'b0 ;
else if (wb_err_i & biu_err_o)
biu_err_cnt <= !biu_err_cnt ;
// BIU rty toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
biu_rty_cnt <= 1'b0 ;
else if (biu_rty)
biu_rty_cnt <= !biu_rty_cnt ;
/or1200_fpu_post_norm_mul.v
139,7 → 139,7
always @(posedge clk_i)
if (!s_fract_48_i[47])
casex(s_fract_48_i[46:1]) // synopsys full_case parallel_case
casez(s_fract_48_i[46:1]) // synopsys full_case parallel_case
46'b1?????????????????????????????????????????????: s_zeros <= 0;
46'b01????????????????????????????????????????????: s_zeros <= 1;
46'b001???????????????????????????????????????????: s_zeros <= 2;
193,7 → 193,7
 
 
always @(posedge clk_i)
casex(s_fract_48_i) // synopsys full_case parallel_case
casez(s_fract_48_i) // synopsys full_case parallel_case
48'b???????????????????????????????????????????????1: s_r_zeros <= 0;
48'b??????????????????????????????????????????????10: s_r_zeros <= 1;
48'b?????????????????????????????????????????????100: s_r_zeros <= 2;
271,7 → 271,7
if ((s_exp_10a[9] | !(|s_exp_10a)))
s_expo1 <= 9'd1;
else if (s_exp_10b[9] | !(|s_exp_10b))
s_expo1 <= 1'd1;
s_expo1 <= 9'd1;
else if (s_exp_10b[8])
s_expo1 <= 9'b011111111;
else
/or1200_du.v
536,39 → 536,39
//
always @(du_except_stop) begin
except_stop = 14'b00_0000_0000_0000;
casex (du_except_stop)
14'b1x_xxxx_xxxx_xxxx:
casez (du_except_stop)
14'b1?_????_????_????:
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
14'b01_xxxx_xxxx_xxxx: begin
14'b01_????_????_????: begin
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
end
14'b00_1xxx_xxxx_xxxx: begin
14'b00_1???_????_????: begin
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
end
14'b00_01xx_xxxx_xxxx:
14'b00_01??_????_????:
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
14'b00_001x_xxxx_xxxx: begin
14'b00_001?_????_????: begin
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
end
14'b00_0001_xxxx_xxxx:
14'b00_0001_????_????:
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
14'b00_0000_1xxx_xxxx: begin
14'b00_0000_1???_????: begin
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
end
14'b00_0000_01xx_xxxx: begin
14'b00_0000_01??_????: begin
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
end
14'b00_0000_001x_xxxx:
14'b00_0000_001?_????:
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
14'b00_0000_0001_xxxx:
14'b00_0000_0001_????:
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
14'b00_0000_0000_1xxx: begin
14'b00_0000_0000_1???: begin
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
end
14'b00_0000_0000_01xx: begin
14'b00_0000_0000_01??: begin
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
end
14'b00_0000_0000_001x: begin
14'b00_0000_0000_001?: begin
except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
end
14'b00_0000_0000_0001:
912,7 → 912,7
or tbar_dat_o or tbts_dat_o
`endif
)
casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
casez (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_DU_DVR0
`OR1200_DU_DVR0:
spr_dat_o = dvr0;
/or1200_fpu_post_norm_intfloat_conv.v
137,7 → 137,7
// Count Leading zeros in fraction
 
always @(/*fract_in*/ posedge clk)
casex(fract_in) // synopsys full_case parallel_case
casez(fract_in) // synopsys full_case parallel_case
48'b1???????????????????????????????????????????????: fi_ldz <= 1;
48'b01??????????????????????????????????????????????: fi_ldz <= 2;
48'b001?????????????????????????????????????????????: fi_ldz <= 3;
294,7 → 294,8
assign exp_in_mi1 = exp_in - 1; // 9 bits - includes carry out
assign exp_out1_mi1 = exp_out1 - 1;
 
assign exp_next_mi = exp_in_pl1 - fi_ldz_mi1; // 9 bits - includes carry out
assign exp_next_mi = exp_in_pl1 -
{3'd0,fi_ldz_mi1}; // 9 bits - includes carry out
 
assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
309,7 → 310,7
?
0 :opas;
 
assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-fi_ldz);
assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-{2'd0,fi_ldz});
assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<<f2i_shft;
assign exp_f2i = f2i_zero ? 0 : f2i_max ? 8'hff : exp_f2i_1[55:48];
assign conv_exp = op_f2i ? exp_f2i : exp_i2f;
319,7 → 320,7
exp_out <= conv_exp;
 
assign ldz_all = fi_ldz;
assign ldz_all = {1'b0,fi_ldz};
assign fi_ldz_2a = 6'd23 - fi_ldz;
assign fi_ldz_2 = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
 
/or1200_gmultp2_32x32.v
103,16 → 103,15
//
// Conversion unsigned to signed
//
/* verilator lint_off COMBDLY */
always @(X)
xi <= X;
xi = X;
 
//
// Conversion unsigned to signed
//
always @(Y)
yi <= Y;
/* verilator lint_on COMBDLY */
yi = Y;
 
//
// First multiply stage
//
/or1200_mult_mac.v
176,10 → 176,10
// to next instruction and to WB stage
//
always @*
casex(alu_op) // synopsys parallel_case
casez(alu_op) // synopsys parallel_case
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIV: begin
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 32'd1 : mul_prod_r[31:0];
end
`OR1200_ALUOP_DIVU,
`endif
233,7 → 233,7
mul_prod_r <= {mul_prod_r[62:0], 1'b0};
else
mul_prod_r <= {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
div_cntr <= div_cntr - 1'b1;
div_cntr <= div_cntr - 6'd1;
end
else if (alu_op_div_divu && div_free) begin
mul_prod_r <= {31'b0, x[31:0], 1'b0};
/or1200_wbmux.v
113,9 → 113,9
//
always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif
`OR1200_RFWBOP_ALU: muxout = muxin_a;
`OR1200_RFWBOP_LSU: begin
151,7 → 151,11
// synopsys translate_on
`endif
end
`endif
`endif
default : begin
muxout = 0;
end
endcase
end
 
/or1200_operandmuxes.v
128,9 → 128,9
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_a) // synopsys parallel_case infer_mux
casez (sel_a) // synopsys parallel_case infer_mux
`else
casex (sel_a) // synopsys parallel_case
casez (sel_a) // synopsys parallel_case
`endif
`OR1200_SEL_EX_FORW:
muxed_a = ex_forw;
146,9 → 146,9
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_b) // synopsys parallel_case infer_mux
casez (sel_b) // synopsys parallel_case infer_mux
`else
casex (sel_b) // synopsys parallel_case
casez (sel_b) // synopsys parallel_case
`endif
`OR1200_SEL_IMM:
muxed_b = simm;
/or1200_fpu_pre_norm_addsub.v
152,39 → 152,39
 
// count the zeros from right to check if result is inexact
always @(s_fract_sm_28)
casex(s_fract_sm_28) // synopsys full_case parallel_case
28'b???????????????????????????1: s_rzeros <= 0;
28'b??????????????????????????10: s_rzeros <= 1;
28'b?????????????????????????100: s_rzeros <= 2;
28'b????????????????????????1000: s_rzeros <= 3;
28'b???????????????????????10000: s_rzeros <= 4;
28'b??????????????????????100000: s_rzeros <= 5;
28'b?????????????????????1000000: s_rzeros <= 6;
28'b????????????????????10000000: s_rzeros <= 7;
28'b???????????????????100000000: s_rzeros <= 8;
28'b??????????????????1000000000: s_rzeros <= 9;
28'b?????????????????10000000000: s_rzeros <= 10;
28'b????????????????100000000000: s_rzeros <= 11;
28'b???????????????1000000000000: s_rzeros <= 12;
28'b??????????????10000000000000: s_rzeros <= 13;
28'b?????????????100000000000000: s_rzeros <= 14;
28'b????????????1000000000000000: s_rzeros <= 15;
28'b???????????10000000000000000: s_rzeros <= 16;
28'b??????????100000000000000000: s_rzeros <= 17;
28'b?????????1000000000000000000: s_rzeros <= 18;
28'b????????10000000000000000000: s_rzeros <= 19;
28'b???????100000000000000000000: s_rzeros <= 20;
28'b??????1000000000000000000000: s_rzeros <= 21;
28'b?????10000000000000000000000: s_rzeros <= 22;
28'b????100000000000000000000000: s_rzeros <= 23;
28'b???1000000000000000000000000: s_rzeros <= 24;
28'b??10000000000000000000000000: s_rzeros <= 25;
28'b?100000000000000000000000000: s_rzeros <= 26;
28'b1000000000000000000000000000: s_rzeros <= 27;
28'b0000000000000000000000000000: s_rzeros <= 28;
casez(s_fract_sm_28) // synopsys full_case parallel_case
28'b???????????????????????????1: s_rzeros = 0;
28'b??????????????????????????10: s_rzeros = 1;
28'b?????????????????????????100: s_rzeros = 2;
28'b????????????????????????1000: s_rzeros = 3;
28'b???????????????????????10000: s_rzeros = 4;
28'b??????????????????????100000: s_rzeros = 5;
28'b?????????????????????1000000: s_rzeros = 6;
28'b????????????????????10000000: s_rzeros = 7;
28'b???????????????????100000000: s_rzeros = 8;
28'b??????????????????1000000000: s_rzeros = 9;
28'b?????????????????10000000000: s_rzeros = 10;
28'b????????????????100000000000: s_rzeros = 11;
28'b???????????????1000000000000: s_rzeros = 12;
28'b??????????????10000000000000: s_rzeros = 13;
28'b?????????????100000000000000: s_rzeros = 14;
28'b????????????1000000000000000: s_rzeros = 15;
28'b???????????10000000000000000: s_rzeros = 16;
28'b??????????100000000000000000: s_rzeros = 17;
28'b?????????1000000000000000000: s_rzeros = 18;
28'b????????10000000000000000000: s_rzeros = 19;
28'b???????100000000000000000000: s_rzeros = 20;
28'b??????1000000000000000000000: s_rzeros = 21;
28'b?????10000000000000000000000: s_rzeros = 22;
28'b????100000000000000000000000: s_rzeros = 23;
28'b???1000000000000000000000000: s_rzeros = 24;
28'b??10000000000000000000000000: s_rzeros = 25;
28'b?100000000000000000000000000: s_rzeros = 26;
28'b1000000000000000000000000000: s_rzeros = 27;
28'b0000000000000000000000000000: s_rzeros = 28;
endcase // casex (s_fract_sm_28)
assign s_sticky = (s_exp_diff > s_rzeros) & (|s_fract_sm_28);
assign s_sticky = (s_exp_diff > {2'b00,s_rzeros}) & (|s_fract_sm_28);
assign s_fracta_28_o = s_expa_gt_expb ?
s_fracta_28 :
/or1200_dmmu_top.v
233,7 → 233,7
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcpu_vpn_r <= {31-`OR1200_DMMU_PS{1'b0}};
dcpu_vpn_r <= {32-`OR1200_DMMU_PS{1'b0}};
else
dcpu_vpn_r <= dcpu_adr_i[31:`OR1200_DMMU_PS];
 
/or1200_except.v
466,9 → 466,9
state <= `OR1200_EXCEPTFSM_FLU1;
extend_flush <= 1'b1;
esr <= sr_we ? to_sr : sr;
casex (except_trig)
casez (except_trig)
`ifdef OR1200_EXCEPT_ITLBMISS
14'b1x_xxxx_xxxx_xxxx: begin
14'b1?_????_????_????: begin
except_type <= `OR1200_EXCEPT_ITLBMISS;
eear <= ex_dslot ?
ex_pc : ex_pc;
477,7 → 477,7
end
`endif
`ifdef OR1200_EXCEPT_IPF
14'b01_xxxx_xxxx_xxxx: begin
14'b01_????_????_????: begin
except_type <= `OR1200_EXCEPT_IPF;
eear <= ex_dslot ?
ex_pc : delayed1_ex_dslot ?
490,7 → 490,7
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
14'b00_1xxx_xxxx_xxxx: begin // Insn. Bus Error
14'b00_1???_????_????: begin // Insn. Bus Error
except_type <= `OR1200_EXCEPT_BUSERR;
eear <= ex_dslot ?
wb_pc : ex_pc;
499,7 → 499,7
end
`endif
`ifdef OR1200_EXCEPT_ILLEGAL
14'b00_01xx_xxxx_xxxx: begin
14'b00_01??_????_????: begin
except_type <= `OR1200_EXCEPT_ILLEGAL;
eear <= ex_pc;
epcr <= ex_dslot ?
507,7 → 507,7
end
`endif
`ifdef OR1200_EXCEPT_ALIGN
14'b00_001x_xxxx_xxxx: begin
14'b00_001?_????_????: begin
except_type <= `OR1200_EXCEPT_ALIGN;
eear <= lsu_addr;
epcr <= ex_dslot ?
515,7 → 515,7
end
`endif
`ifdef OR1200_EXCEPT_DTLBMISS
14'b00_0001_xxxx_xxxx: begin
14'b00_0001_????_????: begin
except_type <= `OR1200_EXCEPT_DTLBMISS;
eear <= lsu_addr;
epcr <= ex_dslot ?
524,7 → 524,7
end
`endif
`ifdef OR1200_EXCEPT_TRAP
14'b00_0000_1xxx_xxxx: begin
14'b00_0000_1???_????: begin
except_type <= `OR1200_EXCEPT_TRAP;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
532,7 → 532,7
end
`endif
`ifdef OR1200_EXCEPT_SYSCALL
14'b00_0000_01xx_xxxx: begin
14'b00_0000_01??_????: begin
except_type <= `OR1200_EXCEPT_SYSCALL;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
541,7 → 541,7
end
`endif
`ifdef OR1200_EXCEPT_DPF
14'b00_0000_001x_xxxx: begin
14'b00_0000_001?_????: begin
except_type <= `OR1200_EXCEPT_DPF;
eear <= lsu_addr;
epcr <= ex_dslot ?
550,7 → 550,7
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
14'b00_0000_0001_xxxx: begin // Data Bus Error
14'b00_0000_0001_????: begin // Data Bus Error
except_type <= `OR1200_EXCEPT_BUSERR;
eear <= lsu_addr;
epcr <= ex_dslot ?
559,7 → 559,7
end
`endif
`ifdef OR1200_EXCEPT_RANGE
14'b00_0000_0000_1xxx: begin
14'b00_0000_0000_1???: begin
except_type <= `OR1200_EXCEPT_RANGE;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
568,13 → 568,13
end
`endif
`ifdef OR1200_EXCEPT_FLOAT
14'b00_0000_0000_01xx: begin
14'b00_0000_0000_01??: begin
except_type <= `OR1200_EXCEPT_FLOAT;
epcr <= id_pc;
end
`endif
`ifdef OR1200_EXCEPT_INT
14'b00_0000_0000_001x: begin
14'b00_0000_0000_001?: begin
except_type <= `OR1200_EXCEPT_INT;
epcr <= id_pc;
end
/or1200_genpc.v
154,7 → 154,7
or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or
except_prefix)
begin
casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
casez ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
{2'b00, `OR1200_BRANCHOP_NOP}: begin
pc = {pcreg + 30'd1, 2'b0};
ex_branch_taken = 1'b0;
229,7 → 229,7
pc = epcr;
ex_branch_taken = 1'b1;
end
{2'b01, 3'bxxx}: begin
{2'b01, 3'b???}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("Starting exception: %h.", except_type);
/or1200_top.v
258,7 → 258,8
wire [dw-1:0] spr_dat_cpu;
wire [31:0] spr_cs;
wire spr_we;
 
wire mtspr_dc_done;
//
// SB
//

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