URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/or1200/rtl/verilog
- from Rev 674 to Rev 679
- ↔ Reverse comparison
Rev 674 → Rev 679
/or1200_immu_top.v
75,6 → 75,7
|
parameter dw = `OR1200_OPERAND_WIDTH; |
parameter aw = `OR1200_OPERAND_WIDTH; |
parameter boot_adr = `OR1200_BOOT_ADR; |
|
// |
// I/O |
148,7 → 149,6
wire miss; |
wire page_cross; |
reg [31:0] icpu_adr_default; |
wire [31:0] icpu_adr_boot; |
reg icpu_adr_select; |
reg [31:0] icpu_adr_o; |
reg [31:`OR1200_IMMU_PS] icpu_vpn_r; |
176,6 → 176,8
// icpu_adr_o |
// |
`ifdef OR1200_REGISTERED_OUTPUTS |
wire [31:0] icpu_adr_boot = boot_adr; |
|
always @(`OR1200_RST_EVENT rst or posedge clk) |
// default value |
if (rst == `OR1200_RST_VALUE) begin |
199,7 → 201,6
// selected after boot! |
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : |
// `OR1200_EXCEPT_EPH0_P), 12'h100} ; |
assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb |
|
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select) |
if (icpu_adr_select) |
/or1200_top.v
97,6 → 97,7
parameter dw = `OR1200_OPERAND_WIDTH; |
parameter aw = `OR1200_OPERAND_WIDTH; |
parameter ppic_ints = `OR1200_PIC_INTS; |
parameter boot_adr = `OR1200_BOOT_ADR; |
|
// |
// I/O |
523,7 → 524,9
// |
// Instantiation of IMMU |
// |
or1200_immu_top or1200_immu_top( |
or1200_immu_top |
#(.boot_adr(boot_adr)) |
or1200_immu_top( |
// Rst and clk |
.clk(clk_i), |
.rst(rst_i), |