URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/bench/sysc/src
- from Rev 861 to Rev 862
- ↔ Reverse comparison
Rev 861 → Rev 862
/OrpsocAccess.cpp
29,6 → 29,8
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#include "OrpsocAccess.h" |
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#include "Vorpsoc_top__Syms.h" |
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#include "Vorpsoc_top.h" |
#include "Vorpsoc_top_orpsoc_top.h" |
#include "Vorpsoc_top_or1200_top.h" |
38,11 → 40,6
#include "Vorpsoc_top_or1200_sprs.h" |
#include "Vorpsoc_top_or1200_rf.h" |
#include "Vorpsoc_top_or1200_dpram.h" |
// Need RAM instantiation has parameters after module name |
// Include for ram_wb |
#include "Vorpsoc_top_ram_wb__A20_D20_M800000_MB17.h" |
// Include for ram_wb_b3 |
#include "Vorpsoc_top_ram_wb_b3__pi3.h" |
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//! Constructor for the ORPSoC access class |
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58,13 → 55,8
or1200_except = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_except; |
or1200_sprs = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_sprs; |
rf_a = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_rf->rf_a; |
// Assign main memory accessor objects |
// For old ram_wb: ram_wb_sc_sw = orpsoc_top->v->ram_wb0->ram0; |
//ram_wb_sc_sw = orpsoc_top->v->wb_ram_b3_0; |
wishbone_ram = orpsoc_top->v->ram_wb0->ram_wb_b3_0; |
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// Assign arbiter accessor object |
//wb_arbiter = orpsoc_top->v->wb_conbus; |
this->orpsoc_top = orpsoc_top; |
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} // OrpsocAccess () |
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