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    /openrisc/trunk/orpsocv2/boards
    from Rev 568 to Rev 627
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Rev 568 → Rev 627

/xilinx/atlys/rtl/verilog/clkgen/clkgen.v
0,0 → 1,245
/*
*
* Clock, reset generation unit for Atlys board
*
* Implements clock generation according to design defines
*
*/
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
`include "orpsoc-defines.v"
`include "synthesis-defines.v"
 
module clkgen
(
// Main clocks in, depending on board
sys_clk_in,
 
// Wishbone clock and reset out
wb_clk_o,
wb_rst_o,
 
// JTAG clock
`ifdef JTAG_DEBUG
tck_pad_i,
dbg_tck_o,
`endif
// Main memory clocks
`ifdef XILINX_DDR2
ddr2_if_clk_o,
ddr2_if_rst_o,
clk100_o,
`endif
 
// Asynchronous, active low reset in
rst_n_pad_i
);
 
input sys_clk_in;
 
output wb_rst_o;
output wb_clk_o;
 
`ifdef JTAG_DEBUG
input tck_pad_i;
output dbg_tck_o;
`endif
`ifdef XILINX_DDR2
output ddr2_if_clk_o;
output ddr2_if_rst_o;
output clk100_o;
`endif
 
// Asynchronous, active low reset (pushbutton, typically)
input rst_n_pad_i;
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
 
// Xilinx synthesis tools appear cluey enough to instantiate buffers when and
// where they're needed, so we do simple assigns for this tech.
assign async_rst_n = rst_n_pad_i;
 
// Everyone likes active-high reset signals...
assign async_rst = ~async_rst_n;
`ifdef JTAG_DEBUG
assign dbg_tck_o = tck_pad_i;
`endif
 
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
wire sync_rst_n;
 
// An active-low synchronous reset from ethernet PLL
wire sync_eth_rst_n;
wire sys_clk_in_200;
wire sys_clk_ibufg;
/* DCM0 wires */
wire dcm0_clk0_prebufg, dcm0_clk0;
wire dcm0_clkfx_prebufg, dcm0_clkfx;
wire dcm0_clkdv_prebufg, dcm0_clkdv;
wire dcm0_clk2x_prebufg, dcm0_clk2x;
wire dcm0_locked;
`ifdef FPGA_BOARD_XILINX_ML501
/* Dif. input buffer for 200MHz board clock, generate SE 200MHz */
IBUFGDS_LVPECL_25 sys_clk_in_ibufds
(
.O(sys_clk_in_200),
.I(sys_clk_in_p),
.IB(sys_clk_in_n));
 
/* DCM providing main system/Wishbone clock */
DCM_BASE dcm0
(
// Outputs
.CLK0 (dcm0_clk0_prebufg),
.CLK180 (),
.CLK270 (),
.CLK2X180 (),
.CLK2X (dcm0_clk2x_prebufg),
.CLK90 (),
.CLKDV (dcm0_clkdv_prebufg),
.CLKFX180 (),
.CLKFX (dcm0_clkfx_prebufg),
.LOCKED (dcm0_locked),
// Inputs
.CLKFB (dcm0_clk0),
.CLKIN (sys_clk_in_200),
.RST (1'b0));
 
`endif
`ifdef FPGA_BOARD_XILINX_ATLYS
IBUFG sys_clk_in_ibufg
(
.I (sys_clk_in),
.O (sys_clk_ibufg)
);
 
 
/* DCM providing main system/Wishbone clock */
DCM_SP dcm0
(
// Outputs
.CLK0 (dcm0_clk0_prebufg),
.CLK180 (),
.CLK270 (),
.CLK2X180 (),
.CLK2X (dcm0_clk2x_prebufg),
.CLK90 (),
.CLKDV (dcm0_clkdv_prebufg),
.CLKFX180 (),
.CLKFX (dcm0_clkfx_prebufg),
.LOCKED (dcm0_locked),
// Inputs
.CLKFB (dcm0_clk0),
.CLKIN (sys_clk_ibufg),
.PSEN (1'b0),
.RST (1'b0));
`endif
// Generate 266 MHz from CLKFX
defparam dcm0.CLKFX_MULTIPLY = 8;
defparam dcm0.CLKFX_DIVIDE = 3;
 
// Generate 50 MHz from CLKDV
defparam dcm0.CLKDV_DIVIDE = 2.0;
 
BUFG dcm0_clk0_bufg
(// Outputs
.O (dcm0_clk0),
// Inputs
.I (dcm0_clk0_prebufg));
BUFG dcm0_clk2x_bufg
(// Outputs
.O (dcm0_clk2x),
// Inputs
.I (dcm0_clk2x_prebufg));
 
BUFG dcm0_clkfx_bufg
(// Outputs
.O (dcm0_clkfx),
// Inputs
.I (dcm0_clkfx_prebufg));
 
BUFG dcm0_clkdv_bufg
(// Outputs
.O (dcm0_clkdv),
// Inputs
.I (dcm0_clkdv_prebufg));
 
assign wb_clk_o = dcm0_clkdv;
assign sync_rst_n = dcm0_locked;
 
`ifdef XILINX_DDR2
assign ddr2_if_clk_o = dcm0_clkfx; // 266MHz
assign clk100_o = dcm0_clk0; // 100MHz
`endif
//
// Reset generation
//
//
 
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
 
`ifdef XILINX_DDR2
// Reset generation for DDR2 controller
reg [15:0] ddr2_if_rst_shr;
always @(posedge ddr2_if_clk_o or posedge async_rst)
if (async_rst)
ddr2_if_rst_shr <= 16'hffff;
else
ddr2_if_rst_shr <= {ddr2_if_rst_shr[14:0], ~(sync_rst_n)};
assign ddr2_if_rst_o = ddr2_if_rst_shr[15];
`endif
endmodule // clkgen
/xilinx/atlys/rtl/verilog/include/ethmac_defines.v
0,0 → 1,246
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_defines.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// Modified by: ////
//// - Julius Baxter (julius@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
 
//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
 
`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
 
// Generic FIFO implementation - hopefully synthesizable with Synplify
//`define ETH_FIFO_GENERIC
// specific elements.
`define ETH_FIFO_XILINX
//`define ETH_FIFO_RAMB18
 
 
`define ETH_MODER_ADR 8'h0 // 0x0
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
`define ETH_INT_MASK_ADR 8'h2 // 0x8
`define ETH_IPGT_ADR 8'h3 // 0xC
`define ETH_IPGR1_ADR 8'h4 // 0x10
`define ETH_IPGR2_ADR 8'h5 // 0x14
`define ETH_PACKETLEN_ADR 8'h6 // 0x18
`define ETH_COLLCONF_ADR 8'h7 // 0x1C
`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
`define ETH_CTRLMODER_ADR 8'h9 // 0x24
`define ETH_MIIMODER_ADR 8'hA // 0x28
`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
`define ETH_MIIADDRESS_ADR 8'hC // 0x30
`define ETH_MIITX_DATA_ADR 8'hD // 0x34
`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
`define ETH_MIISTATUS_ADR 8'hF // 0x3C
`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
`define ETH_HASH0_ADR 8'h12 // 0x48
`define ETH_HASH1_ADR 8'h13 // 0x4C
`define ETH_TX_CTRL_ADR 8'h14 // 0x50
`define ETH_RX_CTRL_ADR 8'h15 // 0x54
`define ETH_DBG_ADR 8'h16 // 0x58
 
 
`define ETH_MODER_DEF_0 8'h00
`define ETH_MODER_DEF_1 8'hA0
`define ETH_MODER_DEF_2 1'h0
`define ETH_INT_MASK_DEF_0 7'h0
`define ETH_IPGT_DEF_0 7'h12
`define ETH_IPGR1_DEF_0 7'h0C
`define ETH_IPGR2_DEF_0 7'h12
`define ETH_PACKETLEN_DEF_0 8'h00
`define ETH_PACKETLEN_DEF_1 8'h06
`define ETH_PACKETLEN_DEF_2 8'h40
`define ETH_PACKETLEN_DEF_3 8'h00
`define ETH_COLLCONF_DEF_0 6'h3f
`define ETH_COLLCONF_DEF_2 4'hF
`define ETH_TX_BD_NUM_DEF_0 8'h40
`define ETH_CTRLMODER_DEF_0 3'h0
`define ETH_MIIMODER_DEF_0 8'h64
`define ETH_MIIMODER_DEF_1 1'h0
`define ETH_MIIADDRESS_DEF_0 5'h00
`define ETH_MIIADDRESS_DEF_1 5'h00
`define ETH_MIITX_DATA_DEF_0 8'h00
`define ETH_MIITX_DATA_DEF_1 8'h00
`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB
`define ETH_MAC_ADDR0_DEF_0 8'h00
`define ETH_MAC_ADDR0_DEF_1 8'h00
`define ETH_MAC_ADDR0_DEF_2 8'h00
`define ETH_MAC_ADDR0_DEF_3 8'h00
`define ETH_MAC_ADDR1_DEF_0 8'h00
`define ETH_MAC_ADDR1_DEF_1 8'h00
`define ETH_HASH0_DEF_0 8'h00
`define ETH_HASH0_DEF_1 8'h00
`define ETH_HASH0_DEF_2 8'h00
`define ETH_HASH0_DEF_3 8'h00
`define ETH_HASH1_DEF_0 8'h00
`define ETH_HASH1_DEF_1 8'h00
`define ETH_HASH1_DEF_2 8'h00
`define ETH_HASH1_DEF_3 8'h00
`define ETH_TX_CTRL_DEF_0 8'h00 //
`define ETH_TX_CTRL_DEF_1 8'h00 //
`define ETH_TX_CTRL_DEF_2 1'h0 //
`define ETH_RX_CTRL_DEF_0 8'h00
`define ETH_RX_CTRL_DEF_1 8'h00
 
 
`define ETH_MODER_WIDTH_0 8
`define ETH_MODER_WIDTH_1 8
`define ETH_MODER_WIDTH_2 1
`define ETH_INT_SOURCE_WIDTH_0 7
`define ETH_INT_MASK_WIDTH_0 7
`define ETH_IPGT_WIDTH_0 7
`define ETH_IPGR1_WIDTH_0 7
`define ETH_IPGR2_WIDTH_0 7
`define ETH_PACKETLEN_WIDTH_0 8
`define ETH_PACKETLEN_WIDTH_1 8
`define ETH_PACKETLEN_WIDTH_2 8
`define ETH_PACKETLEN_WIDTH_3 8
`define ETH_COLLCONF_WIDTH_0 6
`define ETH_COLLCONF_WIDTH_2 4
`define ETH_TX_BD_NUM_WIDTH_0 8
`define ETH_CTRLMODER_WIDTH_0 3
`define ETH_MIIMODER_WIDTH_0 8
`define ETH_MIIMODER_WIDTH_1 1
`define ETH_MIICOMMAND_WIDTH_0 3
`define ETH_MIIADDRESS_WIDTH_0 5
`define ETH_MIIADDRESS_WIDTH_1 5
`define ETH_MIITX_DATA_WIDTH_0 8
`define ETH_MIITX_DATA_WIDTH_1 8
`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB
`define ETH_MIISTATUS_WIDTH 3 // not written from WB
`define ETH_MAC_ADDR0_WIDTH_0 8
`define ETH_MAC_ADDR0_WIDTH_1 8
`define ETH_MAC_ADDR0_WIDTH_2 8
`define ETH_MAC_ADDR0_WIDTH_3 8
`define ETH_MAC_ADDR1_WIDTH_0 8
`define ETH_MAC_ADDR1_WIDTH_1 8
`define ETH_HASH0_WIDTH_0 8
`define ETH_HASH0_WIDTH_1 8
`define ETH_HASH0_WIDTH_2 8
`define ETH_HASH0_WIDTH_3 8
`define ETH_HASH1_WIDTH_0 8
`define ETH_HASH1_WIDTH_1 8
`define ETH_HASH1_WIDTH_2 8
`define ETH_HASH1_WIDTH_3 8
`define ETH_TX_CTRL_WIDTH_0 8
`define ETH_TX_CTRL_WIDTH_1 8
`define ETH_TX_CTRL_WIDTH_2 1
`define ETH_RX_CTRL_WIDTH_0 8
`define ETH_RX_CTRL_WIDTH_1 8
 
 
// Outputs are registered (uncomment when needed)
`define ETH_REGISTERED_OUTPUTS
 
// Settings for TX FIFO
`define ETH_TX_FIFO_DATA_WIDTH 32
 
// Defines for ethernet TX fifo size - impacts FPGA resource usage
 
//`define ETH_TX_64BYTE_FIFO // 64 byte TX buffer - uncomment this
//`define ETH_TX_128BYTE_FIFO // 128 byte TX buffer - uncomment this
`define ETH_TX_256BYTE_FIFO // 256 byte TX buffer - uncomment this
//`define ETH_TX_512BYTE_FIFO // 512 byte TX buffer - uncomment this
//`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this
 
`ifdef ETH_TX_FULL_PACKET_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_DEPTH 375
`endif
`ifdef ETH_TX_1KBYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_DEPTH 256
`endif
`ifdef ETH_TX_512BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_DEPTH 128
`endif
`ifdef ETH_TX_256BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 6
`define ETH_TX_FIFO_DEPTH 64
`endif
`ifdef ETH_TX_128BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_DEPTH 32
`endif
`ifdef ETH_TX_128BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 4
`define ETH_TX_FIFO_DEPTH 16
`endif
 
 
 
 
// Settings for RX FIFO
//`define ETH_RX_FIFO_CNT_WIDTH 8
//`define ETH_RX_FIFO_DEPTH 256
//`define ETH_RX_FIFO_CNT_WIDTH 7
`define ETH_RX_FIFO_DEPTH 128
`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_DEPTH 64
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 32
//`define ETH_RX_FIFO_CNT_WIDTH 4
//`define ETH_RX_FIFO_DEPTH 16
 
`define ETH_RX_FIFO_DATA_WIDTH 32
 
// Burst length
`define BURST_4BEAT
`ifdef BURST_4BEAT
`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH
`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH
`endif
 
//`define ETH_BURST_LENGTH 32 // Change also ETH_BURST_CNT_WIDTH
//`define ETH_BURST_CNT_WIDTH 7 // The counter must be width enough to count to ETH_BURST_LENGTH
 
// Undefine this to enable bursting for RX (writing to memory)
`define ETH_RX_BURST_EN
 
// WISHBONE interface is Revision B3 compliant (uncomment when needed)
`define ETH_WISHBONE_B3
 
// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on
//`define TXBD_POLL
 
// Define this to allow reading of the Wishbone control state machine on reg
// address 0x58
//`define WISHBONE_DEBUG
/xilinx/atlys/rtl/verilog/include/i2c_master_slave_defines.v
0,0 → 1,66
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master controller defines ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: i2c_master_defines.v,v 1.3 2001-11-05 11:59:25 rherveille Exp $
//
// $Date: 2001-11-05 11:59:25 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
 
 
// I2C registers wishbone addresses
 
// bitcontroller states
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
 
`define I2C_SLAVE_CMD_WRITE 2'b01
`define I2C_SLAVE_CMD_READ 2'b10
`define I2C_SLAVE_CMD_NOP 2'b00
 
 
 
/xilinx/atlys/rtl/verilog/include/dbg_cpu_defines.v
0,0 → 1,85
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_cpu_defines.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor (igorm@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// Defining length of the command
`define DBG_CPU_CMD_LEN 3'd4
`define DBG_CPU_CMD_CNT_WIDTH 3
 
// Defining length of the access_type field
`define DBG_CPU_ACC_TYPE_LEN 4
 
// Defining length of the address
`define DBG_CPU_ADR_LEN 32
 
// Defining length of the length register
`define DBG_CPU_LEN_LEN 16
 
// Defining total length of the DR needed
`define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
// Defining length of the CRC
`define DBG_CPU_CRC_LEN 6'd32
`define DBG_CPU_CRC_CNT_WIDTH 6
 
// Defining length of status
`define DBG_CPU_STATUS_LEN 3'd4
`define DBG_CPU_STATUS_CNT_WIDTH 3
 
// Defining length of the data
//define DBG_CPU_DATA_CNT_WIDTH `DBG_CPU_LEN_LEN + 3
`define DBG_CPU_DATA_CNT_WIDTH 19
//define DBG_CPU_DATA_CNT_LIM_WIDTH `DBG_CPU_LEN_LEN
`define DBG_CPU_DATA_CNT_LIM_WIDTH 16
// Defining length of the control register
`define DBG_CPU_CTRL_LEN 2
 
//Defining commands
`define DBG_CPU_GO 4'h0
`define DBG_CPU_RD_COMM 4'h1
`define DBG_CPU_WR_COMM 4'h2
`define DBG_CPU_RD_CTRL 4'h3
`define DBG_CPU_WR_CTRL 4'h4
 
// Defining access types for wishbone
`define DBG_CPU_WRITE 4'h2
`define DBG_CPU_READ 4'h6
 
 
/xilinx/atlys/rtl/verilog/include/or1200_defines.v
0,0 → 1,1822
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's definitions ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Defines for the OR1200 core ////
//// ////
//// To Do: ////
//// - add parameters that are missing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_defines.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Defines added, bugs fixed.
 
//
// Dump VCD
//
//`define OR1200_VCD_DUMP
 
//
// Generate debug messages during simulation
//
//`define OR1200_VERBOSE
 
// `define OR1200_ASIC
////////////////////////////////////////////////////////
//
// Typical configuration for an ASIC
//
`ifdef OR1200_ASIC
 
//
// Target ASIC memories
//
//`define OR1200_ARTISAN_SSP
//`define OR1200_ARTISAN_SDP
//`define OR1200_ARTISAN_STP
`define OR1200_VIRTUALSILICON_SSP
//`define OR1200_VIRTUALSILICON_STP_T1
//`define OR1200_VIRTUALSILICON_STP_T2
 
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
 
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
 
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
 
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
 
//
// Select between ASIC optimized and generic multiplier
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
 
//
// Size/type of insn/data cache if implemented
//
// `define OR1200_IC_1W_512B
// `define OR1200_IC_1W_4KB
`define OR1200_IC_1W_8KB
// `define OR1200_DC_1W_4KB
`define OR1200_DC_1W_8KB
 
`else
 
 
/////////////////////////////////////////////////////////
//
// Typical configuration for an FPGA
//
 
//
// Target FPGA memories
//
//`define OR1200_ALTERA_LPM
//`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
// Generic models should infer RAM blocks at synthesis time (not only effects
// single port ram.)
`define OR1200_GENERIC
 
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
 
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
 
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
 
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
 
//
// Select between ASIC and generic multiplier
//
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
 
//
// Size/type of insn/data cache if implemented
// (consider available FPGA memory resources)
//
//`define OR1200_IC_1W_512B
//`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_8KB
//`define OR1200_IC_1W_16KB
`define OR1200_IC_1W_32KB
//`define OR1200_DC_1W_4KB
//`define OR1200_DC_1W_8KB
//`define OR1200_DC_1W_16KB
`define OR1200_DC_1W_32KB
 
`endif
 
 
//////////////////////////////////////////////////////////
//
// Do not change below unless you know what you are doing
//
 
//
// Reset active low
//
//`define OR1200_RST_ACT_LOW
 
//
// Enable RAM BIST
//
// At the moment this only works for Virtual Silicon
// single port RAMs. For other RAMs it has not effect.
// Special wrapper for VS RAMs needs to be provided
// with scan flops to facilitate bist scan.
//
//`define OR1200_BIST
 
//
// Register OR1200 WISHBONE outputs
// (must be defined/enabled)
//
`define OR1200_REGISTERED_OUTPUTS
 
//
// Register OR1200 WISHBONE inputs
//
// (must be undefined/disabled)
//
//`define OR1200_REGISTERED_INPUTS
 
//
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
//
 
//
// WISHBONE retry counter range
//
// 2^value range for retry counter. Retry counter
// is activated whenever *wb_rty_i is asserted and
// until retry counter expires, corresponding
// WISHBONE interface is deactivated.
//
// To disable retry counters and *wb_rty_i all together,
// undefine this macro.
//
//`define OR1200_WB_RETRY 7
 
//
// WISHBONE Consecutive Address Burst
//
// This was used prior to WISHBONE B3 specification
// to identify bursts. It is no longer needed but
// remains enabled for compatibility with old designs.
//
// To remove *wb_cab_o ports undefine this macro.
//
//`define OR1200_WB_CAB
 
//
// WISHBONE B3 compatible interface
//
// This follows the WISHBONE B3 specification.
// It is not enabled by default because most
// designs still don't use WB b3.
//
// To enable *wb_cti_o/*wb_bte_o ports,
// define this macro.
//
`define OR1200_WB_B3
 
//
// LOG all WISHBONE accesses
//
`define OR1200_LOG_WB_ACCESS
 
//
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
//
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
 
//
// Enables default statement in some case blocks
// and disables Synopsys synthesis directive full_case
//
// By default it is enabled. When disabled it
// can increase clock frequency.
//
`define OR1200_CASE_DEFAULT
 
//
// Operand width / register file address width
//
// (DO NOT CHANGE)
//
`define OR1200_OPERAND_WIDTH 32
`define OR1200_REGFILE_ADDR_WIDTH 5
 
//
// l.add/l.addi/l.and and optional l.addc/l.addic
// also set (compare) flag when result of their
// operation equals zero
//
// At the time of writing this, default or32
// C/C++ compiler doesn't generate code that
// would benefit from this optimization.
//
// By default this optimization is disabled to
// save area.
//
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
 
//
// Implement l.addc/l.addic instructions
//
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// to save area.
//
`define OR1200_IMPL_ADDC
 
//
// Implement l.sub instruction
//
// By default implementation of l.sub instructions
// is enabled to be compliant with the simulator.
// If you don't use carry bit, then disable
// implementation to save area.
//
`define OR1200_IMPL_SUB
 
//
// Implement carry bit SR[CY]
//
//
// By default implementation of SR[CY] is enabled
// to be compliant with the simulator. However SR[CY]
// is explicitly only used by l.addc/l.addic/l.sub
// instructions and if these three insns are not
// implemented there is not much point having SR[CY].
//
`define OR1200_IMPL_CY
 
//
// Implement carry bit SR[OV]
//
// Compiler doesn't use this, but other code may like
// to.
//
`define OR1200_IMPL_OV
 
//
// Implement carry bit SR[OVE]
//
// Overflow interrupt indicator. When enabled, SR[OV] flag
// does not remain asserted after exception.
//
`define OR1200_IMPL_OVE
 
 
//
// Implement rotate in the ALU
//
// At the time of writing this, or32
// C/C++ compiler doesn't generate rotate
// instructions. However or32 assembler
// can assemble code that uses rotate insn.
// This means that rotate instructions
// must be used manually inserted.
//
// By default implementation of rotate
// is disabled to save area and increase
// clock frequency.
//
//`define OR1200_IMPL_ALU_ROTATE
 
//
// Type of ALU compare to implement
//
// Try either one to find what yields
// higher clock frequencyin your case.
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
 
//
// Implement Find First/Last '1'
//
`define OR1200_IMPL_ALU_FFL1
 
//
// Implement l.cust5 ALU instruction
//
//`define OR1200_IMPL_ALU_CUST5
 
//
// Implement l.extXs and l.extXz instructions
//
`define OR1200_IMPL_ALU_EXT
 
//
// Implement multiplier
//
// By default multiplier is implemented
//
`define OR1200_MULT_IMPLEMENTED
 
//
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier (non-serial) needs to be
// implemented.
//
`define OR1200_MAC_IMPLEMENTED
 
//
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area.
//
//
`define OR1200_DIV_IMPLEMENTED
 
//
// Serial multiplier.
//
//`define OR1200_MULT_SERIAL
 
//
// Serial divider.
// Uncomment to use a serial divider, otherwise will
// be a generic parallel implementation.
//
`define OR1200_DIV_SERIAL
 
//
// Implement HW Single Precision FPU
//
`define OR1200_FPU_IMPLEMENTED
 
//
// Clock ratio RISC clock versus WB clock
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// both defines
//
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
// and use clmode to set ratio
//
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
// clmode to set ratio
//
//`define OR1200_CLKDIV_2_SUPPORTED
//`define OR1200_CLKDIV_4_SUPPORTED
 
//
// Type of register file RAM
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
//`define OR1200_RFRAM_TWOPORT
//
// Memory macro dual port (see or1200_dpram.v)
`define OR1200_RFRAM_DUALPORT
 
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
//`define OR1200_RFRAM_GENERIC
// Generic register file supports - 16 registers
`ifdef OR1200_RFRAM_GENERIC
// `define OR1200_RFRAM_16REG
`endif
 
//
// Type of mem2reg aligner to implement.
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// circuit, however with today tools it will
// most probably give you slower circuit.
//
`define OR1200_IMPL_MEM2REG1
//`define OR1200_IMPL_MEM2REG2
 
//
// Reset value and event
//
`ifdef OR1200_RST_ACT_LOW
`define OR1200_RST_VALUE (1'b0)
`define OR1200_RST_EVENT negedge
`else
`define OR1200_RST_VALUE (1'b1)
`define OR1200_RST_EVENT posedge
`endif
 
//
// ALUOPs
//
`define OR1200_ALUOP_WIDTH 5
`define OR1200_ALUOP_NOP 5'b0_0100
/* LS-nibble encodings correspond to bits [3:0] of instruction */
`define OR1200_ALUOP_ADD 5'b0_0000 // 0
`define OR1200_ALUOP_ADDC 5'b0_0001 // 1
`define OR1200_ALUOP_SUB 5'b0_0010 // 2
`define OR1200_ALUOP_AND 5'b0_0011 // 3
`define OR1200_ALUOP_OR 5'b0_0100 // 4
`define OR1200_ALUOP_XOR 5'b0_0101 // 5
`define OR1200_ALUOP_MUL 5'b0_0110 // 6
`define OR1200_ALUOP_RESERVED 5'b0_0111 // 7
`define OR1200_ALUOP_SHROT 5'b0_1000 // 8
`define OR1200_ALUOP_DIV 5'b0_1001 // 9
`define OR1200_ALUOP_DIVU 5'b0_1010 // a
`define OR1200_ALUOP_MULU 5'b0_1011 // b
`define OR1200_ALUOP_EXTHB 5'b0_1100 // c
`define OR1200_ALUOP_EXTW 5'b0_1101 // d
`define OR1200_ALUOP_CMOV 5'b0_1110 // e
`define OR1200_ALUOP_FFL1 5'b0_1111 // f
 
/* Values sent to ALU from decode unit - not defined by ISA */
`define OR1200_ALUOP_COMP 5'b1_0000 // Comparison
`define OR1200_ALUOP_MOVHI 5'b1_0001 // Move-high
`define OR1200_ALUOP_CUST5 5'b1_0010 // l.cust5
 
// ALU instructions second opcode field
`define OR1200_ALUOP2_POS 9:6
`define OR1200_ALUOP2_WIDTH 4
 
//
// MACOPs
//
`define OR1200_MACOP_WIDTH 3
`define OR1200_MACOP_NOP 3'b000
`define OR1200_MACOP_MAC 3'b001
`define OR1200_MACOP_MSB 3'b010
 
//
// Shift/rotate ops
//
`define OR1200_SHROTOP_WIDTH 4
`define OR1200_SHROTOP_NOP 4'd0
`define OR1200_SHROTOP_SLL 4'd0
`define OR1200_SHROTOP_SRL 4'd1
`define OR1200_SHROTOP_SRA 4'd2
`define OR1200_SHROTOP_ROR 4'd3
 
//
// Zero/Sign Extend ops
//
`define OR1200_EXTHBOP_WIDTH 4
`define OR1200_EXTHBOP_BS 4'h1
`define OR1200_EXTHBOP_HS 4'h0
`define OR1200_EXTHBOP_BZ 4'h3
`define OR1200_EXTHBOP_HZ 4'h2
`define OR1200_EXTWOP_WIDTH 4
`define OR1200_EXTWOP_WS 4'h0
`define OR1200_EXTWOP_WZ 4'h1
 
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 3
`define OR1200_ONE_CYCLE 3'd0
`define OR1200_TWO_CYCLES 3'd1
 
// Execution control which will "wait on" a module to finish
`define OR1200_WAIT_ON_WIDTH 2
`define OR1200_WAIT_ON_NOTHING `OR1200_WAIT_ON_WIDTH'd0
`define OR1200_WAIT_ON_MULTMAC `OR1200_WAIT_ON_WIDTH'd1
`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd2
`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd3
 
 
// Operand MUX selects
`define OR1200_SEL_WIDTH 2
`define OR1200_SEL_RF 2'd0
`define OR1200_SEL_IMM 2'd1
`define OR1200_SEL_EX_FORW 2'd2
`define OR1200_SEL_WB_FORW 2'd3
 
//
// BRANCHOPs
//
`define OR1200_BRANCHOP_WIDTH 3
`define OR1200_BRANCHOP_NOP 3'd0
`define OR1200_BRANCHOP_J 3'd1
`define OR1200_BRANCHOP_JR 3'd2
`define OR1200_BRANCHOP_BAL 3'd3
`define OR1200_BRANCHOP_BF 3'd4
`define OR1200_BRANCHOP_BNF 3'd5
`define OR1200_BRANCHOP_RFE 3'd6
 
//
// LSUOPs
//
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define OR1200_LSUOP_WIDTH 4
`define OR1200_LSUOP_NOP 4'b0000
`define OR1200_LSUOP_LBZ 4'b0010
`define OR1200_LSUOP_LBS 4'b0011
`define OR1200_LSUOP_LHZ 4'b0100
`define OR1200_LSUOP_LHS 4'b0101
`define OR1200_LSUOP_LWZ 4'b0110
`define OR1200_LSUOP_LWS 4'b0111
`define OR1200_LSUOP_LD 4'b0001
`define OR1200_LSUOP_SD 4'b1000
`define OR1200_LSUOP_SB 4'b1010
`define OR1200_LSUOP_SH 4'b1100
`define OR1200_LSUOP_SW 4'b1110
 
// Number of bits of load/store EA precalculated in ID stage
// for balancing ID and EX stages.
//
// Valid range: 2,3,...,30,31
`define OR1200_LSUEA_PRECALC 2
 
// FETCHOPs
`define OR1200_FETCHOP_WIDTH 1
`define OR1200_FETCHOP_NOP 1'b0
`define OR1200_FETCHOP_LW 1'b1
 
//
// Register File Write-Back OPs
//
// Bit 0: register file write enable
// Bits 3-1: write-back mux selects
//
`define OR1200_RFWBOP_WIDTH 4
`define OR1200_RFWBOP_NOP 4'b0000
`define OR1200_RFWBOP_ALU 3'b000
`define OR1200_RFWBOP_LSU 3'b001
`define OR1200_RFWBOP_SPRS 3'b010
`define OR1200_RFWBOP_LR 3'b011
`define OR1200_RFWBOP_FPU 3'b100
 
// Compare instructions
`define OR1200_COP_SFEQ 3'b000
`define OR1200_COP_SFNE 3'b001
`define OR1200_COP_SFGT 3'b010
`define OR1200_COP_SFGE 3'b011
`define OR1200_COP_SFLT 3'b100
`define OR1200_COP_SFLE 3'b101
`define OR1200_COP_X 3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH 4
 
//
// FP OPs
//
// MSbit indicates FPU operation valid
//
`define OR1200_FPUOP_WIDTH 8
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
`define OR1200_FPUOP_CYCLES 3'd4
// FP instruction is double precision if bit 4 is set. We're a 32-bit
// implementation thus do not support double precision FP
`define OR1200_FPUOP_DOUBLE_BIT 4
`define OR1200_FPUOP_ADD 8'b0000_0000
`define OR1200_FPUOP_SUB 8'b0000_0001
`define OR1200_FPUOP_MUL 8'b0000_0010
`define OR1200_FPUOP_DIV 8'b0000_0011
`define OR1200_FPUOP_ITOF 8'b0000_0100
`define OR1200_FPUOP_FTOI 8'b0000_0101
`define OR1200_FPUOP_REM 8'b0000_0110
`define OR1200_FPUOP_RESERVED 8'b0000_0111
// FP Compare instructions
`define OR1200_FPCOP_SFEQ 8'b0000_1000
`define OR1200_FPCOP_SFNE 8'b0000_1001
`define OR1200_FPCOP_SFGT 8'b0000_1010
`define OR1200_FPCOP_SFGE 8'b0000_1011
`define OR1200_FPCOP_SFLT 8'b0000_1100
`define OR1200_FPCOP_SFLE 8'b0000_1101
 
//
// TAGs for instruction bus
//
`define OR1200_ITAG_IDLE 4'h0 // idle bus
`define OR1200_ITAG_NI 4'h1 // normal insn
`define OR1200_ITAG_BE 4'hb // Bus error exception
`define OR1200_ITAG_PE 4'hc // Page fault exception
`define OR1200_ITAG_TE 4'hd // TLB miss exception
 
//
// TAGs for data bus
//
`define OR1200_DTAG_IDLE 4'h0 // idle bus
`define OR1200_DTAG_ND 4'h1 // normal data
`define OR1200_DTAG_AE 4'ha // Alignment exception
`define OR1200_DTAG_BE 4'hb // Bus error exception
`define OR1200_DTAG_PE 4'hc // Page fault exception
`define OR1200_DTAG_TE 4'hd // TLB miss exception
 
 
//////////////////////////////////////////////
//
// ORBIS32 ISA specifics
//
 
// SHROT_OP position in machine word
`define OR1200_SHROTOP_POS 7:6
 
//
// Instruction opcode groups (basic)
//
`define OR1200_OR32_J 6'b000000
`define OR1200_OR32_JAL 6'b000001
`define OR1200_OR32_BNF 6'b000011
`define OR1200_OR32_BF 6'b000100
`define OR1200_OR32_NOP 6'b000101
`define OR1200_OR32_MOVHI 6'b000110
`define OR1200_OR32_MACRC 6'b000110
`define OR1200_OR32_XSYNC 6'b001000
`define OR1200_OR32_RFE 6'b001001
/* */
`define OR1200_OR32_JR 6'b010001
`define OR1200_OR32_JALR 6'b010010
`define OR1200_OR32_MACI 6'b010011
/* */
`define OR1200_OR32_LWZ 6'b100001
`define OR1200_OR32_LBZ 6'b100011
`define OR1200_OR32_LBS 6'b100100
`define OR1200_OR32_LHZ 6'b100101
`define OR1200_OR32_LHS 6'b100110
`define OR1200_OR32_ADDI 6'b100111
`define OR1200_OR32_ADDIC 6'b101000
`define OR1200_OR32_ANDI 6'b101001
`define OR1200_OR32_ORI 6'b101010
`define OR1200_OR32_XORI 6'b101011
`define OR1200_OR32_MULI 6'b101100
`define OR1200_OR32_MFSPR 6'b101101
`define OR1200_OR32_SH_ROTI 6'b101110
`define OR1200_OR32_SFXXI 6'b101111
/* */
`define OR1200_OR32_MTSPR 6'b110000
`define OR1200_OR32_MACMSB 6'b110001
`define OR1200_OR32_FLOAT 6'b110010
/* */
`define OR1200_OR32_SW 6'b110101
`define OR1200_OR32_SB 6'b110110
`define OR1200_OR32_SH 6'b110111
`define OR1200_OR32_ALU 6'b111000
`define OR1200_OR32_SFXX 6'b111001
`define OR1200_OR32_CUST5 6'b111100
 
/////////////////////////////////////////////////////
//
// Exceptions
//
 
//
// Exception vectors per OR1K architecture:
// 0xPPPPP100 - reset
// 0xPPPPP200 - bus error
// ... etc
// where P represents exception prefix.
//
// Exception vectors can be customized as per
// the following formula:
// 0xPPPPPNVV - exception N
//
// P represents exception prefix
// N represents exception N
// VV represents length of the individual vector space,
// usually it is 8 bits wide and starts with all bits zero
//
 
//
// PPPPP and VV parts
//
// Sum of these two defines needs to be 28
//
`define OR1200_EXCEPT_EPH0_P 20'h00000
`define OR1200_EXCEPT_EPH1_P 20'hF0000
`define OR1200_EXCEPT_V 8'h00
 
//
// N part width
//
`define OR1200_EXCEPT_WIDTH 4
 
//
// Definition of exception vectors
//
// To avoid implementation of a certain exception,
// simply comment out corresponding line
//
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_FLOAT `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
 
 
/////////////////////////////////////////////////////
//
// SPR groups
//
 
// Bits that define the group
`define OR1200_SPR_GROUP_BITS 15:11
 
// Width of the group bits
`define OR1200_SPR_GROUP_WIDTH 5
 
// Bits that define offset inside the group
`define OR1200_SPR_OFS_BITS 10:0
 
// List of groups
`define OR1200_SPR_GROUP_SYS 5'd00
`define OR1200_SPR_GROUP_DMMU 5'd01
`define OR1200_SPR_GROUP_IMMU 5'd02
`define OR1200_SPR_GROUP_DC 5'd03
`define OR1200_SPR_GROUP_IC 5'd04
`define OR1200_SPR_GROUP_MAC 5'd05
`define OR1200_SPR_GROUP_DU 5'd06
`define OR1200_SPR_GROUP_PM 5'd08
`define OR1200_SPR_GROUP_PIC 5'd09
`define OR1200_SPR_GROUP_TT 5'd10
`define OR1200_SPR_GROUP_FPU 5'd11
 
/////////////////////////////////////////////////////
//
// System group
//
 
//
// System registers
//
`define OR1200_SPR_CFGR 7'd0
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
`define OR1200_SPR_NPC 11'd16
`define OR1200_SPR_SR 11'd17
`define OR1200_SPR_PPC 11'd18
`define OR1200_SPR_FPCSR 11'd20
`define OR1200_SPR_EPCR 11'd32
`define OR1200_SPR_EEAR 11'd48
`define OR1200_SPR_ESR 11'd64
 
//
// SR bits
//
`define OR1200_SR_WIDTH 17
`define OR1200_SR_SM 0
`define OR1200_SR_TEE 1
`define OR1200_SR_IEE 2
`define OR1200_SR_DCE 3
`define OR1200_SR_ICE 4
`define OR1200_SR_DME 5
`define OR1200_SR_IME 6
`define OR1200_SR_LEE 7
`define OR1200_SR_CE 8
`define OR1200_SR_F 9
`define OR1200_SR_CY 10 // Optional
`define OR1200_SR_OV 11 // Optional
`define OR1200_SR_OVE 12 // Optional
`define OR1200_SR_DSX 13 // Unused
`define OR1200_SR_EPH 14
`define OR1200_SR_FO 15
`define OR1200_SR_TED 16
`define OR1200_SR_CID 31:28 // Unimplemented
 
//
// Bits that define offset inside the group
//
`define OR1200_SPROFS_BITS 10:0
 
//
// Default Exception Prefix
//
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b0
 
 
//
// FPCSR bits
//
`define OR1200_FPCSR_WIDTH 12
`define OR1200_FPCSR_FPEE 0
`define OR1200_FPCSR_RM 2:1
`define OR1200_FPCSR_OVF 3
`define OR1200_FPCSR_UNF 4
`define OR1200_FPCSR_SNF 5
`define OR1200_FPCSR_QNF 6
`define OR1200_FPCSR_ZF 7
`define OR1200_FPCSR_IXF 8
`define OR1200_FPCSR_IVF 9
`define OR1200_FPCSR_INF 10
`define OR1200_FPCSR_DZF 11
`define OR1200_FPCSR_RES 31:12
 
/////////////////////////////////////////////////////
//
// Power Management (PM)
//
 
// Define it if you want PM implemented
//`define OR1200_PM_IMPLEMENTED
 
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_DCGE 6
`define OR1200_PM_PMR_UNUSED 31:7
 
// PMR offset inside PM group of registers
`define OR1200_PM_OFS_PMR 11'b0
 
// PM group
`define OR1200_SPRGRP_PM 5'd8
 
// Define if PMR can be read/written at any address inside PM group
`define OR1200_PM_PARTIAL_DECODING
 
// Define if reading PMR is allowed
`define OR1200_PM_READREGS
 
// Define if unused PMR bits should be zero
`define OR1200_PM_UNUSED_ZERO
 
 
/////////////////////////////////////////////////////
//
// Debug Unit (DU)
//
 
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
 
//
// Define if you want HW Breakpoints
// (if HW breakpoints are not implemented
// only default software trapping is
// possible with l.trap insn - this is
// however already enough for use
// with or32 gdb)
//
//`define OR1200_DU_HWBKPTS
 
// Number of DVR/DCR pairs if HW breakpoints enabled
// Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number !
// DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS
`define OR1200_DU_DVRDCR_PAIRS 8
 
// Define if you want trace buffer
// (for now only available for Xilinx Virtex FPGAs)
//`define OR1200_DU_TB_IMPLEMENTED
 
 
//
// Address offsets of DU registers inside DU group
//
// To not implement a register, doq not define its address
//
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DVR0 11'd0
`define OR1200_DU_DVR1 11'd1
`define OR1200_DU_DVR2 11'd2
`define OR1200_DU_DVR3 11'd3
`define OR1200_DU_DVR4 11'd4
`define OR1200_DU_DVR5 11'd5
`define OR1200_DU_DVR6 11'd6
`define OR1200_DU_DVR7 11'd7
`define OR1200_DU_DCR0 11'd8
`define OR1200_DU_DCR1 11'd9
`define OR1200_DU_DCR2 11'd10
`define OR1200_DU_DCR3 11'd11
`define OR1200_DU_DCR4 11'd12
`define OR1200_DU_DCR5 11'd13
`define OR1200_DU_DCR6 11'd14
`define OR1200_DU_DCR7 11'd15
`endif
`define OR1200_DU_DMR1 11'd16
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DMR2 11'd17
`define OR1200_DU_DWCR0 11'd18
`define OR1200_DU_DWCR1 11'd19
`endif
`define OR1200_DU_DSR 11'd20
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1??
`define OR1200_DU_TBIM 11'h2??
`define OR1200_DU_TBAR 11'h3??
`define OR1200_DU_TBTS 11'h4??
`endif
 
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 10:0
 
// DCR bits
`define OR1200_DU_DCR_DP 0
`define OR1200_DU_DCR_CC 3:1
`define OR1200_DU_DCR_SC 4
`define OR1200_DU_DCR_CT 7:5
 
// DMR1 bits
`define OR1200_DU_DMR1_CW0 1:0
`define OR1200_DU_DMR1_CW1 3:2
`define OR1200_DU_DMR1_CW2 5:4
`define OR1200_DU_DMR1_CW3 7:6
`define OR1200_DU_DMR1_CW4 9:8
`define OR1200_DU_DMR1_CW5 11:10
`define OR1200_DU_DMR1_CW6 13:12
`define OR1200_DU_DMR1_CW7 15:14
`define OR1200_DU_DMR1_CW8 17:16
`define OR1200_DU_DMR1_CW9 19:18
`define OR1200_DU_DMR1_CW10 21:20
`define OR1200_DU_DMR1_ST 22
`define OR1200_DU_DMR1_BT 23
`define OR1200_DU_DMR1_DXFW 24
`define OR1200_DU_DMR1_ETE 25
 
// DMR2 bits
`define OR1200_DU_DMR2_WCE0 0
`define OR1200_DU_DMR2_WCE1 1
`define OR1200_DU_DMR2_AWTC 12:2
`define OR1200_DU_DMR2_WGB 23:13
 
// DWCR bits
`define OR1200_DU_DWCR_COUNT 15:0
`define OR1200_DU_DWCR_MATCH 31:16
 
// DSR bits
`define OR1200_DU_DSR_WIDTH 14
`define OR1200_DU_DSR_RSTE 0
`define OR1200_DU_DSR_BUSEE 1
`define OR1200_DU_DSR_DPFE 2
`define OR1200_DU_DSR_IPFE 3
`define OR1200_DU_DSR_TTE 4
`define OR1200_DU_DSR_AE 5
`define OR1200_DU_DSR_IIE 6
`define OR1200_DU_DSR_IE 7
`define OR1200_DU_DSR_DME 8
`define OR1200_DU_DSR_IME 9
`define OR1200_DU_DSR_RE 10
`define OR1200_DU_DSR_SCE 11
`define OR1200_DU_DSR_FPE 12
`define OR1200_DU_DSR_TE 13
 
// DRR bits
`define OR1200_DU_DRR_RSTE 0
`define OR1200_DU_DRR_BUSEE 1
`define OR1200_DU_DRR_DPFE 2
`define OR1200_DU_DRR_IPFE 3
`define OR1200_DU_DRR_TTE 4
`define OR1200_DU_DRR_AE 5
`define OR1200_DU_DRR_IIE 6
`define OR1200_DU_DRR_IE 7
`define OR1200_DU_DRR_DME 8
`define OR1200_DU_DRR_IME 9
`define OR1200_DU_DRR_RE 10
`define OR1200_DU_DRR_SCE 11
`define OR1200_DU_DRR_FPE 12
`define OR1200_DU_DRR_TE 13
 
// Define if reading DU regs is allowed
`define OR1200_DU_READREGS
 
// Define if unused DU registers bits should be zero
`define OR1200_DU_UNUSED_ZERO
 
// Define if IF/LSU status is not needed by devel i/f
`define OR1200_DU_STATUS_UNIMPLEMENTED
 
/////////////////////////////////////////////////////
//
// Programmable Interrupt Controller (PIC)
//
 
// Define it if you want PIC implemented
`define OR1200_PIC_IMPLEMENTED
 
// Define number of interrupt inputs (2-31)
`define OR1200_PIC_INTS 31
 
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
 
// Position of offset bits inside SPR address
`define OR1200_PICOFS_BITS 1:0
 
// Define if you want these PIC registers to be implemented
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICSR
 
// Define if reading PIC registers is allowed
`define OR1200_PIC_READREGS
 
// Define if unused PIC register bits should be zero
`define OR1200_PIC_UNUSED_ZERO
 
 
/////////////////////////////////////////////////////
//
// Tick Timer (TT)
//
 
// Define it if you want TT implemented
`define OR1200_TT_IMPLEMENTED
 
// Address offsets of TT registers inside TT group
`define OR1200_TT_OFS_TTMR 1'd0
`define OR1200_TT_OFS_TTCR 1'd1
 
// Position of offset bits inside SPR group
`define OR1200_TTOFS_BITS 0
 
// Define if you want these TT registers to be implemented
`define OR1200_TT_TTMR
`define OR1200_TT_TTCR
 
// TTMR bits
`define OR1200_TT_TTMR_TP 27:0
`define OR1200_TT_TTMR_IP 28
`define OR1200_TT_TTMR_IE 29
`define OR1200_TT_TTMR_M 31:30
 
// Define if reading TT registers is allowed
`define OR1200_TT_READREGS
 
 
//////////////////////////////////////////////
//
// MAC
//
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable
 
//
// Shift {MACHI,MACLO} into destination register when executing l.macrc
//
// According to architecture manual there is no shift, so default value is 0.
// However the implementation has deviated in this from the arch manual and had
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding
// (if using libmad fixed point library). Shifts are no longer default setup,
// but if you need to remain backward compatible, define your shift bits, which
// were normally
// dest_GPR = {MACHI,MACLO}[59:28]
`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility
 
 
//////////////////////////////////////////////
//
// Data MMU (DMMU)
//
 
//
// Address that selects between TLB TR and MR
//
`define OR1200_DTLB_TM_ADDR 7
 
//
// DTLBMR fields
//
`define OR1200_DTLBMR_V_BITS 0
`define OR1200_DTLBMR_CID_BITS 4:1
`define OR1200_DTLBMR_RES_BITS 11:5
`define OR1200_DTLBMR_VPN_BITS 31:13
 
//
// DTLBTR fields
//
`define OR1200_DTLBTR_CC_BITS 0
`define OR1200_DTLBTR_CI_BITS 1
`define OR1200_DTLBTR_WBC_BITS 2
`define OR1200_DTLBTR_WOM_BITS 3
`define OR1200_DTLBTR_A_BITS 4
`define OR1200_DTLBTR_D_BITS 5
`define OR1200_DTLBTR_URE_BITS 6
`define OR1200_DTLBTR_UWE_BITS 7
`define OR1200_DTLBTR_SRE_BITS 8
`define OR1200_DTLBTR_SWE_BITS 9
`define OR1200_DTLBTR_RES_BITS 11:10
`define OR1200_DTLBTR_PPN_BITS 31:13
 
//
// DTLB configuration
//
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
 
//
// Cache inhibit while DMMU is not enabled/implemented
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_DMMU_CI dcpu_adr_i[31]
 
 
//////////////////////////////////////////////
//
// Insn MMU (IMMU)
//
 
//
// Address that selects between TLB TR and MR
//
`define OR1200_ITLB_TM_ADDR 7
 
//
// ITLBMR fields
//
`define OR1200_ITLBMR_V_BITS 0
`define OR1200_ITLBMR_CID_BITS 4:1
`define OR1200_ITLBMR_RES_BITS 11:5
`define OR1200_ITLBMR_VPN_BITS 31:13
 
//
// ITLBTR fields
//
`define OR1200_ITLBTR_CC_BITS 0
`define OR1200_ITLBTR_CI_BITS 1
`define OR1200_ITLBTR_WBC_BITS 2
`define OR1200_ITLBTR_WOM_BITS 3
`define OR1200_ITLBTR_A_BITS 4
`define OR1200_ITLBTR_D_BITS 5
`define OR1200_ITLBTR_SXE_BITS 6
`define OR1200_ITLBTR_UXE_BITS 7
`define OR1200_ITLBTR_RES_BITS 11:8
`define OR1200_ITLBTR_PPN_BITS 31:13
 
//
// ITLB configuration
//
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
 
//
// Cache inhibit while IMMU is not enabled/implemented
// Note: all combinations that use icpu_adr_i cause async loop
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !icpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_IMMU_CI 1'b0
 
 
/////////////////////////////////////////////////
//
// Insn cache (IC)
//
 
// 4 for 16 byte line, 5 for 32 byte lines.
`ifdef OR1200_IC_1W_32KB
`define OR1200_ICLS 5
`else
`define OR1200_ICLS 4
`endif
 
//
// IC configurations
//
`ifdef OR1200_IC_1W_512B
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`endif
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE 12 // 4096
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
`define OR1200_ICTAG_W 21
`endif
`ifdef OR1200_IC_1W_8KB
`define OR1200_ICSIZE 13 // 8192
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
`define OR1200_ICTAG_W 20
`endif
`ifdef OR1200_IC_1W_16KB
`define OR1200_ICSIZE 14 // 16384
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 12
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
`define OR1200_ICTAG_W 19
`endif
`ifdef OR1200_IC_1W_32KB
`define OR1200_ICSIZE 15 // 32768
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 13
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 14
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
`define OR1200_ICTAG_W 18
`endif
 
 
/////////////////////////////////////////////////
//
// Data cache (DC)
//
 
// 4 for 16 bytes, 5 for 32 bytes
`ifdef OR1200_DC_1W_32KB
`define OR1200_DCLS 5
`else
`define OR1200_DCLS 4
`endif
 
// Define to enable default behavior of cache as write through
// Turning this off enabled write back statergy
//
`define OR1200_DC_WRITETHROUGH
 
// Define to enable stores from the stack not doing writethrough.
// EXPERIMENTAL
//`define OR1200_DC_NOSTACKWRITETHROUGH
 
// Data cache SPR definitions
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
// Data cache group SPR addresses
`define OR1200_SPRGRP_DC_DCCR 3'd0 // Not implemented
`define OR1200_SPRGRP_DC_DCBPR 3'd1 // Not implemented
`define OR1200_SPRGRP_DC_DCBFR 3'd2
`define OR1200_SPRGRP_DC_DCBIR 3'd3
`define OR1200_SPRGRP_DC_DCBWR 3'd4 // Not implemented
`define OR1200_SPRGRP_DC_DCBLR 3'd5 // Not implemented
 
//
// DC configurations
//
`ifdef OR1200_DC_1W_4KB
`define OR1200_DCSIZE 12 // 4096
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
`define OR1200_DCTAG_W 21
`endif
`ifdef OR1200_DC_1W_8KB
`define OR1200_DCSIZE 13 // 8192
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
`define OR1200_DCTAG_W 20
`endif
`ifdef OR1200_DC_1W_16KB
`define OR1200_DCSIZE 14 // 16384
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 12
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
`define OR1200_DCTAG_W 19
`endif
`ifdef OR1200_DC_1W_32KB
`define OR1200_DCSIZE 15 // 32768
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 13
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 14
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 15
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
`define OR1200_DCTAG_W 18
`endif
 
 
/////////////////////////////////////////////////
//
// Store buffer (SB)
//
 
//
// Store buffer
//
// It will improve performance by "caching" CPU stores
// using store buffer. This is most important for function
// prologues because DC can only work in write though mode
// and all stores would have to complete external WB writes
// to memory.
// Store buffer is between DC and data BIU.
// All stores will be stored into store buffer and immediately
// completed by the CPU, even though actual external writes
// will be performed later. As a consequence store buffer masks
// all data bus errors related to stores (data bus errors
// related to loads are delivered normally).
// All pending CPU loads will wait until store buffer is empty to
// ensure strict memory model. Right now this is necessary because
// we don't make destinction between cached and cache inhibited
// address space, so we simply empty store buffer until loads
// can begin.
//
// It makes design a bit bigger, depending what is the number of
// entries in SB FIFO. Number of entries can be changed further
// down.
//
//`define OR1200_SB_IMPLEMENTED
 
//
// Number of store buffer entries
//
// Verified number of entries are 4 and 8 entries
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
// always match 2**OR1200_SB_LOG.
// To disable store buffer, undefine
// OR1200_SB_IMPLEMENTED.
//
`define OR1200_SB_LOG 2 // 2 or 3
`define OR1200_SB_ENTRIES 4 // 4 or 8
 
 
/////////////////////////////////////////////////
//
// Quick Embedded Memory (QMEM)
//
 
//
// Quick Embedded Memory
//
// Instantiation of dedicated insn/data memory (RAM or ROM).
// Insn fetch has effective throughput 1insn / clock cycle.
// Data load takes two clock cycles / access, data store
// takes 1 clock cycle / access (if there is no insn fetch)).
// Memory instantiation is shared between insn and data,
// meaning if insn fetch are performed, data load/store
// performance will be lower.
//
// Main reason for QMEM is to put some time critical functions
// into this memory and to have predictable and fast access
// to these functions. (soft fpu, context switch, exception
// handlers, stack, etc)
//
// It makes design a bit bigger and slower. QMEM sits behind
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// used with QMEM and QMEM is seen by the CPU just like any other
// memory in the system). IC/DC are sitting behind QMEM so the
// whole design timing might be worse with QMEM implemented.
//
//`define OR1200_QMEM_IMPLEMENTED
 
//
// Base address and mask of QMEM
//
// Base address defines first address of QMEM. Mask defines
// QMEM range in address space. Actual size of QMEM is however
// determined with instantiated RAM/ROM. However bigger
// mask will reserve more address space for QMEM, but also
// make design faster, while more tight mask will take
// less address space but also make design slower. If
// instantiated RAM/ROM is smaller than space reserved with
// the mask, instatiated RAM/ROM will also be shadowed
// at higher addresses in reserved space.
//
`define OR1200_QMEM_IADDR 32'h0080_0000
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
`define OR1200_QMEM_DADDR 32'h0080_0000
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
 
//
// QMEM interface byte-select capability
//
// To enable qmem_sel* ports, define this macro.
//
//`define OR1200_QMEM_BSEL
 
//
// QMEM interface acknowledge
//
// To enable qmem_ack port, define this macro.
//
//`define OR1200_QMEM_ACK
 
/////////////////////////////////////////////////////
//
// VR, UPR and Configuration Registers
//
//
// VR, UPR and configuration registers are optional. If
// implemented, operating system can automatically figure
// out how to use the processor because it knows
// what units are available in the processor and how they
// are configured.
//
// This section must be last in or1200_defines.v file so
// that all units are already configured and thus
// configuration registers are properly set.
//
 
// Define if you want configuration registers implemented
`define OR1200_CFGR_IMPLEMENTED
 
// Define if you want full address decode inside SYS group
`define OR1200_SYS_FULL_DECODE
 
// Offsets of VR, UPR and CFGR registers
`define OR1200_SPRGRP_SYS_VR 4'h0
`define OR1200_SPRGRP_SYS_UPR 4'h1
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
 
// VR fields
`define OR1200_VR_REV_BITS 5:0
`define OR1200_VR_RES1_BITS 15:6
`define OR1200_VR_CFG_BITS 23:16
`define OR1200_VR_VER_BITS 31:24
 
// VR values
`define OR1200_VR_REV 6'h08
`define OR1200_VR_RES1 10'h000
`define OR1200_VR_CFG 8'h00
`define OR1200_VR_VER 8'h12
 
// UPR fields
`define OR1200_UPR_UP_BITS 0
`define OR1200_UPR_DCP_BITS 1
`define OR1200_UPR_ICP_BITS 2
`define OR1200_UPR_DMP_BITS 3
`define OR1200_UPR_IMP_BITS 4
`define OR1200_UPR_MP_BITS 5
`define OR1200_UPR_DUP_BITS 6
`define OR1200_UPR_PCUP_BITS 7
`define OR1200_UPR_PMP_BITS 8
`define OR1200_UPR_PICP_BITS 9
`define OR1200_UPR_TTP_BITS 10
`define OR1200_UPR_FPP_BITS 11
`define OR1200_UPR_RES1_BITS 23:12
`define OR1200_UPR_CUP_BITS 31:24
 
// UPR values
`define OR1200_UPR_UP 1'b1
`ifdef OR1200_NO_DC
`define OR1200_UPR_DCP 1'b0
`else
`define OR1200_UPR_DCP 1'b1
`endif
`ifdef OR1200_NO_IC
`define OR1200_UPR_ICP 1'b0
`else
`define OR1200_UPR_ICP 1'b1
`endif
`ifdef OR1200_NO_DMMU
`define OR1200_UPR_DMP 1'b0
`else
`define OR1200_UPR_DMP 1'b1
`endif
`ifdef OR1200_NO_IMMU
`define OR1200_UPR_IMP 1'b0
`else
`define OR1200_UPR_IMP 1'b1
`endif
`ifdef OR1200_MAC_IMPLEMENTED
`define OR1200_UPR_MP 1'b1
`else
`define OR1200_UPR_MP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_DUP 1'b1
`else
`define OR1200_UPR_DUP 1'b0
`endif
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
`ifdef OR1200_PM_IMPLEMENTED
`define OR1200_UPR_PMP 1'b1
`else
`define OR1200_UPR_PMP 1'b0
`endif
`ifdef OR1200_PIC_IMPLEMENTED
`define OR1200_UPR_PICP 1'b1
`else
`define OR1200_UPR_PICP 1'b0
`endif
`ifdef OR1200_TT_IMPLEMENTED
`define OR1200_UPR_TTP 1'b1
`else
`define OR1200_UPR_TTP 1'b0
`endif
`ifdef OR1200_FPU_IMPLEMENTED
`define OR1200_UPR_FPP 1'b1
`else
`define OR1200_UPR_FPP 1'b0
`endif
`define OR1200_UPR_RES1 12'h000
`define OR1200_UPR_CUP 8'h00
 
// CPUCFGR fields
`define OR1200_CPUCFGR_NSGF_BITS 3:0
`define OR1200_CPUCFGR_HGF_BITS 4
`define OR1200_CPUCFGR_OB32S_BITS 5
`define OR1200_CPUCFGR_OB64S_BITS 6
`define OR1200_CPUCFGR_OF32S_BITS 7
`define OR1200_CPUCFGR_OF64S_BITS 8
`define OR1200_CPUCFGR_OV64S_BITS 9
`define OR1200_CPUCFGR_RES1_BITS 31:10
 
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF 4'h0
`ifdef OR1200_RFRAM_16REG
`define OR1200_CPUCFGR_HGF 1'b1
`else
`define OR1200_CPUCFGR_HGF 1'b0
`endif
`define OR1200_CPUCFGR_OB32S 1'b1
`define OR1200_CPUCFGR_OB64S 1'b0
`ifdef OR1200_FPU_IMPLEMENTED
`define OR1200_CPUCFGR_OF32S 1'b1
`else
`define OR1200_CPUCFGR_OF32S 1'b0
`endif
 
`define OR1200_CPUCFGR_OF64S 1'b0
`define OR1200_CPUCFGR_OV64S 1'b0
`define OR1200_CPUCFGR_RES1 22'h000000
 
// DMMUCFGR fields
`define OR1200_DMMUCFGR_NTW_BITS 1:0
`define OR1200_DMMUCFGR_NTS_BITS 4:2
`define OR1200_DMMUCFGR_NAE_BITS 7:5
`define OR1200_DMMUCFGR_CRI_BITS 8
`define OR1200_DMMUCFGR_PRI_BITS 9
`define OR1200_DMMUCFGR_TEIRI_BITS 10
`define OR1200_DMMUCFGR_HTR_BITS 11
`define OR1200_DMMUCFGR_RES1_BITS 31:12
 
// DMMUCFGR values
`ifdef OR1200_NO_DMMU
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_RES1 20'h00000
`else
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_DMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl.
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_DMMUCFGR_RES1 20'h00000
`endif
 
// IMMUCFGR fields
`define OR1200_IMMUCFGR_NTW_BITS 1:0
`define OR1200_IMMUCFGR_NTS_BITS 4:2
`define OR1200_IMMUCFGR_NAE_BITS 7:5
`define OR1200_IMMUCFGR_CRI_BITS 8
`define OR1200_IMMUCFGR_PRI_BITS 9
`define OR1200_IMMUCFGR_TEIRI_BITS 10
`define OR1200_IMMUCFGR_HTR_BITS 11
`define OR1200_IMMUCFGR_RES1_BITS 31:12
 
// IMMUCFGR values
`ifdef OR1200_NO_IMMU
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_RES1 20'h00000
`else
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_IMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_IMMUCFGR_RES1 20'h00000
`endif
 
// DCCFGR fields
`define OR1200_DCCFGR_NCW_BITS 2:0
`define OR1200_DCCFGR_NCS_BITS 6:3
`define OR1200_DCCFGR_CBS_BITS 7
`define OR1200_DCCFGR_CWS_BITS 8
`define OR1200_DCCFGR_CCRI_BITS 9
`define OR1200_DCCFGR_CBIRI_BITS 10
`define OR1200_DCCFGR_CBPRI_BITS 11
`define OR1200_DCCFGR_CBLRI_BITS 12
`define OR1200_DCCFGR_CBFRI_BITS 13
`define OR1200_DCCFGR_CBWBRI_BITS 14
`define OR1200_DCCFGR_RES1_BITS 31:15
 
// DCCFGR values
`ifdef OR1200_NO_DC
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_RES1 17'h00000
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
`ifdef OR1200_DC_WRITETHROUGH
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`else
`define OR1200_DCCFGR_CWS 1'b1 // Write-back strategy
`endif
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`ifdef OR1200_DC_WRITETHROUGH
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
`else
`define OR1200_DCCFGR_CBWBRI 1'b1 // Cache block WB reg impl.
`endif
`define OR1200_DCCFGR_RES1 17'h00000
`endif
 
// ICCFGR fields
`define OR1200_ICCFGR_NCW_BITS 2:0
`define OR1200_ICCFGR_NCS_BITS 6:3
`define OR1200_ICCFGR_CBS_BITS 7
`define OR1200_ICCFGR_CWS_BITS 8
`define OR1200_ICCFGR_CCRI_BITS 9
`define OR1200_ICCFGR_CBIRI_BITS 10
`define OR1200_ICCFGR_CBPRI_BITS 11
`define OR1200_ICCFGR_CBLRI_BITS 12
`define OR1200_ICCFGR_CBFRI_BITS 13
`define OR1200_ICCFGR_CBWBRI_BITS 14
`define OR1200_ICCFGR_RES1_BITS 31:15
 
// ICCFGR values
`ifdef OR1200_NO_IC
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1 // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`endif
 
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS 3:0
`define OR1200_DCFGR_WPCI_BITS 4
`define OR1200_DCFGR_RES1_BITS 31:5
 
// DCFGR values
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DCFGR_NDP 4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`ifdef OR1200_DU_DWCR0
`define OR1200_DCFGR_WPCI 1'b1
`else
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`else
`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 27'd0
 
///////////////////////////////////////////////////////////////////////////////
// Boot Address Selection //
// //
// Allows a definable boot address, potentially different to the usual reset //
// vector to allow for power-on code to be run, if desired. //
// //
// OR1200_BOOT_ADR should be the 32-bit address of the boot location //
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2) //
// //
// For default reset behavior uncomment the settings under the "Boot 0x100" //
// comment below. //
// //
///////////////////////////////////////////////////////////////////////////////
// Boot from 0xf0000100
`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
`define OR1200_BOOT_ADR 32'hf0000100
// Boot from 0x100
//`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
//`define OR1200_BOOT_ADR 32'h00000100
/xilinx/atlys/rtl/verilog/include/orpsoc-defines.v
0,0 → 1,99
//////////////////////////////////////////////////////////////////////
//// ////
//// orpsoc-defines ////
//// ////
//// Top level ORPSoC defines file ////
//// ////
//// Included in toplevel and testbench ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
// Uncomment a `define BOARD_XYZ to configure design RTL for it.
//
// Mainly presets are for internal frequency settings, and what
// external oscillator is expected (ordb1's were made with various
// XTALs.)
//
//////////////////////////////////////////////////////////////////////
 
`define XILINX
`define XILINX_PLL
`define FPGA_BOARD_XILINX_ATLYS
`define IOCONFIG_XILINX_ATLYS
`define BOARD_CLOCK_PERIOD 10000 // 100MHz (pS accuracy for Xilinx sims.)
 
`define JTAG_DEBUG
// `define RAM_WB
`define XILINX_DDR2
`define UART0
// `define UART0_EXPHEADER
`define GPIO0
`define SPI0
// `define I2C0
// `define I2C1
`define ETH0
`define ETH0_PHY_RST
 
// end of included module defines - keep this comment line here, scripts depend on it!!
 
 
//
// Arbiter defines
//
 
// Uncomment to register things through arbiter (hopefully quicker design)
// Instruction bus arbiter
//`define ARBITER_IBUS_REGISTERING
`define ARBITER_IBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
// This has to be kind of long, as DDR2 initialisation can take a little while
// and after reset, and if this is too short we'll always get bus error.
`ifdef XILINX_DDR2
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
`else
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 6
`endif
 
// Data bus arbiter
 
//`define ARBITER_DBUS_REGISTERING
`define ARBITER_DBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`ifdef XILINX_DDR2
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
`else
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 6
`endif
 
// Byte bus (peripheral bus) arbiter
// Don't really need the watchdog here - the databus will pick it up
//`define ARBITER_BYTEBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
 
/xilinx/atlys/rtl/verilog/include/dbg_wb_defines.v
0,0 → 1,113
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_wb_defines.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor (igorm@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_wb_defines.v,v $
// Revision 1.7 2004/03/31 14:34:08 igorm
// data_cnt_lim length changed to reduce number of warnings.
//
// Revision 1.6 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.5 2004/03/22 16:35:46 igorm
// Temp version before changing dbg interface.
//
// Revision 1.4 2004/01/16 14:51:33 mohor
// cpu registers added.
//
// Revision 1.3 2004/01/08 17:53:36 mohor
// tmp version.
//
// Revision 1.2 2004/01/06 17:15:19 mohor
// temp3 version.
//
// Revision 1.1 2003/12/23 15:09:04 mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// Defining length of the command
`define DBG_WB_CMD_LEN 3'd4
`define DBG_WB_CMD_LEN_INT 4
`define DBG_WB_CMD_CNT_WIDTH 3
 
// Defining length of the access_type field
`define DBG_WB_ACC_TYPE_LEN 4
 
 
// Defining length of the address
`define DBG_WB_ADR_LEN 32
 
// Defining length of the length register
`define DBG_WB_LEN_LEN 16
 
// Defining total length of the DR needed
`define DBG_WB_DR_LEN (`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN)
 
// Defining length of the CRC
`define DBG_WB_CRC_LEN 6'd32
`define DBG_WB_CRC_CNT_WIDTH 6
 
// Defining length of status
`define DBG_WB_STATUS_LEN 3'd4
`define DBG_WB_STATUS_CNT_WIDTH 3
 
// Defining length of the data
`define DBG_WB_DATA_CNT_WIDTH (`DBG_WB_LEN_LEN + 3)
`define DBG_WB_DATA_CNT_LIM_WIDTH `DBG_WB_LEN_LEN
 
//Defining commands
`define DBG_WB_GO 4'h0
`define DBG_WB_RD_COMM 4'h1
`define DBG_WB_WR_COMM 4'h2
 
// Defining access types for wishbone
`define DBG_WB_WRITE8 4'h0
`define DBG_WB_WRITE16 4'h1
`define DBG_WB_WRITE32 4'h2
`define DBG_WB_READ8 4'h4
`define DBG_WB_READ16 4'h5
`define DBG_WB_READ32 4'h6
 
 
/xilinx/atlys/rtl/verilog/include/tap_defines.v
0,0 → 1,69
//////////////////////////////////////////////////////////////////////
//// ////
//// tap_defines.v ////
//// ////
//// ////
//// This file is part of the JTAG Test Access Port (TAP) ////
//// http://www.opencores.org/projects/jtag/ ////
//// ////
//// Author(s): ////
//// Igor Mohor (igorm@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2003 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: tap_defines.v,v $
// Revision 1.2 2004/01/27 10:00:33 mohor
// Unused registers removed.
//
// Revision 1.1 2003/12/23 14:52:14 mohor
// Directory structure changed. New version of TAP.
//
//
//
 
 
// Define IDCODE Value
`define IDCODE_VALUE 32'h14951185
 
// Length of the Instruction register
`define IR_LENGTH 4
 
// Supported Instructions
`define EXTEST 4'b0000
`define SAMPLE_PRELOAD 4'b0001
`define IDCODE 4'b0010
`define DEBUG 4'b1000
`define MBIST 4'b1001
`define BYPASS 4'b1111
 
/xilinx/atlys/rtl/verilog/include/orpsoc-params.v
0,0 → 1,165
//////////////////////////////////////////////////////////////////////
//// ////
//// orpsoc-params ////
//// ////
//// Top level ORPSoC parameters file ////
//// ////
//// Included in toplevel and testbench ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
///////////////////////////
// //
// Peripheral parameters //
// //
///////////////////////////
 
// SPI 0 params
parameter spi0_ss_width = 1;
parameter spi0_wb_adr = 8'hb0;
parameter wbs_d_spi0_data_width = 8;
parameter spi0_wb_adr_width = 3;
 
// i2c master slave params
// Slave addresses
parameter HV0_SADR = 8'h44;
parameter HV1_SADR = 8'h45;
parameter HV2_SADR = 8'h46;
parameter HV3_SADR = 8'h47;
 
// i2c 0 params
parameter i2c_0_wb_adr = 8'ha0;
parameter i2c_0_wb_adr_width = 3;
parameter wbs_d_i2c0_data_width = 8;
 
// i2c 1 params
parameter i2c_1_wb_adr = 8'ha1;
parameter i2c_1_wb_adr_width = 3;
parameter wbs_d_i2c1_data_width = 8;
 
 
// GPIO 0 params
parameter wbs_d_gpio0_data_width = 8;
parameter gpio0_wb_adr_width = 3;
parameter gpio0_io_width = 24;
parameter gpio0_wb_adr = 8'h91;
parameter gpio0_dir_reset_val = 0;
parameter gpio0_o_reset_val = 0;
 
// UART 0 params
parameter wbs_d_uart0_data_width = 8;
parameter uart0_wb_adr = 8'h90;
parameter uart0_data_width = 8;
parameter uart0_addr_width = 3;
 
// ROM
parameter wbs_i_rom0_data_width = 32;
parameter wbs_i_rom0_addr_width = 6;
parameter rom0_wb_adr = 4'hf;
 
// MC0 (SDRAM, or other)
parameter wbs_i_mc0_data_width = 32;
parameter wbs_d_mc0_data_width = 32;
 
// ETH0 defines
parameter eth0_wb_adr = 8'h92;
parameter wbs_d_eth0_data_width = 32;
parameter wbs_d_eth0_addr_width = 12;
parameter wbm_eth0_data_width = 32;
parameter wbm_eth0_addr_width = 32;
 
// Memory sizing for synthesis (small)
parameter internal_sram_mem_span = 32'h0080_0000;
parameter internal_sram_adr_width_for_span = 23;
 
//////////////////////////////////////////////////////
// //
// Wishbone bus parameters //
// //
//////////////////////////////////////////////////////
 
////////////////////////
// //
// Arbiter parameters //
// //
////////////////////////
 
parameter wb_dw = 32; // Default Wishbone full word width
parameter wb_aw = 32; // Default Wishbone full address width
 
///////////////////////////
// //
// Instruction bus //
// //
///////////////////////////
parameter ibus_arb_addr_match_width = 4;
// Slave addresses
parameter ibus_arb_slave0_adr = rom0_wb_adr; // FLASH ROM
parameter ibus_arb_slave1_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)
 
///////////////////////////
// //
// Data bus //
// //
///////////////////////////
// Has auto foward to last slave when no address hits
parameter dbus_arb_wb_addr_match_width = 8;
parameter dbus_arb_wb_num_slaves = 5;
// Slave addresses
parameter dbus_arb_slave0_adr = 4'h0; // Main memory (SDRAM/FPGA SRAM)
parameter dbus_arb_slave1_adr = eth0_wb_adr; // Ethernet 0
 
///////////////////////////////
// //
// Byte-wide peripheral bus //
// //
///////////////////////////////
parameter bbus_arb_wb_addr_match_width = 8;
parameter bbus_arb_wb_num_slaves = 5; // Update this when changing slaves!
// Slave addresses
parameter bbus_arb_slave0_adr = uart0_wb_adr;
parameter bbus_arb_slave1_adr = gpio0_wb_adr;
parameter bbus_arb_slave2_adr = i2c_0_wb_adr;
parameter bbus_arb_slave3_adr = i2c_1_wb_adr;
parameter bbus_arb_slave4_adr = spi0_wb_adr;
parameter bbus_arb_slave5_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave6_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave7_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave8_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave9_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave10_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave11_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave12_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave13_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave14_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave15_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave16_adr = 0 /* UNASSIGNED */;
 
 
 
 
/xilinx/atlys/rtl/verilog/include/uart_defines.v
0,0 → 1,254
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_defines.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.13 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.12 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.10 2001/12/11 08:55:40 mohor
// Scratch register define added.
//
// Revision 1.9 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.8 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.7 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.6 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.5 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.4 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.3 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
 
// remove comments to restore to use the new version with 8 data bit interface
// in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place
// also, in 8-bit version there'll be no debugging features included
// CAUTION: doesn't work with current version of OR1200
`define DATA_BUS_WIDTH_8
 
`ifdef DATA_BUS_WIDTH_8
`define UART_ADDR_WIDTH 3
`define UART_DATA_WIDTH 8
`else
`define UART_ADDR_WIDTH 5
`define UART_DATA_WIDTH 32
`endif
 
// Uncomment this if you want your UART to have
// 16xBaudrate output port.
// If defined, the enable signal will be used to drive baudrate_o signal
// It's frequency is 16xbaudrate
 
// `define UART_HAS_BAUDRATE_OUTPUT
 
// Register addresses
`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer
`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter
`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable
`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification
`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control
`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control
`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control
`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status
`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status
`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register
`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2)
`define UART_REG_DL2 `UART_ADDR_WIDTH'd1
 
// Interrupt Enable register bits
`define UART_IE_RDA 0 // Received Data available interrupt
`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
`define UART_IE_RLS 2 // Receiver Line Status Interrupt
`define UART_IE_MS 3 // Modem Status Interrupt
 
// Interrupt Identification register bits
`define UART_II_IP 0 // Interrupt pending when 0
`define UART_II_II 3:1 // Interrupt identification
 
// Interrupt identification values for bits 3:1
`define UART_II_RLS 3'b011 // Receiver Line Status
`define UART_II_RDA 3'b010 // Receiver Data available
`define UART_II_TI 3'b110 // Timeout Indication
`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
`define UART_II_MS 3'b000 // Modem Status
 
// FIFO Control Register bits
`define UART_FC_TL 1:0 // Trigger level
 
// FIFO trigger level values
`define UART_FC_1 2'b00
`define UART_FC_4 2'b01
`define UART_FC_8 2'b10
`define UART_FC_14 2'b11
 
// Line Control register bits
`define UART_LC_BITS 1:0 // bits in character
`define UART_LC_SB 2 // stop bits
`define UART_LC_PE 3 // parity enable
`define UART_LC_EP 4 // even parity
`define UART_LC_SP 5 // stick parity
`define UART_LC_BC 6 // Break control
`define UART_LC_DL 7 // Divisor Latch access bit
 
// Modem Control register bits
`define UART_MC_DTR 0
`define UART_MC_RTS 1
`define UART_MC_OUT1 2
`define UART_MC_OUT2 3
`define UART_MC_LB 4 // Loopback mode
 
// Line Status Register bits
`define UART_LS_DR 0 // Data ready
`define UART_LS_OE 1 // Overrun Error
`define UART_LS_PE 2 // Parity Error
`define UART_LS_FE 3 // Framing Error
`define UART_LS_BI 4 // Break interrupt
`define UART_LS_TFE 5 // Transmit FIFO is empty
`define UART_LS_TE 6 // Transmitter Empty indicator
`define UART_LS_EI 7 // Error indicator
 
// Modem Status Register bits
`define UART_MS_DCTS 0 // Delta signals
`define UART_MS_DDSR 1
`define UART_MS_TERI 2
`define UART_MS_DDCD 3
`define UART_MS_CCTS 4 // Complement signals
`define UART_MS_CDSR 5
`define UART_MS_CRI 6
`define UART_MS_CDCD 7
 
// FIFO parameter defines
 
`define UART_FIFO_WIDTH 8
`define UART_FIFO_DEPTH 16
`define UART_FIFO_POINTER_W 4
`define UART_FIFO_COUNTER_W 5
// receiver fifo has width 11 because it has break, parity and framing error bits
`define UART_FIFO_REC_WIDTH 11
 
 
`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded
`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register)
`define FAST_TEST 1 // 64/1024 packets are sent
 
// Defines hard baud prescaler register - uncomment to enable
//`define PRESCALER_PRESET_HARD
// 115200 baud preset values
// 20MHz: prescaler 10.8 (11, rounded up)
//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd11
// 50MHz: prescaler 27.1
//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd27
// 66MHz: prescaler 36.1
//`define PRESCALER_HIGH_PRESET 8'd0
//`define PRESCALER_LOW_PRESET 8'd36
 
/xilinx/atlys/rtl/verilog/include/dbg_defines.v
0,0 → 1,153
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_defines.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor (igorm@opencores.org) ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_defines.v,v $
// Revision 1.20 2004/04/01 11:56:59 igorm
// Port names and defines for the supported CPUs changed.
//
// Revision 1.19 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.18 2004/03/22 16:35:46 igorm
// Temp version before changing dbg interface.
//
// Revision 1.17 2004/01/30 10:24:30 mohor
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
// turned on.
//
// Revision 1.16 2004/01/20 14:23:45 mohor
// Define name changed.
//
// Revision 1.15 2003/12/23 15:07:34 mohor
// New directory structure. New version of the debug interface.
// Files that are not needed removed.
//
// Revision 1.14 2003/10/23 16:17:00 mohor
// CRC logic changed.
//
// Revision 1.13 2003/10/21 09:48:31 simons
// Mbist support added.
//
// Revision 1.12 2003/09/17 14:38:57 simons
// WB_CNTL register added, some syncronization fixes.
//
// Revision 1.11 2003/08/28 13:55:21 simons
// Three more chains added for cpu debug access.
//
// Revision 1.10 2003/07/31 12:19:49 simons
// Multiple cpu support added.
//
// Revision 1.9 2002/05/07 14:43:59 mohor
// mon_cntl_o signals that controls monitor mux added.
//
// Revision 1.8 2002/01/25 07:58:34 mohor
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
// not filled-in. Tested in hw.
//
// Revision 1.7 2001/12/06 10:08:06 mohor
// Warnings from synthesys tools fixed.
//
// Revision 1.6 2001/11/28 09:38:30 mohor
// Trace disabled by default.
//
// Revision 1.5 2001/10/15 09:55:47 mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.4 2001/09/24 14:06:42 mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.3 2001/09/20 10:11:25 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.2 2001/09/18 14:13:47 mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
// Revision 1.3 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:08 mohor
// Initial release
//
//
 
 
// Length of the MODULE ID register
`define DBG_TOP_MODULE_ID_LENGTH 4
 
// Length of data
`define DBG_TOP_MODULE_DATA_LEN `DBG_TOP_MODULE_ID_LENGTH + 1
`define DBG_TOP_DATA_CNT 3
 
// Length of status
`define DBG_TOP_STATUS_LEN 3'd4
`define DBG_TOP_STATUS_CNT_WIDTH 3
 
// Length of the CRC
`define DBG_TOP_CRC_LEN 32
`define DBG_TOP_CRC_CNT 6
 
// Chains
`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0
`define DBG_TOP_CPU0_DEBUG_MODULE 4'h1
`define DBG_TOP_CPU1_DEBUG_MODULE 4'h2
 
// If WISHBONE sub-module is supported uncomment the folowing line
`define DBG_WISHBONE_SUPPORTED
 
// If CPU_0 sub-module is supported uncomment the folowing line
`define DBG_CPU0_SUPPORTED
 
// If CPU_1 sub-module is supported uncomment the folowing line
//`define DBG_CPU1_SUPPORTED
 
// If more debug info is needed, uncomment the follofing line
//`define DBG_MORE_INFO
 
/xilinx/atlys/rtl/verilog/include/xilinx_ddr2_params.v
0,0 → 1,24
parameter C3_P0_MASK_SIZE = 16;
parameter C3_P0_DATA_PORT_SIZE = 128;
parameter DEBUG_EN = 0;
parameter C3_MEMCLK_PERIOD = 3750;
parameter C3_CALIB_SOFT_IP = "TRUE";
parameter C3_SIMULATION = "FALSE";
parameter C3_RST_ACT_LOW = 0;
parameter C3_INPUT_CLK_TYPE = "SINGLE_ENDED";
parameter C3_MEM_ADDR_ORDER = "BANK_ROW_COLUMN";
parameter C3_NUM_DQ_PINS = 16;
parameter C3_MEM_ADDR_WIDTH = 13;
parameter C3_MEM_BANKADDR_WIDTH = 3;
// Simulation parameter defines
parameter DQ_WIDTH = 16;
parameter DQS_WIDTH = 1;
parameter DM_WIDTH = 1;
parameter CLK_WIDTH = 1;
parameter ROW_WIDTH = 13;
parameter BANK_WIDTH = 3;
parameter CKE_WIDTH = 1;
parameter ODT_WIDTH = 1;
 
/xilinx/atlys/rtl/verilog/lfsr/lfsr.v
0,0 → 1,118
//////////////////////////////////////////////////////////////////////
//// ////
//// Linear feedback shift register with Wishbone interface ////
//// ////
//// Description ////
//// Simple LFSR module (feedback hardcoded) ////
//// Two accessible registers: ////
//// Address 0: LFSR Register (R/W) ////
//// Address 4: Control register, active high, self resetting (WO)////
//// Bit[0]: lfsr shift enable ////
//// Bit[1]: lfsr reset ////
//// ////
//// To Do: ////
//// Perhaps make feedback parameterisable ////
//// ////
//// Author(s): ////
//// - Julius Baxter, julius.baxter@orsoc.se ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module wb_lfsr( wb_clk, wb_rst, wb_adr_i, wb_dat_i, wb_cyc_i, wb_stb_i, wb_we_i,
wb_dat_o, wb_ack_o);
parameter width = 32;
parameter lfsr_rst_value = 32'b0011_0001_0000_1010;
input wb_clk;
input wb_rst;
input [2:0] wb_adr_i;
input [width-1:0] wb_dat_i;
input wb_cyc_i, wb_stb_i, wb_we_i;
output [width-1:0] wb_dat_o;
output reg wb_ack_o;
wire wb_req;
assign wb_req = wb_stb_i & wb_cyc_i;
reg [width-1:0] lfsr;
wire lfsr_feedback;
 
assign wb_dat_o = lfsr;
 
// Only 2 registers here, the lfsr itself and
wire lfsr_sel;
assign lfsr_sel = !wb_adr_i[2];
wire lfsr_control_reg_sel;
assign lfsr_control_reg_sel = wb_adr_i[2];
 
// [0]: shift enable, [1]: reset
reg [1:0] lfsr_control_reg;
wire lfsr_control_enable;
wire lfsr_control_rst;
 
// Load the control reg when required,
always @(posedge wb_clk)
begin
if (wb_rst)
lfsr_control_reg <= 0;
else if (wb_req & wb_we_i & lfsr_control_reg_sel & wb_ack_o)
lfsr_control_reg <= wb_dat_i;
if (lfsr_control_reg[0])
lfsr_control_reg[0] <= 0;
if (lfsr_control_reg[1])
lfsr_control_reg[1] <= 0;
end // always @ (posedge wb_clk)
 
assign lfsr_control_enable = lfsr_control_reg[0];
assign lfsr_control_rst = lfsr_control_reg[1];
assign lfsr_feedback = !(((lfsr[27] ^ lfsr[13]) ^ lfsr[8]) ^ lfsr[5]);
always @(posedge wb_clk)
if (wb_rst)
lfsr <= lfsr_rst_value;
else if (lfsr_control_rst)
lfsr <= lfsr_rst_value;
else if (wb_req & wb_we_i & lfsr_sel & wb_ack_o) // Set lfsr
lfsr <= wb_dat_i;
else if (lfsr_control_enable)
lfsr <= {lfsr[width-2:0], lfsr_feedback};
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_req & !wb_ack_o)
wb_ack_o <= 1;
else if (wb_ack_o)
wb_ack_o <= 0;
 
endmodule // lfsr
/xilinx/atlys/rtl/verilog/xilinx_ddr2/infrastructure.v
0,0 → 1,296
//*****************************************************************************
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : infrastructure.v
// /___/ /\ Date Last Modified : $Date: 2010/10/27 17:40:11 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
//Device : Spartan-6
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : Clock generation/distribution and reset synchronization
//Reference :
//Revision History :
//*****************************************************************************
 
 
`timescale 1ns/1ps
 
module infrastructure #
(
parameter C_INCLK_PERIOD = 2500,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CLKFBOUT_MULT = 2,
parameter C_DIVCLK_DIVIDE = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input sys_rst_n,
output clk0,
output rst0,
output async_rst,
output sysclk_2x,
output sysclk_2x_180,
output mcb_drp_clk,
output pll_ce_0,
output pll_ce_90,
output pll_lock
 
);
 
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
 
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = C_INCLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = C_INCLK_PERIOD/1000;
 
wire clk_2x_0;
wire clk_2x_180;
wire clk0_bufg;
wire clk0_bufg_in;
wire mcb_drp_clk_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
reg powerup_pll_locked;
 
wire sys_rst;
wire bufpll_mcb_locked;
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
 
assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_n: sys_rst_n;
assign clk0 = clk0_bufg;
assign pll_lock = bufpll_mcb_locked;
 
generate
if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
 
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
 
IBUFGDS #
(
.DIFF_TERM ("TRUE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
 
end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
 
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
/* SJK
IBUFG u_ibufg_sys_clk
(
.I (sys_clk),
.O (sys_clk_ibufg)
);
*/
assign sys_clk_ibufg = sys_clk;
end
endgenerate
 
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
 
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (CLK_PERIOD_NS),
.CLKOUT0_DIVIDE (C_CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (C_CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (C_CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (C_CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (C_DIVCLK_DIVIDE),
.CLKFBOUT_MULT (C_CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk_2x_0),
.CLKOUT1 (clk_2x_180),
.CLKOUT2 (clk0_bufg_in),
.CLKOUT3 (mcb_drp_clk_bufg_in),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
 
 
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
 
BUFG U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in)
);
 
 
always @(posedge clk0_bufg , posedge sys_rst)
if(sys_rst)
powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
powerup_pll_locked <= 1'b1;
 
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
// 3. asynchronous reset only look at pll_lock from PLL during power up. After
// power up and pll_lock is asserted, the powerup_pll_locked will be asserted
// forever until sys_rst is asserted again. PLL will lose lock when FPGA
// enters suspend mode. We don't want reset to MCB get
// asserted in the application that needs suspend feature.
//***************************************************************************
 
assign rst_tmp = sys_rst | ~powerup_pll_locked;
 
assign async_rst = rst_tmp;
// synthesis attribute max_fanout of rst0_sync_r is 10
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
 
 
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
 
 
BUFPLL_MCB BUFPLL_MCB1
( .IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.LOCKED (locked),
.GCLK (mcb_drp_clk),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.PLLIN0 (clk_2x_0),
.PLLIN1 (clk_2x_180),
.LOCK (bufpll_mcb_locked)
);
 
 
endmodule
xilinx/atlys/rtl/verilog/xilinx_ddr2/infrastructure.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v (revision 627) @@ -0,0 +1,302 @@ +//***************************************************************************** +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: iodrp_controller.v +// /___/ /\ Date Last Modified: $Date: 2010/10/27 17:40:12 $ +// \ \ / \ Date Created: Mon Feb 9 2009 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: Xilinx reference design for IODRP controller for v0.9 device +// +//Reference: +// +// Revision: Date: Comment +// 1.0: 02/06/09: Initial version for MIG wrapper. +// 1.1: 02/01/09: updates to indentations. +// 1.2: 02/12/09: changed non-blocking assignments to blocking ones +// for state machine always block. Also, assigned +// intial value to load_shift_n to avoid latch +// End Revision +//******************************************************************************* + +`timescale 1ps/1ps + +module iodrp_controller( + input wire [7:0] memcell_address, + input wire [7:0] write_data, + output reg [7:0] read_data, + input wire rd_not_write, + input wire cmd_valid, + output wire rdy_busy_n, + input wire use_broadcast, + input wire sync_rst, + input wire DRP_CLK, + output reg DRP_CS, + output wire DRP_SDI, //output to IODRP SDI pin + output reg DRP_ADD, + output reg DRP_BKST, + input wire DRP_SDO //input from IODRP SDO pin + ); + + reg [7:0] memcell_addr_reg; // Register where memcell_address is captured during the READY state + reg [7:0] data_reg; // Register which stores the write data until it is ready to be shifted out + reg [7:0] shift_through_reg; // The shift register which shifts out SDO and shifts in SDI. + // This register is loaded before the address or data phase, but continues + // to shift for a writeback of read data + reg load_shift_n; // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO + reg addr_data_sel_n; // The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg + reg [2:0] bit_cnt; // The counter for which bit is being shifted during address or data phase + reg rd_not_write_reg; + reg AddressPhase; // This is set after the first address phase has executed + reg capture_read_data; + + (* FSM_ENCODING="one-hot" *) reg [2:0] state, nextstate; + + wire [7:0] data_out_mux; // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg + wire DRP_SDI_pre; // added so that DRP_SDI output is only active when DRP_CS is active + + localparam READY = 3'h0; + localparam DECIDE = 3'h1; + localparam ADDR_PHASE = 3'h2; + localparam ADDR_TO_DATA_GAP = 3'h3; + localparam ADDR_TO_DATA_GAP2 = 3'h4; + localparam ADDR_TO_DATA_GAP3 = 3'h5; + localparam DATA_PHASE = 3'h6; + localparam ALMOST_READY = 3'h7; + + localparam IOI_DQ0 = 5'h01; + localparam IOI_DQ1 = 5'h00; + localparam IOI_DQ2 = 5'h03; + localparam IOI_DQ3 = 5'h02; + localparam IOI_DQ4 = 5'h05; + localparam IOI_DQ5 = 5'h04; + localparam IOI_DQ6 = 5'h07; + localparam IOI_DQ7 = 5'h06; + localparam IOI_DQ8 = 5'h09; + localparam IOI_DQ9 = 5'h08; + localparam IOI_DQ10 = 5'h0B; + localparam IOI_DQ11 = 5'h0A; + localparam IOI_DQ12 = 5'h0D; + localparam IOI_DQ13 = 5'h0C; + localparam IOI_DQ14 = 5'h0F; + localparam IOI_DQ15 = 5'h0E; + localparam IOI_UDQS_CLK = 5'h1D; + localparam IOI_UDQS_PIN = 5'h1C; + localparam IOI_LDQS_CLK = 5'h1F; + localparam IOI_LDQS_PIN = 5'h1E; + //synthesis translate_off + reg [32*8-1:0] state_ascii; + always @ (state) begin + case (state) + READY :state_ascii <= "READY"; + DECIDE :state_ascii <= "DECIDE"; + ADDR_PHASE :state_ascii <= "ADDR_PHASE"; + ADDR_TO_DATA_GAP :state_ascii <= "ADDR_TO_DATA_GAP"; + ADDR_TO_DATA_GAP2 :state_ascii <= "ADDR_TO_DATA_GAP2"; + ADDR_TO_DATA_GAP3 :state_ascii <= "ADDR_TO_DATA_GAP3"; + DATA_PHASE :state_ascii <= "DATA_PHASE"; + ALMOST_READY :state_ascii <= "ALMOST_READY"; + endcase // case(state) + end + //synthesis translate_on + /********************************************* + * Input Registers + *********************************************/ + always @ (posedge DRP_CLK) begin + if(state == READY) begin + memcell_addr_reg <= memcell_address; + data_reg <= write_data; + rd_not_write_reg <= rd_not_write; + end + end + + assign rdy_busy_n = (state == READY); + + + /********************************************* + * Shift Registers / Bit Counter + *********************************************/ + assign data_out_mux = addr_data_sel_n ? memcell_addr_reg : data_reg; + + always @ (posedge DRP_CLK) begin + if(sync_rst) + shift_through_reg <= 8'b0; + else begin + if (load_shift_n) //Assume the shifter is either loading or shifting, bit 0 is shifted out first + shift_through_reg <= data_out_mux; + else + shift_through_reg <= {DRP_SDO, shift_through_reg[7:1]}; + end + end + + always @ (posedge DRP_CLK) begin + if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst) + bit_cnt <= bit_cnt + 1; + else + bit_cnt <= 3'b000; + end + + always @ (posedge DRP_CLK) begin + if(sync_rst) begin + read_data <= 8'h00; +// capture_read_data <= 1'b0; + end + else begin +// capture_read_data <= (state == DATA_PHASE); +// if(capture_read_data) + if(state == ALMOST_READY) + read_data <= shift_through_reg; +// else +// read_data <= read_data; + end + end + + always @ (posedge DRP_CLK) begin + if(sync_rst) begin + AddressPhase <= 1'b0; + end + else begin + if (AddressPhase) begin + // Keep it set until we finish the cycle + AddressPhase <= AddressPhase && ~(state == ALMOST_READY); + end + else begin + // set the address phase when ever we finish the address phase + AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111); + end + end + end + + /********************************************* + * DRP Signals + *********************************************/ + always @ (posedge DRP_CLK) begin + DRP_ADD <= (nextstate == ADDR_PHASE); + DRP_CS <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); + if (state == READY) + DRP_BKST <= use_broadcast; + end + +// assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance +// assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance + assign DRP_SDI = shift_through_reg[0]; // The new read method only requires that we shift out the address and the write data + + /********************************************* + * State Machine + *********************************************/ + always @ (*) begin + addr_data_sel_n = 1'b0; + load_shift_n = 1'b0; + case (state) + READY: begin + if(cmd_valid) + nextstate = DECIDE; + else + nextstate = READY; + end + DECIDE: begin + load_shift_n = 1; + addr_data_sel_n = 1; + nextstate = ADDR_PHASE; + end + ADDR_PHASE: begin + if(&bit_cnt) + if (rd_not_write_reg) + if (AddressPhase) + // After the second pass go to end of statemachine + nextstate = ALMOST_READY; + else + // execute a second address phase for the read access. + nextstate = DECIDE; + else + nextstate = ADDR_TO_DATA_GAP; + else + nextstate = ADDR_PHASE; + end + ADDR_TO_DATA_GAP: begin + load_shift_n = 1; + nextstate = ADDR_TO_DATA_GAP2; + end + ADDR_TO_DATA_GAP2: begin + load_shift_n = 1; + nextstate = ADDR_TO_DATA_GAP3; + end + ADDR_TO_DATA_GAP3: begin + load_shift_n = 1; + nextstate = DATA_PHASE; + end + DATA_PHASE: begin + if(&bit_cnt) + nextstate = ALMOST_READY; + else + nextstate = DATA_PHASE; + end + ALMOST_READY: begin + nextstate = READY; + end + default: begin + nextstate = READY; + end + endcase + end + + always @ (posedge DRP_CLK) begin + if(sync_rst) + state <= READY; + else + state <= nextstate; + end + +endmodule
xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_controller.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_ui_top.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_ui_top.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_ui_top.v (revision 627) @@ -0,0 +1,2155 @@ +//***************************************************************************** +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: +//Reference: +// This module instantiates the AXI bridges +// +//***************************************************************************** +`timescale 1ps / 1ps + +module mcb_ui_top # + ( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + // Raw Wrapper Parameters + parameter C_MEMCLK_PERIOD = 2500, + parameter C_PORT_ENABLE = 6'b111111, + parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN", + parameter C_ARB_ALGORITHM = 0, + parameter C_ARB_NUM_TIME_SLOTS = 12, + parameter C_ARB_TIME_SLOT_0 = 18'o012345, + parameter C_ARB_TIME_SLOT_1 = 18'o123450, + parameter C_ARB_TIME_SLOT_2 = 18'o234501, + parameter C_ARB_TIME_SLOT_3 = 18'o345012, + parameter C_ARB_TIME_SLOT_4 = 18'o450123, + parameter C_ARB_TIME_SLOT_5 = 18'o501234, + parameter C_ARB_TIME_SLOT_6 = 18'o012345, + parameter C_ARB_TIME_SLOT_7 = 18'o123450, + parameter C_ARB_TIME_SLOT_8 = 18'o234501, + parameter C_ARB_TIME_SLOT_9 = 18'o345012, + parameter C_ARB_TIME_SLOT_10 = 18'o450123, + parameter C_ARB_TIME_SLOT_11 = 18'o501234, + parameter C_PORT_CONFIG = "B128", + parameter C_MEM_TRAS = 45000, + parameter C_MEM_TRCD = 12500, + parameter C_MEM_TREFI = 7800, + parameter C_MEM_TRFC = 127500, + parameter C_MEM_TRP = 12500, + parameter C_MEM_TWR = 15000, + parameter C_MEM_TRTP = 7500, + parameter C_MEM_TWTR = 7500, + parameter C_NUM_DQ_PINS = 8, + parameter C_MEM_TYPE = "DDR3", + parameter C_MEM_DENSITY = "512M", + parameter C_MEM_BURST_LEN = 8, + parameter C_MEM_CAS_LATENCY = 4, + parameter C_MEM_ADDR_WIDTH = 13, + parameter C_MEM_BANKADDR_WIDTH = 3, + parameter C_MEM_NUM_COL_BITS = 11, + parameter C_MEM_DDR3_CAS_LATENCY = 7, + parameter C_MEM_MOBILE_PA_SR = "FULL", + parameter C_MEM_DDR1_2_ODS = "FULL", + parameter C_MEM_DDR3_ODS = "DIV6", + parameter C_MEM_DDR2_RTT = "50OHMS", + parameter C_MEM_DDR3_RTT = "DIV2", + parameter C_MEM_MDDR_ODS = "FULL", + parameter C_MEM_DDR2_DIFF_DQS_EN = "YES", + parameter C_MEM_DDR2_3_PA_SR = "OFF", + parameter C_MEM_DDR3_CAS_WR_LATENCY = 5, + parameter C_MEM_DDR3_AUTO_SR = "ENABLED", + parameter C_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL", + parameter C_MEM_DDR3_DYN_WRT_ODT = "OFF", + parameter C_MEM_TZQINIT_MAXCNT = 10'd512, + parameter C_MC_CALIB_BYPASS = "NO", + parameter C_MC_CALIBRATION_RA = 15'h0000, + parameter C_MC_CALIBRATION_BA = 3'h0, + parameter C_CALIB_SOFT_IP = "TRUE", + parameter C_SKIP_IN_TERM_CAL = 1'b0, + parameter C_SKIP_DYNAMIC_CAL = 1'b0, + parameter C_SKIP_DYN_IN_TERM = 1'b1, + parameter LDQSP_TAP_DELAY_VAL = 0, + parameter UDQSP_TAP_DELAY_VAL = 0, + parameter LDQSN_TAP_DELAY_VAL = 0, + parameter UDQSN_TAP_DELAY_VAL = 0, + parameter DQ0_TAP_DELAY_VAL = 0, + parameter DQ1_TAP_DELAY_VAL = 0, + parameter DQ2_TAP_DELAY_VAL = 0, + parameter DQ3_TAP_DELAY_VAL = 0, + parameter DQ4_TAP_DELAY_VAL = 0, + parameter DQ5_TAP_DELAY_VAL = 0, + parameter DQ6_TAP_DELAY_VAL = 0, + parameter DQ7_TAP_DELAY_VAL = 0, + parameter DQ8_TAP_DELAY_VAL = 0, + parameter DQ9_TAP_DELAY_VAL = 0, + parameter DQ10_TAP_DELAY_VAL = 0, + parameter DQ11_TAP_DELAY_VAL = 0, + parameter DQ12_TAP_DELAY_VAL = 0, + parameter DQ13_TAP_DELAY_VAL = 0, + parameter DQ14_TAP_DELAY_VAL = 0, + parameter DQ15_TAP_DELAY_VAL = 0, + parameter C_MC_CALIBRATION_CA = 12'h000, + parameter C_MC_CALIBRATION_CLK_DIV = 1, + parameter C_MC_CALIBRATION_MODE = "CALIBRATION", + parameter C_MC_CALIBRATION_DELAY = "HALF", + parameter C_SIMULATION = "FALSE", + parameter C_P0_MASK_SIZE = 4, + parameter C_P0_DATA_PORT_SIZE = 32, + parameter C_P1_MASK_SIZE = 4, + parameter C_P1_DATA_PORT_SIZE = 32, + parameter integer C_MCB_USE_EXTERNAL_BUFPLL = 1, + // AXI Parameters + parameter C_S0_AXI_BASEADDR = 32'h00000000, + parameter C_S0_AXI_HIGHADDR = 32'h00000000, + parameter integer C_S0_AXI_ENABLE = 0, + parameter integer C_S0_AXI_ID_WIDTH = 4, + parameter integer C_S0_AXI_ADDR_WIDTH = 64, + parameter integer C_S0_AXI_DATA_WIDTH = 32, + parameter integer C_S0_AXI_SUPPORTS_READ = 1, + parameter integer C_S0_AXI_SUPPORTS_WRITE = 1, + parameter integer C_S0_AXI_SUPPORTS_NARROW_BURST = 1, + parameter C_S0_AXI_REG_EN0 = 20'h00000, + parameter C_S0_AXI_REG_EN1 = 20'h01000, + parameter integer C_S0_AXI_STRICT_COHERENCY = 1, + parameter integer C_S0_AXI_ENABLE_AP = 0, + parameter C_S1_AXI_BASEADDR = 32'h00000000, + parameter C_S1_AXI_HIGHADDR = 32'h00000000, + parameter integer C_S1_AXI_ENABLE = 0, + parameter integer C_S1_AXI_ID_WIDTH = 4, + parameter integer C_S1_AXI_ADDR_WIDTH = 64, + parameter integer C_S1_AXI_DATA_WIDTH = 32, + parameter integer C_S1_AXI_SUPPORTS_READ = 1, + parameter integer C_S1_AXI_SUPPORTS_WRITE = 1, + parameter integer C_S1_AXI_SUPPORTS_NARROW_BURST = 1, + parameter C_S1_AXI_REG_EN0 = 20'h00000, + parameter C_S1_AXI_REG_EN1 = 20'h01000, + parameter integer C_S1_AXI_STRICT_COHERENCY = 1, + parameter integer C_S1_AXI_ENABLE_AP = 0, + parameter C_S2_AXI_BASEADDR = 32'h00000000, + parameter C_S2_AXI_HIGHADDR = 32'h00000000, + parameter integer C_S2_AXI_ENABLE = 0, + parameter integer C_S2_AXI_ID_WIDTH = 4, + parameter integer C_S2_AXI_ADDR_WIDTH = 64, + parameter integer C_S2_AXI_DATA_WIDTH = 32, + parameter integer C_S2_AXI_SUPPORTS_READ = 1, + parameter integer C_S2_AXI_SUPPORTS_WRITE = 1, + parameter integer C_S2_AXI_SUPPORTS_NARROW_BURST = 1, + parameter C_S2_AXI_REG_EN0 = 20'h00000, + parameter C_S2_AXI_REG_EN1 = 20'h01000, + parameter integer C_S2_AXI_STRICT_COHERENCY = 1, + parameter integer C_S2_AXI_ENABLE_AP = 0, + parameter C_S3_AXI_BASEADDR = 32'h00000000, + parameter C_S3_AXI_HIGHADDR = 32'h00000000, + parameter integer C_S3_AXI_ENABLE = 0, + parameter integer C_S3_AXI_ID_WIDTH = 4, + parameter integer C_S3_AXI_ADDR_WIDTH = 64, + parameter integer C_S3_AXI_DATA_WIDTH = 32, + parameter integer C_S3_AXI_SUPPORTS_READ = 1, + parameter integer C_S3_AXI_SUPPORTS_WRITE = 1, + parameter integer C_S3_AXI_SUPPORTS_NARROW_BURST = 1, + parameter C_S3_AXI_REG_EN0 = 20'h00000, + parameter C_S3_AXI_REG_EN1 = 20'h01000, + parameter integer C_S3_AXI_STRICT_COHERENCY = 1, + parameter integer C_S3_AXI_ENABLE_AP = 0, + parameter C_S4_AXI_BASEADDR = 32'h00000000, + parameter C_S4_AXI_HIGHADDR = 32'h00000000, + parameter integer C_S4_AXI_ENABLE = 0, + parameter integer C_S4_AXI_ID_WIDTH = 4, + parameter integer C_S4_AXI_ADDR_WIDTH = 64, + parameter integer C_S4_AXI_DATA_WIDTH = 32, + parameter integer C_S4_AXI_SUPPORTS_READ = 1, + parameter integer C_S4_AXI_SUPPORTS_WRITE = 1, + parameter integer C_S4_AXI_SUPPORTS_NARROW_BURST = 1, + parameter C_S4_AXI_REG_EN0 = 20'h00000, + parameter C_S4_AXI_REG_EN1 = 20'h01000, + parameter integer C_S4_AXI_STRICT_COHERENCY = 1, + parameter integer C_S4_AXI_ENABLE_AP = 0, + parameter C_S5_AXI_BASEADDR = 32'h00000000, + parameter C_S5_AXI_HIGHADDR = 32'h00000000, + parameter integer C_S5_AXI_ENABLE = 0, + parameter integer C_S5_AXI_ID_WIDTH = 4, + parameter integer C_S5_AXI_ADDR_WIDTH = 64, + parameter integer C_S5_AXI_DATA_WIDTH = 32, + parameter integer C_S5_AXI_SUPPORTS_READ = 1, + parameter integer C_S5_AXI_SUPPORTS_WRITE = 1, + parameter integer C_S5_AXI_SUPPORTS_NARROW_BURST = 1, + parameter C_S5_AXI_REG_EN0 = 20'h00000, + parameter C_S5_AXI_REG_EN1 = 20'h01000, + parameter integer C_S5_AXI_STRICT_COHERENCY = 1, + parameter integer C_S5_AXI_ENABLE_AP = 0 + ) + ( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + // Raw Wrapper Signals + input sysclk_2x , + input sysclk_2x_180 , + input pll_ce_0 , + input pll_ce_90 , + output sysclk_2x_bufpll_o , + output sysclk_2x_180_bufpll_o, + output pll_ce_0_bufpll_o , + output pll_ce_90_bufpll_o , + output pll_lock_bufpll_o , + input pll_lock , + input sys_rst , + input p0_arb_en , + input p0_cmd_clk , + input p0_cmd_en , + input [2:0] p0_cmd_instr , + input [5:0] p0_cmd_bl , + input [29:0] p0_cmd_byte_addr , + output p0_cmd_empty , + output p0_cmd_full , + input p0_wr_clk , + input p0_wr_en , + input [C_P0_MASK_SIZE-1:0] p0_wr_mask , + input [C_P0_DATA_PORT_SIZE-1:0] p0_wr_data , + output p0_wr_full , + output p0_wr_empty , + output [6:0] p0_wr_count , + output p0_wr_underrun , + output p0_wr_error , + input p0_rd_clk , + input p0_rd_en , + output [C_P0_DATA_PORT_SIZE-1:0] p0_rd_data , + output p0_rd_full , + output p0_rd_empty , + output [6:0] p0_rd_count , + output p0_rd_overflow , + output p0_rd_error , + input p1_arb_en , + input p1_cmd_clk , + input p1_cmd_en , + input [2:0] p1_cmd_instr , + input [5:0] p1_cmd_bl , + input [29:0] p1_cmd_byte_addr , + output p1_cmd_empty , + output p1_cmd_full , + input p1_wr_clk , + input p1_wr_en , + input [C_P1_MASK_SIZE-1:0] p1_wr_mask , + input [C_P1_DATA_PORT_SIZE-1:0] p1_wr_data , + output p1_wr_full , + output p1_wr_empty , + output [6:0] p1_wr_count , + output p1_wr_underrun , + output p1_wr_error , + input p1_rd_clk , + input p1_rd_en , + output [C_P1_DATA_PORT_SIZE-1:0] p1_rd_data , + output p1_rd_full , + output p1_rd_empty , + output [6:0] p1_rd_count , + output p1_rd_overflow , + output p1_rd_error , + input p2_arb_en , + input p2_cmd_clk , + input p2_cmd_en , + input [2:0] p2_cmd_instr , + input [5:0] p2_cmd_bl , + input [29:0] p2_cmd_byte_addr , + output p2_cmd_empty , + output p2_cmd_full , + input p2_wr_clk , + input p2_wr_en , + input [3:0] p2_wr_mask , + input [31:0] p2_wr_data , + output p2_wr_full , + output p2_wr_empty , + output [6:0] p2_wr_count , + output p2_wr_underrun , + output p2_wr_error , + input p2_rd_clk , + input p2_rd_en , + output [31:0] p2_rd_data , + output p2_rd_full , + output p2_rd_empty , + output [6:0] p2_rd_count , + output p2_rd_overflow , + output p2_rd_error , + input p3_arb_en , + input p3_cmd_clk , + input p3_cmd_en , + input [2:0] p3_cmd_instr , + input [5:0] p3_cmd_bl , + input [29:0] p3_cmd_byte_addr , + output p3_cmd_empty , + output p3_cmd_full , + input p3_wr_clk , + input p3_wr_en , + input [3:0] p3_wr_mask , + input [31:0] p3_wr_data , + output p3_wr_full , + output p3_wr_empty , + output [6:0] p3_wr_count , + output p3_wr_underrun , + output p3_wr_error , + input p3_rd_clk , + input p3_rd_en , + output [31:0] p3_rd_data , + output p3_rd_full , + output p3_rd_empty , + output [6:0] p3_rd_count , + output p3_rd_overflow , + output p3_rd_error , + input p4_arb_en , + input p4_cmd_clk , + input p4_cmd_en , + input [2:0] p4_cmd_instr , + input [5:0] p4_cmd_bl , + input [29:0] p4_cmd_byte_addr , + output p4_cmd_empty , + output p4_cmd_full , + input p4_wr_clk , + input p4_wr_en , + input [3:0] p4_wr_mask , + input [31:0] p4_wr_data , + output p4_wr_full , + output p4_wr_empty , + output [6:0] p4_wr_count , + output p4_wr_underrun , + output p4_wr_error , + input p4_rd_clk , + input p4_rd_en , + output [31:0] p4_rd_data , + output p4_rd_full , + output p4_rd_empty , + output [6:0] p4_rd_count , + output p4_rd_overflow , + output p4_rd_error , + input p5_arb_en , + input p5_cmd_clk , + input p5_cmd_en , + input [2:0] p5_cmd_instr , + input [5:0] p5_cmd_bl , + input [29:0] p5_cmd_byte_addr , + output p5_cmd_empty , + output p5_cmd_full , + input p5_wr_clk , + input p5_wr_en , + input [3:0] p5_wr_mask , + input [31:0] p5_wr_data , + output p5_wr_full , + output p5_wr_empty , + output [6:0] p5_wr_count , + output p5_wr_underrun , + output p5_wr_error , + input p5_rd_clk , + input p5_rd_en , + output [31:0] p5_rd_data , + output p5_rd_full , + output p5_rd_empty , + output [6:0] p5_rd_count , + output p5_rd_overflow , + output p5_rd_error , + output [C_MEM_ADDR_WIDTH-1:0] mcbx_dram_addr , + output [C_MEM_BANKADDR_WIDTH-1:0] mcbx_dram_ba , + output mcbx_dram_ras_n , + output mcbx_dram_cas_n , + output mcbx_dram_we_n , + output mcbx_dram_cke , + output mcbx_dram_clk , + output mcbx_dram_clk_n , + inout [C_NUM_DQ_PINS-1:0] mcbx_dram_dq , + inout mcbx_dram_dqs , + inout mcbx_dram_dqs_n , + inout mcbx_dram_udqs , + inout mcbx_dram_udqs_n , + output mcbx_dram_udm , + output mcbx_dram_ldm , + output mcbx_dram_odt , + output mcbx_dram_ddr3_rst , + input calib_recal , + inout rzq , + inout zio , + input ui_read , + input ui_add , + input ui_cs , + input ui_clk , + input ui_sdi , + input [4:0] ui_addr , + input ui_broadcast , + input ui_drp_update , + input ui_done_cal , + input ui_cmd , + input ui_cmd_in , + input ui_cmd_en , + input [3:0] ui_dqcount , + input ui_dq_lower_dec , + input ui_dq_lower_inc , + input ui_dq_upper_dec , + input ui_dq_upper_inc , + input ui_udqs_inc , + input ui_udqs_dec , + input ui_ldqs_inc , + input ui_ldqs_dec , + output [7:0] uo_data , + output uo_data_valid , + output uo_done_cal , + output uo_cmd_ready_in , + output uo_refrsh_flag , + output uo_cal_start , + output uo_sdo , + output [31:0] status , + input selfrefresh_enter , + output selfrefresh_mode , + // AXI Signals + input wire s0_axi_aclk , + input wire s0_axi_aresetn , + input wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_awid , + input wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr , + input wire [7:0] s0_axi_awlen , + input wire [2:0] s0_axi_awsize , + input wire [1:0] s0_axi_awburst , + input wire [0:0] s0_axi_awlock , + input wire [3:0] s0_axi_awcache , + input wire [2:0] s0_axi_awprot , + input wire [3:0] s0_axi_awqos , + input wire s0_axi_awvalid , + output wire s0_axi_awready , + input wire [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_wdata , + input wire [C_S0_AXI_DATA_WIDTH/8-1:0] s0_axi_wstrb , + input wire s0_axi_wlast , + input wire s0_axi_wvalid , + output wire s0_axi_wready , + output wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_bid , + output wire [1:0] s0_axi_bresp , + output wire s0_axi_bvalid , + input wire s0_axi_bready , + input wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_arid , + input wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr , + input wire [7:0] s0_axi_arlen , + input wire [2:0] s0_axi_arsize , + input wire [1:0] s0_axi_arburst , + input wire [0:0] s0_axi_arlock , + input wire [3:0] s0_axi_arcache , + input wire [2:0] s0_axi_arprot , + input wire [3:0] s0_axi_arqos , + input wire s0_axi_arvalid , + output wire s0_axi_arready , + output wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_rid , + output wire [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata , + output wire [1:0] s0_axi_rresp , + output wire s0_axi_rlast , + output wire s0_axi_rvalid , + input wire s0_axi_rready , + + input wire s1_axi_aclk , + input wire s1_axi_aresetn , + input wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_awid , + input wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_awaddr , + input wire [7:0] s1_axi_awlen , + input wire [2:0] s1_axi_awsize , + input wire [1:0] s1_axi_awburst , + input wire [0:0] s1_axi_awlock , + input wire [3:0] s1_axi_awcache , + input wire [2:0] s1_axi_awprot , + input wire [3:0] s1_axi_awqos , + input wire s1_axi_awvalid , + output wire s1_axi_awready , + input wire [C_S1_AXI_DATA_WIDTH-1:0] s1_axi_wdata , + input wire [C_S1_AXI_DATA_WIDTH/8-1:0] s1_axi_wstrb , + input wire s1_axi_wlast , + input wire s1_axi_wvalid , + output wire s1_axi_wready , + output wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_bid , + output wire [1:0] s1_axi_bresp , + output wire s1_axi_bvalid , + input wire s1_axi_bready , + input wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_arid , + input wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_araddr , + input wire [7:0] s1_axi_arlen , + input wire [2:0] s1_axi_arsize , + input wire [1:0] s1_axi_arburst , + input wire [0:0] s1_axi_arlock , + input wire [3:0] s1_axi_arcache , + input wire [2:0] s1_axi_arprot , + input wire [3:0] s1_axi_arqos , + input wire s1_axi_arvalid , + output wire s1_axi_arready , + output wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_rid , + output wire [C_S1_AXI_DATA_WIDTH-1:0] s1_axi_rdata , + output wire [1:0] s1_axi_rresp , + output wire s1_axi_rlast , + output wire s1_axi_rvalid , + input wire s1_axi_rready , + + input wire s2_axi_aclk , + input wire s2_axi_aresetn , + input wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_awid , + input wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_awaddr , + input wire [7:0] s2_axi_awlen , + input wire [2:0] s2_axi_awsize , + input wire [1:0] s2_axi_awburst , + input wire [0:0] s2_axi_awlock , + input wire [3:0] s2_axi_awcache , + input wire [2:0] s2_axi_awprot , + input wire [3:0] s2_axi_awqos , + input wire s2_axi_awvalid , + output wire s2_axi_awready , + input wire [C_S2_AXI_DATA_WIDTH-1:0] s2_axi_wdata , + input wire [C_S2_AXI_DATA_WIDTH/8-1:0] s2_axi_wstrb , + input wire s2_axi_wlast , + input wire s2_axi_wvalid , + output wire s2_axi_wready , + output wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_bid , + output wire [1:0] s2_axi_bresp , + output wire s2_axi_bvalid , + input wire s2_axi_bready , + input wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_arid , + input wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_araddr , + input wire [7:0] s2_axi_arlen , + input wire [2:0] s2_axi_arsize , + input wire [1:0] s2_axi_arburst , + input wire [0:0] s2_axi_arlock , + input wire [3:0] s2_axi_arcache , + input wire [2:0] s2_axi_arprot , + input wire [3:0] s2_axi_arqos , + input wire s2_axi_arvalid , + output wire s2_axi_arready , + output wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_rid , + output wire [C_S2_AXI_DATA_WIDTH-1:0] s2_axi_rdata , + output wire [1:0] s2_axi_rresp , + output wire s2_axi_rlast , + output wire s2_axi_rvalid , + input wire s2_axi_rready , + + input wire s3_axi_aclk , + input wire s3_axi_aresetn , + input wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_awid , + input wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_awaddr , + input wire [7:0] s3_axi_awlen , + input wire [2:0] s3_axi_awsize , + input wire [1:0] s3_axi_awburst , + input wire [0:0] s3_axi_awlock , + input wire [3:0] s3_axi_awcache , + input wire [2:0] s3_axi_awprot , + input wire [3:0] s3_axi_awqos , + input wire s3_axi_awvalid , + output wire s3_axi_awready , + input wire [C_S3_AXI_DATA_WIDTH-1:0] s3_axi_wdata , + input wire [C_S3_AXI_DATA_WIDTH/8-1:0] s3_axi_wstrb , + input wire s3_axi_wlast , + input wire s3_axi_wvalid , + output wire s3_axi_wready , + output wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_bid , + output wire [1:0] s3_axi_bresp , + output wire s3_axi_bvalid , + input wire s3_axi_bready , + input wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_arid , + input wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_araddr , + input wire [7:0] s3_axi_arlen , + input wire [2:0] s3_axi_arsize , + input wire [1:0] s3_axi_arburst , + input wire [0:0] s3_axi_arlock , + input wire [3:0] s3_axi_arcache , + input wire [2:0] s3_axi_arprot , + input wire [3:0] s3_axi_arqos , + input wire s3_axi_arvalid , + output wire s3_axi_arready , + output wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_rid , + output wire [C_S3_AXI_DATA_WIDTH-1:0] s3_axi_rdata , + output wire [1:0] s3_axi_rresp , + output wire s3_axi_rlast , + output wire s3_axi_rvalid , + input wire s3_axi_rready , + + input wire s4_axi_aclk , + input wire s4_axi_aresetn , + input wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_awid , + input wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_awaddr , + input wire [7:0] s4_axi_awlen , + input wire [2:0] s4_axi_awsize , + input wire [1:0] s4_axi_awburst , + input wire [0:0] s4_axi_awlock , + input wire [3:0] s4_axi_awcache , + input wire [2:0] s4_axi_awprot , + input wire [3:0] s4_axi_awqos , + input wire s4_axi_awvalid , + output wire s4_axi_awready , + input wire [C_S4_AXI_DATA_WIDTH-1:0] s4_axi_wdata , + input wire [C_S4_AXI_DATA_WIDTH/8-1:0] s4_axi_wstrb , + input wire s4_axi_wlast , + input wire s4_axi_wvalid , + output wire s4_axi_wready , + output wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_bid , + output wire [1:0] s4_axi_bresp , + output wire s4_axi_bvalid , + input wire s4_axi_bready , + input wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_arid , + input wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_araddr , + input wire [7:0] s4_axi_arlen , + input wire [2:0] s4_axi_arsize , + input wire [1:0] s4_axi_arburst , + input wire [0:0] s4_axi_arlock , + input wire [3:0] s4_axi_arcache , + input wire [2:0] s4_axi_arprot , + input wire [3:0] s4_axi_arqos , + input wire s4_axi_arvalid , + output wire s4_axi_arready , + output wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_rid , + output wire [C_S4_AXI_DATA_WIDTH-1:0] s4_axi_rdata , + output wire [1:0] s4_axi_rresp , + output wire s4_axi_rlast , + output wire s4_axi_rvalid , + input wire s4_axi_rready , + + input wire s5_axi_aclk , + input wire s5_axi_aresetn , + input wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_awid , + input wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_awaddr , + input wire [7:0] s5_axi_awlen , + input wire [2:0] s5_axi_awsize , + input wire [1:0] s5_axi_awburst , + input wire [0:0] s5_axi_awlock , + input wire [3:0] s5_axi_awcache , + input wire [2:0] s5_axi_awprot , + input wire [3:0] s5_axi_awqos , + input wire s5_axi_awvalid , + output wire s5_axi_awready , + input wire [C_S5_AXI_DATA_WIDTH-1:0] s5_axi_wdata , + input wire [C_S5_AXI_DATA_WIDTH/8-1:0] s5_axi_wstrb , + input wire s5_axi_wlast , + input wire s5_axi_wvalid , + output wire s5_axi_wready , + output wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_bid , + output wire [1:0] s5_axi_bresp , + output wire s5_axi_bvalid , + input wire s5_axi_bready , + input wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_arid , + input wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_araddr , + input wire [7:0] s5_axi_arlen , + input wire [2:0] s5_axi_arsize , + input wire [1:0] s5_axi_arburst , + input wire [0:0] s5_axi_arlock , + input wire [3:0] s5_axi_arcache , + input wire [2:0] s5_axi_arprot , + input wire [3:0] s5_axi_arqos , + input wire s5_axi_arvalid , + output wire s5_axi_arready , + output wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_rid , + output wire [C_S5_AXI_DATA_WIDTH-1:0] s5_axi_rdata , + output wire [1:0] s5_axi_rresp , + output wire s5_axi_rlast , + output wire s5_axi_rvalid , + input wire s5_axi_rready + ); + +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +// Barrel Left Shift Octal +function [17:0] blso ( + input [17:0] a, + input integer shift, + input integer width +); +begin : func_blso + integer i; + integer w; + integer s; + w = width*3; + s = (shift*3) % w; + blso = 18'o000000; + for (i = 0; i < w; i = i + 1) begin + blso[i] = a[(i+w-s)%w]; + //bls[i] = 1'b1; + end +end +endfunction + +// For a given port_config, port_enable and slot, calculate the round robin +// arbitration that would be generated by the gui. +function [17:0] rr ( + input [5:0] port_enable, + input integer port_config, + input integer slot_num +); +begin : func_rr + integer i; + integer max_ports; + integer num_ports; + integer port_cnt; + + case (port_config) + 1: max_ports = 6; + 2: max_ports = 4; + 3: max_ports = 3; + 4: max_ports = 2; + 5: max_ports = 1; +// synthesis translate_off + default : $display("ERROR: Port Config can't be %d", port_config); +// synthesis translate_on + endcase + + num_ports = 0; + for (i = 0; i < max_ports; i = i + 1) begin + if (port_enable[i] == 1'b1) begin + num_ports = num_ports + 1; + end + end + + rr = 18'o000000; + port_cnt = 0; + + for (i = (num_ports-1); i >= 0; i = i - 1) begin + while (port_enable[port_cnt] != 1'b1) begin + port_cnt = port_cnt + 1; + end + rr[i*3 +: 3] = port_cnt[2:0]; + port_cnt = port_cnt +1; + end + + + rr = blso(rr, slot_num, num_ports); +end +endfunction + +function [17:0] convert_arb_slot ( + input [5:0] port_enable, + input integer port_config, + input [17:0] mig_arb_slot +); +begin : func_convert_arb_slot + integer i; + integer num_ports; + integer mig_port_num; + reg [17:0] port_map; + num_ports = 0; + + // Enumerated port configuration for ease of use + case (port_config) + 1: port_map = 18'o543210; + 2: port_map = 18'o774210; + 3: port_map = 18'o777420; + 4: port_map = 18'o777720; + 5: port_map = 18'o777770; +// synthesis translate_off + default : $display ("ERROR: Invalid Port Configuration."); +// synthesis translate_on + endcase + + // Count the number of ports + for (i = 0; i < 6; i = i + 1) begin + if (port_enable[i] == 1'b1) begin + num_ports = num_ports + 1; + end + end + + // Map the ports from the MIG GUI to the MCB Wrapper + for (i = 0; i < 6; i = i + 1) begin + if (i < num_ports) begin + mig_port_num = mig_arb_slot[3*(num_ports-i-1) +: 3]; + convert_arb_slot[3*i +: 3] = port_map[3*mig_port_num +: 3]; + end else begin + convert_arb_slot[3*i +: 3] = 3'b111; + end + end +end +endfunction + +// Function to calculate the number of time slots automatically based on the +// number of ports used. Will choose 10 if the number of valid ports is 5, +// otherwise it will be 12. +function integer calc_num_time_slots ( + input [5:0] port_enable, + input integer port_config +); +begin : func_calc_num_tim_slots + integer num_ports; + integer i; + num_ports = 0; + for (i = 0; i < 6; i = i + 1) begin + if (port_enable[i] == 1'b1) begin + num_ports = num_ports + 1; + end + end + calc_num_time_slots = (port_config == 1 && num_ports == 5) ? 10 : 12; +end +endfunction +//////////////////////////////////////////////////////////////////////////////// +// Local Parameters +//////////////////////////////////////////////////////////////////////////////// + localparam P_S0_AXI_ADDRMASK = C_S0_AXI_BASEADDR ^ C_S0_AXI_HIGHADDR; + localparam P_S1_AXI_ADDRMASK = C_S1_AXI_BASEADDR ^ C_S1_AXI_HIGHADDR; + localparam P_S2_AXI_ADDRMASK = C_S2_AXI_BASEADDR ^ C_S2_AXI_HIGHADDR; + localparam P_S3_AXI_ADDRMASK = C_S3_AXI_BASEADDR ^ C_S3_AXI_HIGHADDR; + localparam P_S4_AXI_ADDRMASK = C_S4_AXI_BASEADDR ^ C_S4_AXI_HIGHADDR; + localparam P_S5_AXI_ADDRMASK = C_S5_AXI_BASEADDR ^ C_S5_AXI_HIGHADDR; + localparam P_PORT_CONFIG = (C_PORT_CONFIG == "B32_B32_B32_B32") ? 2 : + (C_PORT_CONFIG == "B64_B32_B32" ) ? 3 : + (C_PORT_CONFIG == "B64_B64" ) ? 4 : + (C_PORT_CONFIG == "B128" ) ? 5 : + 1; // B32_B32_x32_x32_x32_x32 case + localparam P_ARB_NUM_TIME_SLOTS = (C_ARB_ALGORITHM == 0) ? calc_num_time_slots(C_PORT_ENABLE, P_PORT_CONFIG) : C_ARB_NUM_TIME_SLOTS; + localparam P_0_ARB_TIME_SLOT_0 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 0 ) : C_ARB_TIME_SLOT_0 ; + localparam P_0_ARB_TIME_SLOT_1 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 1 ) : C_ARB_TIME_SLOT_1 ; + localparam P_0_ARB_TIME_SLOT_2 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 2 ) : C_ARB_TIME_SLOT_2 ; + localparam P_0_ARB_TIME_SLOT_3 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 3 ) : C_ARB_TIME_SLOT_3 ; + localparam P_0_ARB_TIME_SLOT_4 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 4 ) : C_ARB_TIME_SLOT_4 ; + localparam P_0_ARB_TIME_SLOT_5 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 5 ) : C_ARB_TIME_SLOT_5 ; + localparam P_0_ARB_TIME_SLOT_6 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 6 ) : C_ARB_TIME_SLOT_6 ; + localparam P_0_ARB_TIME_SLOT_7 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 7 ) : C_ARB_TIME_SLOT_7 ; + localparam P_0_ARB_TIME_SLOT_8 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 8 ) : C_ARB_TIME_SLOT_8 ; + localparam P_0_ARB_TIME_SLOT_9 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 9 ) : C_ARB_TIME_SLOT_9 ; + localparam P_0_ARB_TIME_SLOT_10 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 10) : C_ARB_TIME_SLOT_10; + localparam P_0_ARB_TIME_SLOT_11 = (C_ARB_ALGORITHM == 0) ? rr(C_PORT_ENABLE, P_PORT_CONFIG, 11) : C_ARB_TIME_SLOT_11; + localparam P_ARB_TIME_SLOT_0 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_0); + localparam P_ARB_TIME_SLOT_1 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_1); + localparam P_ARB_TIME_SLOT_2 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_2); + localparam P_ARB_TIME_SLOT_3 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_3); + localparam P_ARB_TIME_SLOT_4 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_4); + localparam P_ARB_TIME_SLOT_5 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_5); + localparam P_ARB_TIME_SLOT_6 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_6); + localparam P_ARB_TIME_SLOT_7 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_7); + localparam P_ARB_TIME_SLOT_8 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_8); + localparam P_ARB_TIME_SLOT_9 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_9); + localparam P_ARB_TIME_SLOT_10 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_10); + localparam P_ARB_TIME_SLOT_11 = convert_arb_slot(C_PORT_ENABLE, P_PORT_CONFIG, P_0_ARB_TIME_SLOT_11); + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// + wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr_i; + wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr_i; + wire p0_arb_en_i; + wire p0_cmd_clk_i; + wire p0_cmd_en_i; + wire [2:0] p0_cmd_instr_i; + wire [5:0] p0_cmd_bl_i; + wire [29:0] p0_cmd_byte_addr_i; + wire p0_cmd_empty_i; + wire p0_cmd_full_i; + wire p0_wr_clk_i; + wire p0_wr_en_i; + wire [C_P0_MASK_SIZE-1:0] p0_wr_mask_i; + wire [C_P0_DATA_PORT_SIZE-1:0] p0_wr_data_i; + wire p0_wr_full_i; + wire p0_wr_empty_i; + wire [6:0] p0_wr_count_i; + wire p0_wr_underrun_i; + wire p0_wr_error_i; + wire p0_rd_clk_i; + wire p0_rd_en_i; + wire [C_P0_DATA_PORT_SIZE-1:0] p0_rd_data_i; + wire p0_rd_full_i; + wire p0_rd_empty_i; + wire [6:0] p0_rd_count_i; + wire p0_rd_overflow_i; + wire p0_rd_error_i; + + wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_araddr_i; + wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_awaddr_i; + wire p1_arb_en_i; + wire p1_cmd_clk_i; + wire p1_cmd_en_i; + wire [2:0] p1_cmd_instr_i; + wire [5:0] p1_cmd_bl_i; + wire [29:0] p1_cmd_byte_addr_i; + wire p1_cmd_empty_i; + wire p1_cmd_full_i; + wire p1_wr_clk_i; + wire p1_wr_en_i; + wire [C_P1_MASK_SIZE-1:0] p1_wr_mask_i; + wire [C_P1_DATA_PORT_SIZE-1:0] p1_wr_data_i; + wire p1_wr_full_i; + wire p1_wr_empty_i; + wire [6:0] p1_wr_count_i; + wire p1_wr_underrun_i; + wire p1_wr_error_i; + wire p1_rd_clk_i; + wire p1_rd_en_i; + wire [C_P1_DATA_PORT_SIZE-1:0] p1_rd_data_i; + wire p1_rd_full_i; + wire p1_rd_empty_i; + wire [6:0] p1_rd_count_i; + wire p1_rd_overflow_i; + wire p1_rd_error_i; + + wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_araddr_i; + wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_awaddr_i; + wire p2_arb_en_i; + wire p2_cmd_clk_i; + wire p2_cmd_en_i; + wire [2:0] p2_cmd_instr_i; + wire [5:0] p2_cmd_bl_i; + wire [29:0] p2_cmd_byte_addr_i; + wire p2_cmd_empty_i; + wire p2_cmd_full_i; + wire p2_wr_clk_i; + wire p2_wr_en_i; + wire [3:0] p2_wr_mask_i; + wire [31:0] p2_wr_data_i; + wire p2_wr_full_i; + wire p2_wr_empty_i; + wire [6:0] p2_wr_count_i; + wire p2_wr_underrun_i; + wire p2_wr_error_i; + wire p2_rd_clk_i; + wire p2_rd_en_i; + wire [31:0] p2_rd_data_i; + wire p2_rd_full_i; + wire p2_rd_empty_i; + wire [6:0] p2_rd_count_i; + wire p2_rd_overflow_i; + wire p2_rd_error_i; + + wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_araddr_i; + wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_awaddr_i; + wire p3_arb_en_i; + wire p3_cmd_clk_i; + wire p3_cmd_en_i; + wire [2:0] p3_cmd_instr_i; + wire [5:0] p3_cmd_bl_i; + wire [29:0] p3_cmd_byte_addr_i; + wire p3_cmd_empty_i; + wire p3_cmd_full_i; + wire p3_wr_clk_i; + wire p3_wr_en_i; + wire [3:0] p3_wr_mask_i; + wire [31:0] p3_wr_data_i; + wire p3_wr_full_i; + wire p3_wr_empty_i; + wire [6:0] p3_wr_count_i; + wire p3_wr_underrun_i; + wire p3_wr_error_i; + wire p3_rd_clk_i; + wire p3_rd_en_i; + wire [31:0] p3_rd_data_i; + wire p3_rd_full_i; + wire p3_rd_empty_i; + wire [6:0] p3_rd_count_i; + wire p3_rd_overflow_i; + wire p3_rd_error_i; + + wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_araddr_i; + wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_awaddr_i; + wire p4_arb_en_i; + wire p4_cmd_clk_i; + wire p4_cmd_en_i; + wire [2:0] p4_cmd_instr_i; + wire [5:0] p4_cmd_bl_i; + wire [29:0] p4_cmd_byte_addr_i; + wire p4_cmd_empty_i; + wire p4_cmd_full_i; + wire p4_wr_clk_i; + wire p4_wr_en_i; + wire [3:0] p4_wr_mask_i; + wire [31:0] p4_wr_data_i; + wire p4_wr_full_i; + wire p4_wr_empty_i; + wire [6:0] p4_wr_count_i; + wire p4_wr_underrun_i; + wire p4_wr_error_i; + wire p4_rd_clk_i; + wire p4_rd_en_i; + wire [31:0] p4_rd_data_i; + wire p4_rd_full_i; + wire p4_rd_empty_i; + wire [6:0] p4_rd_count_i; + wire p4_rd_overflow_i; + wire p4_rd_error_i; + + wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_araddr_i; + wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_awaddr_i; + wire p5_arb_en_i; + wire p5_cmd_clk_i; + wire p5_cmd_en_i; + wire [2:0] p5_cmd_instr_i; + wire [5:0] p5_cmd_bl_i; + wire [29:0] p5_cmd_byte_addr_i; + wire p5_cmd_empty_i; + wire p5_cmd_full_i; + wire p5_wr_clk_i; + wire p5_wr_en_i; + wire [3:0] p5_wr_mask_i; + wire [31:0] p5_wr_data_i; + wire p5_wr_full_i; + wire p5_wr_empty_i; + wire [6:0] p5_wr_count_i; + wire p5_wr_underrun_i; + wire p5_wr_error_i; + wire p5_rd_clk_i; + wire p5_rd_en_i; + wire [31:0] p5_rd_data_i; + wire p5_rd_full_i; + wire p5_rd_empty_i; + wire [6:0] p5_rd_count_i; + wire p5_rd_overflow_i; + wire p5_rd_error_i; + + wire ioclk0; + wire ioclk180; + wire pll_ce_0_i; + wire pll_ce_90_i; + + generate + if (C_MCB_USE_EXTERNAL_BUFPLL == 0) begin : gen_spartan6_bufpll_mcb + // Instantiate the PLL for MCB. + BUFPLL_MCB # + ( + .DIVIDE (2), + .LOCK_SRC ("LOCK_TO_0") + ) + bufpll_0 + ( + .IOCLK0 (ioclk0), + .IOCLK1 (ioclk180), + .GCLK (ui_clk), + .LOCKED (pll_lock), + .LOCK (pll_lock_bufpll_o), + .SERDESSTROBE0(pll_ce_0_i), + .SERDESSTROBE1(pll_ce_90_i), + .PLLIN0 (sysclk_2x), + .PLLIN1 (sysclk_2x_180) + ); + end else begin : gen_spartan6_no_bufpll_mcb + // Use external bufpll_mcb. + assign pll_ce_0_i = pll_ce_0; + assign pll_ce_90_i = pll_ce_90; + assign ioclk0 = sysclk_2x; + assign ioclk180 = sysclk_2x_180; + assign pll_lock_bufpll_o = pll_lock; + end + endgenerate + + assign sysclk_2x_bufpll_o = ioclk0; + assign sysclk_2x_180_bufpll_o = ioclk180; + assign pll_ce_0_bufpll_o = pll_ce_0_i; + assign pll_ce_90_bufpll_o = pll_ce_90_i; + +mcb_raw_wrapper # + ( + .C_MEMCLK_PERIOD ( C_MEMCLK_PERIOD ), + .C_PORT_ENABLE ( C_PORT_ENABLE ), + .C_MEM_ADDR_ORDER ( C_MEM_ADDR_ORDER ), + .C_ARB_NUM_TIME_SLOTS ( P_ARB_NUM_TIME_SLOTS ), + .C_ARB_TIME_SLOT_0 ( P_ARB_TIME_SLOT_0 ), + .C_ARB_TIME_SLOT_1 ( P_ARB_TIME_SLOT_1 ), + .C_ARB_TIME_SLOT_2 ( P_ARB_TIME_SLOT_2 ), + .C_ARB_TIME_SLOT_3 ( P_ARB_TIME_SLOT_3 ), + .C_ARB_TIME_SLOT_4 ( P_ARB_TIME_SLOT_4 ), + .C_ARB_TIME_SLOT_5 ( P_ARB_TIME_SLOT_5 ), + .C_ARB_TIME_SLOT_6 ( P_ARB_TIME_SLOT_6 ), + .C_ARB_TIME_SLOT_7 ( P_ARB_TIME_SLOT_7 ), + .C_ARB_TIME_SLOT_8 ( P_ARB_TIME_SLOT_8 ), + .C_ARB_TIME_SLOT_9 ( P_ARB_TIME_SLOT_9 ), + .C_ARB_TIME_SLOT_10 ( P_ARB_TIME_SLOT_10 ), + .C_ARB_TIME_SLOT_11 ( P_ARB_TIME_SLOT_11 ), + .C_PORT_CONFIG ( C_PORT_CONFIG ), + .C_MEM_TRAS ( C_MEM_TRAS ), + .C_MEM_TRCD ( C_MEM_TRCD ), + .C_MEM_TREFI ( C_MEM_TREFI ), + .C_MEM_TRFC ( C_MEM_TRFC ), + .C_MEM_TRP ( C_MEM_TRP ), + .C_MEM_TWR ( C_MEM_TWR ), + .C_MEM_TRTP ( C_MEM_TRTP ), + .C_MEM_TWTR ( C_MEM_TWTR ), + .C_NUM_DQ_PINS ( C_NUM_DQ_PINS ), + .C_MEM_TYPE ( C_MEM_TYPE ), + .C_MEM_DENSITY ( C_MEM_DENSITY ), + .C_MEM_BURST_LEN ( C_MEM_BURST_LEN ), + .C_MEM_CAS_LATENCY ( C_MEM_CAS_LATENCY ), + .C_MEM_ADDR_WIDTH ( C_MEM_ADDR_WIDTH ), + .C_MEM_BANKADDR_WIDTH ( C_MEM_BANKADDR_WIDTH ), + .C_MEM_NUM_COL_BITS ( C_MEM_NUM_COL_BITS ), + .C_MEM_DDR3_CAS_LATENCY ( C_MEM_DDR3_CAS_LATENCY ), + .C_MEM_MOBILE_PA_SR ( C_MEM_MOBILE_PA_SR ), + .C_MEM_DDR1_2_ODS ( C_MEM_DDR1_2_ODS ), + .C_MEM_DDR3_ODS ( C_MEM_DDR3_ODS ), + .C_MEM_DDR2_RTT ( C_MEM_DDR2_RTT ), + .C_MEM_DDR3_RTT ( C_MEM_DDR3_RTT ), + .C_MEM_MDDR_ODS ( C_MEM_MDDR_ODS ), + .C_MEM_DDR2_DIFF_DQS_EN ( C_MEM_DDR2_DIFF_DQS_EN ), + .C_MEM_DDR2_3_PA_SR ( C_MEM_DDR2_3_PA_SR ), + .C_MEM_DDR3_CAS_WR_LATENCY ( C_MEM_DDR3_CAS_WR_LATENCY ), + .C_MEM_DDR3_AUTO_SR ( C_MEM_DDR3_AUTO_SR ), + .C_MEM_DDR2_3_HIGH_TEMP_SR ( C_MEM_DDR2_3_HIGH_TEMP_SR ), + .C_MEM_DDR3_DYN_WRT_ODT ( C_MEM_DDR3_DYN_WRT_ODT ), + // Subtract 16 to stop TRFC violations. + .C_MEM_TZQINIT_MAXCNT ( C_MEM_TZQINIT_MAXCNT - 16 ), + .C_MC_CALIB_BYPASS ( C_MC_CALIB_BYPASS ), + .C_MC_CALIBRATION_RA ( C_MC_CALIBRATION_RA ), + .C_MC_CALIBRATION_BA ( C_MC_CALIBRATION_BA ), + .C_CALIB_SOFT_IP ( C_CALIB_SOFT_IP ), + .C_SKIP_IN_TERM_CAL ( C_SKIP_IN_TERM_CAL ), + .C_SKIP_DYNAMIC_CAL ( C_SKIP_DYNAMIC_CAL ), + .C_SKIP_DYN_IN_TERM ( C_SKIP_DYN_IN_TERM ), + .LDQSP_TAP_DELAY_VAL ( LDQSP_TAP_DELAY_VAL ), + .UDQSP_TAP_DELAY_VAL ( UDQSP_TAP_DELAY_VAL ), + .LDQSN_TAP_DELAY_VAL ( LDQSN_TAP_DELAY_VAL ), + .UDQSN_TAP_DELAY_VAL ( UDQSN_TAP_DELAY_VAL ), + .DQ0_TAP_DELAY_VAL ( DQ0_TAP_DELAY_VAL ), + .DQ1_TAP_DELAY_VAL ( DQ1_TAP_DELAY_VAL ), + .DQ2_TAP_DELAY_VAL ( DQ2_TAP_DELAY_VAL ), + .DQ3_TAP_DELAY_VAL ( DQ3_TAP_DELAY_VAL ), + .DQ4_TAP_DELAY_VAL ( DQ4_TAP_DELAY_VAL ), + .DQ5_TAP_DELAY_VAL ( DQ5_TAP_DELAY_VAL ), + .DQ6_TAP_DELAY_VAL ( DQ6_TAP_DELAY_VAL ), + .DQ7_TAP_DELAY_VAL ( DQ7_TAP_DELAY_VAL ), + .DQ8_TAP_DELAY_VAL ( DQ8_TAP_DELAY_VAL ), + .DQ9_TAP_DELAY_VAL ( DQ9_TAP_DELAY_VAL ), + .DQ10_TAP_DELAY_VAL ( DQ10_TAP_DELAY_VAL ), + .DQ11_TAP_DELAY_VAL ( DQ11_TAP_DELAY_VAL ), + .DQ12_TAP_DELAY_VAL ( DQ12_TAP_DELAY_VAL ), + .DQ13_TAP_DELAY_VAL ( DQ13_TAP_DELAY_VAL ), + .DQ14_TAP_DELAY_VAL ( DQ14_TAP_DELAY_VAL ), + .DQ15_TAP_DELAY_VAL ( DQ15_TAP_DELAY_VAL ), + .C_MC_CALIBRATION_CA ( C_MC_CALIBRATION_CA ), + .C_MC_CALIBRATION_CLK_DIV ( C_MC_CALIBRATION_CLK_DIV ), + .C_MC_CALIBRATION_MODE ( C_MC_CALIBRATION_MODE ), + .C_MC_CALIBRATION_DELAY ( C_MC_CALIBRATION_DELAY ), + // synthesis translate_off + .C_SIMULATION ( C_SIMULATION ), + // synthesis translate_on + .C_P0_MASK_SIZE ( C_P0_MASK_SIZE ), + .C_P0_DATA_PORT_SIZE ( C_P0_DATA_PORT_SIZE ), + .C_P1_MASK_SIZE ( C_P1_MASK_SIZE ), + .C_P1_DATA_PORT_SIZE ( C_P1_DATA_PORT_SIZE ) + ) + mcb_raw_wrapper_inst + ( + .sysclk_2x ( ioclk0 ), + .sysclk_2x_180 ( ioclk180 ), + .pll_ce_0 ( pll_ce_0_i ), + .pll_ce_90 ( pll_ce_90_i ), + .pll_lock ( pll_lock_bufpll_o ), + .sys_rst ( sys_rst ), + .p0_arb_en ( p0_arb_en_i ), + .p0_cmd_clk ( p0_cmd_clk_i ), + .p0_cmd_en ( p0_cmd_en_i ), + .p0_cmd_instr ( p0_cmd_instr_i ), + .p0_cmd_bl ( p0_cmd_bl_i ), + .p0_cmd_byte_addr ( p0_cmd_byte_addr_i ), + .p0_cmd_empty ( p0_cmd_empty_i ), + .p0_cmd_full ( p0_cmd_full_i ), + .p0_wr_clk ( p0_wr_clk_i ), + .p0_wr_en ( p0_wr_en_i ), + .p0_wr_mask ( p0_wr_mask_i ), + .p0_wr_data ( p0_wr_data_i ), + .p0_wr_full ( p0_wr_full_i ), + .p0_wr_empty ( p0_wr_empty_i ), + .p0_wr_count ( p0_wr_count_i ), + .p0_wr_underrun ( p0_wr_underrun_i ), + .p0_wr_error ( p0_wr_error_i ), + .p0_rd_clk ( p0_rd_clk_i ), + .p0_rd_en ( p0_rd_en_i ), + .p0_rd_data ( p0_rd_data_i ), + .p0_rd_full ( p0_rd_full_i ), + .p0_rd_empty ( p0_rd_empty_i ), + .p0_rd_count ( p0_rd_count_i ), + .p0_rd_overflow ( p0_rd_overflow_i ), + .p0_rd_error ( p0_rd_error_i ), + .p1_arb_en ( p1_arb_en_i ), + .p1_cmd_clk ( p1_cmd_clk_i ), + .p1_cmd_en ( p1_cmd_en_i ), + .p1_cmd_instr ( p1_cmd_instr_i ), + .p1_cmd_bl ( p1_cmd_bl_i ), + .p1_cmd_byte_addr ( p1_cmd_byte_addr_i ), + .p1_cmd_empty ( p1_cmd_empty_i ), + .p1_cmd_full ( p1_cmd_full_i ), + .p1_wr_clk ( p1_wr_clk_i ), + .p1_wr_en ( p1_wr_en_i ), + .p1_wr_mask ( p1_wr_mask_i ), + .p1_wr_data ( p1_wr_data_i ), + .p1_wr_full ( p1_wr_full_i ), + .p1_wr_empty ( p1_wr_empty_i ), + .p1_wr_count ( p1_wr_count_i ), + .p1_wr_underrun ( p1_wr_underrun_i ), + .p1_wr_error ( p1_wr_error_i ), + .p1_rd_clk ( p1_rd_clk_i ), + .p1_rd_en ( p1_rd_en_i ), + .p1_rd_data ( p1_rd_data_i ), + .p1_rd_full ( p1_rd_full_i ), + .p1_rd_empty ( p1_rd_empty_i ), + .p1_rd_count ( p1_rd_count_i ), + .p1_rd_overflow ( p1_rd_overflow_i ), + .p1_rd_error ( p1_rd_error_i ), + .p2_arb_en ( p2_arb_en_i ), + .p2_cmd_clk ( p2_cmd_clk_i ), + .p2_cmd_en ( p2_cmd_en_i ), + .p2_cmd_instr ( p2_cmd_instr_i ), + .p2_cmd_bl ( p2_cmd_bl_i ), + .p2_cmd_byte_addr ( p2_cmd_byte_addr_i ), + .p2_cmd_empty ( p2_cmd_empty_i ), + .p2_cmd_full ( p2_cmd_full_i ), + .p2_wr_clk ( p2_wr_clk_i ), + .p2_wr_en ( p2_wr_en_i ), + .p2_wr_mask ( p2_wr_mask_i ), + .p2_wr_data ( p2_wr_data_i ), + .p2_wr_full ( p2_wr_full_i ), + .p2_wr_empty ( p2_wr_empty_i ), + .p2_wr_count ( p2_wr_count_i ), + .p2_wr_underrun ( p2_wr_underrun_i ), + .p2_wr_error ( p2_wr_error_i ), + .p2_rd_clk ( p2_rd_clk_i ), + .p2_rd_en ( p2_rd_en_i ), + .p2_rd_data ( p2_rd_data_i ), + .p2_rd_full ( p2_rd_full_i ), + .p2_rd_empty ( p2_rd_empty_i ), + .p2_rd_count ( p2_rd_count_i ), + .p2_rd_overflow ( p2_rd_overflow_i ), + .p2_rd_error ( p2_rd_error_i ), + .p3_arb_en ( p3_arb_en_i ), + .p3_cmd_clk ( p3_cmd_clk_i ), + .p3_cmd_en ( p3_cmd_en_i ), + .p3_cmd_instr ( p3_cmd_instr_i ), + .p3_cmd_bl ( p3_cmd_bl_i ), + .p3_cmd_byte_addr ( p3_cmd_byte_addr_i ), + .p3_cmd_empty ( p3_cmd_empty_i ), + .p3_cmd_full ( p3_cmd_full_i ), + .p3_wr_clk ( p3_wr_clk_i ), + .p3_wr_en ( p3_wr_en_i ), + .p3_wr_mask ( p3_wr_mask_i ), + .p3_wr_data ( p3_wr_data_i ), + .p3_wr_full ( p3_wr_full_i ), + .p3_wr_empty ( p3_wr_empty_i ), + .p3_wr_count ( p3_wr_count_i ), + .p3_wr_underrun ( p3_wr_underrun_i ), + .p3_wr_error ( p3_wr_error_i ), + .p3_rd_clk ( p3_rd_clk_i ), + .p3_rd_en ( p3_rd_en_i ), + .p3_rd_data ( p3_rd_data_i ), + .p3_rd_full ( p3_rd_full_i ), + .p3_rd_empty ( p3_rd_empty_i ), + .p3_rd_count ( p3_rd_count_i ), + .p3_rd_overflow ( p3_rd_overflow_i ), + .p3_rd_error ( p3_rd_error_i ), + .p4_arb_en ( p4_arb_en_i ), + .p4_cmd_clk ( p4_cmd_clk_i ), + .p4_cmd_en ( p4_cmd_en_i ), + .p4_cmd_instr ( p4_cmd_instr_i ), + .p4_cmd_bl ( p4_cmd_bl_i ), + .p4_cmd_byte_addr ( p4_cmd_byte_addr_i ), + .p4_cmd_empty ( p4_cmd_empty_i ), + .p4_cmd_full ( p4_cmd_full_i ), + .p4_wr_clk ( p4_wr_clk_i ), + .p4_wr_en ( p4_wr_en_i ), + .p4_wr_mask ( p4_wr_mask_i ), + .p4_wr_data ( p4_wr_data_i ), + .p4_wr_full ( p4_wr_full_i ), + .p4_wr_empty ( p4_wr_empty_i ), + .p4_wr_count ( p4_wr_count_i ), + .p4_wr_underrun ( p4_wr_underrun_i ), + .p4_wr_error ( p4_wr_error_i ), + .p4_rd_clk ( p4_rd_clk_i ), + .p4_rd_en ( p4_rd_en_i ), + .p4_rd_data ( p4_rd_data_i ), + .p4_rd_full ( p4_rd_full_i ), + .p4_rd_empty ( p4_rd_empty_i ), + .p4_rd_count ( p4_rd_count_i ), + .p4_rd_overflow ( p4_rd_overflow_i ), + .p4_rd_error ( p4_rd_error_i ), + .p5_arb_en ( p5_arb_en_i ), + .p5_cmd_clk ( p5_cmd_clk_i ), + .p5_cmd_en ( p5_cmd_en_i ), + .p5_cmd_instr ( p5_cmd_instr_i ), + .p5_cmd_bl ( p5_cmd_bl_i ), + .p5_cmd_byte_addr ( p5_cmd_byte_addr_i ), + .p5_cmd_empty ( p5_cmd_empty_i ), + .p5_cmd_full ( p5_cmd_full_i ), + .p5_wr_clk ( p5_wr_clk_i ), + .p5_wr_en ( p5_wr_en_i ), + .p5_wr_mask ( p5_wr_mask_i ), + .p5_wr_data ( p5_wr_data_i ), + .p5_wr_full ( p5_wr_full_i ), + .p5_wr_empty ( p5_wr_empty_i ), + .p5_wr_count ( p5_wr_count_i ), + .p5_wr_underrun ( p5_wr_underrun_i ), + .p5_wr_error ( p5_wr_error_i ), + .p5_rd_clk ( p5_rd_clk_i ), + .p5_rd_en ( p5_rd_en_i ), + .p5_rd_data ( p5_rd_data_i ), + .p5_rd_full ( p5_rd_full_i ), + .p5_rd_empty ( p5_rd_empty_i ), + .p5_rd_count ( p5_rd_count_i ), + .p5_rd_overflow ( p5_rd_overflow_i ), + .p5_rd_error ( p5_rd_error_i ), + .mcbx_dram_addr ( mcbx_dram_addr ), + .mcbx_dram_ba ( mcbx_dram_ba ), + .mcbx_dram_ras_n ( mcbx_dram_ras_n ), + .mcbx_dram_cas_n ( mcbx_dram_cas_n ), + .mcbx_dram_we_n ( mcbx_dram_we_n ), + .mcbx_dram_cke ( mcbx_dram_cke ), + .mcbx_dram_clk ( mcbx_dram_clk ), + .mcbx_dram_clk_n ( mcbx_dram_clk_n ), + .mcbx_dram_dq ( mcbx_dram_dq ), + .mcbx_dram_dqs ( mcbx_dram_dqs ), + .mcbx_dram_dqs_n ( mcbx_dram_dqs_n ), + .mcbx_dram_udqs ( mcbx_dram_udqs ), + .mcbx_dram_udqs_n ( mcbx_dram_udqs_n ), + .mcbx_dram_udm ( mcbx_dram_udm ), + .mcbx_dram_ldm ( mcbx_dram_ldm ), + .mcbx_dram_odt ( mcbx_dram_odt ), + .mcbx_dram_ddr3_rst ( mcbx_dram_ddr3_rst ), + .calib_recal ( calib_recal ), + .rzq ( rzq ), + .zio ( zio ), + .ui_read ( ui_read ), + .ui_add ( ui_add ), + .ui_cs ( ui_cs ), + .ui_clk ( ui_clk ), + .ui_sdi ( ui_sdi ), + .ui_addr ( ui_addr ), + .ui_broadcast ( ui_broadcast ), + .ui_drp_update ( ui_drp_update ), + .ui_done_cal ( ui_done_cal ), + .ui_cmd ( ui_cmd ), + .ui_cmd_in ( ui_cmd_in ), + .ui_cmd_en ( ui_cmd_en ), + .ui_dqcount ( ui_dqcount ), + .ui_dq_lower_dec ( ui_dq_lower_dec ), + .ui_dq_lower_inc ( ui_dq_lower_inc ), + .ui_dq_upper_dec ( ui_dq_upper_dec ), + .ui_dq_upper_inc ( ui_dq_upper_inc ), + .ui_udqs_inc ( ui_udqs_inc ), + .ui_udqs_dec ( ui_udqs_dec ), + .ui_ldqs_inc ( ui_ldqs_inc ), + .ui_ldqs_dec ( ui_ldqs_dec ), + .uo_data ( uo_data ), + .uo_data_valid ( uo_data_valid ), + .uo_done_cal ( uo_done_cal ), + .uo_cmd_ready_in ( uo_cmd_ready_in ), + .uo_refrsh_flag ( uo_refrsh_flag ), + .uo_cal_start ( uo_cal_start ), + .uo_sdo ( uo_sdo ), + .status ( status ), + .selfrefresh_enter ( selfrefresh_enter ), + .selfrefresh_mode ( selfrefresh_mode ) + ); + +// P0 AXI Bridge Mux + generate + if (C_S0_AXI_ENABLE == 0) begin : P0_UI_MCB + assign p0_arb_en_i = p0_arb_en ; // + assign p0_cmd_clk_i = p0_cmd_clk ; // + assign p0_cmd_en_i = p0_cmd_en ; // + assign p0_cmd_instr_i = p0_cmd_instr ; // [2:0] + assign p0_cmd_bl_i = p0_cmd_bl ; // [5:0] + assign p0_cmd_byte_addr_i = p0_cmd_byte_addr ; // [29:0] + assign p0_cmd_empty = p0_cmd_empty_i ; // + assign p0_cmd_full = p0_cmd_full_i ; // + assign p0_wr_clk_i = p0_wr_clk ; // + assign p0_wr_en_i = p0_wr_en ; // + assign p0_wr_mask_i = p0_wr_mask ; // [C_P0_MASK_SIZE-1:0] + assign p0_wr_data_i = p0_wr_data ; // [C_P0_DATA_PORT_SIZE-1:0] + assign p0_wr_full = p0_wr_full_i ; // + assign p0_wr_empty = p0_wr_empty_i ; // + assign p0_wr_count = p0_wr_count_i ; // [6:0] + assign p0_wr_underrun = p0_wr_underrun_i ; // + assign p0_wr_error = p0_wr_error_i ; // + assign p0_rd_clk_i = p0_rd_clk ; // + assign p0_rd_en_i = p0_rd_en ; // + assign p0_rd_data = p0_rd_data_i ; // [C_P0_DATA_PORT_SIZE-1:0] + assign p0_rd_full = p0_rd_full_i ; // + assign p0_rd_empty = p0_rd_empty_i ; // + assign p0_rd_count = p0_rd_count_i ; // [6:0] + assign p0_rd_overflow = p0_rd_overflow_i ; // + assign p0_rd_error = p0_rd_error_i ; // + end + else begin : P0_UI_AXI + assign p0_arb_en_i = p0_arb_en; + assign s0_axi_araddr_i = s0_axi_araddr & P_S0_AXI_ADDRMASK; + assign s0_axi_awaddr_i = s0_axi_awaddr & P_S0_AXI_ADDRMASK; + wire calib_done_synch; + + mcb_ui_top_synch #( + .C_SYNCH_WIDTH ( 1 ) + ) + axi_mcb_synch + ( + .clk ( s0_axi_aclk ) , + .synch_in ( uo_done_cal ) , + .synch_out ( calib_done_synch ) + ); + axi_mcb # + ( + .C_FAMILY ( "spartan6" ) , + .C_S_AXI_ID_WIDTH ( C_S0_AXI_ID_WIDTH ) , + .C_S_AXI_ADDR_WIDTH ( C_S0_AXI_ADDR_WIDTH ) , + .C_S_AXI_DATA_WIDTH ( C_S0_AXI_DATA_WIDTH ) , + .C_S_AXI_SUPPORTS_READ ( C_S0_AXI_SUPPORTS_READ ) , + .C_S_AXI_SUPPORTS_WRITE ( C_S0_AXI_SUPPORTS_WRITE ) , + .C_S_AXI_REG_EN0 ( C_S0_AXI_REG_EN0 ) , + .C_S_AXI_REG_EN1 ( C_S0_AXI_REG_EN1 ) , + .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S0_AXI_SUPPORTS_NARROW_BURST ) , + .C_MCB_ADDR_WIDTH ( 30 ) , + .C_MCB_DATA_WIDTH ( C_P0_DATA_PORT_SIZE ) , + .C_STRICT_COHERENCY ( C_S0_AXI_STRICT_COHERENCY ) , + .C_ENABLE_AP ( C_S0_AXI_ENABLE_AP ) + ) + p0_axi_mcb + ( + .aclk ( s0_axi_aclk ), + .aresetn ( s0_axi_aresetn ), + .s_axi_awid ( s0_axi_awid ), + .s_axi_awaddr ( s0_axi_awaddr_i ), + .s_axi_awlen ( s0_axi_awlen ), + .s_axi_awsize ( s0_axi_awsize ), + .s_axi_awburst ( s0_axi_awburst ), + .s_axi_awlock ( s0_axi_awlock ), + .s_axi_awcache ( s0_axi_awcache ), + .s_axi_awprot ( s0_axi_awprot ), + .s_axi_awqos ( s0_axi_awqos ), + .s_axi_awvalid ( s0_axi_awvalid ), + .s_axi_awready ( s0_axi_awready ), + .s_axi_wdata ( s0_axi_wdata ), + .s_axi_wstrb ( s0_axi_wstrb ), + .s_axi_wlast ( s0_axi_wlast ), + .s_axi_wvalid ( s0_axi_wvalid ), + .s_axi_wready ( s0_axi_wready ), + .s_axi_bid ( s0_axi_bid ), + .s_axi_bresp ( s0_axi_bresp ), + .s_axi_bvalid ( s0_axi_bvalid ), + .s_axi_bready ( s0_axi_bready ), + .s_axi_arid ( s0_axi_arid ), + .s_axi_araddr ( s0_axi_araddr_i ), + .s_axi_arlen ( s0_axi_arlen ), + .s_axi_arsize ( s0_axi_arsize ), + .s_axi_arburst ( s0_axi_arburst ), + .s_axi_arlock ( s0_axi_arlock ), + .s_axi_arcache ( s0_axi_arcache ), + .s_axi_arprot ( s0_axi_arprot ), + .s_axi_arqos ( s0_axi_arqos ), + .s_axi_arvalid ( s0_axi_arvalid ), + .s_axi_arready ( s0_axi_arready ), + .s_axi_rid ( s0_axi_rid ), + .s_axi_rdata ( s0_axi_rdata ), + .s_axi_rresp ( s0_axi_rresp ), + .s_axi_rlast ( s0_axi_rlast ), + .s_axi_rvalid ( s0_axi_rvalid ), + .s_axi_rready ( s0_axi_rready ), + .mcb_cmd_clk ( p0_cmd_clk_i ), + .mcb_cmd_en ( p0_cmd_en_i ), + .mcb_cmd_instr ( p0_cmd_instr_i ), + .mcb_cmd_bl ( p0_cmd_bl_i ), + .mcb_cmd_byte_addr ( p0_cmd_byte_addr_i ), + .mcb_cmd_empty ( p0_cmd_empty_i ), + .mcb_cmd_full ( p0_cmd_full_i ), + .mcb_wr_clk ( p0_wr_clk_i ), + .mcb_wr_en ( p0_wr_en_i ), + .mcb_wr_mask ( p0_wr_mask_i ), + .mcb_wr_data ( p0_wr_data_i ), + .mcb_wr_full ( p0_wr_full_i ), + .mcb_wr_empty ( p0_wr_empty_i ), + .mcb_wr_count ( p0_wr_count_i ), + .mcb_wr_underrun ( p0_wr_underrun_i ), + .mcb_wr_error ( p0_wr_error_i ), + .mcb_rd_clk ( p0_rd_clk_i ), + .mcb_rd_en ( p0_rd_en_i ), + .mcb_rd_data ( p0_rd_data_i ), + .mcb_rd_full ( p0_rd_full_i ), + .mcb_rd_empty ( p0_rd_empty_i ), + .mcb_rd_count ( p0_rd_count_i ), + .mcb_rd_overflow ( p0_rd_overflow_i ), + .mcb_rd_error ( p0_rd_error_i ), + .mcb_calib_done ( calib_done_synch ) + ); + end + endgenerate + +// P1 AXI Bridge Mux + generate + if (C_S1_AXI_ENABLE == 0) begin : P1_UI_MCB + assign p1_arb_en_i = p1_arb_en ; // + assign p1_cmd_clk_i = p1_cmd_clk ; // + assign p1_cmd_en_i = p1_cmd_en ; // + assign p1_cmd_instr_i = p1_cmd_instr ; // [2:0] + assign p1_cmd_bl_i = p1_cmd_bl ; // [5:0] + assign p1_cmd_byte_addr_i = p1_cmd_byte_addr ; // [29:0] + assign p1_cmd_empty = p1_cmd_empty_i ; // + assign p1_cmd_full = p1_cmd_full_i ; // + assign p1_wr_clk_i = p1_wr_clk ; // + assign p1_wr_en_i = p1_wr_en ; // + assign p1_wr_mask_i = p1_wr_mask ; // [C_P1_MASK_SIZE-1:0] + assign p1_wr_data_i = p1_wr_data ; // [C_P1_DATA_PORT_SIZE-1:0] + assign p1_wr_full = p1_wr_full_i ; // + assign p1_wr_empty = p1_wr_empty_i ; // + assign p1_wr_count = p1_wr_count_i ; // [6:0] + assign p1_wr_underrun = p1_wr_underrun_i ; // + assign p1_wr_error = p1_wr_error_i ; // + assign p1_rd_clk_i = p1_rd_clk ; // + assign p1_rd_en_i = p1_rd_en ; // + assign p1_rd_data = p1_rd_data_i ; // [C_P1_DATA_PORT_SIZE-1:0] + assign p1_rd_full = p1_rd_full_i ; // + assign p1_rd_empty = p1_rd_empty_i ; // + assign p1_rd_count = p1_rd_count_i ; // [6:0] + assign p1_rd_overflow = p1_rd_overflow_i ; // + assign p1_rd_error = p1_rd_error_i ; // + end + else begin : P1_UI_AXI + assign p1_arb_en_i = p1_arb_en; + assign s1_axi_araddr_i = s1_axi_araddr & P_S1_AXI_ADDRMASK; + assign s1_axi_awaddr_i = s1_axi_awaddr & P_S1_AXI_ADDRMASK; + wire calib_done_synch; + + mcb_ui_top_synch #( + .C_SYNCH_WIDTH ( 1 ) + ) + axi_mcb_synch + ( + .clk ( s1_axi_aclk ), + .synch_in ( uo_done_cal ), + .synch_out ( calib_done_synch ) + ); + axi_mcb # + ( + .C_FAMILY ( "spartan6" ) , + .C_S_AXI_ID_WIDTH ( C_S1_AXI_ID_WIDTH ) , + .C_S_AXI_ADDR_WIDTH ( C_S1_AXI_ADDR_WIDTH ) , + .C_S_AXI_DATA_WIDTH ( C_S1_AXI_DATA_WIDTH ) , + .C_S_AXI_SUPPORTS_READ ( C_S1_AXI_SUPPORTS_READ ) , + .C_S_AXI_SUPPORTS_WRITE ( C_S1_AXI_SUPPORTS_WRITE ) , + .C_S_AXI_REG_EN0 ( C_S1_AXI_REG_EN0 ) , + .C_S_AXI_REG_EN1 ( C_S1_AXI_REG_EN1 ) , + .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S1_AXI_SUPPORTS_NARROW_BURST ) , + .C_MCB_ADDR_WIDTH ( 30 ) , + .C_MCB_DATA_WIDTH ( C_P1_DATA_PORT_SIZE ) , + .C_STRICT_COHERENCY ( C_S1_AXI_STRICT_COHERENCY ) , + .C_ENABLE_AP ( C_S1_AXI_ENABLE_AP ) + ) + p1_axi_mcb + ( + .aclk ( s1_axi_aclk ), + .aresetn ( s1_axi_aresetn ), + .s_axi_awid ( s1_axi_awid ), + .s_axi_awaddr ( s1_axi_awaddr_i ), + .s_axi_awlen ( s1_axi_awlen ), + .s_axi_awsize ( s1_axi_awsize ), + .s_axi_awburst ( s1_axi_awburst ), + .s_axi_awlock ( s1_axi_awlock ), + .s_axi_awcache ( s1_axi_awcache ), + .s_axi_awprot ( s1_axi_awprot ), + .s_axi_awqos ( s1_axi_awqos ), + .s_axi_awvalid ( s1_axi_awvalid ), + .s_axi_awready ( s1_axi_awready ), + .s_axi_wdata ( s1_axi_wdata ), + .s_axi_wstrb ( s1_axi_wstrb ), + .s_axi_wlast ( s1_axi_wlast ), + .s_axi_wvalid ( s1_axi_wvalid ), + .s_axi_wready ( s1_axi_wready ), + .s_axi_bid ( s1_axi_bid ), + .s_axi_bresp ( s1_axi_bresp ), + .s_axi_bvalid ( s1_axi_bvalid ), + .s_axi_bready ( s1_axi_bready ), + .s_axi_arid ( s1_axi_arid ), + .s_axi_araddr ( s1_axi_araddr_i ), + .s_axi_arlen ( s1_axi_arlen ), + .s_axi_arsize ( s1_axi_arsize ), + .s_axi_arburst ( s1_axi_arburst ), + .s_axi_arlock ( s1_axi_arlock ), + .s_axi_arcache ( s1_axi_arcache ), + .s_axi_arprot ( s1_axi_arprot ), + .s_axi_arqos ( s1_axi_arqos ), + .s_axi_arvalid ( s1_axi_arvalid ), + .s_axi_arready ( s1_axi_arready ), + .s_axi_rid ( s1_axi_rid ), + .s_axi_rdata ( s1_axi_rdata ), + .s_axi_rresp ( s1_axi_rresp ), + .s_axi_rlast ( s1_axi_rlast ), + .s_axi_rvalid ( s1_axi_rvalid ), + .s_axi_rready ( s1_axi_rready ), + .mcb_cmd_clk ( p1_cmd_clk_i ), + .mcb_cmd_en ( p1_cmd_en_i ), + .mcb_cmd_instr ( p1_cmd_instr_i ), + .mcb_cmd_bl ( p1_cmd_bl_i ), + .mcb_cmd_byte_addr ( p1_cmd_byte_addr_i ), + .mcb_cmd_empty ( p1_cmd_empty_i ), + .mcb_cmd_full ( p1_cmd_full_i ), + .mcb_wr_clk ( p1_wr_clk_i ), + .mcb_wr_en ( p1_wr_en_i ), + .mcb_wr_mask ( p1_wr_mask_i ), + .mcb_wr_data ( p1_wr_data_i ), + .mcb_wr_full ( p1_wr_full_i ), + .mcb_wr_empty ( p1_wr_empty_i ), + .mcb_wr_count ( p1_wr_count_i ), + .mcb_wr_underrun ( p1_wr_underrun_i ), + .mcb_wr_error ( p1_wr_error_i ), + .mcb_rd_clk ( p1_rd_clk_i ), + .mcb_rd_en ( p1_rd_en_i ), + .mcb_rd_data ( p1_rd_data_i ), + .mcb_rd_full ( p1_rd_full_i ), + .mcb_rd_empty ( p1_rd_empty_i ), + .mcb_rd_count ( p1_rd_count_i ), + .mcb_rd_overflow ( p1_rd_overflow_i ), + .mcb_rd_error ( p1_rd_error_i ), + .mcb_calib_done ( calib_done_synch ) + ); + end + endgenerate + +// P2 AXI Bridge Mux + generate + if (C_S2_AXI_ENABLE == 0) begin : P2_UI_MCB + assign p2_arb_en_i = p2_arb_en ; // + assign p2_cmd_clk_i = p2_cmd_clk ; // + assign p2_cmd_en_i = p2_cmd_en ; // + assign p2_cmd_instr_i = p2_cmd_instr ; // [2:0] + assign p2_cmd_bl_i = p2_cmd_bl ; // [5:0] + assign p2_cmd_byte_addr_i = p2_cmd_byte_addr ; // [29:0] + assign p2_cmd_empty = p2_cmd_empty_i ; // + assign p2_cmd_full = p2_cmd_full_i ; // + assign p2_wr_clk_i = p2_wr_clk ; // + assign p2_wr_en_i = p2_wr_en ; // + assign p2_wr_mask_i = p2_wr_mask ; // [3:0] + assign p2_wr_data_i = p2_wr_data ; // [31:0] + assign p2_wr_full = p2_wr_full_i ; // + assign p2_wr_empty = p2_wr_empty_i ; // + assign p2_wr_count = p2_wr_count_i ; // [6:0] + assign p2_wr_underrun = p2_wr_underrun_i ; // + assign p2_wr_error = p2_wr_error_i ; // + assign p2_rd_clk_i = p2_rd_clk ; // + assign p2_rd_en_i = p2_rd_en ; // + assign p2_rd_data = p2_rd_data_i ; // [31:0] + assign p2_rd_full = p2_rd_full_i ; // + assign p2_rd_empty = p2_rd_empty_i ; // + assign p2_rd_count = p2_rd_count_i ; // [6:0] + assign p2_rd_overflow = p2_rd_overflow_i ; // + assign p2_rd_error = p2_rd_error_i ; // + end + else begin : P2_UI_AXI + assign p2_arb_en_i = p2_arb_en; + assign s2_axi_araddr_i = s2_axi_araddr & P_S2_AXI_ADDRMASK; + assign s2_axi_awaddr_i = s2_axi_awaddr & P_S2_AXI_ADDRMASK; + wire calib_done_synch; + + mcb_ui_top_synch #( + .C_SYNCH_WIDTH ( 1 ) + ) + axi_mcb_synch + ( + .clk ( s2_axi_aclk ), + .synch_in ( uo_done_cal ), + .synch_out ( calib_done_synch ) + ); + axi_mcb # + ( + .C_FAMILY ( "spartan6" ) , + .C_S_AXI_ID_WIDTH ( C_S2_AXI_ID_WIDTH ) , + .C_S_AXI_ADDR_WIDTH ( C_S2_AXI_ADDR_WIDTH ) , + .C_S_AXI_DATA_WIDTH ( 32 ) , + .C_S_AXI_SUPPORTS_READ ( C_S2_AXI_SUPPORTS_READ ) , + .C_S_AXI_SUPPORTS_WRITE ( C_S2_AXI_SUPPORTS_WRITE ) , + .C_S_AXI_REG_EN0 ( C_S2_AXI_REG_EN0 ) , + .C_S_AXI_REG_EN1 ( C_S2_AXI_REG_EN1 ) , + .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S2_AXI_SUPPORTS_NARROW_BURST ) , + .C_MCB_ADDR_WIDTH ( 30 ) , + .C_MCB_DATA_WIDTH ( 32 ) , + .C_STRICT_COHERENCY ( C_S2_AXI_STRICT_COHERENCY ) , + .C_ENABLE_AP ( C_S2_AXI_ENABLE_AP ) + ) + p2_axi_mcb + ( + .aclk ( s2_axi_aclk ), + .aresetn ( s2_axi_aresetn ), + .s_axi_awid ( s2_axi_awid ), + .s_axi_awaddr ( s2_axi_awaddr_i ), + .s_axi_awlen ( s2_axi_awlen ), + .s_axi_awsize ( s2_axi_awsize ), + .s_axi_awburst ( s2_axi_awburst ), + .s_axi_awlock ( s2_axi_awlock ), + .s_axi_awcache ( s2_axi_awcache ), + .s_axi_awprot ( s2_axi_awprot ), + .s_axi_awqos ( s2_axi_awqos ), + .s_axi_awvalid ( s2_axi_awvalid ), + .s_axi_awready ( s2_axi_awready ), + .s_axi_wdata ( s2_axi_wdata ), + .s_axi_wstrb ( s2_axi_wstrb ), + .s_axi_wlast ( s2_axi_wlast ), + .s_axi_wvalid ( s2_axi_wvalid ), + .s_axi_wready ( s2_axi_wready ), + .s_axi_bid ( s2_axi_bid ), + .s_axi_bresp ( s2_axi_bresp ), + .s_axi_bvalid ( s2_axi_bvalid ), + .s_axi_bready ( s2_axi_bready ), + .s_axi_arid ( s2_axi_arid ), + .s_axi_araddr ( s2_axi_araddr_i ), + .s_axi_arlen ( s2_axi_arlen ), + .s_axi_arsize ( s2_axi_arsize ), + .s_axi_arburst ( s2_axi_arburst ), + .s_axi_arlock ( s2_axi_arlock ), + .s_axi_arcache ( s2_axi_arcache ), + .s_axi_arprot ( s2_axi_arprot ), + .s_axi_arqos ( s2_axi_arqos ), + .s_axi_arvalid ( s2_axi_arvalid ), + .s_axi_arready ( s2_axi_arready ), + .s_axi_rid ( s2_axi_rid ), + .s_axi_rdata ( s2_axi_rdata ), + .s_axi_rresp ( s2_axi_rresp ), + .s_axi_rlast ( s2_axi_rlast ), + .s_axi_rvalid ( s2_axi_rvalid ), + .s_axi_rready ( s2_axi_rready ), + .mcb_cmd_clk ( p2_cmd_clk_i ), + .mcb_cmd_en ( p2_cmd_en_i ), + .mcb_cmd_instr ( p2_cmd_instr_i ), + .mcb_cmd_bl ( p2_cmd_bl_i ), + .mcb_cmd_byte_addr ( p2_cmd_byte_addr_i ), + .mcb_cmd_empty ( p2_cmd_empty_i ), + .mcb_cmd_full ( p2_cmd_full_i ), + .mcb_wr_clk ( p2_wr_clk_i ), + .mcb_wr_en ( p2_wr_en_i ), + .mcb_wr_mask ( p2_wr_mask_i ), + .mcb_wr_data ( p2_wr_data_i ), + .mcb_wr_full ( p2_wr_full_i ), + .mcb_wr_empty ( p2_wr_empty_i ), + .mcb_wr_count ( p2_wr_count_i ), + .mcb_wr_underrun ( p2_wr_underrun_i ), + .mcb_wr_error ( p2_wr_error_i ), + .mcb_rd_clk ( p2_rd_clk_i ), + .mcb_rd_en ( p2_rd_en_i ), + .mcb_rd_data ( p2_rd_data_i ), + .mcb_rd_full ( p2_rd_full_i ), + .mcb_rd_empty ( p2_rd_empty_i ), + .mcb_rd_count ( p2_rd_count_i ), + .mcb_rd_overflow ( p2_rd_overflow_i ), + .mcb_rd_error ( p2_rd_error_i ), + .mcb_calib_done ( calib_done_synch ) + ); + end + endgenerate + +// P3 AXI Bridge Mux + generate + if (C_S3_AXI_ENABLE == 0) begin : P3_UI_MCB + assign p3_arb_en_i = p3_arb_en ; // + assign p3_cmd_clk_i = p3_cmd_clk ; // + assign p3_cmd_en_i = p3_cmd_en ; // + assign p3_cmd_instr_i = p3_cmd_instr ; // [2:0] + assign p3_cmd_bl_i = p3_cmd_bl ; // [5:0] + assign p3_cmd_byte_addr_i = p3_cmd_byte_addr ; // [29:0] + assign p3_cmd_empty = p3_cmd_empty_i ; // + assign p3_cmd_full = p3_cmd_full_i ; // + assign p3_wr_clk_i = p3_wr_clk ; // + assign p3_wr_en_i = p3_wr_en ; // + assign p3_wr_mask_i = p3_wr_mask ; // [3:0] + assign p3_wr_data_i = p3_wr_data ; // [31:0] + assign p3_wr_full = p3_wr_full_i ; // + assign p3_wr_empty = p3_wr_empty_i ; // + assign p3_wr_count = p3_wr_count_i ; // [6:0] + assign p3_wr_underrun = p3_wr_underrun_i ; // + assign p3_wr_error = p3_wr_error_i ; // + assign p3_rd_clk_i = p3_rd_clk ; // + assign p3_rd_en_i = p3_rd_en ; // + assign p3_rd_data = p3_rd_data_i ; // [31:0] + assign p3_rd_full = p3_rd_full_i ; // + assign p3_rd_empty = p3_rd_empty_i ; // + assign p3_rd_count = p3_rd_count_i ; // [6:0] + assign p3_rd_overflow = p3_rd_overflow_i ; // + assign p3_rd_error = p3_rd_error_i ; // + end + else begin : P3_UI_AXI + assign p3_arb_en_i = p3_arb_en; + assign s3_axi_araddr_i = s3_axi_araddr & P_S3_AXI_ADDRMASK; + assign s3_axi_awaddr_i = s3_axi_awaddr & P_S3_AXI_ADDRMASK; + wire calib_done_synch; + + mcb_ui_top_synch #( + .C_SYNCH_WIDTH ( 1 ) + ) + axi_mcb_synch + ( + .clk ( s3_axi_aclk ), + .synch_in ( uo_done_cal ), + .synch_out ( calib_done_synch ) + ); + + axi_mcb # + ( + .C_FAMILY ( "spartan6" ) , + .C_S_AXI_ID_WIDTH ( C_S3_AXI_ID_WIDTH ) , + .C_S_AXI_ADDR_WIDTH ( C_S3_AXI_ADDR_WIDTH ) , + .C_S_AXI_DATA_WIDTH ( 32 ) , + .C_S_AXI_SUPPORTS_READ ( C_S3_AXI_SUPPORTS_READ ) , + .C_S_AXI_SUPPORTS_WRITE ( C_S3_AXI_SUPPORTS_WRITE ) , + .C_S_AXI_REG_EN0 ( C_S3_AXI_REG_EN0 ) , + .C_S_AXI_REG_EN1 ( C_S3_AXI_REG_EN1 ) , + .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S3_AXI_SUPPORTS_NARROW_BURST ) , + .C_MCB_ADDR_WIDTH ( 30 ) , + .C_MCB_DATA_WIDTH ( 32 ) , + .C_STRICT_COHERENCY ( C_S3_AXI_STRICT_COHERENCY ) , + .C_ENABLE_AP ( C_S3_AXI_ENABLE_AP ) + ) + p3_axi_mcb + ( + .aclk ( s3_axi_aclk ), + .aresetn ( s3_axi_aresetn ), + .s_axi_awid ( s3_axi_awid ), + .s_axi_awaddr ( s3_axi_awaddr_i ), + .s_axi_awlen ( s3_axi_awlen ), + .s_axi_awsize ( s3_axi_awsize ), + .s_axi_awburst ( s3_axi_awburst ), + .s_axi_awlock ( s3_axi_awlock ), + .s_axi_awcache ( s3_axi_awcache ), + .s_axi_awprot ( s3_axi_awprot ), + .s_axi_awqos ( s3_axi_awqos ), + .s_axi_awvalid ( s3_axi_awvalid ), + .s_axi_awready ( s3_axi_awready ), + .s_axi_wdata ( s3_axi_wdata ), + .s_axi_wstrb ( s3_axi_wstrb ), + .s_axi_wlast ( s3_axi_wlast ), + .s_axi_wvalid ( s3_axi_wvalid ), + .s_axi_wready ( s3_axi_wready ), + .s_axi_bid ( s3_axi_bid ), + .s_axi_bresp ( s3_axi_bresp ), + .s_axi_bvalid ( s3_axi_bvalid ), + .s_axi_bready ( s3_axi_bready ), + .s_axi_arid ( s3_axi_arid ), + .s_axi_araddr ( s3_axi_araddr_i ), + .s_axi_arlen ( s3_axi_arlen ), + .s_axi_arsize ( s3_axi_arsize ), + .s_axi_arburst ( s3_axi_arburst ), + .s_axi_arlock ( s3_axi_arlock ), + .s_axi_arcache ( s3_axi_arcache ), + .s_axi_arprot ( s3_axi_arprot ), + .s_axi_arqos ( s3_axi_arqos ), + .s_axi_arvalid ( s3_axi_arvalid ), + .s_axi_arready ( s3_axi_arready ), + .s_axi_rid ( s3_axi_rid ), + .s_axi_rdata ( s3_axi_rdata ), + .s_axi_rresp ( s3_axi_rresp ), + .s_axi_rlast ( s3_axi_rlast ), + .s_axi_rvalid ( s3_axi_rvalid ), + .s_axi_rready ( s3_axi_rready ), + .mcb_cmd_clk ( p3_cmd_clk_i ), + .mcb_cmd_en ( p3_cmd_en_i ), + .mcb_cmd_instr ( p3_cmd_instr_i ), + .mcb_cmd_bl ( p3_cmd_bl_i ), + .mcb_cmd_byte_addr ( p3_cmd_byte_addr_i ), + .mcb_cmd_empty ( p3_cmd_empty_i ), + .mcb_cmd_full ( p3_cmd_full_i ), + .mcb_wr_clk ( p3_wr_clk_i ), + .mcb_wr_en ( p3_wr_en_i ), + .mcb_wr_mask ( p3_wr_mask_i ), + .mcb_wr_data ( p3_wr_data_i ), + .mcb_wr_full ( p3_wr_full_i ), + .mcb_wr_empty ( p3_wr_empty_i ), + .mcb_wr_count ( p3_wr_count_i ), + .mcb_wr_underrun ( p3_wr_underrun_i ), + .mcb_wr_error ( p3_wr_error_i ), + .mcb_rd_clk ( p3_rd_clk_i ), + .mcb_rd_en ( p3_rd_en_i ), + .mcb_rd_data ( p3_rd_data_i ), + .mcb_rd_full ( p3_rd_full_i ), + .mcb_rd_empty ( p3_rd_empty_i ), + .mcb_rd_count ( p3_rd_count_i ), + .mcb_rd_overflow ( p3_rd_overflow_i ), + .mcb_rd_error ( p3_rd_error_i ), + .mcb_calib_done ( calib_done_synch ) + ); + end + endgenerate + +// P4 AXI Bridge Mux + generate + if (C_S4_AXI_ENABLE == 0) begin : P4_UI_MCB + assign p4_arb_en_i = p4_arb_en ; // + assign p4_cmd_clk_i = p4_cmd_clk ; // + assign p4_cmd_en_i = p4_cmd_en ; // + assign p4_cmd_instr_i = p4_cmd_instr ; // [2:0] + assign p4_cmd_bl_i = p4_cmd_bl ; // [5:0] + assign p4_cmd_byte_addr_i = p4_cmd_byte_addr ; // [29:0] + assign p4_cmd_empty = p4_cmd_empty_i ; // + assign p4_cmd_full = p4_cmd_full_i ; // + assign p4_wr_clk_i = p4_wr_clk ; // + assign p4_wr_en_i = p4_wr_en ; // + assign p4_wr_mask_i = p4_wr_mask ; // [3:0] + assign p4_wr_data_i = p4_wr_data ; // [31:0] + assign p4_wr_full = p4_wr_full_i ; // + assign p4_wr_empty = p4_wr_empty_i ; // + assign p4_wr_count = p4_wr_count_i ; // [6:0] + assign p4_wr_underrun = p4_wr_underrun_i ; // + assign p4_wr_error = p4_wr_error_i ; // + assign p4_rd_clk_i = p4_rd_clk ; // + assign p4_rd_en_i = p4_rd_en ; // + assign p4_rd_data = p4_rd_data_i ; // [31:0] + assign p4_rd_full = p4_rd_full_i ; // + assign p4_rd_empty = p4_rd_empty_i ; // + assign p4_rd_count = p4_rd_count_i ; // [6:0] + assign p4_rd_overflow = p4_rd_overflow_i ; // + assign p4_rd_error = p4_rd_error_i ; // + end + else begin : P4_UI_AXI + assign p4_arb_en_i = p4_arb_en; + assign s4_axi_araddr_i = s4_axi_araddr & P_S4_AXI_ADDRMASK; + assign s4_axi_awaddr_i = s4_axi_awaddr & P_S4_AXI_ADDRMASK; + wire calib_done_synch; + + mcb_ui_top_synch #( + .C_SYNCH_WIDTH ( 1 ) + ) + axi_mcb_synch + ( + .clk ( s4_axi_aclk ), + .synch_in ( uo_done_cal ), + .synch_out ( calib_done_synch ) + ); + + axi_mcb # + ( + .C_FAMILY ( "spartan6" ) , + .C_S_AXI_ID_WIDTH ( C_S4_AXI_ID_WIDTH ) , + .C_S_AXI_ADDR_WIDTH ( C_S4_AXI_ADDR_WIDTH ) , + .C_S_AXI_DATA_WIDTH ( 32 ) , + .C_S_AXI_SUPPORTS_READ ( C_S4_AXI_SUPPORTS_READ ) , + .C_S_AXI_SUPPORTS_WRITE ( C_S4_AXI_SUPPORTS_WRITE ) , + .C_S_AXI_REG_EN0 ( C_S4_AXI_REG_EN0 ) , + .C_S_AXI_REG_EN1 ( C_S4_AXI_REG_EN1 ) , + .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S4_AXI_SUPPORTS_NARROW_BURST ) , + .C_MCB_ADDR_WIDTH ( 30 ) , + .C_MCB_DATA_WIDTH ( 32 ) , + .C_STRICT_COHERENCY ( C_S4_AXI_STRICT_COHERENCY ) , + .C_ENABLE_AP ( C_S4_AXI_ENABLE_AP ) + ) + p4_axi_mcb + ( + .aclk ( s4_axi_aclk ), + .aresetn ( s4_axi_aresetn ), + .s_axi_awid ( s4_axi_awid ), + .s_axi_awaddr ( s4_axi_awaddr_i ), + .s_axi_awlen ( s4_axi_awlen ), + .s_axi_awsize ( s4_axi_awsize ), + .s_axi_awburst ( s4_axi_awburst ), + .s_axi_awlock ( s4_axi_awlock ), + .s_axi_awcache ( s4_axi_awcache ), + .s_axi_awprot ( s4_axi_awprot ), + .s_axi_awqos ( s4_axi_awqos ), + .s_axi_awvalid ( s4_axi_awvalid ), + .s_axi_awready ( s4_axi_awready ), + .s_axi_wdata ( s4_axi_wdata ), + .s_axi_wstrb ( s4_axi_wstrb ), + .s_axi_wlast ( s4_axi_wlast ), + .s_axi_wvalid ( s4_axi_wvalid ), + .s_axi_wready ( s4_axi_wready ), + .s_axi_bid ( s4_axi_bid ), + .s_axi_bresp ( s4_axi_bresp ), + .s_axi_bvalid ( s4_axi_bvalid ), + .s_axi_bready ( s4_axi_bready ), + .s_axi_arid ( s4_axi_arid ), + .s_axi_araddr ( s4_axi_araddr_i ), + .s_axi_arlen ( s4_axi_arlen ), + .s_axi_arsize ( s4_axi_arsize ), + .s_axi_arburst ( s4_axi_arburst ), + .s_axi_arlock ( s4_axi_arlock ), + .s_axi_arcache ( s4_axi_arcache ), + .s_axi_arprot ( s4_axi_arprot ), + .s_axi_arqos ( s4_axi_arqos ), + .s_axi_arvalid ( s4_axi_arvalid ), + .s_axi_arready ( s4_axi_arready ), + .s_axi_rid ( s4_axi_rid ), + .s_axi_rdata ( s4_axi_rdata ), + .s_axi_rresp ( s4_axi_rresp ), + .s_axi_rlast ( s4_axi_rlast ), + .s_axi_rvalid ( s4_axi_rvalid ), + .s_axi_rready ( s4_axi_rready ), + .mcb_cmd_clk ( p4_cmd_clk_i ), + .mcb_cmd_en ( p4_cmd_en_i ), + .mcb_cmd_instr ( p4_cmd_instr_i ), + .mcb_cmd_bl ( p4_cmd_bl_i ), + .mcb_cmd_byte_addr ( p4_cmd_byte_addr_i ), + .mcb_cmd_empty ( p4_cmd_empty_i ), + .mcb_cmd_full ( p4_cmd_full_i ), + .mcb_wr_clk ( p4_wr_clk_i ), + .mcb_wr_en ( p4_wr_en_i ), + .mcb_wr_mask ( p4_wr_mask_i ), + .mcb_wr_data ( p4_wr_data_i ), + .mcb_wr_full ( p4_wr_full_i ), + .mcb_wr_empty ( p4_wr_empty_i ), + .mcb_wr_count ( p4_wr_count_i ), + .mcb_wr_underrun ( p4_wr_underrun_i ), + .mcb_wr_error ( p4_wr_error_i ), + .mcb_rd_clk ( p4_rd_clk_i ), + .mcb_rd_en ( p4_rd_en_i ), + .mcb_rd_data ( p4_rd_data_i ), + .mcb_rd_full ( p4_rd_full_i ), + .mcb_rd_empty ( p4_rd_empty_i ), + .mcb_rd_count ( p4_rd_count_i ), + .mcb_rd_overflow ( p4_rd_overflow_i ), + .mcb_rd_error ( p4_rd_error_i ), + .mcb_calib_done ( calib_done_synch ) + ); + end + endgenerate + +// P5 AXI Bridge Mux + generate + if (C_S5_AXI_ENABLE == 0) begin : P5_UI_MCB + assign p5_arb_en_i = p5_arb_en ; // + assign p5_cmd_clk_i = p5_cmd_clk ; // + assign p5_cmd_en_i = p5_cmd_en ; // + assign p5_cmd_instr_i = p5_cmd_instr ; // [2:0] + assign p5_cmd_bl_i = p5_cmd_bl ; // [5:0] + assign p5_cmd_byte_addr_i = p5_cmd_byte_addr ; // [29:0] + assign p5_cmd_empty = p5_cmd_empty_i ; // + assign p5_cmd_full = p5_cmd_full_i ; // + assign p5_wr_clk_i = p5_wr_clk ; // + assign p5_wr_en_i = p5_wr_en ; // + assign p5_wr_mask_i = p5_wr_mask ; // [3:0] + assign p5_wr_data_i = p5_wr_data ; // [31:0] + assign p5_wr_full = p5_wr_full_i ; // + assign p5_wr_empty = p5_wr_empty_i ; // + assign p5_wr_count = p5_wr_count_i ; // [6:0] + assign p5_wr_underrun = p5_wr_underrun_i ; // + assign p5_wr_error = p5_wr_error_i ; // + assign p5_rd_clk_i = p5_rd_clk ; // + assign p5_rd_en_i = p5_rd_en ; // + assign p5_rd_data = p5_rd_data_i ; // [31:0] + assign p5_rd_full = p5_rd_full_i ; // + assign p5_rd_empty = p5_rd_empty_i ; // + assign p5_rd_count = p5_rd_count_i ; // [6:0] + assign p5_rd_overflow = p5_rd_overflow_i ; // + assign p5_rd_error = p5_rd_error_i ; // + end + else begin : P5_UI_AXI + assign p5_arb_en_i = p5_arb_en; + assign s5_axi_araddr_i = s5_axi_araddr & P_S5_AXI_ADDRMASK; + assign s5_axi_awaddr_i = s5_axi_awaddr & P_S5_AXI_ADDRMASK; + wire calib_done_synch; + + mcb_ui_top_synch #( + .C_SYNCH_WIDTH ( 1 ) + ) + axi_mcb_synch + ( + .clk ( s5_axi_aclk ), + .synch_in ( uo_done_cal ), + .synch_out ( calib_done_synch ) + ); + + axi_mcb # + ( + .C_FAMILY ( "spartan6" ) , + .C_S_AXI_ID_WIDTH ( C_S5_AXI_ID_WIDTH ) , + .C_S_AXI_ADDR_WIDTH ( C_S5_AXI_ADDR_WIDTH ) , + .C_S_AXI_DATA_WIDTH ( 32 ) , + .C_S_AXI_SUPPORTS_READ ( C_S5_AXI_SUPPORTS_READ ) , + .C_S_AXI_SUPPORTS_WRITE ( C_S5_AXI_SUPPORTS_WRITE ) , + .C_S_AXI_REG_EN0 ( C_S5_AXI_REG_EN0 ) , + .C_S_AXI_REG_EN1 ( C_S5_AXI_REG_EN1 ) , + .C_S_AXI_SUPPORTS_NARROW_BURST ( C_S5_AXI_SUPPORTS_NARROW_BURST ) , + .C_MCB_ADDR_WIDTH ( 30 ) , + .C_MCB_DATA_WIDTH ( 32 ) , + .C_STRICT_COHERENCY ( C_S5_AXI_STRICT_COHERENCY ) , + .C_ENABLE_AP ( C_S5_AXI_ENABLE_AP ) + ) + p5_axi_mcb + ( + .aclk ( s5_axi_aclk ), + .aresetn ( s5_axi_aresetn ), + .s_axi_awid ( s5_axi_awid ), + .s_axi_awaddr ( s5_axi_awaddr_i ), + .s_axi_awlen ( s5_axi_awlen ), + .s_axi_awsize ( s5_axi_awsize ), + .s_axi_awburst ( s5_axi_awburst ), + .s_axi_awlock ( s5_axi_awlock ), + .s_axi_awcache ( s5_axi_awcache ), + .s_axi_awprot ( s5_axi_awprot ), + .s_axi_awqos ( s5_axi_awqos ), + .s_axi_awvalid ( s5_axi_awvalid ), + .s_axi_awready ( s5_axi_awready ), + .s_axi_wdata ( s5_axi_wdata ), + .s_axi_wstrb ( s5_axi_wstrb ), + .s_axi_wlast ( s5_axi_wlast ), + .s_axi_wvalid ( s5_axi_wvalid ), + .s_axi_wready ( s5_axi_wready ), + .s_axi_bid ( s5_axi_bid ), + .s_axi_bresp ( s5_axi_bresp ), + .s_axi_bvalid ( s5_axi_bvalid ), + .s_axi_bready ( s5_axi_bready ), + .s_axi_arid ( s5_axi_arid ), + .s_axi_araddr ( s5_axi_araddr_i ), + .s_axi_arlen ( s5_axi_arlen ), + .s_axi_arsize ( s5_axi_arsize ), + .s_axi_arburst ( s5_axi_arburst ), + .s_axi_arlock ( s5_axi_arlock ), + .s_axi_arcache ( s5_axi_arcache ), + .s_axi_arprot ( s5_axi_arprot ), + .s_axi_arqos ( s5_axi_arqos ), + .s_axi_arvalid ( s5_axi_arvalid ), + .s_axi_arready ( s5_axi_arready ), + .s_axi_rid ( s5_axi_rid ), + .s_axi_rdata ( s5_axi_rdata ), + .s_axi_rresp ( s5_axi_rresp ), + .s_axi_rlast ( s5_axi_rlast ), + .s_axi_rvalid ( s5_axi_rvalid ), + .s_axi_rready ( s5_axi_rready ), + .mcb_cmd_clk ( p5_cmd_clk_i ), + .mcb_cmd_en ( p5_cmd_en_i ), + .mcb_cmd_instr ( p5_cmd_instr_i ), + .mcb_cmd_bl ( p5_cmd_bl_i ), + .mcb_cmd_byte_addr ( p5_cmd_byte_addr_i ), + .mcb_cmd_empty ( p5_cmd_empty_i ), + .mcb_cmd_full ( p5_cmd_full_i ), + .mcb_wr_clk ( p5_wr_clk_i ), + .mcb_wr_en ( p5_wr_en_i ), + .mcb_wr_mask ( p5_wr_mask_i ), + .mcb_wr_data ( p5_wr_data_i ), + .mcb_wr_full ( p5_wr_full_i ), + .mcb_wr_empty ( p5_wr_empty_i ), + .mcb_wr_count ( p5_wr_count_i ), + .mcb_wr_underrun ( p5_wr_underrun_i ), + .mcb_wr_error ( p5_wr_error_i ), + .mcb_rd_clk ( p5_rd_clk_i ), + .mcb_rd_en ( p5_rd_en_i ), + .mcb_rd_data ( p5_rd_data_i ), + .mcb_rd_full ( p5_rd_full_i ), + .mcb_rd_empty ( p5_rd_empty_i ), + .mcb_rd_count ( p5_rd_count_i ), + .mcb_rd_overflow ( p5_rd_overflow_i ), + .mcb_rd_error ( p5_rd_error_i ), + .mcb_calib_done ( calib_done_synch ) + ); + end + endgenerate + +endmodule +
xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_ui_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v (revision 627) @@ -0,0 +1,427 @@ +//***************************************************************************** +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: iodrp_mcb_controller.v +// /___/ /\ Date Last Modified: $Date: 2010/10/27 17:40:12 $ +// \ \ / \ Date Created: Mon Feb 9 2009 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: Xilinx reference design for IODRP controller for v0.9 device +//Reference: +// +// Revision: Date: Comment +// 1.0: 3/19/09: Initial version for IODRP_MCB read operations. +// 1.1: 4/03/09: SLH - Added left shift for certain IOI's +// End Revision +//********************************************************************************** + +`timescale 1ps/1ps + +`ifdef ALTERNATE_READ +`else + `define ALTERNATE_READ 1'b1 +`endif + +module iodrp_mcb_controller( + input wire [7:0] memcell_address, + input wire [7:0] write_data, + output reg [7:0] read_data = 0, + input wire rd_not_write, + input wire cmd_valid, + output wire rdy_busy_n, + input wire use_broadcast, + input wire [4:0] drp_ioi_addr, + input wire sync_rst, + input wire DRP_CLK, + output reg DRP_CS, + output wire DRP_SDI, //output to IODRP SDI pin + output reg DRP_ADD, + output reg DRP_BKST, + input wire DRP_SDO, //input from IODRP SDO pin + output reg MCB_UIREAD = 1'b0 + ); + + reg [7:0] memcell_addr_reg; // Register where memcell_address is captured during the READY state + reg [7:0] data_reg; // Register which stores the write data until it is ready to be shifted out + reg [8:0] shift_through_reg; // The shift register which shifts out SDO and shifts in SDI. + // This register is loaded before the address or data phase, but continues to shift for a writeback of read data + reg load_shift_n; // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO + reg addr_data_sel_n; // The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg + reg [2:0] bit_cnt= 3'b0; // The counter for which bit is being shifted during address or data phase + reg rd_not_write_reg; + reg AddressPhase; // This is set after the first address phase has executed + reg DRP_CS_pre; + reg extra_cs; + + (* FSM_ENCODING="GRAY" *) reg [3:0] state, nextstate; + + wire [8:0] data_out; + reg [8:0] data_out_mux; // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg + wire DRP_SDI_pre; //added so that DRP_SDI output is only active when DRP_CS is active + + localparam READY = 4'h0; + localparam DECIDE = 4'h1; + localparam ADDR_PHASE = 4'h2; + localparam ADDR_TO_DATA_GAP = 4'h3; + localparam ADDR_TO_DATA_GAP2 = 4'h4; + localparam ADDR_TO_DATA_GAP3 = 4'h5; + localparam DATA_PHASE = 4'h6; + localparam ALMOST_READY = 4'h7; + localparam ALMOST_READY2 = 4'h8; + localparam ALMOST_READY3 = 4'h9; + + localparam IOI_DQ0 = 5'h01; + localparam IOI_DQ1 = 5'h00; + localparam IOI_DQ2 = 5'h03; + localparam IOI_DQ3 = 5'h02; + localparam IOI_DQ4 = 5'h05; + localparam IOI_DQ5 = 5'h04; + localparam IOI_DQ6 = 5'h07; + localparam IOI_DQ7 = 5'h06; + localparam IOI_DQ8 = 5'h09; + localparam IOI_DQ9 = 5'h08; + localparam IOI_DQ10 = 5'h0B; + localparam IOI_DQ11 = 5'h0A; + localparam IOI_DQ12 = 5'h0D; + localparam IOI_DQ13 = 5'h0C; + localparam IOI_DQ14 = 5'h0F; + localparam IOI_DQ15 = 5'h0E; + localparam IOI_UDQS_CLK = 5'h1D; + localparam IOI_UDQS_PIN = 5'h1C; + localparam IOI_LDQS_CLK = 5'h1F; + localparam IOI_LDQS_PIN = 5'h1E; + + //synthesis translate_off + reg [32*8-1:0] state_ascii; + always @ (state) begin + case (state) + READY :state_ascii<="READY"; + DECIDE :state_ascii<="DECIDE"; + ADDR_PHASE :state_ascii<="ADDR_PHASE"; + ADDR_TO_DATA_GAP :state_ascii<="ADDR_TO_DATA_GAP"; + ADDR_TO_DATA_GAP2 :state_ascii<="ADDR_TO_DATA_GAP2"; + ADDR_TO_DATA_GAP3 :state_ascii<="ADDR_TO_DATA_GAP3"; + DATA_PHASE :state_ascii<="DATA_PHASE"; + ALMOST_READY :state_ascii<="ALMOST_READY"; + ALMOST_READY2 :state_ascii<="ALMOST_READY2"; + ALMOST_READY3 :state_ascii<="ALMOST_READY3"; + endcase // case(state) + end + //synthesis translate_on + + /********************************************* + * Input Registers + *********************************************/ + always @ (posedge DRP_CLK) begin + if(state == READY) begin + memcell_addr_reg <= memcell_address; + data_reg <= write_data; + rd_not_write_reg <= rd_not_write; + end + end + + assign rdy_busy_n = (state == READY); + + // The changes below are to compensate for an issue with 1.0 silicon. + // It may still be necessary to add a clock cycle to the ADD and CS signals + +//`define DRP_v1_0_FIX // Uncomment out this line for synthesis + +task shift_n_expand ( + input [7:0] data_in, + output [8:0] data_out + ); + + begin + if (data_in[0]) + data_out[1:0] = 2'b11; + else + data_out[1:0] = 2'b00; + + if (data_in[1:0] == 2'b10) + data_out[2:1] = 2'b11; + else + data_out[2:1] = {data_in[1], data_out[1]}; + + if (data_in[2:1] == 2'b10) + data_out[3:2] = 2'b11; + else + data_out[3:2] = {data_in[2], data_out[2]}; + + if (data_in[3:2] == 2'b10) + data_out[4:3] = 2'b11; + else + data_out[4:3] = {data_in[3], data_out[3]}; + + if (data_in[4:3] == 2'b10) + data_out[5:4] = 2'b11; + else + data_out[5:4] = {data_in[4], data_out[4]}; + + if (data_in[5:4] == 2'b10) + data_out[6:5] = 2'b11; + else + data_out[6:5] = {data_in[5], data_out[5]}; + + if (data_in[6:5] == 2'b10) + data_out[7:6] = 2'b11; + else + data_out[7:6] = {data_in[6], data_out[6]}; + + if (data_in[7:6] == 2'b10) + data_out[8:7] = 2'b11; + else + data_out[8:7] = {data_in[7], data_out[7]}; + end +endtask + + + always @(*) begin + case(drp_ioi_addr) +`ifdef DRP_v1_0_FIX + IOI_DQ0 : data_out_mux = data_out<<1; + IOI_DQ1 : data_out_mux = data_out; + IOI_DQ2 : data_out_mux = data_out<<1; +// IOI_DQ2 : data_out_mux = data_out; + IOI_DQ3 : data_out_mux = data_out; + IOI_DQ4 : data_out_mux = data_out; + IOI_DQ5 : data_out_mux = data_out; + IOI_DQ6 : shift_n_expand (data_out, data_out_mux); +// IOI_DQ6 : data_out_mux = data_out; + IOI_DQ7 : data_out_mux = data_out; + IOI_DQ8 : data_out_mux = data_out<<1; + IOI_DQ9 : data_out_mux = data_out; + IOI_DQ10 : data_out_mux = data_out<<1; + IOI_DQ11 : data_out_mux = data_out; + IOI_DQ12 : data_out_mux = data_out<<1; + IOI_DQ13 : data_out_mux = data_out; + IOI_DQ14 : data_out_mux = data_out<<1; + IOI_DQ15 : data_out_mux = data_out; + IOI_UDQS_CLK : data_out_mux = data_out<<1; + IOI_UDQS_PIN : data_out_mux = data_out<<1; + IOI_LDQS_CLK : data_out_mux = data_out; + IOI_LDQS_PIN : data_out_mux = data_out; +`else +`endif + IOI_DQ0 : data_out_mux = data_out; + IOI_DQ1 : data_out_mux = data_out; + IOI_DQ2 : data_out_mux = data_out; + IOI_DQ3 : data_out_mux = data_out; + IOI_DQ4 : data_out_mux = data_out; + IOI_DQ5 : data_out_mux = data_out; + IOI_DQ6 : data_out_mux = data_out; + IOI_DQ7 : data_out_mux = data_out; + IOI_DQ8 : data_out_mux = data_out; + IOI_DQ9 : data_out_mux = data_out; + IOI_DQ10 : data_out_mux = data_out; + IOI_DQ11 : data_out_mux = data_out; + IOI_DQ12 : data_out_mux = data_out; + IOI_DQ13 : data_out_mux = data_out; + IOI_DQ14 : data_out_mux = data_out; + IOI_DQ15 : data_out_mux = data_out; + IOI_UDQS_CLK : data_out_mux = data_out; + IOI_UDQS_PIN : data_out_mux = data_out; + IOI_LDQS_CLK : data_out_mux = data_out; + IOI_LDQS_PIN : data_out_mux = data_out; + default : data_out_mux = data_out; + endcase + end + + + /********************************************* + * Shift Registers / Bit Counter + *********************************************/ + assign data_out = (addr_data_sel_n)? {1'b0, memcell_addr_reg} : {1'b0, data_reg}; + + always @ (posedge DRP_CLK) begin + if(sync_rst) + shift_through_reg <= 9'b0; + else begin + if (load_shift_n) //Assume the shifter is either loading or shifting, bit 0 is shifted out first + shift_through_reg <= data_out_mux; + else + shift_through_reg <= {1'b0, DRP_SDO, shift_through_reg[7:1]}; + end + end + + always @ (posedge DRP_CLK) begin + if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst) + bit_cnt <= bit_cnt + 1; + else + bit_cnt <= 3'b0; + end + + always @ (posedge DRP_CLK) begin + if(sync_rst) begin + read_data <= 8'h00; + end + else begin + if(state == ALMOST_READY3) + read_data <= shift_through_reg; + end + end + + always @ (posedge DRP_CLK) begin + if(sync_rst) begin + AddressPhase <= 1'b0; + end + else begin + if (AddressPhase) begin + // Keep it set until we finish the cycle + AddressPhase <= AddressPhase && ~(state == ALMOST_READY2); + end + else begin + // set the address phase when ever we finish the address phase + AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111); + end + end + end + + /********************************************* + * DRP Signals + *********************************************/ + always @ (posedge DRP_CLK) begin + DRP_ADD <= (nextstate == ADDR_PHASE); + DRP_CS <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); +// DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE); + MCB_UIREAD <= (nextstate == DATA_PHASE) && rd_not_write_reg; + if (state == READY) + DRP_BKST <= use_broadcast; + end + + assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance + assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance + + + /********************************************* + * State Machine + *********************************************/ + always @ (*) begin + addr_data_sel_n = 1'b0; + load_shift_n = 1'b0; + case (state) + READY: begin + load_shift_n = 0; + if(cmd_valid) + nextstate = DECIDE; + else + nextstate = READY; + end + DECIDE: begin + load_shift_n = 1; + addr_data_sel_n = 1; + nextstate = ADDR_PHASE; + end + ADDR_PHASE: begin + load_shift_n = 0; + if(&bit_cnt[2:0]) + if (`ALTERNATE_READ && rd_not_write_reg) + if (AddressPhase) + // After the second pass go to end of statemachine + nextstate = ALMOST_READY; + else + // execute a second address phase for the alternative access method. + nextstate = DECIDE; + else + nextstate = ADDR_TO_DATA_GAP; + else + nextstate = ADDR_PHASE; + end + ADDR_TO_DATA_GAP: begin + load_shift_n = 1; + nextstate = ADDR_TO_DATA_GAP2; + end + ADDR_TO_DATA_GAP2: begin + load_shift_n = 1; + nextstate = ADDR_TO_DATA_GAP3; + end + ADDR_TO_DATA_GAP3: begin + load_shift_n = 1; + nextstate = DATA_PHASE; + end + DATA_PHASE: begin + load_shift_n = 0; + if(&bit_cnt) + nextstate = ALMOST_READY; + else + nextstate = DATA_PHASE; + end + ALMOST_READY: begin + load_shift_n = 0; + nextstate = ALMOST_READY2; + end + ALMOST_READY2: begin + load_shift_n = 0; + nextstate = ALMOST_READY3; + end + ALMOST_READY3: begin + load_shift_n = 0; + nextstate = READY; + end + default: begin + load_shift_n = 0; + nextstate = READY; + end + endcase + end + + always @ (posedge DRP_CLK) begin + if(sync_rst) + state <= READY; + else + state <= nextstate; + end + +endmodule
xilinx/atlys/rtl/verilog/xilinx_ddr2/iodrp_mcb_controller.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/memc_wrapper.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/memc_wrapper.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/memc_wrapper.v (revision 627) @@ -0,0 +1,1239 @@ +//***************************************************************************** +// (c) Copyright 2009-10 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Application : MIG +// \ \ Filename : memc_wrapper.v +// / / Date Last Modified : $Date: 2010/08/ +// /___/ /\ Date Created : Mon Mar 2 2009 +// \ \ / \ +// \___\/\___\ +// +//Device : Spartan-6 +//Design Name : DDR/DDR2/DDR3/LPDDR +//Purpose : This is a static top level module instantiating the mcb_ui_top, +// which provides interface to all the standard as well as AXI ports. +// This module memc_wrapper provides interface to only the standard ports. +//Reference : +//Revision History : +//***************************************************************************** +`timescale 1ns/1ps + +module memc_wrapper # + ( + parameter C_MEMCLK_PERIOD = 2500, + parameter C_P0_MASK_SIZE = 4, + parameter C_P0_DATA_PORT_SIZE = 32, + parameter C_P1_MASK_SIZE = 4, + parameter C_P1_DATA_PORT_SIZE = 32, + + parameter C_PORT_ENABLE = 6'b111111, + parameter C_PORT_CONFIG = "B128", + parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN", + // The following parameter reflects the GUI selection of the Arbitration algorithm. + // Zero value corresponds to round robin algorithm and one to custom selection. + // The parameter is used to calculate the arbitration time slot parameters. + parameter C_ARB_ALGORITHM = 0, + parameter C_ARB_NUM_TIME_SLOTS = 12, + parameter C_ARB_TIME_SLOT_0 = 18'o012345, + parameter C_ARB_TIME_SLOT_1 = 18'o123450, + parameter C_ARB_TIME_SLOT_2 = 18'o234501, + parameter C_ARB_TIME_SLOT_3 = 18'o345012, + parameter C_ARB_TIME_SLOT_4 = 18'o450123, + parameter C_ARB_TIME_SLOT_5 = 18'o501234, + parameter C_ARB_TIME_SLOT_6 = 18'o012345, + parameter C_ARB_TIME_SLOT_7 = 18'o123450, + parameter C_ARB_TIME_SLOT_8 = 18'o234501, + parameter C_ARB_TIME_SLOT_9 = 18'o345012, + parameter C_ARB_TIME_SLOT_10 = 18'o450123, + parameter C_ARB_TIME_SLOT_11 = 18'o501234, + parameter C_MEM_TRAS = 45000, + parameter C_MEM_TRCD = 12500, + parameter C_MEM_TREFI = 7800, + parameter C_MEM_TRFC = 127500, + parameter C_MEM_TRP = 12500, + parameter C_MEM_TWR = 15000, + parameter C_MEM_TRTP = 7500, + parameter C_MEM_TWTR = 7500, + parameter C_NUM_DQ_PINS = 8, + parameter C_MEM_TYPE = "DDR3", + parameter C_MEM_DENSITY = "512M", + parameter C_MEM_BURST_LEN = 8, + parameter C_MEM_CAS_LATENCY = 4, + parameter C_MEM_ADDR_WIDTH = 13, + parameter C_MEM_BANKADDR_WIDTH = 3, + parameter C_MEM_NUM_COL_BITS = 11, + parameter C_MEM_DDR3_CAS_LATENCY = 7, + parameter C_MEM_MOBILE_PA_SR = "FULL", + parameter C_MEM_DDR1_2_ODS = "FULL", + parameter C_MEM_DDR3_ODS = "DIV6", + parameter C_MEM_DDR2_RTT = "50OHMS", + parameter C_MEM_DDR3_RTT = "DIV2", + parameter C_MEM_MDDR_ODS = "FULL", + parameter C_MEM_DDR2_DIFF_DQS_EN = "YES", + parameter C_MEM_DDR2_3_PA_SR = "OFF", + parameter C_MEM_DDR3_CAS_WR_LATENCY = 5, + parameter C_MEM_DDR3_AUTO_SR = "ENABLED", + parameter C_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL", + parameter C_MEM_DDR3_DYN_WRT_ODT = "OFF", + parameter C_MC_CALIB_BYPASS = "NO", + + parameter LDQSP_TAP_DELAY_VAL = 0, + parameter UDQSP_TAP_DELAY_VAL = 0, + parameter LDQSN_TAP_DELAY_VAL = 0, + parameter UDQSN_TAP_DELAY_VAL = 0, + parameter DQ0_TAP_DELAY_VAL = 0, + parameter DQ1_TAP_DELAY_VAL = 0, + parameter DQ2_TAP_DELAY_VAL = 0, + parameter DQ3_TAP_DELAY_VAL = 0, + parameter DQ4_TAP_DELAY_VAL = 0, + parameter DQ5_TAP_DELAY_VAL = 0, + parameter DQ6_TAP_DELAY_VAL = 0, + parameter DQ7_TAP_DELAY_VAL = 0, + parameter DQ8_TAP_DELAY_VAL = 0, + parameter DQ9_TAP_DELAY_VAL = 0, + parameter DQ10_TAP_DELAY_VAL = 0, + parameter DQ11_TAP_DELAY_VAL = 0, + parameter DQ12_TAP_DELAY_VAL = 0, + parameter DQ13_TAP_DELAY_VAL = 0, + parameter DQ14_TAP_DELAY_VAL = 0, + parameter DQ15_TAP_DELAY_VAL = 0, + + parameter C_CALIB_SOFT_IP = "TRUE", + parameter C_SIMULATION = "FALSE", + parameter C_SKIP_IN_TERM_CAL = 1'b0, + parameter C_SKIP_DYNAMIC_CAL = 1'b0, + parameter C_MC_CALIBRATION_MODE = "CALIBRATION", + parameter C_MC_CALIBRATION_DELAY = "HALF" + + ) + + ( + + // Raw Wrapper Signals + input sysclk_2x, + input sysclk_2x_180, + input pll_ce_0, + input pll_ce_90, + input pll_lock, + input async_rst, + input mcb_drp_clk, + output [C_MEM_ADDR_WIDTH-1:0] mcbx_dram_addr, + output [C_MEM_BANKADDR_WIDTH-1:0] mcbx_dram_ba, + output mcbx_dram_ras_n, + output mcbx_dram_cas_n, + output mcbx_dram_we_n, + output mcbx_dram_cke, + output mcbx_dram_clk, + output mcbx_dram_clk_n, + inout [C_NUM_DQ_PINS-1:0] mcbx_dram_dq, + inout mcbx_dram_dqs, + inout mcbx_dram_dqs_n, + inout mcbx_dram_udqs, + inout mcbx_dram_udqs_n, + output mcbx_dram_udm, + output mcbx_dram_ldm, + output mcbx_dram_odt, + output mcbx_dram_ddr3_rst, + inout mcbx_rzq, + inout mcbx_zio, + output calib_done, + input selfrefresh_enter, + output selfrefresh_mode, + +// This new memc_wrapper shows all the six logical static user ports. The port +// configuration parameter and the port enable parameter are the ones that +// determine the active and non-active ports. The following list shows the +// default active ports for each port configuration. +// +// Config 1: "B32_B32_X32_X32_X32_X32" +// User port 0 --> 32 bit, User port 1 --> 32 bit +// User port 2 --> 32 bit, User port 3 --> 32 bit +// User port 4 --> 32 bit, User port 5 --> 32 bit +// Config 2: "B32_B32_B32_B32" +// User port 0 --> 32 bit +// User port 1 --> 32 bit +// User port 2 --> 32 bit +// User port 3 --> 32 bit +// Config 3: "B64_B32_B3" +// User port 0 --> 64 bit +// User port 1 --> 32 bit +// User port 2 --> 32 bit +// Config 4: "B64_B64" +// User port 0 --> 64 bit +// User port 1 --> 64 bit +// Config 5 "B128" +// User port 0 --> 128 bit + + + // User Port-0 command interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5 + input p0_cmd_clk, + input p0_cmd_en, + input [2:0] p0_cmd_instr, + input [5:0] p0_cmd_bl, + input [29:0] p0_cmd_byte_addr, + output p0_cmd_full, + output p0_cmd_empty, + // User Port-0 data write interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5 + input p0_wr_clk, + input p0_wr_en, + input [C_P0_MASK_SIZE-1:0] p0_wr_mask, + input [C_P0_DATA_PORT_SIZE-1:0] p0_wr_data, + output p0_wr_full, + output [6:0] p0_wr_count, + output p0_wr_empty, + output p0_wr_underrun, + output p0_wr_error, + // User Port-0 data read interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5 + input p0_rd_clk, + input p0_rd_en, + output [C_P0_DATA_PORT_SIZE-1:0] p0_rd_data, + output p0_rd_empty, + output [6:0] p0_rd_count, + output p0_rd_full, + output p0_rd_overflow, + output p0_rd_error, + + // User Port-1 command interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3 and Config-4 + input p1_cmd_clk, + input p1_cmd_en, + input [2:0] p1_cmd_instr, + input [5:0] p1_cmd_bl, + input [29:0] p1_cmd_byte_addr, + output p1_cmd_full, + output p1_cmd_empty, + // User Port-1 data write interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3 and Config-4 + input p1_wr_clk, + input p1_wr_en, + input [C_P1_MASK_SIZE-1:0] p1_wr_mask, + input [C_P1_DATA_PORT_SIZE-1:0] p1_wr_data, + output p1_wr_full, + output [6:0] p1_wr_count, + output p1_wr_empty, + output p1_wr_underrun, + output p1_wr_error, + // User Port-1 data read interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3 and Config-4 + input p1_rd_clk, + input p1_rd_en, + output [C_P1_DATA_PORT_SIZE-1:0] p1_rd_data, + output p1_rd_empty, + output [6:0] p1_rd_count, + output p1_rd_full, + output p1_rd_overflow, + output p1_rd_error, + + // User Port-2 command interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2 and Config-3 + input p2_cmd_clk, + input p2_cmd_en, + input [2:0] p2_cmd_instr, + input [5:0] p2_cmd_bl, + input [29:0] p2_cmd_byte_addr, + output p2_cmd_full, + output p2_cmd_empty, + // User Port-2 data write interface will be active only when the port is enabled in + // the port configurations Config-1 write direction, Config-2 and Config-3 + input p2_wr_clk, + input p2_wr_en, + input [3:0] p2_wr_mask, + input [31:0] p2_wr_data, + output p2_wr_full, + output [6:0] p2_wr_count, + output p2_wr_empty, + output p2_wr_underrun, + output p2_wr_error, + // User Port-2 data read interface will be active only when the port is enabled in + // the port configurations Config-1 read direction, Config-2 and Config-3 + input p2_rd_clk, + input p2_rd_en, + output [31:0] p2_rd_data, + output p2_rd_empty, + output [6:0] p2_rd_count, + output p2_rd_full, + output p2_rd_overflow, + output p2_rd_error, + + // User Port-3 command interface will be active only when the port is enabled in + // the port configurations Config-1 and Config-2 + input p3_cmd_clk, + input p3_cmd_en, + input [2:0] p3_cmd_instr, + input [5:0] p3_cmd_bl, + input [29:0] p3_cmd_byte_addr, + output p3_cmd_full, + output p3_cmd_empty, + // User Port-3 data write interface will be active only when the port is enabled in + // the port configurations Config-1 write direction and Config-2 + input p3_wr_clk, + input p3_wr_en, + input [3:0] p3_wr_mask, + input [31:0] p3_wr_data, + output p3_wr_full, + output [6:0] p3_wr_count, + output p3_wr_empty, + output p3_wr_underrun, + output p3_wr_error, + // User Port-3 data read interface will be active only when the port is enabled in + // the port configurations Config-1 read direction and Config-2 + input p3_rd_clk, + input p3_rd_en, + output [31:0] p3_rd_data, + output p3_rd_empty, + output [6:0] p3_rd_count, + output p3_rd_full, + output p3_rd_overflow, + output p3_rd_error, + + // User Port-4 command interface will be active only when the port is enabled in + // the port configuration Config-1 + input p4_cmd_clk, + input p4_cmd_en, + input [2:0] p4_cmd_instr, + input [5:0] p4_cmd_bl, + input [29:0] p4_cmd_byte_addr, + output p4_cmd_full, + output p4_cmd_empty, + // User Port-4 data write interface will be active only when the port is enabled in + // the port configuration Config-1 write direction + input p4_wr_clk, + input p4_wr_en, + input [3:0] p4_wr_mask, + input [31:0] p4_wr_data, + output p4_wr_full, + output [6:0] p4_wr_count, + output p4_wr_empty, + output p4_wr_underrun, + output p4_wr_error, + // User Port-4 data read interface will be active only when the port is enabled in + // the port configuration Config-1 read direction + input p4_rd_clk, + input p4_rd_en, + output [31:0] p4_rd_data, + output p4_rd_empty, + output [6:0] p4_rd_count, + output p4_rd_full, + output p4_rd_overflow, + output p4_rd_error, + // User Port-5 command interface will be active only when the port is enabled in + // the port configuration Config-1 + input p5_cmd_clk, + input p5_cmd_en, + input [2:0] p5_cmd_instr, + input [5:0] p5_cmd_bl, + input [29:0] p5_cmd_byte_addr, + output p5_cmd_full, + output p5_cmd_empty, + // User Port-5 data write interface will be active only when the port is enabled in + // the port configuration Config-1 write direction + input p5_wr_clk, + input p5_wr_en, + input [3:0] p5_wr_mask, + input [31:0] p5_wr_data, + output p5_wr_full, + output [6:0] p5_wr_count, + output p5_wr_empty, + output p5_wr_underrun, + output p5_wr_error, + // User Port-5 data read interface will be active only when the port is enabled in + // the port configuration Config-1 read direction + input p5_rd_clk, + input p5_rd_en, + output [31:0] p5_rd_data, + output p5_rd_empty, + output [6:0] p5_rd_count, + output p5_rd_full, + output p5_rd_overflow, + output p5_rd_error + + ); + + localparam C_MC_CALIBRATION_CLK_DIV = 1; + localparam C_MEM_TZQINIT_MAXCNT = 10'd512 + 10'd16; // 16 clock cycles are added to avoid trfc violations + localparam C_SKIP_DYN_IN_TERM = 1'b1; + + localparam C_MC_CALIBRATION_RA = 16'h0000; + localparam C_MC_CALIBRATION_BA = 3'h0; + localparam C_MC_CALIBRATION_CA = 12'h000; + +// All the following new localparams and signals are added to support +// the AXI slave interface. They have no function to play in a standard +// interface design and can be ignored. + localparam C_S0_AXI_ID_WIDTH = 4; + localparam C_S0_AXI_ADDR_WIDTH = 64; + localparam C_S0_AXI_DATA_WIDTH = 32; + localparam C_S1_AXI_ID_WIDTH = 4; + localparam C_S1_AXI_ADDR_WIDTH = 64; + localparam C_S1_AXI_DATA_WIDTH = 32; + localparam C_S2_AXI_ID_WIDTH = 4; + localparam C_S2_AXI_ADDR_WIDTH = 64; + localparam C_S2_AXI_DATA_WIDTH = 32; + localparam C_S3_AXI_ID_WIDTH = 4; + localparam C_S3_AXI_ADDR_WIDTH = 64; + localparam C_S3_AXI_DATA_WIDTH = 32; + localparam C_S4_AXI_ID_WIDTH = 4; + localparam C_S4_AXI_ADDR_WIDTH = 64; + localparam C_S4_AXI_DATA_WIDTH = 32; + localparam C_S5_AXI_ID_WIDTH = 4; + localparam C_S5_AXI_ADDR_WIDTH = 64; + localparam C_S5_AXI_DATA_WIDTH = 32; + localparam C_MCB_USE_EXTERNAL_BUFPLL = 1; + +// AXI wire declarations +// AXI interface of the mcb_ui_top module is connected to the following +// floating wires in all the standard interface designs. + wire s0_axi_aclk; + wire s0_axi_aresetn; + wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_awid; + wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr; + wire [7:0] s0_axi_awlen; + wire [2:0] s0_axi_awsize; + wire [1:0] s0_axi_awburst; + wire [0:0] s0_axi_awlock; + wire [3:0] s0_axi_awcache; + wire [2:0] s0_axi_awprot; + wire [3:0] s0_axi_awqos; + wire s0_axi_awvalid; + wire s0_axi_awready; + wire [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_wdata; + wire [C_S0_AXI_DATA_WIDTH/8-1:0] s0_axi_wstrb; + wire s0_axi_wlast; + wire s0_axi_wvalid; + wire s0_axi_wready; + wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_bid; + wire [1:0] s0_axi_bresp; + wire s0_axi_bvalid; + wire s0_axi_bready; + wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_arid; + wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr; + wire [7:0] s0_axi_arlen; + wire [2:0] s0_axi_arsize; + wire [1:0] s0_axi_arburst; + wire [0:0] s0_axi_arlock; + wire [3:0] s0_axi_arcache; + wire [2:0] s0_axi_arprot; + wire [3:0] s0_axi_arqos; + wire s0_axi_arvalid; + wire s0_axi_arready; + wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_rid; + wire [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata; + wire [1:0] s0_axi_rresp; + wire s0_axi_rlast; + wire s0_axi_rvalid; + wire s0_axi_rready; + + wire s1_axi_aclk; + wire s1_axi_aresetn; + wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_awid; + wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_awaddr; + wire [7:0] s1_axi_awlen; + wire [2:0] s1_axi_awsize; + wire [1:0] s1_axi_awburst; + wire [0:0] s1_axi_awlock; + wire [3:0] s1_axi_awcache; + wire [2:0] s1_axi_awprot; + wire [3:0] s1_axi_awqos; + wire s1_axi_awvalid; + wire s1_axi_awready; + wire [C_S1_AXI_DATA_WIDTH-1:0] s1_axi_wdata; + wire [C_S1_AXI_DATA_WIDTH/8-1:0] s1_axi_wstrb; + wire s1_axi_wlast; + wire s1_axi_wvalid; + wire s1_axi_wready; + wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_bid; + wire [1:0] s1_axi_bresp; + wire s1_axi_bvalid; + wire s1_axi_bready; + wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_arid; + wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_araddr; + wire [7:0] s1_axi_arlen; + wire [2:0] s1_axi_arsize; + wire [1:0] s1_axi_arburst; + wire [0:0] s1_axi_arlock; + wire [3:0] s1_axi_arcache; + wire [2:0] s1_axi_arprot; + wire [3:0] s1_axi_arqos; + wire s1_axi_arvalid; + wire s1_axi_arready; + wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_rid; + wire [C_S1_AXI_DATA_WIDTH-1:0] s1_axi_rdata; + wire [1:0] s1_axi_rresp; + wire s1_axi_rlast; + wire s1_axi_rvalid; + wire s1_axi_rready; + + wire s2_axi_aclk; + wire s2_axi_aresetn; + wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_awid; + wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_awaddr; + wire [7:0] s2_axi_awlen; + wire [2:0] s2_axi_awsize; + wire [1:0] s2_axi_awburst; + wire [0:0] s2_axi_awlock; + wire [3:0] s2_axi_awcache; + wire [2:0] s2_axi_awprot; + wire [3:0] s2_axi_awqos; + wire s2_axi_awvalid; + wire s2_axi_awready; + wire [C_S2_AXI_DATA_WIDTH-1:0] s2_axi_wdata; + wire [C_S2_AXI_DATA_WIDTH/8-1:0] s2_axi_wstrb; + wire s2_axi_wlast; + wire s2_axi_wvalid; + wire s2_axi_wready; + wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_bid; + wire [1:0] s2_axi_bresp; + wire s2_axi_bvalid; + wire s2_axi_bready; + wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_arid; + wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_araddr; + wire [7:0] s2_axi_arlen; + wire [2:0] s2_axi_arsize; + wire [1:0] s2_axi_arburst; + wire [0:0] s2_axi_arlock; + wire [3:0] s2_axi_arcache; + wire [2:0] s2_axi_arprot; + wire [3:0] s2_axi_arqos; + wire s2_axi_arvalid; + wire s2_axi_arready; + wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_rid; + wire [C_S2_AXI_DATA_WIDTH-1:0] s2_axi_rdata; + wire [1:0] s2_axi_rresp; + wire s2_axi_rlast; + wire s2_axi_rvalid; + wire s2_axi_rready; + + wire s3_axi_aclk; + wire s3_axi_aresetn; + wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_awid; + wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_awaddr; + wire [7:0] s3_axi_awlen; + wire [2:0] s3_axi_awsize; + wire [1:0] s3_axi_awburst; + wire [0:0] s3_axi_awlock; + wire [3:0] s3_axi_awcache; + wire [2:0] s3_axi_awprot; + wire [3:0] s3_axi_awqos; + wire s3_axi_awvalid; + wire s3_axi_awready; + wire [C_S3_AXI_DATA_WIDTH-1:0] s3_axi_wdata; + wire [C_S3_AXI_DATA_WIDTH/8-1:0] s3_axi_wstrb; + wire s3_axi_wlast; + wire s3_axi_wvalid; + wire s3_axi_wready; + wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_bid; + wire [1:0] s3_axi_bresp; + wire s3_axi_bvalid; + wire s3_axi_bready; + wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_arid; + wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_araddr; + wire [7:0] s3_axi_arlen; + wire [2:0] s3_axi_arsize; + wire [1:0] s3_axi_arburst; + wire [0:0] s3_axi_arlock; + wire [3:0] s3_axi_arcache; + wire [2:0] s3_axi_arprot; + wire [3:0] s3_axi_arqos; + wire s3_axi_arvalid; + wire s3_axi_arready; + wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_rid; + wire [C_S3_AXI_DATA_WIDTH-1:0] s3_axi_rdata; + wire [1:0] s3_axi_rresp; + wire s3_axi_rlast; + wire s3_axi_rvalid; + wire s3_axi_rready; + + wire s4_axi_aclk; + wire s4_axi_aresetn; + wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_awid; + wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_awaddr; + wire [7:0] s4_axi_awlen; + wire [2:0] s4_axi_awsize; + wire [1:0] s4_axi_awburst; + wire [0:0] s4_axi_awlock; + wire [3:0] s4_axi_awcache; + wire [2:0] s4_axi_awprot; + wire [3:0] s4_axi_awqos; + wire s4_axi_awvalid; + wire s4_axi_awready; + wire [C_S4_AXI_DATA_WIDTH-1:0] s4_axi_wdata; + wire [C_S4_AXI_DATA_WIDTH/8-1:0] s4_axi_wstrb; + wire s4_axi_wlast; + wire s4_axi_wvalid; + wire s4_axi_wready; + wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_bid; + wire [1:0] s4_axi_bresp; + wire s4_axi_bvalid; + wire s4_axi_bready; + wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_arid; + wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_araddr; + wire [7:0] s4_axi_arlen; + wire [2:0] s4_axi_arsize; + wire [1:0] s4_axi_arburst; + wire [0:0] s4_axi_arlock; + wire [3:0] s4_axi_arcache; + wire [2:0] s4_axi_arprot; + wire [3:0] s4_axi_arqos; + wire s4_axi_arvalid; + wire s4_axi_arready; + wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_rid; + wire [C_S4_AXI_DATA_WIDTH-1:0] s4_axi_rdata; + wire [1:0] s4_axi_rresp; + wire s4_axi_rlast; + wire s4_axi_rvalid; + wire s4_axi_rready; + + wire s5_axi_aclk; + wire s5_axi_aresetn; + wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_awid; + wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_awaddr; + wire [7:0] s5_axi_awlen; + wire [2:0] s5_axi_awsize; + wire [1:0] s5_axi_awburst; + wire [0:0] s5_axi_awlock; + wire [3:0] s5_axi_awcache; + wire [2:0] s5_axi_awprot; + wire [3:0] s5_axi_awqos; + wire s5_axi_awvalid; + wire s5_axi_awready; + wire [C_S5_AXI_DATA_WIDTH-1:0] s5_axi_wdata; + wire [C_S5_AXI_DATA_WIDTH/8-1:0] s5_axi_wstrb; + wire s5_axi_wlast; + wire s5_axi_wvalid; + wire s5_axi_wready; + wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_bid; + wire [1:0] s5_axi_bresp; + wire s5_axi_bvalid; + wire s5_axi_bready; + wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_arid; + wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_araddr; + wire [7:0] s5_axi_arlen; + wire [2:0] s5_axi_arsize; + wire [1:0] s5_axi_arburst; + wire [0:0] s5_axi_arlock; + wire [3:0] s5_axi_arcache; + wire [2:0] s5_axi_arprot; + wire [3:0] s5_axi_arqos; + wire s5_axi_arvalid; + wire s5_axi_arready; + wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_rid; + wire [C_S5_AXI_DATA_WIDTH-1:0] s5_axi_rdata; + wire [1:0] s5_axi_rresp; + wire s5_axi_rlast; + wire s5_axi_rvalid; + wire s5_axi_rready; + + wire [7:0] uo_data; + wire uo_data_valid; + wire uo_cmd_ready_in; + wire uo_refrsh_flag; + wire uo_cal_start; + wire uo_sdo; + wire [31:0] status; + wire sysclk_2x_bufpll_o; + wire sysclk_2x_180_bufpll_o; + wire pll_ce_0_bufpll_o; + wire pll_ce_90_bufpll_o; + wire pll_lock_bufpll_o; + + +// mcb_ui_top instantiation +mcb_ui_top # + ( + // Raw Wrapper Parameters + .C_MEMCLK_PERIOD (C_MEMCLK_PERIOD), + .C_PORT_ENABLE (C_PORT_ENABLE), + .C_MEM_ADDR_ORDER (C_MEM_ADDR_ORDER), + .C_ARB_ALGORITHM (C_ARB_ALGORITHM), + .C_ARB_NUM_TIME_SLOTS (C_ARB_NUM_TIME_SLOTS), + .C_ARB_TIME_SLOT_0 (C_ARB_TIME_SLOT_0), + .C_ARB_TIME_SLOT_1 (C_ARB_TIME_SLOT_1), + .C_ARB_TIME_SLOT_2 (C_ARB_TIME_SLOT_2), + .C_ARB_TIME_SLOT_3 (C_ARB_TIME_SLOT_3), + .C_ARB_TIME_SLOT_4 (C_ARB_TIME_SLOT_4), + .C_ARB_TIME_SLOT_5 (C_ARB_TIME_SLOT_5), + .C_ARB_TIME_SLOT_6 (C_ARB_TIME_SLOT_6), + .C_ARB_TIME_SLOT_7 (C_ARB_TIME_SLOT_7), + .C_ARB_TIME_SLOT_8 (C_ARB_TIME_SLOT_8), + .C_ARB_TIME_SLOT_9 (C_ARB_TIME_SLOT_9), + .C_ARB_TIME_SLOT_10 (C_ARB_TIME_SLOT_10), + .C_ARB_TIME_SLOT_11 (C_ARB_TIME_SLOT_11), + .C_PORT_CONFIG (C_PORT_CONFIG), + .C_MEM_TRAS (C_MEM_TRAS), + .C_MEM_TRCD (C_MEM_TRCD), + .C_MEM_TREFI (C_MEM_TREFI), + .C_MEM_TRFC (C_MEM_TRFC), + .C_MEM_TRP (C_MEM_TRP), + .C_MEM_TWR (C_MEM_TWR), + .C_MEM_TRTP (C_MEM_TRTP), + .C_MEM_TWTR (C_MEM_TWTR), + .C_NUM_DQ_PINS (C_NUM_DQ_PINS), + .C_MEM_TYPE (C_MEM_TYPE), + .C_MEM_DENSITY (C_MEM_DENSITY), + .C_MEM_BURST_LEN (C_MEM_BURST_LEN), + .C_MEM_CAS_LATENCY (C_MEM_CAS_LATENCY), + .C_MEM_ADDR_WIDTH (C_MEM_ADDR_WIDTH), + .C_MEM_BANKADDR_WIDTH (C_MEM_BANKADDR_WIDTH), + .C_MEM_NUM_COL_BITS (C_MEM_NUM_COL_BITS), + .C_MEM_DDR3_CAS_LATENCY (C_MEM_DDR3_CAS_LATENCY), + .C_MEM_MOBILE_PA_SR (C_MEM_MOBILE_PA_SR), + .C_MEM_DDR1_2_ODS (C_MEM_DDR1_2_ODS), + .C_MEM_DDR3_ODS (C_MEM_DDR3_ODS), + .C_MEM_DDR2_RTT (C_MEM_DDR2_RTT), + .C_MEM_DDR3_RTT (C_MEM_DDR3_RTT), + .C_MEM_MDDR_ODS (C_MEM_MDDR_ODS), + .C_MEM_DDR2_DIFF_DQS_EN (C_MEM_DDR2_DIFF_DQS_EN), + .C_MEM_DDR2_3_PA_SR (C_MEM_DDR2_3_PA_SR), + .C_MEM_DDR3_CAS_WR_LATENCY (C_MEM_DDR3_CAS_WR_LATENCY), + .C_MEM_DDR3_AUTO_SR (C_MEM_DDR3_AUTO_SR), + .C_MEM_DDR2_3_HIGH_TEMP_SR (C_MEM_DDR2_3_HIGH_TEMP_SR), + .C_MEM_DDR3_DYN_WRT_ODT (C_MEM_DDR3_DYN_WRT_ODT), + .C_MEM_TZQINIT_MAXCNT (C_MEM_TZQINIT_MAXCNT), + .C_MC_CALIB_BYPASS (C_MC_CALIB_BYPASS), + .C_MC_CALIBRATION_RA (C_MC_CALIBRATION_RA), + .C_MC_CALIBRATION_BA (C_MC_CALIBRATION_BA), + .C_MC_CALIBRATION_CA (C_MC_CALIBRATION_CA), + .C_CALIB_SOFT_IP (C_CALIB_SOFT_IP), + .C_SKIP_IN_TERM_CAL (C_SKIP_IN_TERM_CAL), + .C_SKIP_DYNAMIC_CAL (C_SKIP_DYNAMIC_CAL), + .C_SKIP_DYN_IN_TERM (C_SKIP_DYN_IN_TERM), + .LDQSP_TAP_DELAY_VAL (LDQSP_TAP_DELAY_VAL), + .UDQSP_TAP_DELAY_VAL (UDQSP_TAP_DELAY_VAL), + .LDQSN_TAP_DELAY_VAL (LDQSN_TAP_DELAY_VAL), + .UDQSN_TAP_DELAY_VAL (UDQSN_TAP_DELAY_VAL), + .DQ0_TAP_DELAY_VAL (DQ0_TAP_DELAY_VAL), + .DQ1_TAP_DELAY_VAL (DQ1_TAP_DELAY_VAL), + .DQ2_TAP_DELAY_VAL (DQ2_TAP_DELAY_VAL), + .DQ3_TAP_DELAY_VAL (DQ3_TAP_DELAY_VAL), + .DQ4_TAP_DELAY_VAL (DQ4_TAP_DELAY_VAL), + .DQ5_TAP_DELAY_VAL (DQ5_TAP_DELAY_VAL), + .DQ6_TAP_DELAY_VAL (DQ6_TAP_DELAY_VAL), + .DQ7_TAP_DELAY_VAL (DQ7_TAP_DELAY_VAL), + .DQ8_TAP_DELAY_VAL (DQ8_TAP_DELAY_VAL), + .DQ9_TAP_DELAY_VAL (DQ9_TAP_DELAY_VAL), + .DQ10_TAP_DELAY_VAL (DQ10_TAP_DELAY_VAL), + .DQ11_TAP_DELAY_VAL (DQ11_TAP_DELAY_VAL), + .DQ12_TAP_DELAY_VAL (DQ12_TAP_DELAY_VAL), + .DQ13_TAP_DELAY_VAL (DQ13_TAP_DELAY_VAL), + .DQ14_TAP_DELAY_VAL (DQ14_TAP_DELAY_VAL), + .DQ15_TAP_DELAY_VAL (DQ15_TAP_DELAY_VAL), + .C_MC_CALIBRATION_CLK_DIV (C_MC_CALIBRATION_CLK_DIV), + .C_MC_CALIBRATION_MODE (C_MC_CALIBRATION_MODE), + .C_MC_CALIBRATION_DELAY (C_MC_CALIBRATION_DELAY), + .C_SIMULATION (C_SIMULATION), + .C_P0_MASK_SIZE (C_P0_MASK_SIZE), + .C_P0_DATA_PORT_SIZE (C_P0_DATA_PORT_SIZE), + .C_P1_MASK_SIZE (C_P1_MASK_SIZE), + .C_P1_DATA_PORT_SIZE (C_P1_DATA_PORT_SIZE), + .C_MCB_USE_EXTERNAL_BUFPLL (C_MCB_USE_EXTERNAL_BUFPLL) + ) +mcb_ui_top_inst + ( + // Raw Wrapper Signals + .sysclk_2x (sysclk_2x), + .sysclk_2x_180 (sysclk_2x_180), + .pll_ce_0 (pll_ce_0), + .pll_ce_90 (pll_ce_90), + .pll_lock (pll_lock), + .sysclk_2x_bufpll_o (sysclk_2x_bufpll_o), + .sysclk_2x_180_bufpll_o (sysclk_2x_180_bufpll_o), + .pll_ce_0_bufpll_o (pll_ce_0_bufpll_o), + .pll_ce_90_bufpll_o (pll_ce_90_bufpll_o), + .pll_lock_bufpll_o (pll_lock_bufpll_o), + .sys_rst (async_rst), + .p0_arb_en (1'b1), + .p0_cmd_clk (p0_cmd_clk), + .p0_cmd_en (p0_cmd_en), + .p0_cmd_instr (p0_cmd_instr), + .p0_cmd_bl (p0_cmd_bl), + .p0_cmd_byte_addr (p0_cmd_byte_addr), + .p0_cmd_empty (p0_cmd_empty), + .p0_cmd_full (p0_cmd_full), + .p0_wr_clk (p0_wr_clk), + .p0_wr_en (p0_wr_en), + .p0_wr_mask (p0_wr_mask), + .p0_wr_data (p0_wr_data), + .p0_wr_full (p0_wr_full), + .p0_wr_empty (p0_wr_empty), + .p0_wr_count (p0_wr_count), + .p0_wr_underrun (p0_wr_underrun), + .p0_wr_error (p0_wr_error), + .p0_rd_clk (p0_rd_clk), + .p0_rd_en (p0_rd_en), + .p0_rd_data (p0_rd_data), + .p0_rd_full (p0_rd_full), + .p0_rd_empty (p0_rd_empty), + .p0_rd_count (p0_rd_count), + .p0_rd_overflow (p0_rd_overflow), + .p0_rd_error (p0_rd_error), + .p1_arb_en (1'b1), + .p1_cmd_clk (p1_cmd_clk), + .p1_cmd_en (p1_cmd_en), + .p1_cmd_instr (p1_cmd_instr), + .p1_cmd_bl (p1_cmd_bl), + .p1_cmd_byte_addr (p1_cmd_byte_addr), + .p1_cmd_empty (p1_cmd_empty), + .p1_cmd_full (p1_cmd_full), + .p1_wr_clk (p1_wr_clk), + .p1_wr_en (p1_wr_en), + .p1_wr_mask (p1_wr_mask), + .p1_wr_data (p1_wr_data), + .p1_wr_full (p1_wr_full), + .p1_wr_empty (p1_wr_empty), + .p1_wr_count (p1_wr_count), + .p1_wr_underrun (p1_wr_underrun), + .p1_wr_error (p1_wr_error), + .p1_rd_clk (p1_rd_clk), + .p1_rd_en (p1_rd_en), + .p1_rd_data (p1_rd_data), + .p1_rd_full (p1_rd_full), + .p1_rd_empty (p1_rd_empty), + .p1_rd_count (p1_rd_count), + .p1_rd_overflow (p1_rd_overflow), + .p1_rd_error (p1_rd_error), + .p2_arb_en (1'b1), + .p2_cmd_clk (p2_cmd_clk), + .p2_cmd_en (p2_cmd_en), + .p2_cmd_instr (p2_cmd_instr), + .p2_cmd_bl (p2_cmd_bl), + .p2_cmd_byte_addr (p2_cmd_byte_addr), + .p2_cmd_empty (p2_cmd_empty), + .p2_cmd_full (p2_cmd_full), + .p2_wr_clk (p2_wr_clk), + .p2_wr_en (p2_wr_en), + .p2_wr_mask (p2_wr_mask), + .p2_wr_data (p2_wr_data), + .p2_wr_full (p2_wr_full), + .p2_wr_empty (p2_wr_empty), + .p2_wr_count (p2_wr_count), + .p2_wr_underrun (p2_wr_underrun), + .p2_wr_error (p2_wr_error), + .p2_rd_clk (p2_rd_clk), + .p2_rd_en (p2_rd_en), + .p2_rd_data (p2_rd_data), + .p2_rd_full (p2_rd_full), + .p2_rd_empty (p2_rd_empty), + .p2_rd_count (p2_rd_count), + .p2_rd_overflow (p2_rd_overflow), + .p2_rd_error (p2_rd_error), + .p3_arb_en (1'b1), + .p3_cmd_clk (p3_cmd_clk), + .p3_cmd_en (p3_cmd_en), + .p3_cmd_instr (p3_cmd_instr), + .p3_cmd_bl (p3_cmd_bl), + .p3_cmd_byte_addr (p3_cmd_byte_addr), + .p3_cmd_empty (p3_cmd_empty), + .p3_cmd_full (p3_cmd_full), + .p3_wr_clk (p3_wr_clk), + .p3_wr_en (p3_wr_en), + .p3_wr_mask (p3_wr_mask), + .p3_wr_data (p3_wr_data), + .p3_wr_full (p3_wr_full), + .p3_wr_empty (p3_wr_empty), + .p3_wr_count (p3_wr_count), + .p3_wr_underrun (p3_wr_underrun), + .p3_wr_error (p3_wr_error), + .p3_rd_clk (p3_rd_clk), + .p3_rd_en (p3_rd_en), + .p3_rd_data (p3_rd_data), + .p3_rd_full (p3_rd_full), + .p3_rd_empty (p3_rd_empty), + .p3_rd_count (p3_rd_count), + .p3_rd_overflow (p3_rd_overflow), + .p3_rd_error (p3_rd_error), + .p4_arb_en (1'b1), + .p4_cmd_clk (p4_cmd_clk), + .p4_cmd_en (p4_cmd_en), + .p4_cmd_instr (p4_cmd_instr), + .p4_cmd_bl (p4_cmd_bl), + .p4_cmd_byte_addr (p4_cmd_byte_addr), + .p4_cmd_empty (p4_cmd_empty), + .p4_cmd_full (p4_cmd_full), + .p4_wr_clk (p4_wr_clk), + .p4_wr_en (p4_wr_en), + .p4_wr_mask (p4_wr_mask), + .p4_wr_data (p4_wr_data), + .p4_wr_full (p4_wr_full), + .p4_wr_empty (p4_wr_empty), + .p4_wr_count (p4_wr_count), + .p4_wr_underrun (p4_wr_underrun), + .p4_wr_error (p4_wr_error), + .p4_rd_clk (p4_rd_clk), + .p4_rd_en (p4_rd_en), + .p4_rd_data (p4_rd_data), + .p4_rd_full (p4_rd_full), + .p4_rd_empty (p4_rd_empty), + .p4_rd_count (p4_rd_count), + .p4_rd_overflow (p4_rd_overflow), + .p4_rd_error (p4_rd_error), + .p5_arb_en (1'b1), + .p5_cmd_clk (p5_cmd_clk), + .p5_cmd_en (p5_cmd_en), + .p5_cmd_instr (p5_cmd_instr), + .p5_cmd_bl (p5_cmd_bl), + .p5_cmd_byte_addr (p5_cmd_byte_addr), + .p5_cmd_empty (p5_cmd_empty), + .p5_cmd_full (p5_cmd_full), + .p5_wr_clk (p5_wr_clk), + .p5_wr_en (p5_wr_en), + .p5_wr_mask (p5_wr_mask), + .p5_wr_data (p5_wr_data), + .p5_wr_full (p5_wr_full), + .p5_wr_empty (p5_wr_empty), + .p5_wr_count (p5_wr_count), + .p5_wr_underrun (p5_wr_underrun), + .p5_wr_error (p5_wr_error), + .p5_rd_clk (p5_rd_clk), + .p5_rd_en (p5_rd_en), + .p5_rd_data (p5_rd_data), + .p5_rd_full (p5_rd_full), + .p5_rd_empty (p5_rd_empty), + .p5_rd_count (p5_rd_count), + .p5_rd_overflow (p5_rd_overflow), + .p5_rd_error (p5_rd_error), + .mcbx_dram_addr (mcbx_dram_addr), + .mcbx_dram_ba (mcbx_dram_ba), + .mcbx_dram_ras_n (mcbx_dram_ras_n), + .mcbx_dram_cas_n (mcbx_dram_cas_n), + .mcbx_dram_we_n (mcbx_dram_we_n), + .mcbx_dram_cke (mcbx_dram_cke), + .mcbx_dram_clk (mcbx_dram_clk), + .mcbx_dram_clk_n (mcbx_dram_clk_n), + .mcbx_dram_dq (mcbx_dram_dq), + .mcbx_dram_dqs (mcbx_dram_dqs), + .mcbx_dram_dqs_n (mcbx_dram_dqs_n), + .mcbx_dram_udqs (mcbx_dram_udqs), + .mcbx_dram_udqs_n (mcbx_dram_udqs_n), + .mcbx_dram_udm (mcbx_dram_udm), + .mcbx_dram_ldm (mcbx_dram_ldm), + .mcbx_dram_odt (mcbx_dram_odt), + .mcbx_dram_ddr3_rst (mcbx_dram_ddr3_rst), + .calib_recal (1'b0), + .rzq (mcbx_rzq), + .zio (mcbx_zio), + .ui_read (1'b0), + .ui_add (1'b0), + .ui_cs (1'b0), + .ui_clk (mcb_drp_clk), + .ui_sdi (1'b0), + .ui_addr (5'b0), + .ui_broadcast (1'b0), + .ui_drp_update (1'b0), + .ui_done_cal (1'b1), + .ui_cmd (1'b0), + .ui_cmd_in (1'b0), + .ui_cmd_en (1'b0), + .ui_dqcount (4'b0), + .ui_dq_lower_dec (1'b0), + .ui_dq_lower_inc (1'b0), + .ui_dq_upper_dec (1'b0), + .ui_dq_upper_inc (1'b0), + .ui_udqs_inc (1'b0), + .ui_udqs_dec (1'b0), + .ui_ldqs_inc (1'b0), + .ui_ldqs_dec (1'b0), + .uo_data (uo_data), + .uo_data_valid (uo_data_valid), + .uo_done_cal (calib_done), + .uo_cmd_ready_in (uo_cmd_ready_in), + .uo_refrsh_flag (uo_refrsh_flag), + .uo_cal_start (uo_cal_start), + .uo_sdo (uo_sdo), + .status (status), + .selfrefresh_enter (selfrefresh_enter), + .selfrefresh_mode (selfrefresh_mode), + + // AXI Signals + .s0_axi_aclk (s0_axi_aclk), + .s0_axi_aresetn (s0_axi_aresetn), + .s0_axi_awid (s0_axi_awid), + .s0_axi_awaddr (s0_axi_awaddr), + .s0_axi_awlen (s0_axi_awlen), + .s0_axi_awsize (s0_axi_awsize), + .s0_axi_awburst (s0_axi_awburst), + .s0_axi_awlock (s0_axi_awlock), + .s0_axi_awcache (s0_axi_awcache), + .s0_axi_awprot (s0_axi_awprot), + .s0_axi_awqos (s0_axi_awqos), + .s0_axi_awvalid (s0_axi_awvalid), + .s0_axi_awready (s0_axi_awready), + .s0_axi_wdata (s0_axi_wdata), + .s0_axi_wstrb (s0_axi_wstrb), + .s0_axi_wlast (s0_axi_wlast), + .s0_axi_wvalid (s0_axi_wvalid), + .s0_axi_wready (s0_axi_wready), + .s0_axi_bid (s0_axi_bid), + .s0_axi_bresp (s0_axi_bresp), + .s0_axi_bvalid (s0_axi_bvalid), + .s0_axi_bready (s0_axi_bready), + .s0_axi_arid (s0_axi_arid), + .s0_axi_araddr (s0_axi_araddr), + .s0_axi_arlen (s0_axi_arlen), + .s0_axi_arsize (s0_axi_arsize), + .s0_axi_arburst (s0_axi_arburst), + .s0_axi_arlock (s0_axi_arlock), + .s0_axi_arcache (s0_axi_arcache), + .s0_axi_arprot (s0_axi_arprot), + .s0_axi_arqos (s0_axi_arqos), + .s0_axi_arvalid (s0_axi_arvalid), + .s0_axi_arready (s0_axi_arready), + .s0_axi_rid (s0_axi_rid), + .s0_axi_rdata (s0_axi_rdata), + .s0_axi_rresp (s0_axi_rresp), + .s0_axi_rlast (s0_axi_rlast), + .s0_axi_rvalid (s0_axi_rvalid), + .s0_axi_rready (s0_axi_rready), + + .s1_axi_aclk (s1_axi_aclk), + .s1_axi_aresetn (s1_axi_aresetn), + .s1_axi_awid (s1_axi_awid), + .s1_axi_awaddr (s1_axi_awaddr), + .s1_axi_awlen (s1_axi_awlen), + .s1_axi_awsize (s1_axi_awsize), + .s1_axi_awburst (s1_axi_awburst), + .s1_axi_awlock (s1_axi_awlock), + .s1_axi_awcache (s1_axi_awcache), + .s1_axi_awprot (s1_axi_awprot), + .s1_axi_awqos (s1_axi_awqos), + .s1_axi_awvalid (s1_axi_awvalid), + .s1_axi_awready (s1_axi_awready), + .s1_axi_wdata (s1_axi_wdata), + .s1_axi_wstrb (s1_axi_wstrb), + .s1_axi_wlast (s1_axi_wlast), + .s1_axi_wvalid (s1_axi_wvalid), + .s1_axi_wready (s1_axi_wready), + .s1_axi_bid (s1_axi_bid), + .s1_axi_bresp (s1_axi_bresp), + .s1_axi_bvalid (s1_axi_bvalid), + .s1_axi_bready (s1_axi_bready), + .s1_axi_arid (s1_axi_arid), + .s1_axi_araddr (s1_axi_araddr), + .s1_axi_arlen (s1_axi_arlen), + .s1_axi_arsize (s1_axi_arsize), + .s1_axi_arburst (s1_axi_arburst), + .s1_axi_arlock (s1_axi_arlock), + .s1_axi_arcache (s1_axi_arcache), + .s1_axi_arprot (s1_axi_arprot), + .s1_axi_arqos (s1_axi_arqos), + .s1_axi_arvalid (s1_axi_arvalid), + .s1_axi_arready (s1_axi_arready), + .s1_axi_rid (s1_axi_rid), + .s1_axi_rdata (s1_axi_rdata), + .s1_axi_rresp (s1_axi_rresp), + .s1_axi_rlast (s1_axi_rlast), + .s1_axi_rvalid (s1_axi_rvalid), + .s1_axi_rready (s1_axi_rready), + + .s2_axi_aclk (s2_axi_aclk), + .s2_axi_aresetn (s2_axi_aresetn), + .s2_axi_awid (s2_axi_awid), + .s2_axi_awaddr (s2_axi_awaddr), + .s2_axi_awlen (s2_axi_awlen), + .s2_axi_awsize (s2_axi_awsize), + .s2_axi_awburst (s2_axi_awburst), + .s2_axi_awlock (s2_axi_awlock), + .s2_axi_awcache (s2_axi_awcache), + .s2_axi_awprot (s2_axi_awprot), + .s2_axi_awqos (s2_axi_awqos), + .s2_axi_awvalid (s2_axi_awvalid), + .s2_axi_awready (s2_axi_awready), + .s2_axi_wdata (s2_axi_wdata), + .s2_axi_wstrb (s2_axi_wstrb), + .s2_axi_wlast (s2_axi_wlast), + .s2_axi_wvalid (s2_axi_wvalid), + .s2_axi_wready (s2_axi_wready), + .s2_axi_bid (s2_axi_bid), + .s2_axi_bresp (s2_axi_bresp), + .s2_axi_bvalid (s2_axi_bvalid), + .s2_axi_bready (s2_axi_bready), + .s2_axi_arid (s2_axi_arid), + .s2_axi_araddr (s2_axi_araddr), + .s2_axi_arlen (s2_axi_arlen), + .s2_axi_arsize (s2_axi_arsize), + .s2_axi_arburst (s2_axi_arburst), + .s2_axi_arlock (s2_axi_arlock), + .s2_axi_arcache (s2_axi_arcache), + .s2_axi_arprot (s2_axi_arprot), + .s2_axi_arqos (s2_axi_arqos), + .s2_axi_arvalid (s2_axi_arvalid), + .s2_axi_arready (s2_axi_arready), + .s2_axi_rid (s2_axi_rid), + .s2_axi_rdata (s2_axi_rdata), + .s2_axi_rresp (s2_axi_rresp), + .s2_axi_rlast (s2_axi_rlast), + .s2_axi_rvalid (s2_axi_rvalid), + .s2_axi_rready (s2_axi_rready), + + .s3_axi_aclk (s3_axi_aclk), + .s3_axi_aresetn (s3_axi_aresetn), + .s3_axi_awid (s3_axi_awid), + .s3_axi_awaddr (s3_axi_awaddr), + .s3_axi_awlen (s3_axi_awlen), + .s3_axi_awsize (s3_axi_awsize), + .s3_axi_awburst (s3_axi_awburst), + .s3_axi_awlock (s3_axi_awlock), + .s3_axi_awcache (s3_axi_awcache), + .s3_axi_awprot (s3_axi_awprot), + .s3_axi_awqos (s3_axi_awqos), + .s3_axi_awvalid (s3_axi_awvalid), + .s3_axi_awready (s3_axi_awready), + .s3_axi_wdata (s3_axi_wdata), + .s3_axi_wstrb (s3_axi_wstrb), + .s3_axi_wlast (s3_axi_wlast), + .s3_axi_wvalid (s3_axi_wvalid), + .s3_axi_wready (s3_axi_wready), + .s3_axi_bid (s3_axi_bid), + .s3_axi_bresp (s3_axi_bresp), + .s3_axi_bvalid (s3_axi_bvalid), + .s3_axi_bready (s3_axi_bready), + .s3_axi_arid (s3_axi_arid), + .s3_axi_araddr (s3_axi_araddr), + .s3_axi_arlen (s3_axi_arlen), + .s3_axi_arsize (s3_axi_arsize), + .s3_axi_arburst (s3_axi_arburst), + .s3_axi_arlock (s3_axi_arlock), + .s3_axi_arcache (s3_axi_arcache), + .s3_axi_arprot (s3_axi_arprot), + .s3_axi_arqos (s3_axi_arqos), + .s3_axi_arvalid (s3_axi_arvalid), + .s3_axi_arready (s3_axi_arready), + .s3_axi_rid (s3_axi_rid), + .s3_axi_rdata (s3_axi_rdata), + .s3_axi_rresp (s3_axi_rresp), + .s3_axi_rlast (s3_axi_rlast), + .s3_axi_rvalid (s3_axi_rvalid), + .s3_axi_rready (s3_axi_rready), + + .s4_axi_aclk (s4_axi_aclk), + .s4_axi_aresetn (s4_axi_aresetn), + .s4_axi_awid (s4_axi_awid), + .s4_axi_awaddr (s4_axi_awaddr), + .s4_axi_awlen (s4_axi_awlen), + .s4_axi_awsize (s4_axi_awsize), + .s4_axi_awburst (s4_axi_awburst), + .s4_axi_awlock (s4_axi_awlock), + .s4_axi_awcache (s4_axi_awcache), + .s4_axi_awprot (s4_axi_awprot), + .s4_axi_awqos (s4_axi_awqos), + .s4_axi_awvalid (s4_axi_awvalid), + .s4_axi_awready (s4_axi_awready), + .s4_axi_wdata (s4_axi_wdata), + .s4_axi_wstrb (s4_axi_wstrb), + .s4_axi_wlast (s4_axi_wlast), + .s4_axi_wvalid (s4_axi_wvalid), + .s4_axi_wready (s4_axi_wready), + .s4_axi_bid (s4_axi_bid), + .s4_axi_bresp (s4_axi_bresp), + .s4_axi_bvalid (s4_axi_bvalid), + .s4_axi_bready (s4_axi_bready), + .s4_axi_arid (s4_axi_arid), + .s4_axi_araddr (s4_axi_araddr), + .s4_axi_arlen (s4_axi_arlen), + .s4_axi_arsize (s4_axi_arsize), + .s4_axi_arburst (s4_axi_arburst), + .s4_axi_arlock (s4_axi_arlock), + .s4_axi_arcache (s4_axi_arcache), + .s4_axi_arprot (s4_axi_arprot), + .s4_axi_arqos (s4_axi_arqos), + .s4_axi_arvalid (s4_axi_arvalid), + .s4_axi_arready (s4_axi_arready), + .s4_axi_rid (s4_axi_rid), + .s4_axi_rdata (s4_axi_rdata), + .s4_axi_rresp (s4_axi_rresp), + .s4_axi_rlast (s4_axi_rlast), + .s4_axi_rvalid (s4_axi_rvalid), + .s4_axi_rready (s4_axi_rready), + + .s5_axi_aclk (s5_axi_aclk), + .s5_axi_aresetn (s5_axi_aresetn), + .s5_axi_awid (s5_axi_awid), + .s5_axi_awaddr (s5_axi_awaddr), + .s5_axi_awlen (s5_axi_awlen), + .s5_axi_awsize (s5_axi_awsize), + .s5_axi_awburst (s5_axi_awburst), + .s5_axi_awlock (s5_axi_awlock), + .s5_axi_awcache (s5_axi_awcache), + .s5_axi_awprot (s5_axi_awprot), + .s5_axi_awqos (s5_axi_awqos), + .s5_axi_awvalid (s5_axi_awvalid), + .s5_axi_awready (s5_axi_awready), + .s5_axi_wdata (s5_axi_wdata), + .s5_axi_wstrb (s5_axi_wstrb), + .s5_axi_wlast (s5_axi_wlast), + .s5_axi_wvalid (s5_axi_wvalid), + .s5_axi_wready (s5_axi_wready), + .s5_axi_bid (s5_axi_bid), + .s5_axi_bresp (s5_axi_bresp), + .s5_axi_bvalid (s5_axi_bvalid), + .s5_axi_bready (s5_axi_bready), + .s5_axi_arid (s5_axi_arid), + .s5_axi_araddr (s5_axi_araddr), + .s5_axi_arlen (s5_axi_arlen), + .s5_axi_arsize (s5_axi_arsize), + .s5_axi_arburst (s5_axi_arburst), + .s5_axi_arlock (s5_axi_arlock), + .s5_axi_arcache (s5_axi_arcache), + .s5_axi_arprot (s5_axi_arprot), + .s5_axi_arqos (s5_axi_arqos), + .s5_axi_arvalid (s5_axi_arvalid), + .s5_axi_arready (s5_axi_arready), + .s5_axi_rid (s5_axi_rid), + .s5_axi_rdata (s5_axi_rdata), + .s5_axi_rresp (s5_axi_rresp), + .s5_axi_rlast (s5_axi_rlast), + .s5_axi_rvalid (s5_axi_rvalid), + .s5_axi_rready (s5_axi_rready) + ); + +endmodule
xilinx/atlys/rtl/verilog/xilinx_ddr2/memc_wrapper.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v (revision 627) @@ -0,0 +1,1268 @@ +//***************************************************************************** +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: mcb_soft_calibration.v +// /___/ /\ Date Last Modified: $Date: 2010/10/27 17:40:12 $ +// \ \ / \ Date Created: Mon Feb 9 2009 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: Xilinx reference design for MCB Soft +// Calibration +//Reference: +// +// Revision: Date: Comment +// 1.0: 2/06/09: Initial version for MIG wrapper. +// 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working correctly) +// 1.2: 2/12/09: Many other changes. +// 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within STATE +// 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD. Also added reg declaration for PREVIOUS_STATE +// 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock. +// 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT. +// 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets +// 2.0: 7/30/09: Added dynamic Input Termination +// 2.1: 8/02/09: Added sampling of DQS input delays to make sure we never decrement below h00 (or increment above hEF). +// 2.2: 8/04/09: Added 2's compliment register "DQS_COUNT_VIRTUAL", and signficantly changed the increment/decrement algorythm - now will track a virtual +// negative DQS_COUNT value if needed. Got rid of DQS_COUNT_UP/DOWN registers +// 2.3: 10/10/09: Massive overhaul +// 2.4: 10/14/09: Fixed: from START, if SKIP_IN_TERM_CAL go to WRITE_CALIBRATE +// 2.5: 10/15/09: Changed OVERRIDE_DQS_CAL to CALMODE_EQ_CALIBRATION, and made it override SKIP_DYNAMIC_CAL (to 1) whenever C_MC_CALIBRATION_MODE="NOCALIBRATION" +// 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to RST_DELAY. +// Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least 16 clocks. Added PNSKEW option. +// 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing. +// 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg. +// 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced with 8bit TARGET_DQS_DELAY which +// will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_Delay into DQS_DELAY_INITIAL. Changed DQS_COUNT* to DQS_DELAY*. +// Changed MCB_SYSRST port back to wire (from reg). +// 3.0: 02/10/10: Added count_inc and count_dec to add a few (4) UI_CLK cycles latency to the INC and DEC signals (to deal with latency on UOREFRSHFLAG) +// 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing. +// 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic; +// 3.3: 03/02/10: Changed PNSKEW to default on (1'b1) +// 3.4: 03/04/10: Recoded the RST_Reg logic. +// 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16) +// 3.6: 03/10/10: Improvements to Reset logic +// 3.7: 04/12/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . +// 3.8: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz. +// End Revision +//********************************************************************************** + + +`timescale 1ps/1ps + +module mcb_soft_calibration # ( + parameter C_MEM_TZQINIT_MAXCNT = 10'd512, // DDR3 Minimum delay between resets + parameter C_MC_CALIBRATION_MODE = "CALIBRATION", // if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values + // if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY (Quarter, etc) + parameter C_SIMULATION = "FALSE", // Tells us whether the design is being simulated or implemented + parameter SKIP_IN_TERM_CAL = 1'b0, // provides option to skip the input termination calibration + parameter SKIP_DYNAMIC_CAL = 1'b0, // provides option to skip the dynamic delay calibration + parameter SKIP_DYN_IN_TERM = 1'b1, // provides option to skip the input termination calibration + parameter C_MEM_TYPE = "DDR" // provides the memory device used for the design + + ) + ( + input wire UI_CLK, // main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB CLK pins + input wire RST, // main system reset for both this Soft Calibration block - also will act as a passthrough to MCB's SYSRST + (* IOB = "FALSE" *) output reg DONE_SOFTANDHARD_CAL, + // active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete) + input wire PLL_LOCK, // Lock signal from PLL + input wire SELFREFRESH_REQ, + input wire SELFREFRESH_MCB_MODE, + output reg SELFREFRESH_MCB_REQ , + output reg SELFREFRESH_MODE, + output wire IODRP_ADD, // IODRP ADD port + output wire IODRP_SDI, // IODRP SDI port + input wire RZQ_IN, // RZQ pin from board - expected to have a 2*R resistor to ground + input wire RZQ_IODRP_SDO, // RZQ IODRP's SDO port + output reg RZQ_IODRP_CS = 1'b0, // RZQ IODRP's CS port + input wire ZIO_IN, // Z-stated IO pin - garanteed not to be driven externally + input wire ZIO_IODRP_SDO, // ZIO IODRP's SDO port + output reg ZIO_IODRP_CS = 1'b0, // ZIO IODRP's CS port + output wire MCB_UIADD, // to MCB's UIADD port + output wire MCB_UISDI, // to MCB's UISDI port + input wire MCB_UOSDO, // from MCB's UOSDO port (User output SDO) + input wire MCB_UODONECAL, // indicates when MCB hard calibration process is complete + input wire MCB_UOREFRSHFLAG, // high during refresh cycle and time when MCB is innactive + output wire MCB_UICS, // to MCB's UICS port (User Input CS) + output reg MCB_UIDRPUPDATE = 1'b1, // MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used during IODRP2_MCB writes). Currently just trasnparent + output wire MCB_UIBROADCAST, // only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) + output reg [4:0] MCB_UIADDR = 5'b0, // to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port + output reg MCB_UICMDEN = 1'b1, // set to 1 to take control of UI interface - removes control from internal calib block + output reg MCB_UIDONECAL = 1'b0, // set to 0 to "tell" controller that it's still in a calibrate state + output reg MCB_UIDQLOWERDEC = 1'b0, + output reg MCB_UIDQLOWERINC = 1'b0, + output reg MCB_UIDQUPPERDEC = 1'b0, + output reg MCB_UIDQUPPERINC = 1'b0, + output reg MCB_UILDQSDEC = 1'b0, + output reg MCB_UILDQSINC = 1'b0, + output wire MCB_UIREAD, // enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. + output reg MCB_UIUDQSDEC = 1'b0, + output reg MCB_UIUDQSINC = 1'b0, + output reg MCB_RECAL = 1'b0, // future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high + output reg MCB_UICMD, + output reg MCB_UICMDIN, + output reg [3:0] MCB_UIDQCOUNT, + input wire [7:0] MCB_UODATA, + input wire MCB_UODATAVALID, + input wire MCB_UOCMDREADY, + input wire MCB_UO_CAL_START, + + output wire MCB_SYSRST, // drives the MCB's SYSRST pin - the main reset for MCB + output reg [7:0] Max_Value, + output reg CKE_Train + ); + + +localparam [4:0] + IOI_DQ0 = {4'h0, 1'b1}, + IOI_DQ1 = {4'h0, 1'b0}, + IOI_DQ2 = {4'h1, 1'b1}, + IOI_DQ3 = {4'h1, 1'b0}, + IOI_DQ4 = {4'h2, 1'b1}, + IOI_DQ5 = {4'h2, 1'b0}, + IOI_DQ6 = {4'h3, 1'b1}, + IOI_DQ7 = {4'h3, 1'b0}, + IOI_DQ8 = {4'h4, 1'b1}, + IOI_DQ9 = {4'h4, 1'b0}, + IOI_DQ10 = {4'h5, 1'b1}, + IOI_DQ11 = {4'h5, 1'b0}, + IOI_DQ12 = {4'h6, 1'b1}, + IOI_DQ13 = {4'h6, 1'b0}, + IOI_DQ14 = {4'h7, 1'b1}, + IOI_DQ15 = {4'h7, 1'b0}, + IOI_UDM = {4'h8, 1'b1}, + IOI_LDM = {4'h8, 1'b0}, + IOI_CK_P = {4'h9, 1'b1}, + IOI_CK_N = {4'h9, 1'b0}, + IOI_RESET = {4'hA, 1'b1}, + IOI_A11 = {4'hA, 1'b0}, + IOI_WE = {4'hB, 1'b1}, + IOI_BA2 = {4'hB, 1'b0}, + IOI_BA0 = {4'hC, 1'b1}, + IOI_BA1 = {4'hC, 1'b0}, + IOI_RASN = {4'hD, 1'b1}, + IOI_CASN = {4'hD, 1'b0}, + IOI_UDQS_CLK = {4'hE, 1'b1}, + IOI_UDQS_PIN = {4'hE, 1'b0}, + IOI_LDQS_CLK = {4'hF, 1'b1}, + IOI_LDQS_PIN = {4'hF, 1'b0}; + +localparam [5:0] START = 6'h00, + LOAD_RZQ_NTERM = 6'h01, + WAIT1 = 6'h02, + LOAD_RZQ_PTERM = 6'h03, + WAIT2 = 6'h04, + INC_PTERM = 6'h05, + MULTIPLY_DIVIDE = 6'h06, + LOAD_ZIO_PTERM = 6'h07, + WAIT3 = 6'h08, + LOAD_ZIO_NTERM = 6'h09, + WAIT4 = 6'h0A, + INC_NTERM = 6'h0B, + SKEW = 6'h0C, + WAIT_FOR_START_BROADCAST = 6'h0D, + BROADCAST_PTERM = 6'h0E, + WAIT5 = 6'h0F, + BROADCAST_NTERM = 6'h10, + WAIT6 = 6'h11, + OFF_RZQ_PTERM = 6'h12, + WAIT7 = 6'h13, + OFF_ZIO_NTERM = 6'h14, + WAIT8 = 6'h15, + RST_DELAY = 6'h16, + START_DYN_CAL_PRE = 6'h17, + WAIT_FOR_UODONE = 6'h18, + LDQS_WRITE_POS_INDELAY = 6'h19, + LDQS_WAIT1 = 6'h1A, + LDQS_WRITE_NEG_INDELAY = 6'h1B, + LDQS_WAIT2 = 6'h1C, + UDQS_WRITE_POS_INDELAY = 6'h1D, + UDQS_WAIT1 = 6'h1E, + UDQS_WRITE_NEG_INDELAY = 6'h1F, + UDQS_WAIT2 = 6'h20, + START_DYN_CAL = 6'h21, + WRITE_CALIBRATE = 6'h22, + WAIT9 = 6'h23, + READ_MAX_VALUE = 6'h24, + WAIT10 = 6'h25, + ANALYZE_MAX_VALUE = 6'h26, + FIRST_DYN_CAL = 6'h27, + INCREMENT = 6'h28, + DECREMENT = 6'h29, + DONE = 6'h2A; + +localparam [1:0] RZQ = 2'b00, + ZIO = 2'b01, + MCB_PORT = 2'b11; +localparam WRITE_MODE = 1'b0; +localparam READ_MODE = 1'b1; + +// IOI Registers +localparam [7:0] NoOp = 8'h00, + DelayControl = 8'h01, + PosEdgeInDly = 8'h02, + NegEdgeInDly = 8'h03, + PosEdgeOutDly = 8'h04, + NegEdgeOutDly = 8'h05, + MiscCtl1 = 8'h06, + MiscCtl2 = 8'h07, + MaxValue = 8'h08; + +// IOB Registers +localparam [7:0] PDrive = 8'h80, + PTerm = 8'h81, + NDrive = 8'h82, + NTerm = 8'h83, + SlewRateCtl = 8'h84, + LVDSControl = 8'h85, + MiscControl = 8'h86, + InputControl = 8'h87, + TestReadback = 8'h88; + +// No multi/divide is required when a 55 ohm resister is used on RZQ +//localparam MULT = 1; +//localparam DIV = 1; +// use 7/4 scaling factor when the 100 ohm RZQ is used +localparam MULT = 7; +localparam DIV = 4; + +localparam PNSKEW = 1'b1; //Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required +localparam PSKEW_MULT = 9; +localparam PSKEW_DIV = 8; +localparam NSKEW_MULT = 7; +localparam NSKEW_DIV = 8; + +localparam DQS_NUMERATOR = 3; +localparam DQS_DENOMINATOR = 8; +localparam INCDEC_THRESHOLD= 8'h03; // parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter, 3 for three eighths + +reg [5:0] P_Term /* synthesis syn_preserve = 1 */; +reg [6:0] N_Term /* synthesis syn_preserve = 1 */; +reg [5:0] P_Term_Prev /* synthesis syn_preserve = 1 */; +reg [6:0] N_Term_Prev /* synthesis syn_preserve = 1 */; +//(* FSM_ENCODING="USER" *) reg [5:0] STATE = START; //XST does not pick up "BINARY" - use COMPACT instead if binary is desired +reg [5:0] STATE = START; +reg [7:0] IODRPCTRLR_MEMCELL_ADDR /* synthesis syn_preserve = 1 */; +reg [7:0] IODRPCTRLR_WRITE_DATA /* synthesis syn_preserve = 1 */; +reg [1:0] Active_IODRP /* synthesis syn_maxfan = 1 */; +// synthesis attribute max_fanout of Active_IODRP is 1 +reg IODRPCTRLR_R_WB = 1'b0; +reg IODRPCTRLR_CMD_VALID = 1'b0; +reg IODRPCTRLR_USE_BKST = 1'b0; +reg MCB_CMD_VALID = 1'b0; +reg MCB_USE_BKST = 1'b0; +reg Pre_SYSRST = 1'b1 /* synthesis syn_maxfan = 5 */; //internally generated reset which will OR with RST input to drive MCB's SYSRST pin (MCB_SYSRST) +// synthesis attribute max_fanout of Pre_SYSRST is 5 +reg IODRP_SDO; +reg [7:0] Max_Value_Previous = 8'b0 /* synthesis syn_preserve = 1 */; +reg [5:0] count = 6'd0; //counter for adding 18 extra clock cycles after setting Calibrate bit +reg counter_en = 1'b0; //counter enable for "count" +reg First_Dyn_Cal_Done = 1'b0; //flag - high after the very first dynamic calibration is done +reg START_BROADCAST = 1'b1; // Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - state machine will wait for this to be high +reg [7:0] DQS_DELAY_INITIAL = 8'b0 /* synthesis syn_preserve = 1 */; +reg [7:0] DQS_DELAY ; // contains the latest values written to LDQS and UDQS Input Delays +reg [7:0] TARGET_DQS_DELAY; // used to track the target for DQS input delays - only gets updated if the Max Value changes by more than the threshold +reg [7:0] counter_inc; // used to delay Inc signal by several ui_clk cycles (to deal with latency on UOREFRSHFLAG) +reg [7:0] counter_dec; // used to delay Dec signal by several ui_clk cycles (to deal with latency on UOREFRSHFLAG) + +wire [7:0] IODRPCTRLR_READ_DATA; +wire IODRPCTRLR_RDY_BUSY_N; +wire IODRP_CS; +wire [7:0] MCB_READ_DATA; + +reg RST_reg; +reg Block_Reset; + +reg MCB_UODATAVALID_U; + +wire [2:0] Inc_Dec_REFRSH_Flag; // 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place +wire [7:0] Max_Value_Delta_Up; // tracks amount latest Max Value has gone up from previous Max Value read +wire [7:0] Half_MV_DU; // half of Max_Value_Delta_Up +wire [7:0] Max_Value_Delta_Dn; // tracks amount latest Max Value has gone down from previous Max Value read +wire [7:0] Half_MV_DD; // half of Max_Value_Delta_Dn + +reg [9:0] RstCounter = 10'h0; +wire rst_tmp; +reg LastPass_DynCal; +reg First_In_Term_Done; +wire Inc_Flag; // flag to increment Dynamic Delay +wire Dec_Flag; // flag to decrement Dynamic Delay + +wire CALMODE_EQ_CALIBRATION; // will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE parameter = "CALIBRATION" +wire [7:0] DQS_DELAY_LOWER_LIMIT; // Lower limit for DQS input delays +wire [7:0] DQS_DELAY_UPPER_LIMIT; // Upper limit for DQS input delays +wire SKIP_DYN_IN_TERMINATION;//wire to allow skipping dynamic input termination if either the one-time or dynamic parameters are 1 +wire SKIP_DYNAMIC_DQS_CAL; //wire allowing skipping dynamic DQS delay calibration if either SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION +wire [7:0] Quarter_Max_Value; +wire [7:0] Half_Max_Value; +reg PLL_LOCK_R1; +reg PLL_LOCK_R2; + +reg SELFREFRESH_REQ_R1; +reg SELFREFRESH_REQ_R2; +reg SELFREFRESH_REQ_R3; +reg SELFREFRESH_MCB_MODE_R1; +reg SELFREFRESH_MCB_MODE_R2; +reg SELFREFRESH_MCB_MODE_R3; + +reg WAIT_SELFREFRESH_EXIT_DQS_CAL; +reg PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; +reg START_DYN_CAL_STATE_R1; +reg PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1; +reg Rst_condition1, Rst_condition2; +wire non_violating_rst; +reg [15:0] WAIT_200us_COUNTER; + +// 'defines for which pass of the interleaved dynamic algorythm is taking place +`define IN_TERM_PASS 1'b0 +`define DYN_CAL_PASS 1'b1 + +assign Inc_Dec_REFRSH_Flag = {Inc_Flag,Dec_Flag,MCB_UOREFRSHFLAG}; +assign Max_Value_Delta_Up = Max_Value - Max_Value_Previous; +assign Half_MV_DU = {1'b0,Max_Value_Delta_Up[7:1]}; +assign Max_Value_Delta_Dn = Max_Value_Previous - Max_Value; +assign Half_MV_DD = {1'b0,Max_Value_Delta_Dn[7:1]}; +assign CALMODE_EQ_CALIBRATION = (C_MC_CALIBRATION_MODE == "CALIBRATION") ? 1'b1 : 1'b0; // will calculate and set the DQS input delays if = 1'b1 +assign Half_Max_Value = Max_Value >> 1; +assign Quarter_Max_Value = Max_Value >> 2; +assign DQS_DELAY_LOWER_LIMIT = Quarter_Max_Value; // limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here +assign DQS_DELAY_UPPER_LIMIT = Half_Max_Value; // limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here +assign SKIP_DYN_IN_TERMINATION = SKIP_DYN_IN_TERM || SKIP_IN_TERM_CAL; //skip dynamic input termination if either the one-time or dynamic parameters are 1 +assign SKIP_DYNAMIC_DQS_CAL = ~CALMODE_EQ_CALIBRATION || SKIP_DYNAMIC_CAL; //skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION + +always @ (posedge UI_CLK) + DONE_SOFTANDHARD_CAL <= ((DQS_DELAY_INITIAL != 8'h00) || (STATE == DONE)) && MCB_UODONECAL; //high when either DQS input delays initialized, or STATE=DONE and UODONECAL high + + +iodrp_controller iodrp_controller( + .memcell_address (IODRPCTRLR_MEMCELL_ADDR), + .write_data (IODRPCTRLR_WRITE_DATA), + .read_data (IODRPCTRLR_READ_DATA), + .rd_not_write (IODRPCTRLR_R_WB), + .cmd_valid (IODRPCTRLR_CMD_VALID), + .rdy_busy_n (IODRPCTRLR_RDY_BUSY_N), + .use_broadcast (1'b0), + .sync_rst (RST_reg), + .DRP_CLK (UI_CLK), + .DRP_CS (IODRP_CS), + .DRP_SDI (IODRP_SDI), + .DRP_ADD (IODRP_ADD), + .DRP_SDO (IODRP_SDO), + .DRP_BKST () + ); + +iodrp_mcb_controller iodrp_mcb_controller( + .memcell_address (IODRPCTRLR_MEMCELL_ADDR), + .write_data (IODRPCTRLR_WRITE_DATA), + .read_data (MCB_READ_DATA), + .rd_not_write (IODRPCTRLR_R_WB), + .cmd_valid (MCB_CMD_VALID), + .rdy_busy_n (MCB_RDY_BUSY_N), + .use_broadcast (MCB_USE_BKST), + .drp_ioi_addr (MCB_UIADDR), + .sync_rst (RST_reg), + .DRP_CLK (UI_CLK), + .DRP_CS (MCB_UICS), + .DRP_SDI (MCB_UISDI), + .DRP_ADD (MCB_UIADD), + .DRP_BKST (MCB_UIBROADCAST), + .DRP_SDO (MCB_UOSDO), + .MCB_UIREAD (MCB_UIREAD) + ); + + +//****************************************************************************************** +// Mult_Divide Function - multiplies by a constant MULT and then divides by the DIV constant +//****************************************************************************************** +function [7:0] Mult_Divide; +input [7:0] Input; +input [7:0] Mult; +input [7:0] Div; +reg [3:0] count; +reg [15:0] Result; +begin + Result = 0; + for (count = 0; count < Mult; count = count+1) begin + Result = Result + Input; + end + Result = Result / Div; + Mult_Divide = Result[7:0]; +end +endfunction + + +generate +if (C_SIMULATION == "FALSE") begin: init_sequence + always @ (posedge UI_CLK, posedge RST) + begin + if (RST) + WAIT_200us_COUNTER <= 'b0; + else + if (WAIT_200us_COUNTER[15]) // UI_CLK maximum is up to 100 MHz. + WAIT_200us_COUNTER <= WAIT_200us_COUNTER ; + else + WAIT_200us_COUNTER <= WAIT_200us_COUNTER + 1'b1; + end +end +else begin: init_sequence_skip +// synthesis translate_off + initial + begin + WAIT_200us_COUNTER = 16'hFFFF; + $display("The 200 us wait period required before CKE goes active has been skipped in Simulation\n"); + end +// synthesis translate_on +end +endgenerate + + +generate +if( C_MEM_TYPE == "DDR2") begin : gen_cketrain_a + + +always @ ( posedge UI_CLK, posedge RST) +begin +if (RST) + CKE_Train <= 1'b0; +else + if (STATE == WAIT_FOR_UODONE && MCB_UODONECAL) + CKE_Train <= 1'b0; + else if (WAIT_200us_COUNTER[15] && ~MCB_UODONECAL) + CKE_Train <= 1'b1; + +end +end +endgenerate + + +generate +if( C_MEM_TYPE != "DDR2") begin : gen_cketrain_b +always @ ( posedge UI_CLK) + CKE_Train <= 1'b0; +end +endgenerate + +//******************************************** +//PLL_LOCK and Reset signals +//******************************************** +localparam RST_CNT = 10'h010; //defines pulse-width for reset +localparam TZQINIT_MAXCNT = C_MEM_TZQINIT_MAXCNT + RST_CNT; +assign MCB_SYSRST = Pre_SYSRST | RST_reg ; //Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's SYSRST pin (MCB_SYSRST) +assign rst_tmp = (~PLL_LOCK_R2 && ~SELFREFRESH_MODE); //rst_tmp becomes 1 if you lose PLL lock (registered twice for metastblty) and the device is not in SUSPEND +assign non_violating_rst = RST && Rst_condition1; //non_violating_rst is when the user-reset RST occurs and TZQINIT (min time between resets for DDR3) is not being violated + + + + +always @ (posedge UI_CLK or posedge RST ) begin + if (RST) begin + Block_Reset <= 1'b0; + RstCounter <= 10'b0; +end + else if (rst_tmp) begin //this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3) + Block_Reset <= 1'b0; + RstCounter <= 10'b0; + end + else begin + Block_Reset <= 1'b0; //default to allow STATE to move out of RST_DELAY state + if (Pre_SYSRST) + RstCounter <= RST_CNT; //whenever STATE wants to reset the MCB, set RstCounter to h10 + else begin + if (RstCounter < TZQINIT_MAXCNT) begin //if RstCounter is less than d512 than this will execute + Block_Reset <= 1'b1; //STATE won't exit RST_DELAY state + RstCounter <= RstCounter + 1'b1; //and Rst_Counter increments + end + end + end +end + + + +always @ (posedge UI_CLK ) begin +if (RstCounter >= TZQINIT_MAXCNT) + Rst_condition1 <= 1'b1; +else + Rst_condition1 <= 1'b0; + +end + +always @ (posedge UI_CLK ) begin +if (RstCounter < RST_CNT) + Rst_condition2 <= 1'b1; + else + Rst_condition2 <= 1'b0; + +end +always @ (posedge UI_CLK or posedge non_violating_rst ) begin + if (non_violating_rst) + RST_reg <= 1'b1; + else if (~WAIT_200us_COUNTER[15]) + RST_reg <= 1'b1; + else + RST_reg <= Rst_condition2 | rst_tmp ; + +end + + +//******************************************** +// SUSPEND Logic +//******************************************** + +always @ ( posedge UI_CLK) begin + //SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180 + SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE; + SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1; + SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2; + + //SELFREFRESH_REQ is clocked by user's application clock + SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ; + SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1; + SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2; + + PLL_LOCK_R1 <= PLL_LOCK; + PLL_LOCK_R2 <= PLL_LOCK_R1; + + +end + +// SELFREFRESH should only be deasserted after PLL_LOCK is asserted. +// This is to make sure MCB get a locked sys_2x_clk before exiting +// SELFREFRESH mode. + +always @ ( posedge UI_CLK) begin + if (RST) + SELFREFRESH_MCB_REQ <= 1'b0; + else if (PLL_LOCK_R2 && ~SELFREFRESH_REQ_R1 && STATE == START_DYN_CAL) + SELFREFRESH_MCB_REQ <= 1'b0; + else if (STATE == START_DYN_CAL && SELFREFRESH_REQ_R1) + SELFREFRESH_MCB_REQ <= 1'b1; +end + + + +always @ (posedge UI_CLK) begin + if (RST) + WAIT_SELFREFRESH_EXIT_DQS_CAL <= 1'b0; + else if (~SELFREFRESH_MCB_MODE_R3 && SELFREFRESH_MCB_MODE_R2) + + WAIT_SELFREFRESH_EXIT_DQS_CAL <= 1'b1; + else if (WAIT_SELFREFRESH_EXIT_DQS_CAL && ~SELFREFRESH_REQ_R3 && PERFORM_START_DYN_CAL_AFTER_SELFREFRESH) // START_DYN_CAL is next state + WAIT_SELFREFRESH_EXIT_DQS_CAL <= 1'b0; +end + +//Need to detect when SM entering START_DYN_CAL +always @ (posedge UI_CLK) begin + if (RST) begin + PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= 1'b0; + START_DYN_CAL_STATE_R1 <= 1'b0; + end + else begin + // register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle + PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH; + if (STATE == START_DYN_CAL) + START_DYN_CAL_STATE_R1 <= 1'b1; + else + START_DYN_CAL_STATE_R1 <= 1'b0; + if (WAIT_SELFREFRESH_EXIT_DQS_CAL && STATE != START_DYN_CAL && START_DYN_CAL_STATE_R1 ) + PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= 1'b1; + else if (STATE == START_DYN_CAL && ~SELFREFRESH_MCB_MODE_R3) + PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= 1'b0; + end + end + + +// SELFREFRESH_MCB_MODE deasserted status is hold off +// until Soft_Calib has at least done one loop of DQS update. +always @ (posedge UI_CLK) begin + if (RST) + SELFREFRESH_MODE <= 1'b0; + else if (SELFREFRESH_MCB_MODE_R2) + SELFREFRESH_MODE <= 1'b1; + else if (!PERFORM_START_DYN_CAL_AFTER_SELFREFRESH && PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1) + SELFREFRESH_MODE <= 1'b0; +end + +//******************************************** +//Comparitors for Dynamic Calibration circuit +//******************************************** +assign Dec_Flag = (TARGET_DQS_DELAY < DQS_DELAY); +assign Inc_Flag = (TARGET_DQS_DELAY > DQS_DELAY); + + +//********************************************************************************************* +//Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal +//********************************************************************************************* + always @(posedge UI_CLK) + begin + if (RST_reg) + count <= 6'd0; + else if (counter_en) + count <= count + 1'b1; + else + count <= 6'd0; + end + +//********************************************************************************************* +// Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide +//********************************************************************************************* + always @(posedge UI_CLK or posedge MCB_UODATAVALID) + begin + if (MCB_UODATAVALID) + MCB_UODATAVALID_U <= 1'b1; + else + MCB_UODATAVALID_U <= MCB_UODATAVALID; + end + + //************************************************************************************************************** + //Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs) + //************************************************************************************************************** + always @(*) begin: ACTIVE_IODRP + case (Active_IODRP) + RZQ: begin + RZQ_IODRP_CS = IODRP_CS; + ZIO_IODRP_CS = 1'b0; + IODRP_SDO = RZQ_IODRP_SDO; + end + ZIO: begin + RZQ_IODRP_CS = 1'b0; + ZIO_IODRP_CS = IODRP_CS; + IODRP_SDO = ZIO_IODRP_SDO; + end + MCB_PORT: begin + RZQ_IODRP_CS = 1'b0; + ZIO_IODRP_CS = 1'b0; + IODRP_SDO = 1'b0; + end + default: begin + RZQ_IODRP_CS = 1'b0; + ZIO_IODRP_CS = 1'b0; + IODRP_SDO = 1'b0; + end + endcase + end + +//****************************************************************** +//State Machine's Always block / Case statement for Next State Logic +// +//The WAIT1,2,etc states were required after every state where the +//DRP controller was used to do a write to the IODRPs - this is because +//there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller +//sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added +//soley for the purpose of reducing power, particularly on RZQ as +//that pin is expected to have a permanent external resistor to gnd. +//****************************************************************** + always @(posedge UI_CLK) begin: NEXT_STATE_LOGIC + if (RST_reg) begin // Synchronous reset + MCB_CMD_VALID <= 1'b0; + MCB_UIADDR <= 5'b0; + MCB_UICMDEN <= 1'b1; // take control of UI/UO port + MCB_UIDONECAL <= 1'b0; // tells MCB that it is in Soft Cal. + MCB_USE_BKST <= 1'b0; + MCB_UIDRPUPDATE <= 1'b1; + Pre_SYSRST <= 1'b1; // keeps MCB in reset + IODRPCTRLR_CMD_VALID <= 1'b0; + IODRPCTRLR_MEMCELL_ADDR <= NoOp; + IODRPCTRLR_WRITE_DATA <= 1'b0; + IODRPCTRLR_R_WB <= WRITE_MODE; + IODRPCTRLR_USE_BKST <= 1'b0; + P_Term <= 6'b0; + N_Term <= 7'b0; + P_Term_Prev <= 6'b0; + N_Term_Prev <= 7'b0; + Active_IODRP <= RZQ; + MCB_UILDQSINC <= 1'b0; //no inc or dec + MCB_UIUDQSINC <= 1'b0; //no inc or dec + MCB_UILDQSDEC <= 1'b0; //no inc or dec + MCB_UIUDQSDEC <= 1'b0; //no inc or dec + counter_en <= 1'b0; + First_Dyn_Cal_Done <= 1'b0; //flag that the First Dynamic Calibration completed + Max_Value <= 8'b0; + Max_Value_Previous <= 8'b0; + STATE <= START; + DQS_DELAY <= 8'h0; //tracks the cumulative incrementing/decrementing that has been done + DQS_DELAY_INITIAL <= 8'h0; + TARGET_DQS_DELAY <= 8'h0; + LastPass_DynCal <= `IN_TERM_PASS; + First_In_Term_Done <= 1'b0; + MCB_UICMD <= 1'b0; + MCB_UICMDIN <= 1'b0; + MCB_UIDQCOUNT <= 4'h0; + counter_inc <= 8'h0; + counter_dec <= 8'h0; + end + else begin + counter_en <= 1'b0; + IODRPCTRLR_CMD_VALID <= 1'b0; + IODRPCTRLR_MEMCELL_ADDR <= NoOp; + IODRPCTRLR_R_WB <= READ_MODE; + IODRPCTRLR_USE_BKST <= 1'b0; + MCB_CMD_VALID <= 1'b0; + MCB_UILDQSINC <= 1'b0; //no inc or dec + MCB_UIUDQSINC <= 1'b0; //no inc or dec + MCB_UILDQSDEC <= 1'b0; //no inc or dec + MCB_UIUDQSDEC <= 1'b0; //no inc or dec + MCB_USE_BKST <= 1'b0; + MCB_UICMDIN <= 1'b0; + DQS_DELAY <= DQS_DELAY; + TARGET_DQS_DELAY <= TARGET_DQS_DELAY; + case (STATE) + START: begin //h00 + MCB_UICMDEN <= 1'b1; // take control of UI/UO port + MCB_UIDONECAL <= 1'b0; // tells MCB that it is in Soft Cal. + P_Term <= 6'b0; + N_Term <= 7'b0; + Pre_SYSRST <= 1'b1; // keeps MCB in reset + LastPass_DynCal <= `IN_TERM_PASS; + if (SKIP_IN_TERM_CAL) + STATE <= WRITE_CALIBRATE; + else if (IODRPCTRLR_RDY_BUSY_N) + STATE <= LOAD_RZQ_NTERM; + else + STATE <= START; + end +//*************************** +// IOB INPUT TERMINATION CAL +//*************************** + LOAD_RZQ_NTERM: begin //h01 + Active_IODRP <= RZQ; + IODRPCTRLR_CMD_VALID <= 1'b1; + IODRPCTRLR_MEMCELL_ADDR <= NTerm; + IODRPCTRLR_WRITE_DATA <= {1'b0,N_Term}; + IODRPCTRLR_R_WB <= WRITE_MODE; + if (IODRPCTRLR_RDY_BUSY_N) + STATE <= LOAD_RZQ_NTERM; + else + STATE <= WAIT1; + end + WAIT1: begin //h02 + if (!IODRPCTRLR_RDY_BUSY_N) + STATE <= WAIT1; + else + STATE <= LOAD_RZQ_PTERM; + end + LOAD_RZQ_PTERM: begin //h03 + IODRPCTRLR_CMD_VALID <= 1'b1; + IODRPCTRLR_MEMCELL_ADDR <= PTerm; + IODRPCTRLR_WRITE_DATA <= {2'b00,P_Term}; + IODRPCTRLR_R_WB <= WRITE_MODE; + if (IODRPCTRLR_RDY_BUSY_N) + STATE <= LOAD_RZQ_PTERM; + else + STATE <= WAIT2; + end + WAIT2: begin //h04 + if (!IODRPCTRLR_RDY_BUSY_N) + STATE <= WAIT2; + else if ((RZQ_IN)||(P_Term == 6'b111111)) begin + STATE <= MULTIPLY_DIVIDE;//LOAD_ZIO_PTERM; + end + else + STATE <= INC_PTERM; + end + INC_PTERM: begin //h05 + P_Term <= P_Term + 1; + STATE <= LOAD_RZQ_PTERM; + end + MULTIPLY_DIVIDE: begin //06 + P_Term <= Mult_Divide(P_Term, MULT, DIV); + STATE <= LOAD_ZIO_PTERM; + end + LOAD_ZIO_PTERM: begin //h07 + Active_IODRP <= ZIO; + IODRPCTRLR_CMD_VALID <= 1'b1; + IODRPCTRLR_MEMCELL_ADDR <= PTerm; + IODRPCTRLR_WRITE_DATA <= {2'b00,P_Term}; + IODRPCTRLR_R_WB <= WRITE_MODE; + if (IODRPCTRLR_RDY_BUSY_N) + STATE <= LOAD_ZIO_PTERM; + else + STATE <= WAIT3; + end + WAIT3: begin //h08 + if (!IODRPCTRLR_RDY_BUSY_N) + STATE <= WAIT3; + else begin + STATE <= LOAD_ZIO_NTERM; + end + end + LOAD_ZIO_NTERM: begin //h09 + Active_IODRP <= ZIO; + IODRPCTRLR_CMD_VALID <= 1'b1; + IODRPCTRLR_MEMCELL_ADDR <= NTerm; + IODRPCTRLR_WRITE_DATA <= {1'b0,N_Term}; + IODRPCTRLR_R_WB <= WRITE_MODE; + if (IODRPCTRLR_RDY_BUSY_N) + STATE <= LOAD_ZIO_NTERM; + else + STATE <= WAIT4; + end + WAIT4: begin //h0A + if (!IODRPCTRLR_RDY_BUSY_N) + STATE <= WAIT4; + else if ((!ZIO_IN)||(N_Term == 7'b1111111)) begin + if (PNSKEW) begin + STATE <= SKEW; + end + else + STATE <= WAIT_FOR_START_BROADCAST; + end + else + STATE <= INC_NTERM; + end + INC_NTERM: begin //h0B + N_Term <= N_Term + 1; + STATE <= LOAD_ZIO_NTERM; + end + SKEW : begin //0C + P_Term <= Mult_Divide(P_Term, PSKEW_MULT, PSKEW_DIV); + N_Term <= Mult_Divide(N_Term, NSKEW_MULT, NSKEW_DIV); + STATE <= WAIT_FOR_START_BROADCAST; + end + WAIT_FOR_START_BROADCAST: begin //h0D + Pre_SYSRST <= 1'b0; //release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while keeping the MCB in calibration mode + Active_IODRP <= MCB_PORT; + if (START_BROADCAST && IODRPCTRLR_RDY_BUSY_N) begin + if (P_Term != P_Term_Prev) begin + STATE <= BROADCAST_PTERM; + P_Term_Prev <= P_Term; + end + else if (N_Term != N_Term_Prev) begin + N_Term_Prev <= N_Term; + STATE <= BROADCAST_NTERM; + end + else + STATE <= OFF_RZQ_PTERM; + end + else + STATE <= WAIT_FOR_START_BROADCAST; + end + BROADCAST_PTERM: begin //h0E +//SBS redundant? MCB_UICMDEN <= 1'b1; // take control of UI/UO port for reentrant use of dynamic In Term tuning + IODRPCTRLR_MEMCELL_ADDR <= PTerm; + IODRPCTRLR_WRITE_DATA <= {2'b00,P_Term}; + IODRPCTRLR_R_WB <= WRITE_MODE; + MCB_CMD_VALID <= 1'b1; + MCB_UIDRPUPDATE <= ~First_In_Term_Done; // Set the update flag if this is the first time through + MCB_USE_BKST <= 1'b1; + if (MCB_RDY_BUSY_N) + STATE <= BROADCAST_PTERM; + else + STATE <= WAIT5; + end + WAIT5: begin //h0F + if (!MCB_RDY_BUSY_N) + STATE <= WAIT5; + else if (First_In_Term_Done) begin // If first time through is already set, then this must be dynamic in term + if (MCB_UOREFRSHFLAG) begin + MCB_UIDRPUPDATE <= 1'b1; + if (N_Term != N_Term_Prev) begin + N_Term_Prev <= N_Term; + STATE <= BROADCAST_NTERM; + end + else + STATE <= OFF_RZQ_PTERM; + end + else + STATE <= WAIT5; // wait for a Refresh cycle + end + else begin + N_Term_Prev <= N_Term; + STATE <= BROADCAST_NTERM; + end + end + BROADCAST_NTERM: begin //h10 + IODRPCTRLR_MEMCELL_ADDR <= NTerm; + IODRPCTRLR_WRITE_DATA <= {2'b00,N_Term}; + IODRPCTRLR_R_WB <= WRITE_MODE; + MCB_CMD_VALID <= 1'b1; + MCB_USE_BKST <= 1'b1; + MCB_UIDRPUPDATE <= ~First_In_Term_Done; // Set the update flag if this is the first time through + if (MCB_RDY_BUSY_N) + STATE <= BROADCAST_NTERM; + else + STATE <= WAIT6; + end + WAIT6: begin // 7'h11 + if (!MCB_RDY_BUSY_N) + STATE <= WAIT6; + else if (First_In_Term_Done) begin // If first time through is already set, then this must be dynamic in term + if (MCB_UOREFRSHFLAG) begin + MCB_UIDRPUPDATE <= 1'b1; + STATE <= OFF_RZQ_PTERM; + end + else + STATE <= WAIT6; // wait for a Refresh cycle + end + else + STATE <= OFF_RZQ_PTERM; + end + OFF_RZQ_PTERM: begin // 7'h12 + Active_IODRP <= RZQ; + IODRPCTRLR_CMD_VALID <= 1'b1; + IODRPCTRLR_MEMCELL_ADDR <= PTerm; + IODRPCTRLR_WRITE_DATA <= 8'b00; + IODRPCTRLR_R_WB <= WRITE_MODE; + P_Term <= 6'b0; + N_Term <= 5'b0; + MCB_UIDRPUPDATE <= ~First_In_Term_Done; // Set the update flag if this is the first time through + if (IODRPCTRLR_RDY_BUSY_N) + STATE <= OFF_RZQ_PTERM; + else + STATE <= WAIT7; + end + WAIT7: begin // 7'h13 + if (!IODRPCTRLR_RDY_BUSY_N) + STATE <= WAIT7; + else + STATE <= OFF_ZIO_NTERM; + end + OFF_ZIO_NTERM: begin // 7'h14 + Active_IODRP <= ZIO; + IODRPCTRLR_CMD_VALID <= 1'b1; + IODRPCTRLR_MEMCELL_ADDR <= NTerm; + IODRPCTRLR_WRITE_DATA <= 8'b00; + IODRPCTRLR_R_WB <= WRITE_MODE; + if (IODRPCTRLR_RDY_BUSY_N) + STATE <= OFF_ZIO_NTERM; + else + STATE <= WAIT8; + end + WAIT8: begin // 7'h15 + if (!IODRPCTRLR_RDY_BUSY_N) + STATE <= WAIT8; + else begin + if (First_In_Term_Done) begin + STATE <= START_DYN_CAL; // No need to reset the MCB if we are in InTerm tuning + end + else begin + STATE <= WRITE_CALIBRATE; // go read the first Max_Value from RZQ + end + end + end + RST_DELAY: begin // 7'h16 + MCB_UICMDEN <= 1'b0; // release control of UI/UO port + if (Block_Reset) begin // this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ??? + STATE <= RST_DELAY; + end + else begin + STATE <= START_DYN_CAL_PRE; + end + end +//**************************** +// DYNAMIC CALIBRATION PORTION +//**************************** + START_DYN_CAL_PRE: begin // 7'h17 + LastPass_DynCal <= `IN_TERM_PASS; + MCB_UICMDEN <= 1'b0; // release UICMDEN + MCB_UIDONECAL <= 1'b1; // release UIDONECAL - MCB will now initialize. + Pre_SYSRST <= 1'b1; // SYSRST pulse + if (~CALMODE_EQ_CALIBRATION) // if C_MC_CALIBRATION_MODE is set to NOCALIBRATION + STATE <= START_DYN_CAL; // we'll skip setting the DQS delays manually + else + STATE <= WAIT_FOR_UODONE; + end + WAIT_FOR_UODONE: begin //7'h18 + Pre_SYSRST <= 1'b0; // SYSRST pulse + if (IODRPCTRLR_RDY_BUSY_N && MCB_UODONECAL) begin //IODRP Controller needs to be ready, & MCB needs to be done with hard calibration + MCB_UICMDEN <= 1'b1; // grab UICMDEN + DQS_DELAY_INITIAL <= Mult_Divide(Max_Value, DQS_NUMERATOR, DQS_DENOMINATOR); + STATE <= LDQS_WRITE_POS_INDELAY; + end + else + STATE <= WAIT_FOR_UODONE; + end + LDQS_WRITE_POS_INDELAY: begin// 7'h19 + IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; + IODRPCTRLR_R_WB <= WRITE_MODE; + IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; + MCB_UIADDR <= IOI_LDQS_CLK; + MCB_CMD_VALID <= 1'b1; + if (MCB_RDY_BUSY_N) + STATE <= LDQS_WRITE_POS_INDELAY; + else + STATE <= LDQS_WAIT1; + end + LDQS_WAIT1: begin // 7'h1A + if (!MCB_RDY_BUSY_N) + STATE <= LDQS_WAIT1; + else begin + STATE <= LDQS_WRITE_NEG_INDELAY; + end + end + LDQS_WRITE_NEG_INDELAY: begin// 7'h1B + IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; + IODRPCTRLR_R_WB <= WRITE_MODE; + IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; + MCB_UIADDR <= IOI_LDQS_CLK; + MCB_CMD_VALID <= 1'b1; + if (MCB_RDY_BUSY_N) + STATE <= LDQS_WRITE_NEG_INDELAY; + else + STATE <= LDQS_WAIT2; + end + LDQS_WAIT2: begin // 7'h1C + if (!MCB_RDY_BUSY_N) + STATE <= LDQS_WAIT2; + else begin + STATE <= UDQS_WRITE_POS_INDELAY; + end + end + UDQS_WRITE_POS_INDELAY: begin// 7'h1D + IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly; + IODRPCTRLR_R_WB <= WRITE_MODE; + IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; + MCB_UIADDR <= IOI_UDQS_CLK; + MCB_CMD_VALID <= 1'b1; + if (MCB_RDY_BUSY_N) + STATE <= UDQS_WRITE_POS_INDELAY; + else + STATE <= UDQS_WAIT1; + end + UDQS_WAIT1: begin // 7'h1E + if (!MCB_RDY_BUSY_N) + STATE <= UDQS_WAIT1; + else begin + STATE <= UDQS_WRITE_NEG_INDELAY; + end + end + UDQS_WRITE_NEG_INDELAY: begin// 7'h1F + IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly; + IODRPCTRLR_R_WB <= WRITE_MODE; + IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL; + MCB_UIADDR <= IOI_UDQS_CLK; + MCB_CMD_VALID <= 1'b1; + if (MCB_RDY_BUSY_N) + STATE <= UDQS_WRITE_NEG_INDELAY; + else + STATE <= UDQS_WAIT2; + end + UDQS_WAIT2: begin // 7'h20 + if (!MCB_RDY_BUSY_N) + STATE <= UDQS_WAIT2; + else begin + DQS_DELAY <= DQS_DELAY_INITIAL; + TARGET_DQS_DELAY <= DQS_DELAY_INITIAL; + STATE <= START_DYN_CAL; + end + end +//************************************************************************************** + START_DYN_CAL: begin // 7'h21 + Pre_SYSRST <= 1'b0; // SYSRST not driven + counter_inc <= 8'b0; + counter_dec <= 8'b0; + if (SKIP_DYNAMIC_DQS_CAL & SKIP_DYN_IN_TERMINATION) + STATE <= DONE; //if we're skipping both dynamic algorythms, go directly to DONE + else + if (IODRPCTRLR_RDY_BUSY_N && MCB_UODONECAL && ~SELFREFRESH_REQ_R1 ) begin //IODRP Controller needs to be ready, & MCB needs to be done with hard calibration + + // Alternate between Dynamic Input Termination and Dynamic Tuning routines + if (~SKIP_DYN_IN_TERMINATION & (LastPass_DynCal == `DYN_CAL_PASS)) begin + LastPass_DynCal <= `IN_TERM_PASS; + STATE <= LOAD_RZQ_NTERM; + end + else begin + LastPass_DynCal <= `DYN_CAL_PASS; + STATE <= WRITE_CALIBRATE; + end + end + else + STATE <= START_DYN_CAL; + end + WRITE_CALIBRATE: begin // 7'h22 + Pre_SYSRST <= 1'b0; // SYSRST not driven + IODRPCTRLR_CMD_VALID <= 1'b1; + IODRPCTRLR_MEMCELL_ADDR <= DelayControl; + IODRPCTRLR_WRITE_DATA <= 8'h20; // Set calibrate bit + IODRPCTRLR_R_WB <= WRITE_MODE; + Active_IODRP <= RZQ; + if (IODRPCTRLR_RDY_BUSY_N) + STATE <= WRITE_CALIBRATE; + else + STATE <= WAIT9; + end + WAIT9: begin // 7'h23 + counter_en <= 1'b1; + if (count < 6'd38) //this adds approximately 22 extra clock cycles after WRITE_CALIBRATE + STATE <= WAIT9; + else + STATE <= READ_MAX_VALUE; + end + READ_MAX_VALUE: begin // 7'h24 + IODRPCTRLR_CMD_VALID <= 1'b1; + IODRPCTRLR_MEMCELL_ADDR <= MaxValue; + IODRPCTRLR_R_WB <= READ_MODE; + Max_Value_Previous <= Max_Value; + if (IODRPCTRLR_RDY_BUSY_N) + STATE <= READ_MAX_VALUE; + else + STATE <= WAIT10; + end + WAIT10: begin // 7'h25 + if (!IODRPCTRLR_RDY_BUSY_N) + STATE <= WAIT10; + else begin + Max_Value <= IODRPCTRLR_READ_DATA; //record the Max_Value from the IODRP controller + if (~First_In_Term_Done) begin + STATE <= RST_DELAY; + First_In_Term_Done <= 1'b1; + end + else + STATE <= ANALYZE_MAX_VALUE; + end + end + ANALYZE_MAX_VALUE: begin // 7'h26 only do a Inc or Dec during a REFRESH cycle. + if (!First_Dyn_Cal_Done) + STATE <= FIRST_DYN_CAL; + else + if ((Max_Value=INCDEC_THRESHOLD)) begin + STATE <= DECREMENT; //May need to Decrement + TARGET_DQS_DELAY <= Mult_Divide(Max_Value, DQS_NUMERATOR, DQS_DENOMINATOR); + end + else + if ((Max_Value>Max_Value_Previous)&&(Max_Value_Delta_Up>=INCDEC_THRESHOLD)) begin + STATE <= INCREMENT; //May need to Increment + TARGET_DQS_DELAY <= Mult_Divide(Max_Value, DQS_NUMERATOR, DQS_DENOMINATOR); + end + else begin + Max_Value <= Max_Value_Previous; + STATE <= START_DYN_CAL; + end + end + FIRST_DYN_CAL: begin // 7'h27 + First_Dyn_Cal_Done <= 1'b1; //set flag that the First Dynamic Calibration has been completed + STATE <= START_DYN_CAL; + end + INCREMENT: begin // 7'h28 + STATE <= START_DYN_CAL; // Default case: Inc is not high or no longer in REFRSH + MCB_UILDQSINC <= 1'b0; // Default case: no inc or dec + MCB_UIUDQSINC <= 1'b0; // Default case: no inc or dec + MCB_UILDQSDEC <= 1'b0; // Default case: no inc or dec + MCB_UIUDQSDEC <= 1'b0; // Default case: no inc or dec + case (Inc_Dec_REFRSH_Flag) // {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, + 3'b101: begin + counter_inc <= counter_inc + 1'b1; + STATE <= INCREMENT; //Increment is still high, still in REFRSH cycle + if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT && counter_inc >= 8'h04) begin //if not at the upper limit yet, and you've waited 4 clks, increment + MCB_UILDQSINC <= 1'b1; //increment + MCB_UIUDQSINC <= 1'b1; //increment + DQS_DELAY <= DQS_DELAY + 1'b1; + end + end + 3'b100: begin + if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) + STATE <= INCREMENT; //Increment is still high, REFRESH ended - wait for next REFRESH + end + default: + STATE <= START_DYN_CAL; // Default case + endcase + end + DECREMENT: begin // 7'h29 + STATE <= START_DYN_CAL; // Default case: Dec is not high or no longer in REFRSH + MCB_UILDQSINC <= 1'b0; // Default case: no inc or dec + MCB_UIUDQSINC <= 1'b0; // Default case: no inc or dec + MCB_UILDQSDEC <= 1'b0; // Default case: no inc or dec + MCB_UIUDQSDEC <= 1'b0; // Default case: no inc or dec + if (DQS_DELAY != 8'h00) begin + case (Inc_Dec_REFRSH_Flag) // {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG}, + 3'b011: begin + counter_dec <= counter_dec + 1'b1; + STATE <= DECREMENT; // Decrement is still high, still in REFRESH cycle + if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT && counter_dec >= 8'h04) begin //if not at the lower limit, and you've waited 4 clks, decrement + MCB_UILDQSDEC <= 1'b1; // decrement + MCB_UIUDQSDEC <= 1'b1; // decrement + DQS_DELAY <= DQS_DELAY - 1'b1; //SBS + end + end + 3'b010: begin + if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) //if not at the lower limit, decrement + STATE <= DECREMENT; //Decrement is still high, REFRESH ended - wait for next REFRESH + end + default: begin + STATE <= START_DYN_CAL; // Default case + end + endcase + end + end + DONE: begin // 7'h2A + Pre_SYSRST <= 1'b0; // SYSRST cleared + MCB_UICMDEN <= 1'b0; // release UICMDEN + STATE <= DONE; + end + default: begin + MCB_UICMDEN <= 1'b0; // release UICMDEN + MCB_UIDONECAL <= 1'b1; // release UIDONECAL - MCB will now initialize. + Pre_SYSRST <= 1'b0; // SYSRST not driven + IODRPCTRLR_CMD_VALID <= 1'b0; + IODRPCTRLR_MEMCELL_ADDR <= 8'h00; + IODRPCTRLR_WRITE_DATA <= 8'h00; + IODRPCTRLR_R_WB <= 1'b0; + IODRPCTRLR_USE_BKST <= 1'b0; + P_Term <= 6'b0; + N_Term <= 5'b0; + Active_IODRP <= ZIO; + Max_Value_Previous <= 8'b0; + MCB_UILDQSINC <= 1'b0; // no inc or dec + MCB_UIUDQSINC <= 1'b0; // no inc or dec + MCB_UILDQSDEC <= 1'b0; // no inc or dec + MCB_UIUDQSDEC <= 1'b0; // no inc or dec + counter_en <= 1'b0; + First_Dyn_Cal_Done <= 1'b0; // flag that the First Dynamic Calibration completed + Max_Value <= Max_Value; + STATE <= START; + end + endcase + end + end + +endmodule
xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v (revision 627) @@ -0,0 +1,979 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Xilinx Spartan-6 DDR2 controller Wishbone Interface //// +//// //// +//// Description //// +//// Simple interface to the Xilinx MIG generated DDR2 controller//// +//// //// +//// To Do: //// +//// Use full capacity of BRAM //// +//// Employ LRU replacement scheme //// +//// Remove hard-coding of things relating to number of lines //// +//// //// +//// Author(s): //// +//// - Julius Baxter, julius.baxter@orsoc.se //// +//// - Stefan Kristiansson, stefan.kristiansson@saunalahti.fi//// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2010 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +/* + * This is an interface to the Xilinx MIG-sourced DDR2 controller. + * + * The interface is based on the ML501 Virtex-5 board implementation + * with the following adaptions to suite the Atlys Spartan-6 MIG and + * DDR2 memory chip: + * - Control and data FIFOs are clocked with the Wishbone bus clock + * and not the DDR2 clock. + * This way alot of clock domain crossing headaches can be avoided + * (Virtex-5 MIG demands control and data FIFOs clocks to be + * synchronous with the DDR2 clock, Spartan-6 have FIFOs that + * are asynchronous to the DDR2 clock) + * - The Atlys board have a DDR2 memory with a 16-bit data bus + * apposed to the ML501 64-bit databus. This in combination + * with changes in the MIG causes the addressing scheme to be a + * bit different. A user port of 128-bit is being used, so + * we are doing memory accesses on 128-bit boundaries + * (4 address bits). + * + * See the Xilinx user guide UG388.pdf for more information on the + * Spartan-6 FPGA memory controller + * + * + * The controller's interface is via FIFO buffers - one for address and control + * the other is for data. The data FIFO interface is 128-bits wide. + * + * This module has a cache with different aspects on each port. As we're to + * ultimately interface to a 32-bit wide Wishbone bus, one side is 32-bits + * and the other is 128-bits wide to accommodate the DDR2 controller's data + * path. + * + * At present, the cache controller doesn't employ associativity, so any + * line can be used for any location. A round-robin approach to line + * use is employed. TODO is LRU scheme instead of round robin. + * + * The cache is a macro generated by Xilinx's IP generation tool. This is + * because memories with dual-aspect ratios cannot be inferred via HDL. + * + * The size of lines, as set by the defines, controls how long each read + * and write burst to/from the SDRAM is. + * + * The control and data FIFOS of the DDR2 interface are asynchronous to the DDR2 bus, + * so they are clocked with the same clock as the Wisbone interface (i.e. wb_clk) +*/ +module xilinx_ddr2_if ( + input [31:0] wb_adr_i, + input wb_stb_i, + input wb_cyc_i, + input [2:0] wb_cti_i, + input [1:0] wb_bte_i, + input wb_we_i, + input [3:0] wb_sel_i, + input [31:0] wb_dat_i, + output [31:0] wb_dat_o, + output reg wb_ack_o, + + output [12:0] ddr2_a, + output [2:0] ddr2_ba, + output ddr2_ras_n, + output ddr2_cas_n, + output ddr2_we_n, + output ddr2_rzq, + output ddr2_zio, + output ddr2_odt, + output ddr2_cke, + output ddr2_dm, + output ddr2_udm, + + inout [15:0] ddr2_dq, + inout ddr2_dqs, + inout ddr2_dqs_n, + inout ddr2_udqs, + inout ddr2_udqs_n, + output ddr2_ck, + output ddr2_ck_n, + + input ddr2_if_clk, + input ddr2_if_rst, + input idly_clk_100, + input wb_clk, + input wb_rst); + +`include "xilinx_ddr2_params.v" + + // Define to add a counter, signaling error if the controller locks up + // (no ack after a certain period of time) + //`define ERR_COUNTER + +/* +`define DDR2_CACHE_NUM_LINES 16 +`define DDR2_CACHE_NUM_LINES_ENC_WIDTH 4 // log2(`DDR2_CACHE_NUM_LINES) + */ +`define DDR2_CACHE_NUM_LINES 4 +`define DDR2_CACHE_NUM_LINES_ENC_WIDTH 2 // log2(`DDR2_CACHE_NUM_LINES) + +`define DDR2_CACHE_NUM_WORDS_PER_LINE 256 +`define DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE 8 +`define DDR2_CACHE_TAG_ADDR_WIDTH (32-`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE-2) + +`define DDR2_CACHE_DDR2_SIDE_NUM_WORDS_PER_LINE (`DDR2_CACHE_NUM_WORDS_PER_LINE/4) +`define DDR2_CACHE_DDR2_SIDE_ADDR_WIDTH_NUM_WORDS_PER_LINE (`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE - 2) +`define DDR2_CACHE_DDR2_SIDE_ADDR_WIDTH (`DDR2_CACHE_NUM_LINES_ENC_WIDTH + `DDR2_CACHE_DDR2_SIDE_ADDR_WIDTH_NUM_WORDS_PER_LINE) + +`define DDR2_CACHE_TAG_BITS 31:(`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE+2) + + wire ddr2_clk; // DDR2 iface domain clock. + wire ddr2_rst; // reset from the ddr2 module + + wire wb_req; + reg wb_req_r; + reg wb_ack_o_r; + + wire wb_req_new; + reg wb_req_new_r; + + wire wb_req_addr_hit; + + wire cached_addr_valid; + + + wire [31:(32 -`DDR2_CACHE_TAG_ADDR_WIDTH)] cached_addr; + +// Spartan-6 MIG doesn't have any defines for the DDR2 burst length, +// only burst length for user data. +// Our user port is 128-bit +//`define DDR2_BURSTLENGTH_1 +//`define DDR2_BURSTLENGTH_2 +//`define DDR2_BURSTLENGTH_4 +//`define DDR2_BURSTLENGTH_8 +`define DDR2_BURSTLENGTH_16 + +`ifdef DDR2_BURSTLENGTH_1 + `define DDR2_BURST_DW128_ADDR_WIDTH 2 // = log2(burst of 1 128-bits = 4 words) + `define DDR2_ADDR_ALIGN 4 +`elsif DDR2_BURSTLENGTH_2 + `define DDR2_BURST_DW128_ADDR_WIDTH 3 // = log2(burst of 2 128-bits = 8 words) + `define DDR2_ADDR_ALIGN 5 +`elsif DDR2_BURSTLENGTH_4 + `define DDR2_BURST_DW128_ADDR_WIDTH 4 // = log2(burst of 4 128-bits = 16 words) + `define DDR2_ADDR_ALIGN 6 +`elsif DDR2_BURSTLENGTH_8 + `define DDR2_BURST_DW128_ADDR_WIDTH 5 // = log2(burst of 8 128-bits = 32 words) + `define DDR2_ADDR_ALIGN 7 +`elsif DDR2_BURSTLENGTH_16 + `define DDR2_BURST_DW128_ADDR_WIDTH 6 // = log2(burst of 16 128-bits = 64 words) + `define DDR2_ADDR_ALIGN 8 +`endif + + // This counts how many addresses we should write to the fifo - the number + // of discrete FIFO transactions. + reg [`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE-`DDR2_BURST_DW128_ADDR_WIDTH - 1:0] addr_counter; + + wire cache_write; + + wire cache_hit; + + wire wb_cache_en; + + reg do_writeback, do_writeback_r; + wire do_writeback_start, do_writeback_finished; + // Wire to indicate writing to data FIFO of MIG has completed + reg do_writeback_data_finished; + + // Wire to indicate that address FIFO of MIG should be written to to + // initiate memory accesses. + reg do_writeback_addresses, do_writeback_addresses_r; + + reg do_readfrom, do_readfrom_r; + wire do_readfrom_start, do_readfrom_finished; + wire doing_readfrom; + + reg do_af_write; + + reg do_writeback_ddr2_fifo_we; + reg ddr2_write_done; + reg [`DDR2_CACHE_DDR2_SIDE_ADDR_WIDTH_NUM_WORDS_PER_LINE - 1:0] ddr2_cache_line_word_addr; + wire [127:0] ddr2_cache_data_o; + reg rd_data_valid_r; + reg ddr2_read_done; + + // DDR2 MIG interface wires + wire ddr2_p0_cmd_en; + wire [30:0] ddr2_p0_cmd_byte_addr; + wire [2:0] ddr2_p0_cmd_instr; + wire ddr2_p0_cmd_full; + wire ddr2_p0_cmd_empty; + wire [5:0] ddr2_p0_cmd_bl; + wire ddr2_p0_wr_en; + wire [(C3_P0_DATA_PORT_SIZE)-1:0] ddr2_p0_wr_data; + wire [(C3_P0_MASK_SIZE)-1:0] ddr2_p0_wr_mask; + wire ddr2_p0_wr_full; + wire ddr2_p0_wr_empty; + wire [6:0] ddr2_p0_wr_count; + wire ddr2_p0_wr_underrun; + wire ddr2_p0_wr_error; + wire ddr2_p0_rd_en; + wire [(C3_P0_DATA_PORT_SIZE)-1:0] ddr2_p0_rd_data; + wire ddr2_p0_rd_full; + wire ddr2_p0_rd_empty; + wire [6:0] ddr2_p0_rd_count; + wire ddr2_p0_rd_overflow; + wire ddr2_p0_rd_error; + wire ddr2_calib_done; + + wire [30:0] readfrom_af_addr; + wire [30:0] writeback_af_addr; + + wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_validate; + wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_invalidate; + wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_addr_valid; + wire [`DDR2_CACHE_NUM_LINES - 1 :0] cache_line_hit; + wire [`DDR2_CACHE_TAG_BITS] cache_line_addr [0:`DDR2_CACHE_NUM_LINES-1] ; + + // Cache control signals + // Wishbone side + wire [`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE-1:0] wb_cache_adr; + wire [3:0] wb_cache_sel_we; + // DDR side + wire ddr2_cache_en; + wire [15:0] ddr2_cache_we; + + reg wb_bursting; // Indicate if burst is enabled + reg [3:0] wb_burst_addr; // Burst counter, up to 16 + wire [1:0] wb_burst_addr_4beat; + wire [2:0] wb_burst_addr_8beat; + wire wb_burst_addr_incr; + wire ack_err; + reg ack_err_r; + + + // Synchronisation signals + reg sync, sync_r; + wire sync_start; + wire sync_done; + + // Decoded select line + wire [`DDR2_CACHE_NUM_LINES-1:0] selected_cache_line; + wire [`DDR2_CACHE_NUM_LINES_ENC_WIDTH-1:0] selected_cache_line_enc; + + genvar i; + generate + for (i=0;i<`DDR2_CACHE_NUM_LINES;i=i+1) begin : cache_addr + xilinx_ddr2_wb_if_cache_adr_reg cache_addr_reg_inst + ( .adr_i(wb_adr_i[`DDR2_CACHE_TAG_BITS]), + .validate(cache_line_addr_validate[i]), + .invalidate(cache_line_addr_invalidate[i]), + .cache_hit(cache_line_hit[i]), + .adr_valid(cache_line_addr_valid[i]), + .cached_adr_o(cache_line_addr[i]), + .clk(wb_clk), + .rst(wb_rst)); + end + endgenerate + + wire start_writeback, start_fill; + + xilinx_ddr2_wb_if_cache_control xilinx_ddr2_wb_if_cache_control0 + ( + // Outputs + .start_writeback (start_writeback), + .start_fill (start_fill), + .cache_line_validate (cache_line_addr_validate), + .cache_line_invalidate (cache_line_addr_invalidate), + .selected_cache_line (selected_cache_line), + .selected_cache_line_enc (selected_cache_line_enc), + .sync_done (sync_done), + // Inputs + .cache_line_addr_valid (cache_line_addr_valid), + .cache_line_addr_hit (cache_line_hit), + .wb_req (wb_req), + .cache_write (cache_write), + .writeback_done (do_writeback_finished), + .fill_done (do_readfrom_finished), + .sync_start (sync_start), + .wb_clk (wb_clk), + .wb_rst (wb_rst)); + + defparam xilinx_ddr2_wb_if_cache_control0.num_lines = `DDR2_CACHE_NUM_LINES; + defparam xilinx_ddr2_wb_if_cache_control0.num_lines_log2 = `DDR2_CACHE_NUM_LINES_ENC_WIDTH; + + assign cached_addr = selected_cache_line[0] ? cache_line_addr[0] : + selected_cache_line[1] ? cache_line_addr[1] : + selected_cache_line[2] ? cache_line_addr[2] : + selected_cache_line[3] ? cache_line_addr[3] : 0; + + assign cache_write = wb_req & wb_we_i & wb_ack_o; + + assign cache_hit = |(selected_cache_line & cache_line_hit); + + assign cached_addr_valid = |(selected_cache_line & cache_line_addr_valid); + + assign wb_req_addr_hit = (wb_req & cache_hit & cached_addr_valid); + + // Wishbone request detection + assign wb_req = wb_stb_i & wb_cyc_i & ddr2_calib_done & !sync; + + always @(posedge wb_clk) + wb_req_r <= wb_req; + + assign wb_req_new = wb_req & !wb_req_r; + + always @(posedge wb_clk) + wb_req_new_r <= wb_req_new; + + always @(posedge wb_clk) + if (wb_rst) + wb_bursting <= 0; + // Reset if acking end of transfer + else if (wb_ack_o && wb_cti_i == 3'b111) + wb_bursting <= 0; + // Set if beginning new transaction and incrementing burst indicated + // TODO - double check if this burst is going to go over a cache line + // boundary - if so don't allow burst, fall back to classic cycles. + else if (wb_req_new) + wb_bursting <= (wb_cti_i == 3'b010); + + // Help constrain additions to appropriate bit-width for wrapping + assign wb_burst_addr_4beat = wb_adr_i[3:2] + 1; + assign wb_burst_addr_8beat = wb_adr_i[4:2] + 1; + + // Increment burst address whenever we get a hit when reading, or + // when acking and writing. + assign wb_burst_addr_incr = (wb_req_addr_hit & (!wb_we_i | + (wb_we_i & wb_ack_o))); + + // Calculate burst address depending on burst type indicator + always @(posedge wb_clk) + if (wb_rst) + wb_burst_addr <= 0; + else if (wb_req_new) + // When we have a bursting read to an address which is in cache then + // initialise the address to the next word in the burst sequence. + // If it's a miss, or it's a write, then we just take what's on the + // bus. + wb_burst_addr <= !(wb_req_addr_hit & !wb_we_i) ? wb_adr_i[5:2] : + wb_bte_i==2'b01 ? {wb_adr_i[5:4], wb_burst_addr_4beat }: + wb_bte_i==2'b10 ? {wb_adr_i[5], wb_burst_addr_8beat }: + wb_bte_i==2'b11 ? wb_adr_i[5:2] + 1 : + wb_adr_i[5:2]; + else if (wb_burst_addr_incr & wb_bte_i==2'b01) + wb_burst_addr[1:0] <= wb_burst_addr[1:0] + 1; + else if (wb_burst_addr_incr & wb_bte_i==2'b10) + wb_burst_addr[2:0] <= wb_burst_addr[2:0] + 1; + else if (wb_burst_addr_incr & wb_bte_i==2'b11) + wb_burst_addr[3:0] <= wb_burst_addr[3:0] + 1; + +`ifdef ERR_COUNTER + reg [26:0] ack_err_cntr; + + always @(posedge wb_clk) + if (wb_rst) + ack_err_cntr <= 0; + else if (!wb_req) + ack_err_cntr <= 0; + else if (|ack_err_cntr) + ack_err_cntr <= ack_err_cntr + 1; + else if (wb_req_new & !(|ack_err_cntr)) + ack_err_cntr <= 1; + + assign ack_err = (&ack_err_cntr); + + always @(posedge wb_clk) + ack_err_r <= ack_err; + + assign wb_err_o = ack_err_r; + +`else // !`ifdef ERR_COUNTER + + assign ack_err = 0; + always @(posedge wb_clk) + ack_err_r <= 0; + + assign wb_err_o = 0; + +`endif + + always @(posedge wb_clk) + if (wb_rst) + wb_ack_o <= 0; + else + wb_ack_o <= wb_req_addr_hit & + ( + // Simple acks on classic cycles + (!wb_bursting && !wb_ack_o && !wb_ack_o_r) + // De-assert ack when we see the final transaction + || (wb_bursting && !(wb_cti_i==3'b111)) + ); + + always @(posedge wb_clk) + wb_ack_o_r <= wb_ack_o; + + // Logic controling synchronisation + always @(posedge wb_clk) + if (wb_rst) + sync <= 0; + else if (sync_done) // Sync. done indicator from cache controller + sync <= 0; + + always @(posedge wb_clk) + sync_r <= sync; + + assign sync_start = sync & !sync_r; + + task do_sync; + begin + // Wait for us to not be doing a transaction. + while(wb_req) + @wb_clk; + // Cache not busy, initiate sync. + sync = 1; + end + endtask // do_sync + + // Writeback/readfrom lower address generation + always @(posedge wb_clk) + if (wb_rst) + addr_counter <= 0; + else if (ddr2_p0_cmd_en) + addr_counter <= addr_counter+1; + + // Determine if we're writing access requests into DDR2 interface AF + always @(posedge wb_clk) + if (wb_rst) + do_af_write <= 0; + else if (do_readfrom_start | do_writeback_data_finished) + do_af_write <= 1; + else if ((&addr_counter) & !ddr2_p0_cmd_full) // Stop when counter rolls over + do_af_write <= 0; + + // Wishbone side of cache enable. Always enabled unless doing DDR2-side + // things (fill or writeback). + assign wb_cache_en = !(do_readfrom | do_writeback); + + + // Writeback detect logic + always @(posedge wb_clk) + if (wb_rst) + do_writeback <= 0; + else if (start_writeback) + do_writeback <= 1; + else if (&ddr2_cache_line_word_addr) + do_writeback <= 0; + + always @(posedge wb_clk) + do_writeback_r <= do_writeback; + + // Detect falling edge of do_writeback + always @(posedge wb_clk) + do_writeback_data_finished <= !do_writeback & do_writeback_r; + + always @(posedge wb_clk) + if (wb_rst) + do_writeback_addresses <= 0; + else if (do_writeback_data_finished) + do_writeback_addresses <= 1; + else if ((&addr_counter) & !ddr2_p0_cmd_full) + do_writeback_addresses <= 0; + + always @(posedge wb_clk) + do_writeback_addresses_r <= do_writeback_addresses; + + // Detect rising edge of do_writeback + assign do_writeback_start = do_writeback & !do_writeback_r; + // Detect falling edge of address writing control signal + assign do_writeback_finished = !do_writeback_addresses & + do_writeback_addresses_r; + + // DDR2 Read detect logic + always @(posedge wb_clk) + if (wb_rst) + do_readfrom <= 0; + else if (start_fill) + do_readfrom <= 1; + else if ((&ddr2_cache_line_word_addr)) + do_readfrom <= 0; + + always @(posedge wb_clk) + do_readfrom_r <= do_readfrom; + + // Detect line fill request rising edge + assign do_readfrom_start = do_readfrom & !do_readfrom_r; + // Detect line fill request falling edge + assign do_readfrom_finished = !do_readfrom & do_readfrom_r; + assign doing_readfrom = do_readfrom | do_readfrom_r; + + // Address fifo signals + assign ddr2_p0_cmd_en = ((do_readfrom_r & ddr2_p0_wr_empty) | (do_writeback_addresses_r & !ddr2_p0_wr_empty)) & + !ddr2_p0_cmd_full & do_af_write; + assign ddr2_p0_cmd_instr[0] = doing_readfrom; // 1 - read, 0 - write + assign ddr2_p0_cmd_instr[2:1] = 0; + + assign writeback_af_addr = {cached_addr, addr_counter, `DDR2_ADDR_ALIGN'd0}; + + assign readfrom_af_addr = {wb_adr_i[`DDR2_CACHE_TAG_BITS], addr_counter, `DDR2_ADDR_ALIGN'd0}; + + assign ddr2_p0_cmd_byte_addr = doing_readfrom ? readfrom_af_addr : writeback_af_addr; + assign ddr2_p0_wr_en = do_writeback_ddr2_fifo_we; + assign ddr2_p0_wr_data = ddr2_cache_data_o; + assign ddr2_p0_wr_mask = 0; + + always @(posedge wb_clk) + if (wb_rst) + ddr2_cache_line_word_addr <= 0; + else if (!ddr2_p0_rd_empty | (do_writeback & !ddr2_p0_wr_full)) + ddr2_cache_line_word_addr <= ddr2_cache_line_word_addr + 1; + else if (ddr2_write_done | ddr2_read_done) + ddr2_cache_line_word_addr <= 0; + + always @(posedge wb_clk) + do_writeback_ddr2_fifo_we <= (do_writeback & !ddr2_p0_wr_full); + + always @(posedge wb_clk) + if (wb_rst) + ddr2_write_done <= 0; + else if ((&ddr2_cache_line_word_addr) & do_writeback) + ddr2_write_done <= 1; + else if (!do_writeback) // sample WB domain + ddr2_write_done <= 0; + + always @(posedge wb_clk) + rd_data_valid_r <= !ddr2_p0_rd_empty; + + // Read done signaling to WB domain + always @(posedge wb_clk) + if (wb_rst) + ddr2_read_done <= 0; + else if (rd_data_valid_r & (&ddr2_cache_line_word_addr)) + ddr2_read_done <= 1; + else if (!do_readfrom) // Read WB domain + ddr2_read_done <= 0; + + // Lower word address uses potentially bursting address counter + assign wb_cache_adr = wb_bursting ? + {wb_adr_i[(`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE+2)-1:6],wb_burst_addr}: + wb_adr_i[(`DDR2_CACHE_ADDR_WIDTH_WORDS_PER_LINE+2)-1:2]; + + assign wb_cache_sel_we = {4{wb_we_i & wb_ack_o}} & wb_sel_i; + assign ddr2_cache_en = (!ddr2_p0_rd_empty |do_writeback); + assign ddr2_cache_we = {16{!ddr2_p0_rd_empty}}; + + // Read enable always on + assign ddr2_p0_rd_en = 1'b1; + +`ifdef DDR2_BURSTLENGTH_1 + assign ddr2_p0_cmd_bl = 0; // burst of 1 * 128-bit +`elsif DDR2_BURSTLENGTH_2 + assign ddr2_p0_cmd_bl = 1; // burst of 2 * 128-bit +`elsif DDR2_BURSTLENGTH_4 + assign ddr2_p0_cmd_bl = 3; // burst of 4 * 128-bit +`elsif DDR2_BURSTLENGTH_8 + assign ddr2_p0_cmd_bl = 7; // burst of 8 * 128-bit +`elsif DDR2_BURSTLENGTH_16 + assign ddr2_p0_cmd_bl = 15; // burst of 16 * 128-bit +`endif + + // Xilinx Coregen true dual-port RAMB + // Wishbone side : 32-bit + // DDR2 side : 128-bit + xilinx_ddr2_if_cache cache_mem0 + ( + // Wishbone side + .clka(wb_clk), + .ena(wb_cache_en), + .wea(wb_cache_sel_we), + .addra({2'd0, selected_cache_line_enc,wb_cache_adr}), + .dina(wb_dat_i), + .douta(wb_dat_o), + + // DDR2 controller side + .clkb(wb_clk), + .enb(ddr2_cache_en), + .web(ddr2_cache_we), + .addrb({2'd0, selected_cache_line_enc, + ddr2_cache_line_word_addr}), + .dinb(ddr2_p0_rd_data), + .doutb(ddr2_cache_data_o)); + + ddr2_mig # + ( + .C3_P0_MASK_SIZE (C3_P0_MASK_SIZE), + .C3_P0_DATA_PORT_SIZE (C3_P0_DATA_PORT_SIZE), + .DEBUG_EN (DEBUG_EN), + .C3_MEMCLK_PERIOD (C3_MEMCLK_PERIOD), + .C3_CALIB_SOFT_IP (C3_CALIB_SOFT_IP), + .C3_SIMULATION (C3_SIMULATION), + .C3_RST_ACT_LOW (C3_RST_ACT_LOW), + .C3_INPUT_CLK_TYPE (C3_INPUT_CLK_TYPE), + .C3_MEM_ADDR_ORDER (C3_MEM_ADDR_ORDER), + .C3_NUM_DQ_PINS (C3_NUM_DQ_PINS), + .C3_MEM_ADDR_WIDTH (C3_MEM_ADDR_WIDTH), + .C3_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH) + ) + ddr2_mig + ( + + .mcb3_dram_dq (ddr2_dq), + .mcb3_dram_a (ddr2_a), + .mcb3_dram_ba (ddr2_ba), + .mcb3_dram_ras_n (ddr2_ras_n), + .mcb3_dram_cas_n (ddr2_cas_n), + .mcb3_dram_we_n (ddr2_we_n), + .mcb3_dram_odt (ddr2_odt), + .mcb3_dram_cke (ddr2_cke), + .mcb3_dram_dm (ddr2_dm), + .mcb3_dram_udqs (ddr2_udqs), + .mcb3_dram_udqs_n (ddr2_udqs_n), + .mcb3_rzq (ddr2_rzq), + .mcb3_zio (ddr2_zio), + .mcb3_dram_udm (ddr2_udm), + .c3_sys_clk (ddr2_if_clk), + .c3_sys_rst_n (ddr2_if_rst), + .c3_calib_done (ddr2_calib_done), + .c3_clk0 (ddr2_clk), + .c3_rst0 (ddr2_rst), + .mcb3_dram_dqs (ddr2_dqs), + .mcb3_dram_dqs_n (ddr2_dqs_n), + .mcb3_dram_ck (ddr2_ck), + .mcb3_dram_ck_n (ddr2_ck_n), + .c3_p0_cmd_clk (wb_clk), + .c3_p0_cmd_en (ddr2_p0_cmd_en), + .c3_p0_cmd_instr (ddr2_p0_cmd_instr), + .c3_p0_cmd_bl (ddr2_p0_cmd_bl), + .c3_p0_cmd_byte_addr (ddr2_p0_cmd_byte_addr[29:0]), + .c3_p0_cmd_empty (ddr2_p0_cmd_empty), + .c3_p0_cmd_full (ddr2_p0_cmd_full), + .c3_p0_wr_clk (wb_clk), + .c3_p0_wr_en (ddr2_p0_wr_en), + .c3_p0_wr_mask (ddr2_p0_wr_mask), + .c3_p0_wr_data (ddr2_p0_wr_data), + .c3_p0_wr_full (ddr2_p0_wr_full), + .c3_p0_wr_empty (ddr2_p0_wr_empty), + .c3_p0_wr_count (ddr2_p0_wr_count), + .c3_p0_wr_underrun (ddr2_p0_wr_underrun), + .c3_p0_wr_error (ddr2_p0_wr_error), + .c3_p0_rd_clk (wb_clk), + .c3_p0_rd_en (ddr2_p0_rd_en), + .c3_p0_rd_data (ddr2_p0_rd_data), + .c3_p0_rd_full (ddr2_p0_rd_full), + .c3_p0_rd_empty (ddr2_p0_rd_empty), + .c3_p0_rd_count (ddr2_p0_rd_count), + .c3_p0_rd_overflow (ddr2_p0_rd_overflow), + .c3_p0_rd_error (ddr2_p0_rd_error) + ); + +endmodule // xilinx_ddr2_if2 + +// Local Variables: +// verilog-library-directories:("." "ddr2_mig") +// verilog-library-extensions:(".v" ".h") +// End: + + +module xilinx_ddr2_wb_if_cache_adr_reg + (adr_i, validate, invalidate, + cached_adr_o, cache_hit, adr_valid, + clk, rst); + + parameter full_adr_width = 32; + parameter word_adr_width = 2; // 4 bytes per word + parameter line_adr_width = 8; // 256 words per "line" + + parameter tag_width = full_adr_width - line_adr_width - word_adr_width; + + + input [full_adr_width-1: word_adr_width + line_adr_width] adr_i; + input validate; + input invalidate; + output [full_adr_width-1: word_adr_width + line_adr_width] cached_adr_o; + output cache_hit; + output reg adr_valid; + + input clk, rst; + + reg [tag_width-1:0] cached_adr; + + assign cached_adr_o = cached_adr; + + always @(posedge clk) + if (rst) + cached_adr <= 0; + else if (validate) + cached_adr <= adr_i; + + always @(posedge clk) + if (rst) + adr_valid <= 0; + else if (validate) + adr_valid <= 1; + else if (invalidate) + adr_valid <= 0; + + assign cache_hit = (adr_i == cached_adr); + +endmodule // xilinx_ddr2_wb_if_cache_adr_reg + +module xilinx_ddr2_wb_if_cache_control + ( cache_line_addr_valid, cache_line_addr_hit, + wb_req, + cache_write, + writeback_done, fill_done, + sync_start, sync_done, + start_writeback, start_fill, + cache_line_validate, cache_line_invalidate, + selected_cache_line, selected_cache_line_enc, + wb_clk, wb_rst); + + parameter num_lines = 16; + parameter num_lines_log2 = 4; + + input [num_lines-1:0] cache_line_addr_valid; + input [num_lines-1:0] cache_line_addr_hit; + + input wb_req; + input cache_write; + input writeback_done, fill_done; + + input sync_start; + output sync_done; + + output reg start_writeback; + output reg start_fill; + output reg [num_lines-1:0] cache_line_validate; + output reg [num_lines-1:0] cache_line_invalidate; + + output [num_lines-1:0] selected_cache_line; + output reg [num_lines_log2-1:0] selected_cache_line_enc; + + input wb_clk, wb_rst; + + reg [num_lines-1:0] lines_dirty; + + reg [num_lines-1:0] selected_cache_line_from_miss; + + reg selected_cache_line_new; + + reg invalidate_clean_line; + + reg [num_lines-1:0] selected_cache_line_r; + reg [num_lines-1:0] selected_cache_line_r2; + + reg wb_req_r; + + wire wb_req_new; + reg wb_req_new_r; + + parameter sync_line_check_wait = 4; + reg [num_lines-1:0] sync_line_counter; + reg sync_doing; + reg [sync_line_check_wait-1:0] sync_line_select_wait_counter_shr; + reg sync_line_done; + wire sync_writeback_line; + + + always @(posedge wb_clk) + wb_req_r <= wb_req; + + assign wb_req_new = wb_req & !wb_req_r; + + always @(posedge wb_clk) + wb_req_new_r <= wb_req_new; + + // Select a cache line when we miss. Currently very simply is round robin + always @(posedge wb_clk) + if (wb_rst) + selected_cache_line_from_miss <= 1; + else if (wb_req_new_r & !(|selected_cache_line_r)) // miss,no line selected + // Shift select bit one + selected_cache_line_from_miss + <= {selected_cache_line_from_miss[num_lines-2:0], + selected_cache_line_from_miss[num_lines-1]}; + + + // Line selection logic, when line address is valid and hit, we select + always @(posedge wb_clk) + if (wb_rst) + selected_cache_line_r <= 0; + else if (wb_req_new) + selected_cache_line_r <= cache_line_addr_valid & cache_line_addr_hit; + else if (wb_req_new_r & !(|selected_cache_line_r)) + selected_cache_line_r <= selected_cache_line_from_miss; + else if (sync_doing) + selected_cache_line_r <= sync_line_counter; + + always @(posedge wb_clk) + selected_cache_line_r2 <= selected_cache_line_r; + + assign selected_cache_line = selected_cache_line_r2; + + // A new line of cache has been selected + always @(posedge wb_clk) + if (wb_rst) + selected_cache_line_new <= 0; + else if (wb_req_new & (&(cache_line_addr_valid & cache_line_addr_hit))) + // New line address selected + selected_cache_line_new <= 1; + else if ((!selected_cache_line_new) & wb_req_new_r) + // Didn't select one last time, so we must have forced ourselves to + // select a new one + selected_cache_line_new <= 1; + else if (selected_cache_line_new) + selected_cache_line_new <= 0; + + always @(posedge wb_clk) + if (wb_rst) + lines_dirty <= 0; + else if (cache_write) + lines_dirty <= lines_dirty | selected_cache_line_r; + else if (writeback_done) + lines_dirty <= lines_dirty & ~(selected_cache_line_r); + + // Validate the cache line address in the register when line filled + always @(posedge wb_clk) + if (wb_rst) + cache_line_validate <= 0; + else if (fill_done) + cache_line_validate <= selected_cache_line_r; + else if (|cache_line_validate) + cache_line_validate <= 0; + + // Invalidate the cache line address in the register when line written back + always @(posedge wb_clk) + if (wb_rst) + cache_line_invalidate <= 0; + else if ((writeback_done & !sync_doing) | invalidate_clean_line) + cache_line_invalidate <= selected_cache_line_r; + else if (|cache_line_invalidate) + cache_line_invalidate <= 0; + + // Initiate-writeback logic + always @(posedge wb_clk) + if (wb_rst) + start_writeback <= 0; + else if (start_writeback) + start_writeback <= 0; + else if (selected_cache_line_new & + (|(lines_dirty & selected_cache_line_r)) & + (|(selected_cache_line_r & cache_line_addr_valid)) & + !(|(cache_line_addr_hit & selected_cache_line_r))) + start_writeback <= 1; + else if (sync_writeback_line) + start_writeback <= 1; + + // Invalidate lines which we haven't written to so we can fill them + always @(posedge wb_clk) + if (wb_rst) + invalidate_clean_line <= 0; + else if (invalidate_clean_line) + invalidate_clean_line <= 0; + else if ((selected_cache_line_new) & // New line selected + !(|(lines_dirty & selected_cache_line_r)) & // It's not dirty + // It's valid, but we've selected it so we're trashing it + (|(selected_cache_line_r & cache_line_addr_valid)) & + !(|(cache_line_addr_hit & selected_cache_line_r))) // Not a hit + invalidate_clean_line <= 1; + + reg invalidate_clean_line_r; + always @(posedge wb_clk) + invalidate_clean_line_r <= invalidate_clean_line; + + + // Initiate-fill logic + always @(posedge wb_clk) + if (wb_rst) + start_fill <= 0; + else if (((selected_cache_line_new) & // New line selected + // not valid + !(|(cache_line_addr_valid & selected_cache_line_r))) | + (writeback_done & !sync_doing) | invalidate_clean_line_r + ) + start_fill <= 1; + else if (start_fill) + start_fill <= 0; + + // Hardcoded to 4 lines currently. + always @(posedge wb_clk) + if (selected_cache_line_r[0]) + selected_cache_line_enc <= 0; + else if (selected_cache_line_r[1]) + selected_cache_line_enc <= 1; + else if (selected_cache_line_r[2]) + selected_cache_line_enc <= 2; + else if (selected_cache_line_r[3]) + selected_cache_line_enc <= 3; + + + // Synchronisation control + + always @(posedge wb_clk) + if (wb_rst) + sync_doing <= 0; + else if (sync_start) + sync_doing <= 1; + else if (sync_done) + sync_doing <= 0; + + always @(posedge wb_clk) + if (wb_rst) + sync_line_counter <= 0; + else if (sync_start) + // Set first line to check + sync_line_counter[0] <= 1'b1; + else if (sync_line_done) + // Shift along, check next line + sync_line_counter <= {sync_line_counter[num_lines-2:0], 1'b0}; + + // Pulse this on finishing of checking lines + assign sync_done = sync_line_counter[num_lines-1] & sync_line_done; + + // Pulses when a dirty line is detected and should be written back. + assign sync_writeback_line = sync_doing & + sync_line_select_wait_counter_shr[0] & + cache_line_addr_valid & + |(sync_line_counter & lines_dirty); + + always @(posedge wb_clk) + if (wb_rst) + sync_line_select_wait_counter_shr <= 0; + else if (|sync_line_select_wait_counter_shr) + sync_line_select_wait_counter_shr + <= {1'b0,sync_line_select_wait_counter_shr[sync_line_check_wait-1:1]}; + else if (sync_start | (sync_line_done & !sync_done)) + sync_line_select_wait_counter_shr[sync_line_check_wait-1] <= 1'b1; + + always @(posedge wb_clk) + if (wb_rst) + sync_line_done <= 1'b0; + else if (sync_line_done) + sync_line_done <= 1'b0; + // Either line doesn't need writeback + else if (sync_line_select_wait_counter_shr[0] & !sync_writeback_line) + sync_line_done <= 1'b1; + // Or writeback finished + else if (writeback_done & sync_doing) + sync_line_done <= 1'b1; + + +endmodule // xilinx_ddr2_wb_if_cache_control Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v (revision 627) @@ -0,0 +1,283 @@ +//***************************************************************************** +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: mcb_soft_calibration_top.v +// /___/ /\ Date Last Modified: $Date: 2010/10/27 17:40:12 $ +// \ \ / \ Date Created: Mon Feb 9 2009 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: Xilinx reference design top-level simulation +// wrapper file for input termination calibration +//Reference: +// +// Revision: Date: Comment +// 1.0: 2/06/09: Initial version for MIG wrapper. +// 1.1: 3/16/09: Added pll_lock port, for using it to gate reset +// 1.2: 6/06/09: Removed MCB_UIDQCOUNT. +// 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port +// 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets +// 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration +// 1.6: 02/04/09: Added condition generate statmenet for ZIO pin. +// 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait . +// +// End Revision +//********************************************************************************** + +`timescale 1ps/1ps + +module mcb_soft_calibration_top # ( + parameter C_MEM_TZQINIT_MAXCNT = 10'h512, // DDR3 Minimum delay between resets + parameter C_MC_CALIBRATION_MODE = "CALIBRATION", // if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values, and does dynamic recal, + // if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* no dynamic recal will be done + parameter SKIP_IN_TERM_CAL = 1'b0, // provides option to skip the input termination calibration + parameter SKIP_DYNAMIC_CAL = 1'b0, // provides option to skip the dynamic delay calibration + parameter SKIP_DYN_IN_TERM = 1'b0, // provides option to skip the input termination calibration + parameter C_SIMULATION = "FALSE", // Tells us whether the design is being simulated or implemented + parameter C_MEM_TYPE = "DDR" // provides the memory device used for the design + ) + ( + input wire UI_CLK, // Input - global clock to be used for input_term_tuner and IODRP clock + input wire RST, // Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for IODRP (sub)controller + input wire IOCLK, // Input - IOCLK input to the IODRP's + output wire DONE_SOFTANDHARD_CAL, // active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete) + input wire PLL_LOCK, // Lock signal from PLL + input wire SELFREFRESH_REQ, + input wire SELFREFRESH_MCB_MODE, + output wire SELFREFRESH_MCB_REQ , + output wire SELFREFRESH_MODE, + + + + + output wire MCB_UIADD, // to MCB's UIADD port + output wire MCB_UISDI, // to MCB's UISDI port + input wire MCB_UOSDO, + input wire MCB_UODONECAL, + input wire MCB_UOREFRSHFLAG, + output wire MCB_UICS, + output wire MCB_UIDRPUPDATE, + output wire MCB_UIBROADCAST, + output wire [4:0] MCB_UIADDR, + output wire MCB_UICMDEN, + output wire MCB_UIDONECAL, + output wire MCB_UIDQLOWERDEC, + output wire MCB_UIDQLOWERINC, + output wire MCB_UIDQUPPERDEC, + output wire MCB_UIDQUPPERINC, + output wire MCB_UILDQSDEC, + output wire MCB_UILDQSINC, + output wire MCB_UIREAD, + output wire MCB_UIUDQSDEC, + output wire MCB_UIUDQSINC, + output wire MCB_RECAL, + output wire MCB_SYSRST, + output wire MCB_UICMD, + output wire MCB_UICMDIN, + output wire [3:0] MCB_UIDQCOUNT, + input wire [7:0] MCB_UODATA, + input wire MCB_UODATAVALID, + input wire MCB_UOCMDREADY, + input wire MCB_UO_CAL_START, + + inout wire RZQ_Pin, + inout wire ZIO_Pin, + output wire CKE_Train + + ); + + wire IODRP_ADD; + wire IODRP_SDI; + wire RZQ_IODRP_SDO; + wire RZQ_IODRP_CS; + wire ZIO_IODRP_SDO; + wire ZIO_IODRP_CS; + wire IODRP_SDO; + wire IODRP_CS; + wire IODRP_BKST; + wire RZQ_ZIO_ODATAIN; + wire RZQ_ZIO_TRISTATE; + wire RZQ_TOUT; + wire ZIO_TOUT; + wire [7:0] Max_Value; + + assign RZQ_ZIO_ODATAIN = ~RST; + assign RZQ_ZIO_TRISTATE = ~RST; + assign IODRP_BKST = 1'b0; //future hook for possible BKST to ZIO and RZQ + + +mcb_soft_calibration #( + .C_MEM_TZQINIT_MAXCNT (C_MEM_TZQINIT_MAXCNT), + .C_MC_CALIBRATION_MODE(C_MC_CALIBRATION_MODE), + .SKIP_IN_TERM_CAL (SKIP_IN_TERM_CAL), + .SKIP_DYNAMIC_CAL (SKIP_DYNAMIC_CAL), + .SKIP_DYN_IN_TERM (SKIP_DYN_IN_TERM), + .C_SIMULATION (C_SIMULATION), + .C_MEM_TYPE (C_MEM_TYPE) + ) +mcb_soft_calibration_inst ( + .UI_CLK (UI_CLK), // main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB CLK pins + .RST (RST), // main system reset for both this Soft Calibration block - also will act as a passthrough to MCB's SYSRST + .PLL_LOCK (PLL_LOCK), //lock signal from PLL + .SELFREFRESH_REQ (SELFREFRESH_REQ), + .SELFREFRESH_MCB_MODE (SELFREFRESH_MCB_MODE), + .SELFREFRESH_MCB_REQ (SELFREFRESH_MCB_REQ ), + .SELFREFRESH_MODE (SELFREFRESH_MODE), + + .DONE_SOFTANDHARD_CAL (DONE_SOFTANDHARD_CAL),// active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete) .IODRP_ADD(IODRP_ADD), // RZQ and ZIO IODRP ADD port, and MCB's UIADD port + .IODRP_ADD (IODRP_ADD), // RZQ and ZIO IODRP ADD port + .IODRP_SDI (IODRP_SDI), // RZQ and ZIO IODRP SDI port, and MCB's UISDI port + .RZQ_IN (RZQ_IN), // RZQ pin from board - expected to have a 2*R resistor to ground + .RZQ_IODRP_SDO (RZQ_IODRP_SDO), // RZQ IODRP's SDO port + .RZQ_IODRP_CS (RZQ_IODRP_CS), // RZQ IODRP's CS port + .ZIO_IN (ZIO_IN), // Z-stated IO pin - garanteed not to be driven externally + .ZIO_IODRP_SDO (ZIO_IODRP_SDO), // ZIO IODRP's SDO port + .ZIO_IODRP_CS (ZIO_IODRP_CS), // ZIO IODRP's CS port + .MCB_UIADD (MCB_UIADD), // to MCB's UIADD port + .MCB_UISDI (MCB_UISDI), // to MCB's UISDI port + .MCB_UOSDO (MCB_UOSDO), // from MCB's UOSDO port (User output SDO) + .MCB_UODONECAL (MCB_UODONECAL), // indicates when MCB hard calibration process is complete + .MCB_UOREFRSHFLAG (MCB_UOREFRSHFLAG), //high during refresh cycle and time when MCB is innactive + .MCB_UICS (MCB_UICS), // to MCB's UICS port (User Input CS) + .MCB_UIDRPUPDATE (MCB_UIDRPUPDATE), // MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used during IODRP2_MCB writes). Currently just trasnparent + .MCB_UIBROADCAST (MCB_UIBROADCAST), // to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) + .MCB_UIADDR (MCB_UIADDR), //to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port + .MCB_UICMDEN (MCB_UICMDEN), //set to take control of UI interface - removes control from internal calib block + .MCB_UIDONECAL (MCB_UIDONECAL), + .MCB_UIDQLOWERDEC (MCB_UIDQLOWERDEC), + .MCB_UIDQLOWERINC (MCB_UIDQLOWERINC), + .MCB_UIDQUPPERDEC (MCB_UIDQUPPERDEC), + .MCB_UIDQUPPERINC (MCB_UIDQUPPERINC), + .MCB_UILDQSDEC (MCB_UILDQSDEC), + .MCB_UILDQSINC (MCB_UILDQSINC), + .MCB_UIREAD (MCB_UIREAD), //enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. + .MCB_UIUDQSDEC (MCB_UIUDQSDEC), + .MCB_UIUDQSINC (MCB_UIUDQSINC), + .MCB_RECAL (MCB_RECAL), //when high initiates a hard re-calibration sequence + .MCB_UICMD (MCB_UICMD ), + .MCB_UICMDIN (MCB_UICMDIN ), + .MCB_UIDQCOUNT (MCB_UIDQCOUNT ), + .MCB_UODATA (MCB_UODATA ), + .MCB_UODATAVALID (MCB_UODATAVALID ), + .MCB_UOCMDREADY (MCB_UOCMDREADY ), + .MCB_UO_CAL_START (MCB_UO_CAL_START), + .MCB_SYSRST (MCB_SYSRST ), //drives the MCB's SYSRST pin - the main reset for MCB + .Max_Value (Max_Value ), // Maximum Tap Value from calibrated IOI + .CKE_Train (CKE_Train) +); + + +IOBUF IOBUF_RZQ ( + .O (RZQ_IN), + .IO (RZQ_Pin), + .I (RZQ_OUT), + .T (RZQ_TOUT) + ); + +IODRP2 IODRP2_RZQ ( + .DATAOUT(), + .DATAOUT2(), + .DOUT(RZQ_OUT), + .SDO(RZQ_IODRP_SDO), + .TOUT(RZQ_TOUT), + .ADD(IODRP_ADD), + .BKST(IODRP_BKST), + .CLK(UI_CLK), + .CS(RZQ_IODRP_CS), + .IDATAIN(RZQ_IN), + .IOCLK0(IOCLK), + .IOCLK1(1'b1), + .ODATAIN(RZQ_ZIO_ODATAIN), + .SDI(IODRP_SDI), + .T(RZQ_ZIO_TRISTATE) + ); + + +generate +if ((C_MEM_TYPE == "DDR" || C_MEM_TYPE == "DDR2" || C_MEM_TYPE == "DDR3") && + (SKIP_IN_TERM_CAL == 1'b0) + ) begin : gen_zio + +IOBUF IOBUF_ZIO ( + .O (ZIO_IN), + .IO (ZIO_Pin), + .I (ZIO_OUT), + .T (ZIO_TOUT) + ); + + +IODRP2 IODRP2_ZIO ( + .DATAOUT(), + .DATAOUT2(), + .DOUT(ZIO_OUT), + .SDO(ZIO_IODRP_SDO), + .TOUT(ZIO_TOUT), + .ADD(IODRP_ADD), + .BKST(IODRP_BKST), + .CLK(UI_CLK), + .CS(ZIO_IODRP_CS), + .IDATAIN(ZIO_IN), + .IOCLK0(IOCLK), + .IOCLK1(1'b1), + .ODATAIN(RZQ_ZIO_ODATAIN), + .SDI(IODRP_SDI), + .T(RZQ_ZIO_TRISTATE) + ); + + +end +endgenerate + + +endmodule
xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v (revision 627) @@ -0,0 +1,225 @@ +/* + * Wrapper for Xilinx MIG'd DDR2 controller, allowing 3 masters + * to contol the single interface. + */ + +module xilinx_ddr2 + ( + // Inputs + input [31:0] wbm0_adr_i, + input [1:0] wbm0_bte_i, + input [2:0] wbm0_cti_i, + input wbm0_cyc_i, + input [31:0] wbm0_dat_i, + input [3:0] wbm0_sel_i, + + input wbm0_stb_i, + input wbm0_we_i, + + // Outputs + output wbm0_ack_o, + output wbm0_err_o, + output wbm0_rty_o, + output [31:0] wbm0_dat_o, + + + // Inputs + input [31:0] wbm1_adr_i, + input [1:0] wbm1_bte_i, + input [2:0] wbm1_cti_i, + input wbm1_cyc_i, + input [31:0] wbm1_dat_i, + input [3:0] wbm1_sel_i, + + input wbm1_stb_i, + input wbm1_we_i, + + // Outputs + output wbm1_ack_o, + output wbm1_err_o, + output wbm1_rty_o, + output [31:0] wbm1_dat_o, + + + + // Inputs + input [31:0] wbm2_adr_i, + input [1:0] wbm2_bte_i, + input [2:0] wbm2_cti_i, + input wbm2_cyc_i, + input [31:0] wbm2_dat_i, + input [3:0] wbm2_sel_i, + + input wbm2_stb_i, + input wbm2_we_i, + + // Outputs + output wbm2_ack_o, + output wbm2_err_o, + output wbm2_rty_o, + output [31:0] wbm2_dat_o, + + input wb_clk, + input wb_rst, + + output [12:0] ddr2_a, + output [2:0] ddr2_ba, + output ddr2_ras_n, + output ddr2_cas_n, + output ddr2_we_n, + output ddr2_rzq, + output ddr2_zio, + + output ddr2_odt, + output ddr2_cke, + output ddr2_dm, + output ddr2_udm, + + inout [15:0] ddr2_dq, + inout ddr2_dqs, + inout ddr2_dqs_n, + inout ddr2_udqs, + inout ddr2_udqs_n, + output ddr2_ck, + output ddr2_ck_n, + + input ddr2_if_clk, + input clk100, + input ddr2_if_rst + + ); + + // Internal wires to actual RAM + wire [31:0] wbs_ram_adr_i; + wire [1:0] wbs_ram_bte_i; + wire [2:0] wbs_ram_cti_i; + wire wbs_ram_cyc_i; + wire [31:0] wbs_ram_dat_i; + wire [3:0] wbs_ram_sel_i; + wire wbs_ram_stb_i; + wire wbs_ram_we_i; + + wire wbs_ram_ack_o; + wire [31:0] wbs_ram_dat_o; + + reg [2:0] input_select, last_selected; + wire arb_for_wbm0, arb_for_wbm1, arb_for_wbm2; + // Wires allowing selection of new input + assign arb_for_wbm0 = (last_selected[1] | last_selected[2] | + !wbm1_cyc_i | !wbm2_cyc_i) & !(|input_select); + assign arb_for_wbm1 = (last_selected[0] | last_selected[2] | + !wbm0_cyc_i | !wbm2_cyc_i) & !(|input_select); + assign arb_for_wbm2 = (last_selected[0] | last_selected[1] | + !wbm0_cyc_i | !wbm1_cyc_i) & !(|input_select); + + // Master select logic + always @(posedge wb_clk) + if (wb_rst) + input_select <= 0; + else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i) + | (input_select[2] & !wbm2_cyc_i)) + input_select <= 0; + else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0) + input_select <= 3'b001; + else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1) + input_select <= 3'b010; + else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2) + input_select <= 3'b100; + + always @(posedge wb_clk) + if (wb_rst) + last_selected <= 0; + else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0) + last_selected <= 3'b001; + else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1) + last_selected <= 3'b010; + else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2) + last_selected <= 3'b100; + + // Mux input signals to RAM (default to wbm0) + assign wbs_ram_adr_i = (input_select[2]) ? wbm2_adr_i : + (input_select[1]) ? wbm1_adr_i : + (input_select[0]) ? wbm0_adr_i : 0; + assign wbs_ram_bte_i = (input_select[2]) ? wbm2_bte_i : + (input_select[1]) ? wbm1_bte_i : + (input_select[0]) ? wbm0_bte_i : 0; + assign wbs_ram_cti_i = (input_select[2]) ? wbm2_cti_i : + (input_select[1]) ? wbm1_cti_i : + (input_select[0]) ? wbm0_cti_i : 0; + assign wbs_ram_cyc_i = (input_select[2]) ? wbm2_cyc_i : + (input_select[1]) ? wbm1_cyc_i : + (input_select[0]) ? wbm0_cyc_i : 0; + assign wbs_ram_dat_i = (input_select[2]) ? wbm2_dat_i : + (input_select[1]) ? wbm1_dat_i : + (input_select[0]) ? wbm0_dat_i : 0; + assign wbs_ram_sel_i = (input_select[2]) ? wbm2_sel_i : + (input_select[1]) ? wbm1_sel_i : + (input_select[0]) ? wbm0_sel_i : 0; + assign wbs_ram_stb_i = (input_select[2]) ? wbm2_stb_i : + (input_select[1]) ? wbm1_stb_i : + (input_select[0]) ? wbm0_stb_i : 0; + assign wbs_ram_we_i = (input_select[2]) ? wbm2_we_i : + (input_select[1]) ? wbm1_we_i : + (input_select[0]) ? wbm0_we_i : 0; + + // Output from RAM, gate the ACK, ERR, RTY signals appropriately + assign wbm0_dat_o = wbs_ram_dat_o; + assign wbm0_ack_o = wbs_ram_ack_o & input_select[0]; + assign wbm0_err_o = 0; + assign wbm0_rty_o = 0; + + assign wbm1_dat_o = wbs_ram_dat_o; + assign wbm1_ack_o = wbs_ram_ack_o & input_select[1]; + assign wbm1_err_o = 0; + assign wbm1_rty_o = 0; + + assign wbm2_dat_o = wbs_ram_dat_o; + assign wbm2_ack_o = wbs_ram_ack_o & input_select[2]; + assign wbm2_err_o = 0; + assign wbm2_rty_o = 0; + + + xilinx_ddr2_if xilinx_ddr2_if0 + ( + + .wb_dat_o (wbs_ram_dat_o), + .wb_ack_o (wbs_ram_ack_o), + .wb_adr_i (wbs_ram_adr_i[31:0]), + .wb_stb_i (wbs_ram_stb_i), + .wb_cti_i (wbs_ram_cti_i), + .wb_bte_i (wbs_ram_bte_i), + .wb_cyc_i (wbs_ram_cyc_i), + .wb_we_i (wbs_ram_we_i), + .wb_sel_i (wbs_ram_sel_i[3:0]), + .wb_dat_i (wbs_ram_dat_i[31:0]), + + .ddr2_a (ddr2_a[12:0]), + .ddr2_ba (ddr2_ba), + .ddr2_ras_n (ddr2_ras_n), + .ddr2_cas_n (ddr2_cas_n), + .ddr2_we_n (ddr2_we_n), + .ddr2_rzq (ddr2_rzq), + .ddr2_zio (ddr2_zio), + .ddr2_odt (ddr2_odt), + .ddr2_cke (ddr2_cke), + .ddr2_dm (ddr2_dm), + .ddr2_udm (ddr2_udm), + .ddr2_ck (ddr2_ck), + .ddr2_ck_n (ddr2_ck_n), + .ddr2_dq (ddr2_dq), + .ddr2_dqs (ddr2_dqs), + .ddr2_dqs_n (ddr2_dqs_n), + .ddr2_udqs (ddr2_udqs), + .ddr2_udqs_n (ddr2_udqs_n), + + .ddr2_if_clk (ddr2_if_clk), + .idly_clk_100 (clk100), //SJK this can be removed, not needed + .ddr2_if_rst (ddr2_if_rst), + .wb_clk (wb_clk), + .wb_rst (wb_rst)); + + + + +endmodule + Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/ddr2_mig.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/ddr2_mig.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/ddr2_mig.v (revision 627) @@ -0,0 +1,731 @@ +//***************************************************************************** +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 3.6.1 +// \ \ Application : MIG +// / / Filename : ddr2_mig #.v +// /___/ /\ Date Last Modified : $Date: 2010/10/27 17:40:11 $ +// \ \ / \ Date Created : Tue Feb 23 2010 +// \___\/\___\ +// +//Device : Spartan-6 +//Design Name : DDR/DDR2/DDR3/LPDDR +//Purpose : This is a template file for the design top module. This module contains +// all the four memory controllers and the two infrastructures. However, +// only the enabled modules will be active and others inactive. +//Reference : +//Revision History : +//***************************************************************************** +`timescale 1ns/1ps + +(* X_CORE_INFO = "mig_v3_61_ddr2_ddr2_s6, Coregen 12.4" , CORE_GENERATION_INFO = "ddr2_ddr2_s6,mig_v3_61,{component_name=ddr2_mig, C3_MEM_INTERFACE_TYPE=DDR2_SDRAM, C3_CLK_PERIOD=3750, C3_MEMORY_PART=mt47h64m16xx-25e, C3_OUTPUT_DRV=FULL, C3_RTT_NOM=50OHMS, C3_DQS#_ENABLE=YES, C3_HIGH_TEMP_SR=NORMAL, C3_PORT_CONFIG=One 128-bit bi-directional port, C3_MEM_ADDR_ORDER=BANK_ROW_COLUMN, C3_PORT_ENABLE=Port0, C3_CLASS_ADDR=II, C3_CLASS_DATA=II, C3_INPUT_PIN_TERMINATION=CALIB_TERM, C3_DATA_TERMINATION=25 Ohms, C3_CLKFBOUT_MULT_F=2, C3_CLKOUT_DIVIDE=1, C3_DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended, LANGUAGE=Verilog, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1}" *) +module ddr2_mig # +( + parameter C3_P0_MASK_SIZE = 16, + parameter C3_P0_DATA_PORT_SIZE = 128, + parameter DEBUG_EN = 0, + parameter C3_MEMCLK_PERIOD = 3750, + parameter C3_CALIB_SOFT_IP = "TRUE", + parameter C3_SIMULATION = "FALSE", + parameter C3_RST_ACT_LOW = 0, + parameter C3_INPUT_CLK_TYPE = "SINGLE_ENDED", + parameter C3_MEM_ADDR_ORDER = "BANK_ROW_COLUMN", + parameter C3_NUM_DQ_PINS = 16, + parameter C3_MEM_ADDR_WIDTH = 13, + parameter C3_MEM_BANKADDR_WIDTH = 3 +) + +( + + inout [C3_NUM_DQ_PINS-1:0] mcb3_dram_dq, + output [C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a, + output [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba, + output mcb3_dram_ras_n, + output mcb3_dram_cas_n, + output mcb3_dram_we_n, + output mcb3_dram_odt, + output mcb3_dram_cke, + output mcb3_dram_dm, + inout mcb3_dram_udqs, + inout mcb3_dram_udqs_n, + inout mcb3_rzq, + inout mcb3_zio, + output mcb3_dram_udm, + input c3_sys_clk, + input c3_sys_rst_n, + output c3_calib_done, + output c3_clk0, + output c3_rst0, + inout mcb3_dram_dqs, + inout mcb3_dram_dqs_n, + output mcb3_dram_ck, + output mcb3_dram_ck_n, + input c3_p0_cmd_clk, + input c3_p0_cmd_en, + input [2:0] c3_p0_cmd_instr, + input [5:0] c3_p0_cmd_bl, + input [29:0] c3_p0_cmd_byte_addr, + output c3_p0_cmd_empty, + output c3_p0_cmd_full, + input c3_p0_wr_clk, + input c3_p0_wr_en, + input [C3_P0_MASK_SIZE - 1:0] c3_p0_wr_mask, + input [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_wr_data, + output c3_p0_wr_full, + output c3_p0_wr_empty, + output [6:0] c3_p0_wr_count, + output c3_p0_wr_underrun, + output c3_p0_wr_error, + input c3_p0_rd_clk, + input c3_p0_rd_en, + output [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_rd_data, + output c3_p0_rd_full, + output c3_p0_rd_empty, + output [6:0] c3_p0_rd_count, + output c3_p0_rd_overflow, + output c3_p0_rd_error +); +// The parameter CX_PORT_ENABLE shows all the active user ports in the design. +// For example, the value 6'b111100 tells that only port-2, port-3, port-4 +// and port-5 are enabled. The other two ports are inactive. An inactive port +// can be a disabled port or an invisible logical port. Few examples to the +// invisible logical port are port-4 and port-5 in the user port configuration, +// Config-2: Four 32-bit bi-directional ports and the ports port-2 through +// port-5 in Config-4: Two 64-bit bi-directional ports. Please look into the +// Chapter-2 of ug388.pdf in the /docs directory for further details. + localparam C3_P1_MASK_SIZE =16; + localparam C3_P1_DATA_PORT_SIZE =128; + localparam C3_PORT_ENABLE = 6'b000001; + localparam C3_PORT_CONFIG = "B128"; + localparam C3_CLKOUT0_DIVIDE = 1; + localparam C3_CLKOUT1_DIVIDE = 1; + localparam C3_CLKOUT2_DIVIDE = 16; + localparam C3_CLKOUT3_DIVIDE = 8; + localparam C3_CLKFBOUT_MULT = 2; + localparam C3_DIVCLK_DIVIDE = 1; + localparam C3_ARB_ALGORITHM = 0; + localparam C3_ARB_NUM_TIME_SLOTS = 12; + localparam C3_ARB_TIME_SLOT_0 = 3'o0; + localparam C3_ARB_TIME_SLOT_1 = 3'o0; + localparam C3_ARB_TIME_SLOT_2 = 3'o0; + localparam C3_ARB_TIME_SLOT_3 = 3'o0; + localparam C3_ARB_TIME_SLOT_4 = 3'o0; + localparam C3_ARB_TIME_SLOT_5 = 3'o0; + localparam C3_ARB_TIME_SLOT_6 = 3'o0; + localparam C3_ARB_TIME_SLOT_7 = 3'o0; + localparam C3_ARB_TIME_SLOT_8 = 3'o0; + localparam C3_ARB_TIME_SLOT_9 = 3'o0; + localparam C3_ARB_TIME_SLOT_10 = 3'o0; + localparam C3_ARB_TIME_SLOT_11 = 3'o0; + localparam C3_MEM_TRAS = 42500; + localparam C3_MEM_TRCD = 12500; + localparam C3_MEM_TREFI = 7800000; + localparam C3_MEM_TRFC = 127500; + localparam C3_MEM_TRP = 12500; + localparam C3_MEM_TWR = 15000; + localparam C3_MEM_TRTP = 7500; + localparam C3_MEM_TWTR = 7500; + localparam C3_MEM_TYPE = "DDR2"; + localparam C3_MEM_DENSITY = "1Gb"; + localparam C3_MEM_BURST_LEN = 8; + localparam C3_MEM_CAS_LATENCY = 4; + localparam C3_MEM_NUM_COL_BITS = 10; + localparam C3_MEM_DDR1_2_ODS = "FULL"; + localparam C3_MEM_DDR2_RTT = "50OHMS"; + localparam C3_MEM_DDR2_DIFF_DQS_EN = "YES"; + localparam C3_MEM_DDR2_3_PA_SR = "FULL"; + localparam C3_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"; + localparam C3_MEM_DDR3_CAS_LATENCY = 6; + localparam C3_MEM_DDR3_ODS = "DIV6"; + localparam C3_MEM_DDR3_RTT = "DIV2"; + localparam C3_MEM_DDR3_CAS_WR_LATENCY = 5; + localparam C3_MEM_DDR3_AUTO_SR = "ENABLED"; + localparam C3_MEM_MOBILE_PA_SR = "FULL"; + localparam C3_MEM_MDDR_ODS = "FULL"; + localparam C3_MC_CALIB_BYPASS = "NO"; + localparam C3_MC_CALIBRATION_MODE = "CALIBRATION"; + localparam C3_MC_CALIBRATION_DELAY = "HALF"; + localparam C3_SKIP_IN_TERM_CAL = 0; + localparam C3_SKIP_DYNAMIC_CAL = 0; + localparam C3_LDQSP_TAP_DELAY_VAL = 0; + localparam C3_LDQSN_TAP_DELAY_VAL = 0; + localparam C3_UDQSP_TAP_DELAY_VAL = 0; + localparam C3_UDQSN_TAP_DELAY_VAL = 0; + localparam C3_DQ0_TAP_DELAY_VAL = 0; + localparam C3_DQ1_TAP_DELAY_VAL = 0; + localparam C3_DQ2_TAP_DELAY_VAL = 0; + localparam C3_DQ3_TAP_DELAY_VAL = 0; + localparam C3_DQ4_TAP_DELAY_VAL = 0; + localparam C3_DQ5_TAP_DELAY_VAL = 0; + localparam C3_DQ6_TAP_DELAY_VAL = 0; + localparam C3_DQ7_TAP_DELAY_VAL = 0; + localparam C3_DQ8_TAP_DELAY_VAL = 0; + localparam C3_DQ9_TAP_DELAY_VAL = 0; + localparam C3_DQ10_TAP_DELAY_VAL = 0; + localparam C3_DQ11_TAP_DELAY_VAL = 0; + localparam C3_DQ12_TAP_DELAY_VAL = 0; + localparam C3_DQ13_TAP_DELAY_VAL = 0; + localparam C3_DQ14_TAP_DELAY_VAL = 0; + localparam C3_DQ15_TAP_DELAY_VAL = 0; + localparam C3_MCB_USE_EXTERNAL_BUFPLL = 1; + localparam C3_INCLK_PERIOD = ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); + localparam C3_ARB_TIME0_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_0[2:0]}; + localparam C3_ARB_TIME1_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_1[2:0]}; + localparam C3_ARB_TIME2_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_2[2:0]}; + localparam C3_ARB_TIME3_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_3[2:0]}; + localparam C3_ARB_TIME4_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_4[2:0]}; + localparam C3_ARB_TIME5_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_5[2:0]}; + localparam C3_ARB_TIME6_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_6[2:0]}; + localparam C3_ARB_TIME7_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_7[2:0]}; + localparam C3_ARB_TIME8_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_8[2:0]}; + localparam C3_ARB_TIME9_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_9[2:0]}; + localparam C3_ARB_TIME10_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_10[2:0]}; + localparam C3_ARB_TIME11_SLOT = {3'b111, 3'b111, 3'b111, 3'b111, 3'b111, C3_ARB_TIME_SLOT_11[2:0]}; + + wire c3_sys_clk_p; + wire c3_sys_clk_n; + wire c3_async_rst; + wire c3_sysclk_2x; + wire c3_sysclk_2x_180; + wire c3_pll_ce_0; + wire c3_pll_ce_90; + wire c3_pll_lock; + wire c3_mcb_drp_clk; + wire c3_cmp_error; + wire c3_cmp_data_valid; + wire c3_vio_modify_enable; + wire [2:0] c3_vio_data_mode_value; + wire [2:0] c3_vio_addr_mode_value; + wire [31:0] c3_cmp_data; +wire c3_p1_cmd_clk; +wire c3_p1_cmd_en; +wire[2:0] c3_p1_cmd_instr; +wire[5:0] c3_p1_cmd_bl; +wire[29:0] c3_p1_cmd_byte_addr; +wire c3_p1_cmd_empty; +wire c3_p1_cmd_full; +wire c3_p1_wr_clk; +wire c3_p1_wr_en; +wire[C3_P1_MASK_SIZE-1:0] c3_p1_wr_mask; +wire[C3_P1_DATA_PORT_SIZE-1:0] c3_p1_wr_data; +wire c3_p1_wr_full; +wire c3_p1_wr_empty; +wire[6:0] c3_p1_wr_count; +wire c3_p1_wr_underrun; +wire c3_p1_wr_error; +wire c3_p1_rd_clk; +wire c3_p1_rd_en; +wire[C3_P1_DATA_PORT_SIZE-1:0] c3_p1_rd_data; +wire c3_p1_rd_full; +wire c3_p1_rd_empty; +wire[6:0] c3_p1_rd_count; +wire c3_p1_rd_overflow; +wire c3_p1_rd_error; +wire c3_p2_cmd_clk; +wire c3_p2_cmd_en; +wire[2:0] c3_p2_cmd_instr; +wire[5:0] c3_p2_cmd_bl; +wire[29:0] c3_p2_cmd_byte_addr; +wire c3_p2_cmd_empty; +wire c3_p2_cmd_full; +wire c3_p2_wr_clk; +wire c3_p2_wr_en; +wire[3:0] c3_p2_wr_mask; +wire[31:0] c3_p2_wr_data; +wire c3_p2_wr_full; +wire c3_p2_wr_empty; +wire[6:0] c3_p2_wr_count; +wire c3_p2_wr_underrun; +wire c3_p2_wr_error; +wire c3_p2_rd_clk; +wire c3_p2_rd_en; +wire[31:0] c3_p2_rd_data; +wire c3_p2_rd_full; +wire c3_p2_rd_empty; +wire[6:0] c3_p2_rd_count; +wire c3_p2_rd_overflow; +wire c3_p2_rd_error; +wire c3_p3_cmd_clk; +wire c3_p3_cmd_en; +wire[2:0] c3_p3_cmd_instr; +wire[5:0] c3_p3_cmd_bl; +wire[29:0] c3_p3_cmd_byte_addr; +wire c3_p3_cmd_empty; +wire c3_p3_cmd_full; +wire c3_p3_wr_clk; +wire c3_p3_wr_en; +wire[3:0] c3_p3_wr_mask; +wire[31:0] c3_p3_wr_data; +wire c3_p3_wr_full; +wire c3_p3_wr_empty; +wire[6:0] c3_p3_wr_count; +wire c3_p3_wr_underrun; +wire c3_p3_wr_error; +wire c3_p3_rd_clk; +wire c3_p3_rd_en; +wire[31:0] c3_p3_rd_data; +wire c3_p3_rd_full; +wire c3_p3_rd_empty; +wire[6:0] c3_p3_rd_count; +wire c3_p3_rd_overflow; +wire c3_p3_rd_error; +wire c3_p4_cmd_clk; +wire c3_p4_cmd_en; +wire[2:0] c3_p4_cmd_instr; +wire[5:0] c3_p4_cmd_bl; +wire[29:0] c3_p4_cmd_byte_addr; +wire c3_p4_cmd_empty; +wire c3_p4_cmd_full; +wire c3_p4_wr_clk; +wire c3_p4_wr_en; +wire[3:0] c3_p4_wr_mask; +wire[31:0] c3_p4_wr_data; +wire c3_p4_wr_full; +wire c3_p4_wr_empty; +wire[6:0] c3_p4_wr_count; +wire c3_p4_wr_underrun; +wire c3_p4_wr_error; +wire c3_p4_rd_clk; +wire c3_p4_rd_en; +wire[31:0] c3_p4_rd_data; +wire c3_p4_rd_full; +wire c3_p4_rd_empty; +wire[6:0] c3_p4_rd_count; +wire c3_p4_rd_overflow; +wire c3_p4_rd_error; +wire c3_p5_cmd_clk; +wire c3_p5_cmd_en; +wire[2:0] c3_p5_cmd_instr; +wire[5:0] c3_p5_cmd_bl; +wire[29:0] c3_p5_cmd_byte_addr; +wire c3_p5_cmd_empty; +wire c3_p5_cmd_full; +wire c3_p5_wr_clk; +wire c3_p5_wr_en; +wire[3:0] c3_p5_wr_mask; +wire[31:0] c3_p5_wr_data; +wire c3_p5_wr_full; +wire c3_p5_wr_empty; +wire[6:0] c3_p5_wr_count; +wire c3_p5_wr_underrun; +wire c3_p5_wr_error; +wire c3_p5_rd_clk; +wire c3_p5_rd_en; +wire[31:0] c3_p5_rd_data; +wire c3_p5_rd_full; +wire c3_p5_rd_empty; +wire[6:0] c3_p5_rd_count; +wire c3_p5_rd_overflow; +wire c3_p5_rd_error; + + + + +assign c3_sys_clk_p = 1'b0; +assign c3_sys_clk_n = 1'b0; + + + +// Infrastructure-3 instantiation + infrastructure # + ( + .C_INCLK_PERIOD (C3_INCLK_PERIOD), + .C_RST_ACT_LOW (C3_RST_ACT_LOW), + .C_INPUT_CLK_TYPE (C3_INPUT_CLK_TYPE), + .C_CLKOUT0_DIVIDE (C3_CLKOUT0_DIVIDE), + .C_CLKOUT1_DIVIDE (C3_CLKOUT1_DIVIDE), + .C_CLKOUT2_DIVIDE (C3_CLKOUT2_DIVIDE), + .C_CLKOUT3_DIVIDE (C3_CLKOUT3_DIVIDE), + .C_CLKFBOUT_MULT (C3_CLKFBOUT_MULT), + .C_DIVCLK_DIVIDE (C3_DIVCLK_DIVIDE) + ) + memc3_infrastructure_inst + ( + .sys_clk_p (c3_sys_clk_p), + .sys_clk_n (c3_sys_clk_n), + .sys_clk (c3_sys_clk), + .sys_rst_n (c3_sys_rst_n), + .clk0 (c3_clk0), + .rst0 (c3_rst0), + .async_rst (c3_async_rst), + .sysclk_2x (c3_sysclk_2x), + .sysclk_2x_180 (c3_sysclk_2x_180), + .pll_ce_0 (c3_pll_ce_0), + .pll_ce_90 (c3_pll_ce_90), + .pll_lock (c3_pll_lock), + .mcb_drp_clk (c3_mcb_drp_clk) + ); + + + +// Controller-3 instantiation + memc_wrapper # + ( + .C_MEMCLK_PERIOD (C3_MEMCLK_PERIOD), + .C_CALIB_SOFT_IP (C3_CALIB_SOFT_IP), + .C_SIMULATION (C3_SIMULATION), + .C_ARB_NUM_TIME_SLOTS (C3_ARB_NUM_TIME_SLOTS), + .C_ARB_TIME_SLOT_0 (C3_ARB_TIME0_SLOT), + .C_ARB_TIME_SLOT_1 (C3_ARB_TIME1_SLOT), + .C_ARB_TIME_SLOT_2 (C3_ARB_TIME2_SLOT), + .C_ARB_TIME_SLOT_3 (C3_ARB_TIME3_SLOT), + .C_ARB_TIME_SLOT_4 (C3_ARB_TIME4_SLOT), + .C_ARB_TIME_SLOT_5 (C3_ARB_TIME5_SLOT), + .C_ARB_TIME_SLOT_6 (C3_ARB_TIME6_SLOT), + .C_ARB_TIME_SLOT_7 (C3_ARB_TIME7_SLOT), + .C_ARB_TIME_SLOT_8 (C3_ARB_TIME8_SLOT), + .C_ARB_TIME_SLOT_9 (C3_ARB_TIME9_SLOT), + .C_ARB_TIME_SLOT_10 (C3_ARB_TIME10_SLOT), + .C_ARB_TIME_SLOT_11 (C3_ARB_TIME11_SLOT), + .C_ARB_ALGORITHM (C3_ARB_ALGORITHM), + .C_PORT_ENABLE (C3_PORT_ENABLE), + .C_PORT_CONFIG (C3_PORT_CONFIG), + .C_MEM_TRAS (C3_MEM_TRAS), + .C_MEM_TRCD (C3_MEM_TRCD), + .C_MEM_TREFI (C3_MEM_TREFI), + .C_MEM_TRFC (C3_MEM_TRFC), + .C_MEM_TRP (C3_MEM_TRP), + .C_MEM_TWR (C3_MEM_TWR), + .C_MEM_TRTP (C3_MEM_TRTP), + .C_MEM_TWTR (C3_MEM_TWTR), + .C_MEM_ADDR_ORDER (C3_MEM_ADDR_ORDER), + .C_NUM_DQ_PINS (C3_NUM_DQ_PINS), + .C_MEM_TYPE (C3_MEM_TYPE), + .C_MEM_DENSITY (C3_MEM_DENSITY), + .C_MEM_BURST_LEN (C3_MEM_BURST_LEN), + .C_MEM_CAS_LATENCY (C3_MEM_CAS_LATENCY), + .C_MEM_ADDR_WIDTH (C3_MEM_ADDR_WIDTH), + .C_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH), + .C_MEM_NUM_COL_BITS (C3_MEM_NUM_COL_BITS), + .C_MEM_DDR1_2_ODS (C3_MEM_DDR1_2_ODS), + .C_MEM_DDR2_RTT (C3_MEM_DDR2_RTT), + .C_MEM_DDR2_DIFF_DQS_EN (C3_MEM_DDR2_DIFF_DQS_EN), + .C_MEM_DDR2_3_PA_SR (C3_MEM_DDR2_3_PA_SR), + .C_MEM_DDR2_3_HIGH_TEMP_SR (C3_MEM_DDR2_3_HIGH_TEMP_SR), + .C_MEM_DDR3_CAS_LATENCY (C3_MEM_DDR3_CAS_LATENCY), + .C_MEM_DDR3_ODS (C3_MEM_DDR3_ODS), + .C_MEM_DDR3_RTT (C3_MEM_DDR3_RTT), + .C_MEM_DDR3_CAS_WR_LATENCY (C3_MEM_DDR3_CAS_WR_LATENCY), + .C_MEM_DDR3_AUTO_SR (C3_MEM_DDR3_AUTO_SR), + .C_MEM_MOBILE_PA_SR (C3_MEM_MOBILE_PA_SR), + .C_MEM_MDDR_ODS (C3_MEM_MDDR_ODS), + .C_MC_CALIB_BYPASS (C3_MC_CALIB_BYPASS), + .C_MC_CALIBRATION_MODE (C3_MC_CALIBRATION_MODE), + .C_MC_CALIBRATION_DELAY (C3_MC_CALIBRATION_DELAY), + .C_SKIP_IN_TERM_CAL (C3_SKIP_IN_TERM_CAL), + .C_SKIP_DYNAMIC_CAL (C3_SKIP_DYNAMIC_CAL), + .LDQSP_TAP_DELAY_VAL (C3_LDQSP_TAP_DELAY_VAL), + .UDQSP_TAP_DELAY_VAL (C3_UDQSP_TAP_DELAY_VAL), + .LDQSN_TAP_DELAY_VAL (C3_LDQSN_TAP_DELAY_VAL), + .UDQSN_TAP_DELAY_VAL (C3_UDQSN_TAP_DELAY_VAL), + .DQ0_TAP_DELAY_VAL (C3_DQ0_TAP_DELAY_VAL), + .DQ1_TAP_DELAY_VAL (C3_DQ1_TAP_DELAY_VAL), + .DQ2_TAP_DELAY_VAL (C3_DQ2_TAP_DELAY_VAL), + .DQ3_TAP_DELAY_VAL (C3_DQ3_TAP_DELAY_VAL), + .DQ4_TAP_DELAY_VAL (C3_DQ4_TAP_DELAY_VAL), + .DQ5_TAP_DELAY_VAL (C3_DQ5_TAP_DELAY_VAL), + .DQ6_TAP_DELAY_VAL (C3_DQ6_TAP_DELAY_VAL), + .DQ7_TAP_DELAY_VAL (C3_DQ7_TAP_DELAY_VAL), + .DQ8_TAP_DELAY_VAL (C3_DQ8_TAP_DELAY_VAL), + .DQ9_TAP_DELAY_VAL (C3_DQ9_TAP_DELAY_VAL), + .DQ10_TAP_DELAY_VAL (C3_DQ10_TAP_DELAY_VAL), + .DQ11_TAP_DELAY_VAL (C3_DQ11_TAP_DELAY_VAL), + .DQ12_TAP_DELAY_VAL (C3_DQ12_TAP_DELAY_VAL), + .DQ13_TAP_DELAY_VAL (C3_DQ13_TAP_DELAY_VAL), + .DQ14_TAP_DELAY_VAL (C3_DQ14_TAP_DELAY_VAL), + .DQ15_TAP_DELAY_VAL (C3_DQ15_TAP_DELAY_VAL), + .C_P0_MASK_SIZE (C3_P0_MASK_SIZE), + .C_P0_DATA_PORT_SIZE (C3_P0_DATA_PORT_SIZE), + .C_P1_MASK_SIZE (C3_P1_MASK_SIZE), + .C_P1_DATA_PORT_SIZE (C3_P1_DATA_PORT_SIZE) + ) + + memc3_wrapper_inst + ( + .mcbx_dram_addr (mcb3_dram_a), + .mcbx_dram_ba (mcb3_dram_ba), + .mcbx_dram_ras_n (mcb3_dram_ras_n), + .mcbx_dram_cas_n (mcb3_dram_cas_n), + .mcbx_dram_we_n (mcb3_dram_we_n), + .mcbx_dram_cke (mcb3_dram_cke), + .mcbx_dram_clk (mcb3_dram_ck), + .mcbx_dram_clk_n (mcb3_dram_ck_n), + .mcbx_dram_dq (mcb3_dram_dq), + .mcbx_dram_dqs (mcb3_dram_dqs), + .mcbx_dram_dqs_n (mcb3_dram_dqs_n), + .mcbx_dram_udqs (mcb3_dram_udqs), + .mcbx_dram_udqs_n (mcb3_dram_udqs_n), + .mcbx_dram_udm (mcb3_dram_udm), + .mcbx_dram_ldm (mcb3_dram_dm), + .mcbx_dram_odt (mcb3_dram_odt), + .mcbx_dram_ddr3_rst ( ), + .mcbx_rzq (mcb3_rzq), + .mcbx_zio (mcb3_zio), + .calib_done (c3_calib_done), + .async_rst (c3_async_rst), + .sysclk_2x (c3_sysclk_2x), + .sysclk_2x_180 (c3_sysclk_2x_180), + .pll_ce_0 (c3_pll_ce_0), + .pll_ce_90 (c3_pll_ce_90), + .pll_lock (c3_pll_lock), + .mcb_drp_clk (c3_mcb_drp_clk), + + // The following port map shows all the six logical user ports. However, all + // of them may not be active in this design. A port should be enabled to + // validate its port map. If it is not,the complete port is going to float + // by getting disconnected from the lower level MCB modules. The port enable + // information of a controller can be obtained from the corresponding local + // parameter CX_PORT_ENABLE. In such a case, we can simply ignore its port map. + // The following comments will explain when a port is going to be active. + // Config-1: Two 32-bit bi-directional and four 32-bit unidirectional ports + // Config-2: Four 32-bit bi-directional ports + // Config-3: One 64-bit bi-directional and two 32-bit bi-directional ports + // Config-4: Two 64-bit bi-directional ports + // Config-5: One 128-bit bi-directional port + + // User Port-0 command interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5 + .p0_cmd_clk (c3_p0_cmd_clk), + .p0_cmd_en (c3_p0_cmd_en), + .p0_cmd_instr (c3_p0_cmd_instr), + .p0_cmd_bl (c3_p0_cmd_bl), + .p0_cmd_byte_addr (c3_p0_cmd_byte_addr), + .p0_cmd_full (c3_p0_cmd_full), + .p0_cmd_empty (c3_p0_cmd_empty), + // User Port-0 data write interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5 + .p0_wr_clk (c3_p0_wr_clk), + .p0_wr_en (c3_p0_wr_en), + .p0_wr_mask (c3_p0_wr_mask), + .p0_wr_data (c3_p0_wr_data), + .p0_wr_full (c3_p0_wr_full), + .p0_wr_count (c3_p0_wr_count), + .p0_wr_empty (c3_p0_wr_empty), + .p0_wr_underrun (c3_p0_wr_underrun), + .p0_wr_error (c3_p0_wr_error), + // User Port-0 data read interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5 + .p0_rd_clk (c3_p0_rd_clk), + .p0_rd_en (c3_p0_rd_en), + .p0_rd_data (c3_p0_rd_data), + .p0_rd_empty (c3_p0_rd_empty), + .p0_rd_count (c3_p0_rd_count), + .p0_rd_full (c3_p0_rd_full), + .p0_rd_overflow (c3_p0_rd_overflow), + .p0_rd_error (c3_p0_rd_error), + + // User Port-1 command interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3 and Config-4 + .p1_cmd_clk (c3_p1_cmd_clk), + .p1_cmd_en (c3_p1_cmd_en), + .p1_cmd_instr (c3_p1_cmd_instr), + .p1_cmd_bl (c3_p1_cmd_bl), + .p1_cmd_byte_addr (c3_p1_cmd_byte_addr), + .p1_cmd_full (c3_p1_cmd_full), + .p1_cmd_empty (c3_p1_cmd_empty), + // User Port-1 data write interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3 and Config-4 + .p1_wr_clk (c3_p1_wr_clk), + .p1_wr_en (c3_p1_wr_en), + .p1_wr_mask (c3_p1_wr_mask), + .p1_wr_data (c3_p1_wr_data), + .p1_wr_full (c3_p1_wr_full), + .p1_wr_count (c3_p1_wr_count), + .p1_wr_empty (c3_p1_wr_empty), + .p1_wr_underrun (c3_p1_wr_underrun), + .p1_wr_error (c3_p1_wr_error), + // User Port-1 data read interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2, Config-3 and Config-4 + .p1_rd_clk (c3_p1_rd_clk), + .p1_rd_en (c3_p1_rd_en), + .p1_rd_data (c3_p1_rd_data), + .p1_rd_empty (c3_p1_rd_empty), + .p1_rd_count (c3_p1_rd_count), + .p1_rd_full (c3_p1_rd_full), + .p1_rd_overflow (c3_p1_rd_overflow), + .p1_rd_error (c3_p1_rd_error), + + // User Port-2 command interface will be active only when the port is enabled in + // the port configurations Config-1, Config-2 and Config-3 + .p2_cmd_clk (c3_p2_cmd_clk), + .p2_cmd_en (c3_p2_cmd_en), + .p2_cmd_instr (c3_p2_cmd_instr), + .p2_cmd_bl (c3_p2_cmd_bl), + .p2_cmd_byte_addr (c3_p2_cmd_byte_addr), + .p2_cmd_full (c3_p2_cmd_full), + .p2_cmd_empty (c3_p2_cmd_empty), + // User Port-2 data write interface will be active only when the port is enabled in + // the port configurations Config-1 write direction, Config-2 and Config-3 + .p2_wr_clk (c3_p2_wr_clk), + .p2_wr_en (c3_p2_wr_en), + .p2_wr_mask (c3_p2_wr_mask), + .p2_wr_data (c3_p2_wr_data), + .p2_wr_full (c3_p2_wr_full), + .p2_wr_count (c3_p2_wr_count), + .p2_wr_empty (c3_p2_wr_empty), + .p2_wr_underrun (c3_p2_wr_underrun), + .p2_wr_error (c3_p2_wr_error), + // User Port-2 data read interface will be active only when the port is enabled in + // the port configurations Config-1 read direction, Config-2 and Config-3 + .p2_rd_clk (c3_p2_rd_clk), + .p2_rd_en (c3_p2_rd_en), + .p2_rd_data (c3_p2_rd_data), + .p2_rd_empty (c3_p2_rd_empty), + .p2_rd_count (c3_p2_rd_count), + .p2_rd_full (c3_p2_rd_full), + .p2_rd_overflow (c3_p2_rd_overflow), + .p2_rd_error (c3_p2_rd_error), + + // User Port-3 command interface will be active only when the port is enabled in + // the port configurations Config-1 and Config-2 + .p3_cmd_clk (c3_p3_cmd_clk), + .p3_cmd_en (c3_p3_cmd_en), + .p3_cmd_instr (c3_p3_cmd_instr), + .p3_cmd_bl (c3_p3_cmd_bl), + .p3_cmd_byte_addr (c3_p3_cmd_byte_addr), + .p3_cmd_full (c3_p3_cmd_full), + .p3_cmd_empty (c3_p3_cmd_empty), + // User Port-3 data write interface will be active only when the port is enabled in + // the port configurations Config-1 write direction and Config-2 + .p3_wr_clk (c3_p3_wr_clk), + .p3_wr_en (c3_p3_wr_en), + .p3_wr_mask (c3_p3_wr_mask), + .p3_wr_data (c3_p3_wr_data), + .p3_wr_full (c3_p3_wr_full), + .p3_wr_count (c3_p3_wr_count), + .p3_wr_empty (c3_p3_wr_empty), + .p3_wr_underrun (c3_p3_wr_underrun), + .p3_wr_error (c3_p3_wr_error), + // User Port-3 data read interface will be active only when the port is enabled in + // the port configurations Config-1 read direction and Config-2 + .p3_rd_clk (c3_p3_rd_clk), + .p3_rd_en (c3_p3_rd_en), + .p3_rd_data (c3_p3_rd_data), + .p3_rd_empty (c3_p3_rd_empty), + .p3_rd_count (c3_p3_rd_count), + .p3_rd_full (c3_p3_rd_full), + .p3_rd_overflow (c3_p3_rd_overflow), + .p3_rd_error (c3_p3_rd_error), + + // User Port-4 command interface will be active only when the port is enabled in + // the port configuration Config-1 + .p4_cmd_clk (c3_p4_cmd_clk), + .p4_cmd_en (c3_p4_cmd_en), + .p4_cmd_instr (c3_p4_cmd_instr), + .p4_cmd_bl (c3_p4_cmd_bl), + .p4_cmd_byte_addr (c3_p4_cmd_byte_addr), + .p4_cmd_full (c3_p4_cmd_full), + .p4_cmd_empty (c3_p4_cmd_empty), + // User Port-4 data write interface will be active only when the port is enabled in + // the port configuration Config-1 write direction + .p4_wr_clk (c3_p4_wr_clk), + .p4_wr_en (c3_p4_wr_en), + .p4_wr_mask (c3_p4_wr_mask), + .p4_wr_data (c3_p4_wr_data), + .p4_wr_full (c3_p4_wr_full), + .p4_wr_count (c3_p4_wr_count), + .p4_wr_empty (c3_p4_wr_empty), + .p4_wr_underrun (c3_p4_wr_underrun), + .p4_wr_error (c3_p4_wr_error), + // User Port-4 data read interface will be active only when the port is enabled in + // the port configuration Config-1 read direction + .p4_rd_clk (c3_p4_rd_clk), + .p4_rd_en (c3_p4_rd_en), + .p4_rd_data (c3_p4_rd_data), + .p4_rd_empty (c3_p4_rd_empty), + .p4_rd_count (c3_p4_rd_count), + .p4_rd_full (c3_p4_rd_full), + .p4_rd_overflow (c3_p4_rd_overflow), + .p4_rd_error (c3_p4_rd_error), + + // User Port-5 command interface will be active only when the port is enabled in + // the port configuration Config-1 + .p5_cmd_clk (c3_p5_cmd_clk), + .p5_cmd_en (c3_p5_cmd_en), + .p5_cmd_instr (c3_p5_cmd_instr), + .p5_cmd_bl (c3_p5_cmd_bl), + .p5_cmd_byte_addr (c3_p5_cmd_byte_addr), + .p5_cmd_full (c3_p5_cmd_full), + .p5_cmd_empty (c3_p5_cmd_empty), + // User Port-5 data write interface will be active only when the port is enabled in + // the port configuration Config-1 write direction + .p5_wr_clk (c3_p5_wr_clk), + .p5_wr_en (c3_p5_wr_en), + .p5_wr_mask (c3_p5_wr_mask), + .p5_wr_data (c3_p5_wr_data), + .p5_wr_full (c3_p5_wr_full), + .p5_wr_count (c3_p5_wr_count), + .p5_wr_empty (c3_p5_wr_empty), + .p5_wr_underrun (c3_p5_wr_underrun), + .p5_wr_error (c3_p5_wr_error), + // User Port-5 data read interface will be active only when the port is enabled in + // the port configuration Config-1 read direction + .p5_rd_clk (c3_p5_rd_clk), + .p5_rd_en (c3_p5_rd_en), + .p5_rd_data (c3_p5_rd_data), + .p5_rd_empty (c3_p5_rd_empty), + .p5_rd_count (c3_p5_rd_count), + .p5_rd_full (c3_p5_rd_full), + .p5_rd_overflow (c3_p5_rd_overflow), + .p5_rd_error (c3_p5_rd_error), + + .selfrefresh_enter (1'b0), + .selfrefresh_mode (c3_selfrefresh_mode) + ); + + + + + + +endmodule + + Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v (revision 627) @@ -0,0 +1,174 @@ +/******************************************************************************* +* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. * +* * +* This file contains confidential and proprietary information * +* of Xilinx, Inc. and is protected under U.S. and * +* international copyright and other intellectual property * +* laws. * +* * +* DISCLAIMER * +* This disclaimer is not a license and does not grant any * +* rights to the materials distributed herewith. Except as * +* otherwise provided in a valid license issued to you by * +* Xilinx, and to the maximum extent permitted by applicable * +* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND * +* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES * +* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING * +* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- * +* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and * +* (2) Xilinx shall not be liable (whether in contract or tort, * +* including negligence, or under any other theory of * +* liability) for any loss or damage of any kind or nature * +* related to, arising under or in connection with these * +* materials, including for any direct, or any indirect, * +* special, incidental, or consequential loss or damage * +* (including loss of data, profits, goodwill, or any type of * +* loss or damage suffered as a result of any action brought * +* by a third party) even if such damage or loss was * +* reasonably foreseeable or Xilinx had been advised of the * +* possibility of the same. * +* * +* CRITICAL APPLICATIONS * +* Xilinx products are not designed or intended to be fail- * +* safe, or for use in any application requiring fail-safe * +* performance, such as life-support or safety devices or * +* systems, Class III medical devices, nuclear facilities, * +* applications related to the deployment of airbags, or any * +* other applications that could lead to death, personal * +* injury, or severe property or environmental damage * +* (individually and collectively, "Critical * +* Applications"). Customer assumes the sole risk and * +* liability of any use of Xilinx products in Critical * +* Applications, subject only to applicable laws and * +* regulations governing limitations on product liability. * +* * +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * +* PART OF THIS FILE AT ALL TIMES. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file xilinx_ddr2_if_cache.v when simulating +// the core, xilinx_ddr2_if_cache. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module xilinx_ddr2_if_cache( + clka, + ena, + wea, + addra, + dina, + douta, + clkb, + enb, + web, + addrb, + dinb, + doutb); + + +input clka; +input ena; +input [3 : 0] wea; +input [11 : 0] addra; +input [31 : 0] dina; +output [31 : 0] douta; +input clkb; +input enb; +input [15 : 0] web; +input [9 : 0] addrb; +input [127 : 0] dinb; +output [127 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V4_3 #( + .C_ADDRA_WIDTH(12), + .C_ADDRB_WIDTH(10), + .C_ALGORITHM(1), + .C_BYTE_SIZE(8), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan6"), + .C_HAS_ENA(1), + .C_HAS_ENB(1), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(2), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(4096), + .C_READ_DEPTH_B(1024), + .C_READ_WIDTH_A(32), + .C_READ_WIDTH_B(128), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(1), + .C_USE_BYTE_WEB(1), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(4), + .C_WEB_WIDTH(16), + .C_WRITE_DEPTH_A(4096), + .C_WRITE_DEPTH_B(1024), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(32), + .C_WRITE_WIDTH_B(128), + .C_XDEVICEFAMILY("spartan6")) + inst ( + .CLKA(clka), + .ENA(ena), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .DOUTA(douta), + .CLKB(clkb), + .ENB(enb), + .WEB(web), + .ADDRB(addrb), + .DINB(dinb), + .DOUTB(doutb), + .RSTA(), + .REGCEA(), + .RSTB(), + .REGCEB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of xilinx_ddr2_if_cache is "black_box" + +endmodule + Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/README =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/README (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/README (revision 627) @@ -0,0 +1,16 @@ +Xilinx DDR2 controller with Wishbone interface + +This is a Xilinx technology-dependent DDR2 memory controller, based on a +controller from Xilinx's memory interface generator (MIG), with a small cache +memory and Wishbone wrapper. + +The xilinx_ddr2_wb_if.v is a 3-master arbiter for the controller. +The xilinx_ddr2_if.v is the actual interface between the Wishbone bus and +Xilinx MIG control interface. + +When synthesizing, take note of the xilinx_ddr2_if_cache module, that is a +dual-port memory, with different aspects on each size, and cannot be inferred. +The NGC should be in the appropriate place in the synthesis or backend +directories. + + Index: xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_raw_wrapper.v =================================================================== --- xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_raw_wrapper.v (nonexistent) +++ xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_raw_wrapper.v (revision 627) @@ -0,0 +1,6496 @@ +//***************************************************************************** +// (c) Copyright 2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: mcb_raw_wrapper.v +// /___/ /\ Date Last Modified: $Date: 2010/10/27 17:40:12 $ +// \ \ / \ Date Created: Thu June 24 2008 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: +//Reference: +// This module is the intialization control logic of the memory interface. +// All commands are issued from here acoording to the burst, CAS Latency and +// the user commands. +// +// Revised History: +// Rev 1.1 - added port_enable assignment for all configurations and rearrange +// assignment siganls according to port number +// - added timescale directive -SN 7-28-08 +// - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through +// 15 -SN 7-28-08 +// - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08 +// - removed ghighb, gpwrdnb, gsr, gwe in port declaration. +// For now tb need to force the signals inside the MCB and Wrapper +// until a glbl.v is ready. Not sure how to do this in NCVerilog +// flow. -SN 7-28-08 +// +// Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08 +// Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08 +// Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09 +// Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08 +// delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90 +// delay_we_90 ,delay_address,delay_ba_90 = +// --removed :assign #50 delay_dqnum = dqnum; +// --removed :assign #50 delay_dqpum = dqpum; +// --removed :assign #50 delay_dqnlm = dqnlm; +// --removed :assign #50 delay_dqplm = dqplm; +// --removed : delay_dqsIO_w_en_90_n +// --removed : delay_dqsIO_w_en_90_p +// --removed : delay_dqsIO_w_en_0 +// -- corrected spelling error: C_MEM_RTRAS +// Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09 +// -- rename the memc_wrapper.v to mcb_raw_wrapper.v +// Rev 1.7 -- .READEN is removed in IODRP2_MCB 1-28-09 +// -- connection has been updated +// Rev 1.8 -- update memory parameter equations. 1-30_2009 +// -- added portion of Soft IP +// -- CAL_CLK_DIV is not used but MCB still has it +// Rev 1.9 -- added Error checking for Invalid command to unidirectional port +// Rev 1.10 -- changed the backend connection so that Simulation will work while +// sw tools try to fix the model issues. 2-3-2009 +// sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions. +// It is acutally 180 degree difference. +// Rev 1.11 -- Added soft_calibration_top. +// Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009 +// Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines. +// Rev 1.14 -- Added minium condition for tRTP valud/ +// REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009 +// Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009 +// Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009 +// Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010 +// Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009. +// Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable +// Dynamic DQS calibration in Soft Calibration module. +// Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if +// RTT value is set to "disabled" +// -- Corrected the UIUDQSDEC connection between soft_calib and MCB. +// -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010 +// Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec . +// Rev 1.23 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE" +//************************************************************************************************************************* +`define DEBUG +`timescale 1ps / 1ps + +module mcb_raw_wrapper # + + ( + +parameter C_MEMCLK_PERIOD = 2500, // /Mem clk period (in ps) +parameter C_PORT_ENABLE = 6'b111111, // config1 : 6b'111111, config2: 4'b1111. config3 : 3'b111, config4: 2'b11, config5 1'b1 + // C_PORT_ENABLE[5] => User port 5, ...,C_PORT_ENABLE[0] => User port 0 +// Should the C_MEM_ADDR_ORDER made available to user ?? +parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN" , //RowBankCol//ADDR_ORDER_MC : 0: Bank Row Col 1: Row Bank Col. User Address mapping oreder + + + +//////////////////////////////////////////////////////////////////////////////////////////////// +// The parameter belows are not exposed to non-embedded users. + +// for now this arb_time_slot_x attributes will not exposed to user and will be generated from MIG tool +// to translate the logical port to physical port. For advance user, translate the logical port +// to physical port before passing them to this wrapper. +// MIG need to save the user setting in project file. +parameter C_ARB_NUM_TIME_SLOTS = 12, // For advance mode, allow user to either choose 10 or 12 +parameter C_ARB_TIME_SLOT_0 = 18'o012345, // Config 1: "B32_B32_X32_X32_X32_X32" +parameter C_ARB_TIME_SLOT_1 = 18'o123450, // User port 0 --->MCB port 0,User port 1 --->MCB port 1 +parameter C_ARB_TIME_SLOT_2 = 18'o234501, // User port 2 --->MCB port 2,User port 3 --->MCB port 3 +parameter C_ARB_TIME_SLOT_3 = 18'o345012, // User port 4 --->MCB port 4,User port 5 --->MCB port 5 +parameter C_ARB_TIME_SLOT_4 = 18'o450123, // Config 2: "B32_B32_B32_B32" +parameter C_ARB_TIME_SLOT_5 = 18'o501234, // User port 0 ---> MCB port 0 +parameter C_ARB_TIME_SLOT_6 = 18'o012345, // User port 1 ---> MCB port 1 +parameter C_ARB_TIME_SLOT_7 = 18'o123450, // User port 2 ---> MCB port 2 +parameter C_ARB_TIME_SLOT_8 = 18'o234501, // User port 3 ---> MCB port 4 +parameter C_ARB_TIME_SLOT_9 = 18'o345012, // Config 3: "B64_B32_B3" +parameter C_ARB_TIME_SLOT_10 = 18'o450123, // User port 0 ---> MCB port 0 +parameter C_ARB_TIME_SLOT_11 = 18'o501234, // User port 1 ---> MCB port 2 + // User port 2 ---> MCB port 4 + // Config 4: "B64_B64" + // User port 0 ---> MCB port 0 + // User port 1 ---> MCB port 2 + // Config 5 "B128" + // User port 0 ---> MCB port 0 +parameter C_PORT_CONFIG = "B128", + + + +// Memory Timings +parameter C_MEM_TRAS = 45000, //CEIL (tRAS/tCK) +parameter C_MEM_TRCD = 12500, //CEIL (tRCD/tCK) +parameter C_MEM_TREFI = 7800, //CEIL (tREFI/tCK) number of clocks +parameter C_MEM_TRFC = 127500, //CEIL (tRFC/tCK) +parameter C_MEM_TRP = 12500, //CEIL (tRP/tCK) +parameter C_MEM_TWR = 15000, //CEIL (tWR/tCK) +parameter C_MEM_TRTP = 7500, //CEIL (tRTP/tCK) +parameter C_MEM_TWTR = 7500, + +parameter C_NUM_DQ_PINS = 8, +parameter C_MEM_TYPE = "DDR3", +parameter C_MEM_DENSITY = "512M", +parameter C_MEM_BURST_LEN = 8, // MIG Rules for setting this parameter + // For DDR3 this one always set to 8; + // For DDR2 Config 1 : MemWidth x8,x16:=> 4; MemWidth x4 => 8 + // Config 2 : MemWidth x8,x16:=> 4; MemWidth x4 => 8 + // Config 3 : Data Port Width: 32 MemWidth x8,x16:=> 4; MemWidth x4 => 8 + // Data Port Width: 64 MemWidth x16 :=> 4; MemWidth x8,x4 => 8 + // Config 4 : Data Port Width: 64 MemWidth x16 :=> 4; MemWidth x4,x8, => 8 + // Config 5 : Data Port Width: 128 MemWidth x4, x8,x16: => 8 + + + +parameter C_MEM_CAS_LATENCY = 4, +parameter C_MEM_ADDR_WIDTH = 13, // extracted from selected Memory part +parameter C_MEM_BANKADDR_WIDTH = 3, // extracted from selected Memory part +parameter C_MEM_NUM_COL_BITS = 11, // extracted from selected Memory part + +parameter C_MEM_DDR3_CAS_LATENCY = 7, +parameter C_MEM_MOBILE_PA_SR = "FULL", //"FULL", "HALF" Mobile DDR Partial Array Self-Refresh +parameter C_MEM_DDR1_2_ODS = "FULL", //"FULL" :REDUCED" +parameter C_MEM_DDR3_ODS = "DIV6", +parameter C_MEM_DDR2_RTT = "50OHMS", +parameter C_MEM_DDR3_RTT = "DIV2", +parameter C_MEM_MDDR_ODS = "FULL", + +parameter C_MEM_DDR2_DIFF_DQS_EN = "YES", +parameter C_MEM_DDR2_3_PA_SR = "OFF", +parameter C_MEM_DDR3_CAS_WR_LATENCY = 5, // this parameter is hardcoded by MIG tool which depends on the memory clock frequency + //C_MEMCLK_PERIOD ave = 2.5ns to < 3.3 ns, CWL = 5 + //C_MEMCLK_PERIOD ave = 1.875ns to < 2.5 ns, CWL = 6 + //C_MEMCLK_PERIOD ave = 1.5ns to <1.875ns, CSL = 7 + //C_MEMCLK_PERIOD avg = 1.25ns to < 1.5ns , CWL = 8 + +parameter C_MEM_DDR3_AUTO_SR = "ENABLED", +parameter C_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL", +parameter C_MEM_DDR3_DYN_WRT_ODT = "OFF", +parameter C_MEM_TZQINIT_MAXCNT = 10'd512, // DDR3 Minimum delay between resets + +//Calibration +parameter C_MC_CALIB_BYPASS = "NO", +parameter C_MC_CALIBRATION_RA = 15'h0000, +parameter C_MC_CALIBRATION_BA = 3'h0, + +parameter C_CALIB_SOFT_IP = "TRUE", +parameter C_SKIP_IN_TERM_CAL = 1'b0, //provides option to skip the input termination calibration +parameter C_SKIP_DYNAMIC_CAL = 1'b0, //provides option to skip the dynamic delay calibration +parameter C_SKIP_DYN_IN_TERM = 1'b1, // provides option to skip the input termination calibration +parameter C_SIMULATION = "FALSE", // Tells us whether the design is being simulated or implemented + +////////////////LUMP DELAY Params //////////////////////////// +/// ADDED for 1.0 silicon support to bypass Calibration ////// +/// 07-10-09 chipl +////////////////////////////////////////////////////////////// +parameter LDQSP_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter UDQSP_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter LDQSN_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter UDQSN_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ0_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ1_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ2_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ3_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ4_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ5_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ6_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ7_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ8_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ9_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ10_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ11_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ12_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ13_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ14_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +parameter DQ15_TAP_DELAY_VAL = 0, // 0 to 255 inclusive +//************* +// MIG tool need to do DRC on this parameter to make sure this is valid Column address to avoid boundary crossing for the current Burst Size setting. +parameter C_MC_CALIBRATION_CA = 12'h000, +parameter C_MC_CALIBRATION_CLK_DIV = 1, +parameter C_MC_CALIBRATION_MODE = "CALIBRATION" , // "CALIBRATION", "NOCALIBRATION" +parameter C_MC_CALIBRATION_DELAY = "HALF", // "QUARTER", "HALF","THREEQUARTER", "FULL" + +parameter C_P0_MASK_SIZE = 4, +parameter C_P0_DATA_PORT_SIZE = 32, +parameter C_P1_MASK_SIZE = 4, +parameter C_P1_DATA_PORT_SIZE = 32 + + ) + ( + + // high-speed PLL clock interface + + input sysclk_2x, + input sysclk_2x_180, + input pll_ce_0, + input pll_ce_90, + input pll_lock, + input sys_rst, + // Not needed as ioi netlist are not used +//*********************************************************************************** +// Below User Port siganls needs to be customized when generating codes from MIG tool +// The corresponding internal codes that directly use the commented out port signals +// needs to be removed when gernerating wrapper outputs. +//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + + //User Port0 Interface Signals + // p0_xxxx signals shows up in Config 1 , Config 2 , Config 3, Config4 and Config 5 + // cmd port 0 signals + + input p0_arb_en, + input p0_cmd_clk, + input p0_cmd_en, + input [2:0] p0_cmd_instr, + input [5:0] p0_cmd_bl, + input [29:0] p0_cmd_byte_addr, + output p0_cmd_empty, + output p0_cmd_full, + + // Data Wr Port signals + // p0_wr_xx signals shows up in Config 1 + // p0_wr_xx signals shows up in Config 2 + // p0_wr_xx signals shows up in Config 3 + // p0_wr_xx signals shows up in Config 4 + // p0_wr_xx signals shows up in Config 5 + + input p0_wr_clk, + input p0_wr_en, + input [C_P0_MASK_SIZE - 1:0] p0_wr_mask, + input [C_P0_DATA_PORT_SIZE - 1:0] p0_wr_data, + output p0_wr_full, // + output p0_wr_empty,// + output [6:0] p0_wr_count,// + output p0_wr_underrun,// + output p0_wr_error,// + + //Data Rd Port signals + // p0_rd_xx signals shows up in Config 1 + // p0_rd_xx signals shows up in Config 2 + // p0_rd_xx signals shows up in Config 3 + // p0_rd_xx signals shows up in Config 4 + // p0_rd_xx signals shows up in Config 5 + + input p0_rd_clk, + input p0_rd_en, + output [C_P0_DATA_PORT_SIZE - 1:0] p0_rd_data, + output p0_rd_full,// + output p0_rd_empty,// + output [6:0] p0_rd_count, + output p0_rd_overflow,// + output p0_rd_error,// + + + //**************************** + //User Port1 Interface Signals + // This group of signals only appear on Config 1,2,3,4 when generated from MIG tool + + input p1_arb_en, + input p1_cmd_clk, + input p1_cmd_en, + input [2:0] p1_cmd_instr, + input [5:0] p1_cmd_bl, + input [29:0] p1_cmd_byte_addr, + output p1_cmd_empty, + output p1_cmd_full, + + // Data Wr Port signals + input p1_wr_clk, + input p1_wr_en, + input [C_P1_MASK_SIZE - 1:0] p1_wr_mask, + input [C_P1_DATA_PORT_SIZE - 1:0] p1_wr_data, + output p1_wr_full, + output p1_wr_empty, + output [6:0] p1_wr_count, + output p1_wr_underrun, + output p1_wr_error, + + //Data Rd Port signals + input p1_rd_clk, + input p1_rd_en, + output [C_P1_DATA_PORT_SIZE - 1:0] p1_rd_data, + output p1_rd_full, + output p1_rd_empty, + output [6:0] p1_rd_count, + output p1_rd_overflow, + output p1_rd_error, + + + //**************************** + //User Port2 Interface Signals + // This group of signals only appear on Config 1,2,3 when generated from MIG tool + // p2_xxxx signals shows up in Config 1 , Config 2 and Config 3 + // p_cmd port 2 signals + + input p2_arb_en, + input p2_cmd_clk, + input p2_cmd_en, + input [2:0] p2_cmd_instr, + input [5:0] p2_cmd_bl, + input [29:0] p2_cmd_byte_addr, + output p2_cmd_empty, + output p2_cmd_full, + + // Data Wr Port signals + // p2_wr_xx signals shows up in Config 1 and Wr Dir + // p2_wr_xx signals shows up in Config 2 + // p2_wr_xx signals shows up in Config 3 + + input p2_wr_clk, + input p2_wr_en, + input [3:0] p2_wr_mask, + input [31:0] p2_wr_data, + output p2_wr_full, + output p2_wr_empty, + output [6:0] p2_wr_count, + output p2_wr_underrun, + output p2_wr_error, + + //Data Rd Port signals + // p2_rd_xx signals shows up in Config 1 and Rd Dir + // p2_rd_xx signals shows up in Config 2 + // p2_rd_xx signals shows up in Config 3 + + input p2_rd_clk, + input p2_rd_en, + output [31:0] p2_rd_data, + output p2_rd_full, + output p2_rd_empty, + output [6:0] p2_rd_count, + output p2_rd_overflow, + output p2_rd_error, + + + //**************************** + //User Port3 Interface Signals + // This group of signals only appear on Config 1,2 when generated from MIG tool + + input p3_arb_en, + input p3_cmd_clk, + input p3_cmd_en, + input [2:0] p3_cmd_instr, + input [5:0] p3_cmd_bl, + input [29:0] p3_cmd_byte_addr, + output p3_cmd_empty, + output p3_cmd_full, + + // Data Wr Port signals + // p3_wr_xx signals shows up in Config 1 and Wr Dir + // p3_wr_xx signals shows up in Config 2 + + input p3_wr_clk, + input p3_wr_en, + input [3:0] p3_wr_mask, + input [31:0] p3_wr_data, + output p3_wr_full, + output p3_wr_empty, + output [6:0] p3_wr_count, + output p3_wr_underrun, + output p3_wr_error, + + //Data Rd Port signals + // p3_rd_xx signals shows up in Config 1 and Rd Dir when generated from MIG ttols + // p3_rd_xx signals shows up in Config 2 + + input p3_rd_clk, + input p3_rd_en, + output [31:0] p3_rd_data, + output p3_rd_full, + output p3_rd_empty, + output [6:0] p3_rd_count, + output p3_rd_overflow, + output p3_rd_error, + //**************************** + //User Port4 Interface Signals + // This group of signals only appear on Config 1,2,3,4 when generated from MIG tool + // p4_xxxx signals only shows up in Config 1 + + input p4_arb_en, + input p4_cmd_clk, + input p4_cmd_en, + input [2:0] p4_cmd_instr, + input [5:0] p4_cmd_bl, + input [29:0] p4_cmd_byte_addr, + output p4_cmd_empty, + output p4_cmd_full, + + // Data Wr Port signals + // p4_wr_xx signals only shows up in Config 1 and Wr Dir + + input p4_wr_clk, + input p4_wr_en, + input [3:0] p4_wr_mask, + input [31:0] p4_wr_data, + output p4_wr_full, + output p4_wr_empty, + output [6:0] p4_wr_count, + output p4_wr_underrun, + output p4_wr_error, + + //Data Rd Port signals + // p4_rd_xx signals only shows up in Config 1 and Rd Dir + + input p4_rd_clk, + input p4_rd_en, + output [31:0] p4_rd_data, + output p4_rd_full, + output p4_rd_empty, + output [6:0] p4_rd_count, + output p4_rd_overflow, + output p4_rd_error, + + + //**************************** + //User Port5 Interface Signals + // p5_xxxx signals only shows up in Config 1; p5_wr_xx or p5_rd_xx depends on the user port settings + + input p5_arb_en, + input p5_cmd_clk, + input p5_cmd_en, + input [2:0] p5_cmd_instr, + input [5:0] p5_cmd_bl, + input [29:0] p5_cmd_byte_addr, + output p5_cmd_empty, + output p5_cmd_full, + + // Data Wr Port signals + input p5_wr_clk, + input p5_wr_en, + input [3:0] p5_wr_mask, + input [31:0] p5_wr_data, + output p5_wr_full, + output p5_wr_empty, + output [6:0] p5_wr_count, + output p5_wr_underrun, + output p5_wr_error, + + //Data Rd Port signals + input p5_rd_clk, + input p5_rd_en, + output [31:0] p5_rd_data, + output p5_rd_full, + output p5_rd_empty, + output [6:0] p5_rd_count, + output p5_rd_overflow, + output p5_rd_error, + +//***************************************************** + // memory interface signals + output [C_MEM_ADDR_WIDTH-1:0] mcbx_dram_addr, + output [C_MEM_BANKADDR_WIDTH-1:0] mcbx_dram_ba, + output mcbx_dram_ras_n, + output mcbx_dram_cas_n, + output mcbx_dram_we_n, + + output mcbx_dram_cke, + output mcbx_dram_clk, + output mcbx_dram_clk_n, + inout [C_NUM_DQ_PINS-1:0] mcbx_dram_dq, + inout mcbx_dram_dqs, + inout mcbx_dram_dqs_n, + inout mcbx_dram_udqs, + inout mcbx_dram_udqs_n, + + output mcbx_dram_udm, + output mcbx_dram_ldm, + output mcbx_dram_odt, + output mcbx_dram_ddr3_rst, + // Calibration signals + input calib_recal, // Input signal to trigger calibration + // output calib_done, // 0=calibration not done or is in progress. + // 1=calibration is complete. Also a MEM_READY indicator + + //Input - RZQ pin from board - expected to have a 2*R resistor to ground + //Input - Z-stated IO pin - either unbonded IO, or IO garanteed not to be driven externally + + inout rzq, // RZQ pin from board - expected to have a 2*R resistor to ground + inout zio, // Z-stated IO pin - either unbonded IO, or IO garanteed not to be driven externally + // new added signals ********************************* + // these signals are for dynamic Calibration IP + input ui_read, + input ui_add, + input ui_cs, + input ui_clk, + input ui_sdi, + input [4:0] ui_addr, + input ui_broadcast, + input ui_drp_update, + input ui_done_cal, + input ui_cmd, + input ui_cmd_in, + input ui_cmd_en, + input [3:0] ui_dqcount, + input ui_dq_lower_dec, + input ui_dq_lower_inc, + input ui_dq_upper_dec, + input ui_dq_upper_inc, + input ui_udqs_inc, + input ui_udqs_dec, + input ui_ldqs_inc, + input ui_ldqs_dec, + output [7:0] uo_data, + output uo_data_valid, + output uo_done_cal, + output uo_cmd_ready_in, + output uo_refrsh_flag, + output uo_cal_start, + output uo_sdo, + output [31:0] status, + input selfrefresh_enter, + output selfrefresh_mode + ); + function integer cdiv (input integer num, + input integer div); // ceiling divide + begin + cdiv = (num/div) + (((num%div)>0) ? 1 : 0); + end + endfunction // cdiv + +// parameters added by AM for OSERDES2 12/09/2008, these parameters may not have to change +localparam C_OSERDES2_DATA_RATE_OQ = "SDR"; //SDR, DDR +localparam C_OSERDES2_DATA_RATE_OT = "SDR"; //SDR, DDR +localparam C_OSERDES2_SERDES_MODE_MASTER = "MASTER"; //MASTER, SLAVE +localparam C_OSERDES2_SERDES_MODE_SLAVE = "SLAVE"; //MASTER, SLAVE +localparam C_OSERDES2_OUTPUT_MODE_SE = "SINGLE_ENDED"; //SINGLE_ENDED, DIFFERENTIAL +localparam C_OSERDES2_OUTPUT_MODE_DIFF = "DIFFERENTIAL"; + +localparam C_BUFPLL_0_LOCK_SRC = "LOCK_TO_0"; + +localparam C_DQ_IODRP2_DATA_RATE = "SDR"; +localparam C_DQ_IODRP2_SERDES_MODE_MASTER = "MASTER"; +localparam C_DQ_IODRP2_SERDES_MODE_SLAVE = "SLAVE"; + +localparam C_DQS_IODRP2_DATA_RATE = "SDR"; +localparam C_DQS_IODRP2_SERDES_MODE_MASTER = "MASTER"; +localparam C_DQS_IODRP2_SERDES_MODE_SLAVE = "SLAVE"; + + + + + + +// MIG always set the below ADD_LATENCY to zero +localparam C_MEM_DDR3_ADD_LATENCY = "OFF"; +localparam C_MEM_DDR2_ADD_LATENCY = 0; +localparam C_MEM_MOBILE_TC_SR = 0; // not supported + + +////////////////////////////////////////////////////////////////////////////////// + // Attribute Declarations + // Attributes set from GUI + // + // + // the local param for the time slot varis according to User Port Configuration + // This section also needs to be customized when gernerating wrapper outputs. + //***************************************************************************** + + +// For Configuration 1 and this section will be used in RAW file +localparam arbtimeslot0 = {C_ARB_TIME_SLOT_0 }; +localparam arbtimeslot1 = {C_ARB_TIME_SLOT_1 }; +localparam arbtimeslot2 = {C_ARB_TIME_SLOT_2 }; +localparam arbtimeslot3 = {C_ARB_TIME_SLOT_3 }; +localparam arbtimeslot4 = {C_ARB_TIME_SLOT_4 }; +localparam arbtimeslot5 = {C_ARB_TIME_SLOT_5 }; +localparam arbtimeslot6 = {C_ARB_TIME_SLOT_6 }; +localparam arbtimeslot7 = {C_ARB_TIME_SLOT_7 }; +localparam arbtimeslot8 = {C_ARB_TIME_SLOT_8 }; +localparam arbtimeslot9 = {C_ARB_TIME_SLOT_9 }; +localparam arbtimeslot10 = {C_ARB_TIME_SLOT_10 }; +localparam arbtimeslot11 = {C_ARB_TIME_SLOT_11 }; + + +// convert the memory timing to memory clock units. I +localparam MEM_RAS_VAL = ((C_MEM_TRAS + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD); +localparam MEM_RCD_VAL = ((C_MEM_TRCD + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD); +localparam MEM_REFI_VAL = ((C_MEM_TREFI + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) - 25; +localparam MEM_RFC_VAL = ((C_MEM_TRFC + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD); +localparam MEM_RP_VAL = ((C_MEM_TRP + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD); +localparam MEM_WR_VAL = ((C_MEM_TWR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD); +localparam MEM_RTP_CK = cdiv(C_MEM_TRTP,C_MEMCLK_PERIOD); +localparam MEM_RTP_VAL = (C_MEM_TYPE == "DDR3") ? (MEM_RTP_CK < 4) ? 4 : MEM_RTP_CK + : (MEM_RTP_CK < 2) ? 2 : MEM_RTP_CK; +localparam MEM_WTR_VAL = (C_MEM_TYPE == "DDR") ? 2 : + (C_MEM_TYPE == "DDR3") ? 4 : + (C_MEM_TYPE == "MDDR") ? C_MEM_TWTR : + (C_MEM_TYPE == "LPDDR") ? C_MEM_TWTR : + ((C_MEM_TYPE == "DDR2") && (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) ? ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) : + (C_MEM_TYPE == "DDR2") ? 2 + : 3 ; +localparam C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TYPE != "DDR2") ? 5: ((C_MEM_TWR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD); +localparam C_MEM_DDR3_WRT_RECOVERY = (C_MEM_TYPE != "DDR3") ? 5: ((C_MEM_TWR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD); +//localparam MEM_TYPE = (C_MEM_TYPE == "LPDDR") ? "MDDR": C_MEM_TYPE; + + + +//////////////////////////////////////////////////////////////////////////// +// wire Declarations +//////////////////////////////////////////////////////////////////////////// + + + + + +wire [31:0] addr_in0; +reg [127:0] allzero = 0; + + +// UNISIM Model <-> IOI +//dqs clock network interface +wire dqs_out_p; +wire dqs_out_n; + +wire dqs_sys_p; //from dqs_gen to IOclk network +wire dqs_sys_n; //from dqs_gen to IOclk network +wire udqs_sys_p; +wire udqs_sys_n; + +wire dqs_p; // open net now ? +wire dqs_n; // open net now ? + + + +// IOI and IOB enable/tristate interface +wire dqIO_w_en_0; //enable DQ pads +wire dqsIO_w_en_90_p; //enable p side of DQS +wire dqsIO_w_en_90_n; //enable n side of DQS + + +//memory chip control interface +wire [14:0] address_90; +wire [2:0] ba_90; +wire ras_90; +wire cas_90; +wire we_90 ; +wire cke_90; +wire odt_90; +wire rst_90; + +// calibration IDELAY control signals +wire ioi_drp_clk; //DRP interface - synchronous clock output +wire [4:0] ioi_drp_addr; //DRP interface - IOI selection +wire ioi_drp_sdo; //DRP interface - serial output for commmands +wire ioi_drp_sdi; //DRP interface - serial input for commands +wire ioi_drp_cs; //DRP interface - chip select doubles as DONE signal +wire ioi_drp_add; //DRP interface - serial address signal +wire ioi_drp_broadcast; +wire ioi_drp_train; + + + // Calibration datacapture siganls + +wire [3:0]dqdonecount; //select signal for the datacapture 16 to 1 mux +wire dq_in_p; //positive signal sent to calibration logic +wire dq_in_n; //negative signal sent to calibration logic +wire cal_done; + + +//DQS calibration interface +wire udqs_n; +wire udqs_p; + + +wire udqs_dqocal_p; +wire udqs_dqocal_n; + + +// MUI enable interface +wire df_en_n90 ; + +//INTERNAL SIGNAL FOR DRP chain +// IOI <-> MUI +wire ioi_int_tmp; + +wire [15:0]dqo_n; +wire [15:0]dqo_p; +wire dqnlm; +wire dqplm; +wire dqnum; +wire dqpum; + + +// IOI <-> IOB routes +wire [C_MEM_ADDR_WIDTH-1:0]ioi_addr; +wire [C_MEM_BANKADDR_WIDTH-1:0]ioi_ba; +wire ioi_cas; +wire ioi_ck; +wire ioi_ckn; +wire ioi_cke; +wire [C_NUM_DQ_PINS-1:0]ioi_dq; +wire ioi_dqs; +wire ioi_dqsn; +wire ioi_udqs; +wire ioi_udqsn; +wire ioi_odt; +wire ioi_ras; +wire ioi_rst; +wire ioi_we; +wire ioi_udm; +wire ioi_ldm; + +wire [15:0] in_dq; +wire [C_NUM_DQ_PINS-1:0] in_pre_dq; + + + +wire in_dqs; +wire in_pre_dqsp; +wire in_pre_dqsn; +wire in_pre_udqsp; +wire in_pre_udqsn; +wire in_udqs; + // Memory tri-state control signals +wire [C_MEM_ADDR_WIDTH-1:0]t_addr; +wire [C_MEM_BANKADDR_WIDTH-1:0]t_ba; +wire t_cas; +wire t_ck ; +wire t_ckn; +wire t_cke; +wire [C_NUM_DQ_PINS-1:0]t_dq; +wire t_dqs; +wire t_dqsn; +wire t_udqs; +wire t_udqsn; +wire t_odt; +wire t_ras; +wire t_rst; +wire t_we ; + + +wire t_udm ; +wire t_ldm ; + + + +wire idelay_dqs_ioi_s; +wire idelay_dqs_ioi_m; +wire idelay_udqs_ioi_s; +wire idelay_udqs_ioi_m; + + +wire dqs_pin; +wire udqs_pin; + +// USER Interface signals + + +// translated memory addresses +wire [14:0]p0_cmd_ra; +wire [2:0]p0_cmd_ba; +wire [11:0]p0_cmd_ca; +wire [14:0]p1_cmd_ra; +wire [2:0]p1_cmd_ba; +wire [11:0]p1_cmd_ca; +wire [14:0]p2_cmd_ra; +wire [2:0]p2_cmd_ba; +wire [11:0]p2_cmd_ca; +wire [14:0]p3_cmd_ra; +wire [2:0]p3_cmd_ba; +wire [11:0]p3_cmd_ca; +wire [14:0]p4_cmd_ra; +wire [2:0]p4_cmd_ba; +wire [11:0]p4_cmd_ca; +wire [14:0]p5_cmd_ra; +wire [2:0]p5_cmd_ba; +wire [11:0]p5_cmd_ca; + + // user command wires mapped from logical ports to physical ports +wire mig_p0_arb_en; +wire mig_p0_cmd_clk; +wire mig_p0_cmd_en; +wire [14:0] mig_p0_cmd_ra; +wire [2:0] mig_p0_cmd_ba; +wire [11:0] mig_p0_cmd_ca; + +wire [2:0] mig_p0_cmd_instr; +wire [5:0] mig_p0_cmd_bl; +wire mig_p0_cmd_empty; +wire mig_p0_cmd_full; + + +wire mig_p1_arb_en; +wire mig_p1_cmd_clk; +wire mig_p1_cmd_en; +wire [14:0] mig_p1_cmd_ra; +wire [2:0] mig_p1_cmd_ba; +wire [11:0] mig_p1_cmd_ca; + +wire [2:0] mig_p1_cmd_instr; +wire [5:0] mig_p1_cmd_bl; +wire mig_p1_cmd_empty; +wire mig_p1_cmd_full; + +wire mig_p2_arb_en; +wire mig_p2_cmd_clk; +wire mig_p2_cmd_en; +wire [14:0] mig_p2_cmd_ra; +wire [2:0] mig_p2_cmd_ba; +wire [11:0] mig_p2_cmd_ca; + +wire [2:0] mig_p2_cmd_instr; +wire [5:0] mig_p2_cmd_bl; +wire mig_p2_cmd_empty; +wire mig_p2_cmd_full; + +wire mig_p3_arb_en; +wire mig_p3_cmd_clk; +wire mig_p3_cmd_en; +wire [14:0] mig_p3_cmd_ra; +wire [2:0] mig_p3_cmd_ba; +wire [11:0] mig_p3_cmd_ca; + +wire [2:0] mig_p3_cmd_instr; +wire [5:0] mig_p3_cmd_bl; +wire mig_p3_cmd_empty; +wire mig_p3_cmd_full; + +wire mig_p4_arb_en; +wire mig_p4_cmd_clk; +wire mig_p4_cmd_en; +wire [14:0] mig_p4_cmd_ra; +wire [2:0] mig_p4_cmd_ba; +wire [11:0] mig_p4_cmd_ca; + +wire [2:0] mig_p4_cmd_instr; +wire [5:0] mig_p4_cmd_bl; +wire mig_p4_cmd_empty; +wire mig_p4_cmd_full; + +wire mig_p5_arb_en; +wire mig_p5_cmd_clk; +wire mig_p5_cmd_en; +wire [14:0] mig_p5_cmd_ra; +wire [2:0] mig_p5_cmd_ba; +wire [11:0] mig_p5_cmd_ca; + +wire [2:0] mig_p5_cmd_instr; +wire [5:0] mig_p5_cmd_bl; +wire mig_p5_cmd_empty; +wire mig_p5_cmd_full; + +wire mig_p0_wr_clk; +wire mig_p0_rd_clk; +wire mig_p1_wr_clk; +wire mig_p1_rd_clk; +wire mig_p2_clk; +wire mig_p3_clk; +wire mig_p4_clk; +wire mig_p5_clk; + +wire mig_p0_wr_en; +wire mig_p0_rd_en; +wire mig_p1_wr_en; +wire mig_p1_rd_en; +wire mig_p2_en; +wire mig_p3_en; +wire mig_p4_en; +wire mig_p5_en; + + +wire [31:0]mig_p0_wr_data; +wire [31:0]mig_p1_wr_data; +wire [31:0]mig_p2_wr_data; +wire [31:0]mig_p3_wr_data; +wire [31:0]mig_p4_wr_data; +wire [31:0]mig_p5_wr_data; + + +wire [C_P0_MASK_SIZE-1:0]mig_p0_wr_mask; +wire [C_P1_MASK_SIZE-1:0]mig_p1_wr_mask; +wire [3:0]mig_p2_wr_mask; +wire [3:0]mig_p3_wr_mask; +wire [3:0]mig_p4_wr_mask; +wire [3:0]mig_p5_wr_mask; + + +wire [31:0]mig_p0_rd_data; +wire [31:0]mig_p1_rd_data; +wire [31:0]mig_p2_rd_data; +wire [31:0]mig_p3_rd_data; +wire [31:0]mig_p4_rd_data; +wire [31:0]mig_p5_rd_data; + +wire mig_p0_rd_overflow; +wire mig_p1_rd_overflow; +wire mig_p2_overflow; +wire mig_p3_overflow; + +wire mig_p4_overflow; +wire mig_p5_overflow; + +wire mig_p0_wr_underrun; +wire mig_p1_wr_underrun; +wire mig_p2_underrun; +wire mig_p3_underrun; +wire mig_p4_underrun; +wire mig_p5_underrun; + +wire mig_p0_rd_error; +wire mig_p0_wr_error; +wire mig_p1_rd_error; +wire mig_p1_wr_error; +wire mig_p2_error; +wire mig_p3_error; +wire mig_p4_error; +wire mig_p5_error; + + +wire [6:0]mig_p0_wr_count; +wire [6:0]mig_p1_wr_count; +wire [6:0]mig_p0_rd_count; +wire [6:0]mig_p1_rd_count; + +wire [6:0]mig_p2_count; +wire [6:0]mig_p3_count; +wire [6:0]mig_p4_count; +wire [6:0]mig_p5_count; + +wire mig_p0_wr_full; +wire mig_p1_wr_full; + +wire mig_p0_rd_empty; +wire mig_p1_rd_empty; +wire mig_p0_wr_empty; +wire mig_p1_wr_empty; +wire mig_p0_rd_full; +wire mig_p1_rd_full; +wire mig_p2_full; +wire mig_p3_full; +wire mig_p4_full; +wire mig_p5_full; +wire mig_p2_empty; +wire mig_p3_empty; +wire mig_p4_empty; +wire mig_p5_empty; + +// SELFREESH control signal for suspend feature +wire selfrefresh_mcb_enter; +wire selfrefresh_mcb_mode ; +// Testing Interface signals +wire tst_cmd_test_en; +wire [7:0] tst_sel; +wire [15:0] tst_in; +wire tst_scan_clk; +wire tst_scan_rst; +wire tst_scan_set; +wire tst_scan_en; +wire tst_scan_in; +wire tst_scan_mode; + +wire p0w_tst_en; +wire p0r_tst_en; +wire p1w_tst_en; +wire p1r_tst_en; +wire p2_tst_en; +wire p3_tst_en; +wire p4_tst_en; +wire p5_tst_en; + +wire p0_tst_wr_clk_en; +wire p0_tst_rd_clk_en; +wire p1_tst_wr_clk_en; +wire p1_tst_rd_clk_en; +wire p2_tst_clk_en; +wire p3_tst_clk_en; +wire p4_tst_clk_en; +wire p5_tst_clk_en; + +wire [3:0] p0w_tst_wr_mode; +wire [3:0] p0r_tst_mode; +wire [3:0] p1w_tst_wr_mode; +wire [3:0] p1r_tst_mode; +wire [3:0] p2_tst_mode; +wire [3:0] p3_tst_mode; +wire [3:0] p4_tst_mode; +wire [3:0] p5_tst_mode; + +wire p0r_tst_pin_en; +wire p0w_tst_pin_en; +wire p1r_tst_pin_en; +wire p1w_tst_pin_en; +wire p2_tst_pin_en; +wire p3_tst_pin_en; +wire p4_tst_pin_en; +wire p5_tst_pin_en; +wire p0w_tst_overflow; +wire p1w_tst_overflow; + +wire [3:0] p0r_tst_mask_o; +wire [3:0] p0w_tst_mask_o; +wire [3:0] p1r_tst_mask_o; +wire [3:0] p1w_tst_mask_o; +wire [3:0] p2_tst_mask_o; +wire [3:0] p3_tst_mask_o; +wire [3:0] p4_tst_mask_o; +wire [3:0] p5_tst_mask_o; +wire [3:0] p0r_tst_wr_mask; + +wire [3:0] p1r_tst_wr_mask; +wire [31:0] p1r_tst_wr_data; +wire [31:0] p0r_tst_wr_data; +wire [31:0] p0w_tst_rd_data; +wire [31:0] p1w_tst_rd_data; + +wire [38:0] tst_cmd_out; +wire MCB_SYSRST; +wire ioclk0; +wire ioclk90; +wire mcb_ui_clk; +wire hard_done_cal; +wire cke_train; +//testing +wire ioi_drp_update; +wire [7:0] aux_sdi_sdo; + +wire [4:0] mcb_ui_addr; +wire [3:0] mcb_ui_dqcount; +reg syn_uiclk_pll_lock; + +wire int_sys_rst /* synthesis syn_maxfan = 1 */; +// synthesis attribute max_fanout of int_sys_rst is 1 + + +reg [15:0] wait_200us_counter; +reg cke_train_reg; +reg wait_200us_done_r1,wait_200us_done_r2; + +assign ioclk0 = sysclk_2x; +assign ioclk90 = sysclk_2x_180; + +//Added 2/22 - Add flop to pll_lock status signal to improve timing +always @ (posedge ui_clk) +begin + + syn_uiclk_pll_lock <= pll_lock; + +end +assign int_sys_rst = sys_rst | ~syn_uiclk_pll_lock; + +//Address Remapping +// Byte Address remapping +// +// Bank Address[x:0] & Row Address[x:0] & Column Address[x:0] +// column address remap for port 0 + generate // port bus remapping sections for CONFIG 2 15,3,12 + +if(C_NUM_DQ_PINS == 16) begin : x16_Addr + if (C_MEM_ADDR_ORDER == "ROW_BANK_COLUMN") begin // C_MEM_ADDR_ORDER = 0 : Bank Row Column + // port 0 address remapping + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p0_cmd_ca = p0_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p0_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p0_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + + // port 1 address remapping + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p1_cmd_ca = p1_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p1_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p1_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + // port 2 address remapping + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p2_cmd_ca = p2_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p2_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p2_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + // port 3 address remapping + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p3_cmd_ca = p3_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p3_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p3_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + // port 4 address remapping + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p4_cmd_ca = p4_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p4_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p4_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + // port 5 address remapping + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS :C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p5_cmd_ca = p5_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p5_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p5_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + + + + end + + else // ***************C_MEM_ADDR_ORDER = 1 : Row Bank Column + begin + // port 0 address remapping + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) + assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p0_cmd_ca = p0_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p0_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p0_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + + // port 1 address remapping + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) + assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p1_cmd_ca = p1_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p1_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p1_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + // port 2 address remapping + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) + assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p2_cmd_ca = p2_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p2_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p2_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + // port 3 address remapping + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) + assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p3_cmd_ca = p3_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p3_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p3_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + // port 4 address remapping + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) + assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p4_cmd_ca = p4_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p4_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p4_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + // port 5 address remapping + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]; + else + assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) + assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]; + else + assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS : C_MEM_NUM_COL_BITS + 1]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p5_cmd_ca = p5_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]; + else + assign p5_cmd_ca = {allzero[12:C_MEM_NUM_COL_BITS + 1], p5_cmd_byte_addr[C_MEM_NUM_COL_BITS : 1]}; + + + end + +end else if(C_NUM_DQ_PINS == 8) begin : x8_Addr + if (C_MEM_ADDR_ORDER == "ROW_BANK_COLUMN") begin // C_MEM_ADDR_ORDER = 1 : Bank Row Column + // port 0 address remapping + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10 + else + assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10 + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p0_cmd_ca[11:0] = p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p0_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + + // port 1 address remapping + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10 + else + assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10 + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p1_cmd_ca[11:0] = p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p1_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + + // port 2 address remapping + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10 + else + assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,2,10 *** + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p2_cmd_ca[11:0] = p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p2_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + + + // port 3 address remapping + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10 + else + assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10 + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p3_cmd_ca[11:0] = p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p3_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + + // port 4 address remapping + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10 + else + assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10 + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p4_cmd_ca[11:0] = p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p4_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + + // port 5 address remapping + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; //14,3,10 + else + assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; //14,3,10 + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p5_cmd_ca[11:0] = p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p5_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + end + + else // x8 ***************C_MEM_ADDR_ORDER = 0 : Bank Row Column + begin + // port 0 address remapping + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; + else + assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p0_cmd_ca[11:0] = p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p0_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + + // port 1 address remapping + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; + else + assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p1_cmd_ca[11:0] = p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p1_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + //port 2 address remapping + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank 2,13,10 24,23 + assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; + else + assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p2_cmd_ca[11:0] = p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p2_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + // port 3 address remapping + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; + else + assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p3_cmd_ca[11:0] = p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p3_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + + // port 4 address remapping + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; + else + assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p4_cmd_ca[11:0] = p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p4_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + // port 5 address remapping + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]; + else + assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH], + p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]; + else + assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 : C_MEM_NUM_COL_BITS ]}; + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p5_cmd_ca[11:0] = p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]; + else + assign p5_cmd_ca[11:0] = {allzero[11 : C_MEM_NUM_COL_BITS] , p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 1 : 0]}; + + end + + // + +end else if(C_NUM_DQ_PINS == 4) begin : x4_Addr + + if (C_MEM_ADDR_ORDER == "ROW_BANK_COLUMN") begin // C_MEM_ADDR_ORDER = 1 : Row Bank Column + + // port 0 address remapping + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p0_cmd_ca = {p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11 + else + assign p0_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + + + // port 1 address remapping + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p1_cmd_ca = {p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11 + else + assign p1_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + + // port 2 address remapping + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p2_cmd_ca = {p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11 + else + assign p2_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + + // port 3 address remapping + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p3_cmd_ca = {p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11 + else + assign p3_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + + + + if(C_PORT_CONFIG == "B32_B32_R32_R32_R32_R32" || + C_PORT_CONFIG == "B32_B32_R32_R32_R32_W32" || + C_PORT_CONFIG == "B32_B32_R32_R32_W32_R32" || + C_PORT_CONFIG == "B32_B32_R32_R32_W32_W32" || + C_PORT_CONFIG == "B32_B32_R32_W32_R32_R32" || + C_PORT_CONFIG == "B32_B32_R32_W32_R32_W32" || + C_PORT_CONFIG == "B32_B32_R32_W32_W32_R32" || + C_PORT_CONFIG == "B32_B32_R32_W32_W32_W32" || + C_PORT_CONFIG == "B32_B32_W32_R32_R32_R32" || + C_PORT_CONFIG == "B32_B32_W32_R32_R32_W32" || + C_PORT_CONFIG == "B32_B32_W32_R32_W32_R32" || + C_PORT_CONFIG == "B32_B32_W32_R32_W32_W32" || + C_PORT_CONFIG == "B32_B32_W32_W32_R32_R32" || + C_PORT_CONFIG == "B32_B32_W32_W32_R32_W32" || + C_PORT_CONFIG == "B32_B32_W32_W32_W32_R32" || + C_PORT_CONFIG == "B32_B32_W32_W32_W32_W32" + ) //begin : x4_Addr_CFG1_OR_CFG2 + begin + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p4_cmd_ca = {p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11 + else + assign p4_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p5_cmd_ca = {p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; //14,3,11 + else + assign p5_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + + end + + + end + else // C_MEM_ADDR_ORDER = 1 : Row Bank Column + begin + + // port 0 address remapping + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p0_cmd_ba = p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p0_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p0_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p0_cmd_ra = p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p0_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p0_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p0_cmd_ca = {p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + else + assign p0_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p0_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + + + // port 1 address remapping + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p1_cmd_ba = p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p1_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p1_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p1_cmd_ra = p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p1_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p1_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p1_cmd_ca = {p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + else + assign p1_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p1_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + // port 2 address remapping + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p2_cmd_ba = p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p2_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p2_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + //*** + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p2_cmd_ra = p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p2_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p2_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p2_cmd_ca = {p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + else + assign p2_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p2_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + // port 3 address remapping + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p3_cmd_ba = p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p3_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p3_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p3_cmd_ra = p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p3_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p3_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p3_cmd_ca = {p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + else + assign p3_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p3_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + + + if(C_PORT_CONFIG == "B32_B32_R32_R32_R32_R32" || + C_PORT_CONFIG == "B32_B32_R32_R32_R32_W32" || + C_PORT_CONFIG == "B32_B32_R32_R32_W32_R32" || + C_PORT_CONFIG == "B32_B32_R32_R32_W32_W32" || + C_PORT_CONFIG == "B32_B32_R32_W32_R32_R32" || + C_PORT_CONFIG == "B32_B32_R32_W32_R32_W32" || + C_PORT_CONFIG == "B32_B32_R32_W32_W32_R32" || + C_PORT_CONFIG == "B32_B32_R32_W32_W32_W32" || + C_PORT_CONFIG == "B32_B32_W32_R32_R32_R32" || + C_PORT_CONFIG == "B32_B32_W32_R32_R32_W32" || + C_PORT_CONFIG == "B32_B32_W32_R32_W32_R32" || + C_PORT_CONFIG == "B32_B32_W32_R32_W32_W32" || + C_PORT_CONFIG == "B32_B32_W32_W32_R32_R32" || + C_PORT_CONFIG == "B32_B32_W32_W32_R32_W32" || + C_PORT_CONFIG == "B32_B32_W32_W32_W32_R32" || + C_PORT_CONFIG == "B32_B32_W32_W32_W32_W32" + ) //begin : x4_Addr_CFG1_OR_CFG2 + begin + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p4_cmd_ba = p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p4_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p4_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p4_cmd_ra = p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p4_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p4_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p4_cmd_ca = {p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + else + assign p4_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p4_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + + + if (C_MEM_BANKADDR_WIDTH == 3 ) //Bank + assign p5_cmd_ba = p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]; + else + assign p5_cmd_ba = {allzero[2 : C_MEM_BANKADDR_WIDTH ] , p5_cmd_byte_addr[C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_ADDR_WIDTH == 15) //Row + assign p5_cmd_ra = p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]; + else + assign p5_cmd_ra = {allzero[14 : C_MEM_ADDR_WIDTH ] , p5_cmd_byte_addr[C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 : C_MEM_NUM_COL_BITS - 1]}; + + + if (C_MEM_NUM_COL_BITS == 12) //Column + assign p5_cmd_ca = {p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + else + assign p5_cmd_ca = {allzero[11 : C_MEM_NUM_COL_BITS ] , p5_cmd_byte_addr[C_MEM_NUM_COL_BITS - 2 : 0] , 1'b0}; + end + + + + end + +end // block: x4_Addr + + +endgenerate + + + +generate + // if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0 + if(C_PORT_CONFIG == "B32_B32_R32_R32_R32_R32" || + C_PORT_CONFIG == "B32_B32_R32_R32_R32_W32" || + C_PORT_CONFIG == "B32_B32_R32_R32_W32_R32" || + C_PORT_CONFIG == "B32_B32_R32_R32_W32_W32" || + C_PORT_CONFIG == "B32_B32_R32_W32_R32_R32" || + C_PORT_CONFIG == "B32_B32_R32_W32_R32_W32" || + C_PORT_CONFIG == "B32_B32_R32_W32_W32_R32" || + C_PORT_CONFIG == "B32_B32_R32_W32_W32_W32" || + C_PORT_CONFIG == "B32_B32_W32_R32_R32_R32" || + C_PORT_CONFIG == "B32_B32_W32_R32_R32_W32" || + C_PORT_CONFIG == "B32_B32_W32_R32_W32_R32" || + C_PORT_CONFIG == "B32_B32_W32_R32_W32_W32" || + C_PORT_CONFIG == "B32_B32_W32_W32_R32_R32" || + C_PORT_CONFIG == "B32_B32_W32_W32_R32_W32" || + C_PORT_CONFIG == "B32_B32_W32_W32_W32_R32" || + C_PORT_CONFIG == "B32_B32_W32_W32_W32_W32" + ) begin : u_config1_0 + + //synthesis translate_off + always @(*) + begin + if ( C_PORT_CONFIG[119:96] == "W32" && p2_cmd_en == 1'b1 + && p2_cmd_instr[2] == 1'b0 && p2_cmd_instr[0] == 1'b1 ) + begin + $display("ERROR - Invalid Command for write only port 2"); + $finish; + end + end + + always @(*) + begin + if ( C_PORT_CONFIG[119:96] == "R32" && p2_cmd_en == 1'b1 + && p2_cmd_instr[2] == 1'b0 && p2_cmd_instr[0] == 1'b0 ) + begin + $display("ERROR - Invalid Command for read only port 2"); + $finish; + end + end +// Catch Invalid command during simulation for Port 3 + always @(*) + begin + if ( C_PORT_CONFIG[87:64] == "W32" && p3_cmd_en == 1'b1 + && p3_cmd_instr[2] == 1'b0 && p3_cmd_instr[0] == 1'b1 ) + begin + $display("ERROR - Invalid Command for write only port 3"); + $finish; + end + end + + always @(*) + begin + if ( C_PORT_CONFIG[87:64] == "R32" && p3_cmd_en == 1'b1 + && p3_cmd_instr[2] == 1'b0 && p3_cmd_instr[0] == 1'b0 ) + begin + $display("ERROR - Invalid Command for read only port 3"); + $finish; + end + end + +// Catch Invalid command during simulation for Port 4 + always @(*) + begin + if ( C_PORT_CONFIG[55:32] == "W32" && p4_cmd_en == 1'b1 + && p4_cmd_instr[2] == 1'b0 && p4_cmd_instr[0] == 1'b1 ) + begin + $display("ERROR - Invalid Command for write only port 4"); + $finish; + end + end + + always @(*) + begin + if ( C_PORT_CONFIG[55:32] == "R32" && p4_cmd_en == 1'b1 + && p4_cmd_instr[2] == 1'b0 && p4_cmd_instr[0] == 1'b0 ) + begin + $display("ERROR - Invalid Command for read only port 4"); + $finish; + end + end +// Catch Invalid command during simulation for Port 5 + always @(*) + begin + if ( C_PORT_CONFIG[23:0] == "W32" && p5_cmd_en == 1'b1 + && p5_cmd_instr[2] == 1'b0 && p5_cmd_instr[0] == 1'b1 ) + begin + $display("ERROR - Invalid Command for write only port 5"); + $finish; + end + end + + always @(*) + begin + if ( C_PORT_CONFIG[23:0] == "R32" && p5_cmd_en == 1'b1 + && p5_cmd_instr[2] == 1'b0 && p5_cmd_instr[0] == 1'b0 ) + begin + $display("ERROR - Invalid Command for read only port 5"); + $finish; + end + end + //synthesis translate_on + + + // the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up + // high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx. + // The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration.. + // + + // Inputs from Application CMD Port + + if (C_PORT_ENABLE[0] == 1'b1) + begin + + assign mig_p0_arb_en = p0_arb_en ; + assign mig_p0_cmd_clk = p0_cmd_clk ; + assign mig_p0_cmd_en = p0_cmd_en ; + assign mig_p0_cmd_ra = p0_cmd_ra ; + assign mig_p0_cmd_ba = p0_cmd_ba ; + assign mig_p0_cmd_ca = p0_cmd_ca ; + assign mig_p0_cmd_instr = p0_cmd_instr; + assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ; + assign p0_cmd_empty = mig_p0_cmd_empty; + assign p0_cmd_full = mig_p0_cmd_full ; + + end else + begin + + assign mig_p0_arb_en = 'b0; + assign mig_p0_cmd_clk = 'b0; + assign mig_p0_cmd_en = 'b0; + assign mig_p0_cmd_ra = 'b0; + assign mig_p0_cmd_ba = 'b0; + assign mig_p0_cmd_ca = 'b0; + assign mig_p0_cmd_instr = 'b0; + assign mig_p0_cmd_bl = 'b0; + assign p0_cmd_empty = 'b0; + assign p0_cmd_full = 'b0; + + end + + + if (C_PORT_ENABLE[1] == 1'b1) + begin + + + assign mig_p1_arb_en = p1_arb_en ; + assign mig_p1_cmd_clk = p1_cmd_clk ; + assign mig_p1_cmd_en = p1_cmd_en ; + assign mig_p1_cmd_ra = p1_cmd_ra ; + assign mig_p1_cmd_ba = p1_cmd_ba ; + assign mig_p1_cmd_ca = p1_cmd_ca ; + assign mig_p1_cmd_instr = p1_cmd_instr; + assign mig_p1_cmd_bl = {(p1_cmd_instr[2] | p1_cmd_bl[5]),p1_cmd_bl[4:0]} ; + assign p1_cmd_empty = mig_p1_cmd_empty; + assign p1_cmd_full = mig_p1_cmd_full ; + + end else + begin + assign mig_p1_arb_en = 'b0; + assign mig_p1_cmd_clk = 'b0; + assign mig_p1_cmd_en = 'b0; + assign mig_p1_cmd_ra = 'b0; + assign mig_p1_cmd_ba = 'b0; + assign mig_p1_cmd_ca = 'b0; + assign mig_p1_cmd_instr = 'b0; + assign mig_p1_cmd_bl = 'b0; + assign p1_cmd_empty = 'b0; + assign p1_cmd_full = 'b0; + + + end + + + if (C_PORT_ENABLE[2] == 1'b1) + begin + + assign mig_p2_arb_en = p2_arb_en ; + assign mig_p2_cmd_clk = p2_cmd_clk ; + assign mig_p2_cmd_en = p2_cmd_en ; + assign mig_p2_cmd_ra = p2_cmd_ra ; + assign mig_p2_cmd_ba = p2_cmd_ba ; + assign mig_p2_cmd_ca = p2_cmd_ca ; + assign mig_p2_cmd_instr = p2_cmd_instr; + assign mig_p2_cmd_bl = {(p2_cmd_instr[2] | p2_cmd_bl[5]),p2_cmd_bl[4:0]} ; + assign p2_cmd_empty = mig_p2_cmd_empty; + assign p2_cmd_full = mig_p2_cmd_full ; + + end else + begin + + assign mig_p2_arb_en = 'b0; + assign mig_p2_cmd_clk = 'b0; + assign mig_p2_cmd_en = 'b0; + assign mig_p2_cmd_ra = 'b0; + assign mig_p2_cmd_ba = 'b0; + assign mig_p2_cmd_ca = 'b0; + assign mig_p2_cmd_instr = 'b0; + assign mig_p2_cmd_bl = 'b0; + assign p2_cmd_empty = 'b0; + assign p2_cmd_full = 'b0; + + end + + + + if (C_PORT_ENABLE[3] == 1'b1) + begin + + assign mig_p3_arb_en = p3_arb_en ; + assign mig_p3_cmd_clk = p3_cmd_clk ; + assign mig_p3_cmd_en = p3_cmd_en ; + assign mig_p3_cmd_ra = p3_cmd_ra ; + assign mig_p3_cmd_ba = p3_cmd_ba ; + assign mig_p3_cmd_ca = p3_cmd_ca ; + assign mig_p3_cmd_instr = p3_cmd_instr; + assign mig_p3_cmd_bl = {(p3_cmd_instr[2] | p3_cmd_bl[5]),p3_cmd_bl[4:0]} ; + assign p3_cmd_empty = mig_p3_cmd_empty; + assign p3_cmd_full = mig_p3_cmd_full ; + + end else + begin + assign mig_p3_arb_en = 'b0; + assign mig_p3_cmd_clk = 'b0; + assign mig_p3_cmd_en = 'b0; + assign mig_p3_cmd_ra = 'b0; + assign mig_p3_cmd_ba = 'b0; + assign mig_p3_cmd_ca = 'b0; + assign mig_p3_cmd_instr = 'b0; + assign mig_p3_cmd_bl = 'b0; + assign p3_cmd_empty = 'b0; + assign p3_cmd_full = 'b0; + + end + + if (C_PORT_ENABLE[4] == 1'b1) + begin + + assign mig_p4_arb_en = p4_arb_en ; + assign mig_p4_cmd_clk = p4_cmd_clk ; + assign mig_p4_cmd_en = p4_cmd_en ; + assign mig_p4_cmd_ra = p4_cmd_ra ; + assign mig_p4_cmd_ba = p4_cmd_ba ; + assign mig_p4_cmd_ca = p4_cmd_ca ; + assign mig_p4_cmd_instr = p4_cmd_instr; + assign mig_p4_cmd_bl = {(p4_cmd_instr[2] | p4_cmd_bl[5]),p4_cmd_bl[4:0]} ; + assign p4_cmd_empty = mig_p4_cmd_empty; + assign p4_cmd_full = mig_p4_cmd_full ; + + end else + begin + assign mig_p4_arb_en = 'b0; + assign mig_p4_cmd_clk = 'b0; + assign mig_p4_cmd_en = 'b0; + assign mig_p4_cmd_ra = 'b0; + assign mig_p4_cmd_ba = 'b0; + assign mig_p4_cmd_ca = 'b0; + assign mig_p4_cmd_instr = 'b0; + assign mig_p4_cmd_bl = 'b0; + assign p4_cmd_empty = 'b0; + assign p4_cmd_full = 'b0; + + + + end + + if (C_PORT_ENABLE[5] == 1'b1) + begin + + assign mig_p5_arb_en = p5_arb_en ; + assign mig_p5_cmd_clk = p5_cmd_clk ; + assign mig_p5_cmd_en = p5_cmd_en ; + assign mig_p5_cmd_ra = p5_cmd_ra ; + assign mig_p5_cmd_ba = p5_cmd_ba ; + assign mig_p5_cmd_ca = p5_cmd_ca ; + assign mig_p5_cmd_instr = p5_cmd_instr; + assign mig_p5_cmd_bl = {(p5_cmd_instr[2] | p5_cmd_bl[5]),p5_cmd_bl[4:0]} ; + assign p5_cmd_empty = mig_p5_cmd_empty; + assign p5_cmd_full = mig_p5_cmd_full ; + + end else + begin + assign mig_p5_arb_en = 'b0; + assign mig_p5_cmd_clk = 'b0; + assign mig_p5_cmd_en = 'b0; + assign mig_p5_cmd_ra = 'b0; + assign mig_p5_cmd_ba = 'b0; + assign mig_p5_cmd_ca = 'b0; + assign mig_p5_cmd_instr = 'b0; + assign mig_p5_cmd_bl = 'b0; + assign p5_cmd_empty = 'b0; + assign p5_cmd_full = 'b0; + + + end + + + + + // Inputs from Application User Port + + // Port 0 + if (C_PORT_ENABLE[0] == 1'b1) + begin + assign mig_p0_wr_clk = p0_wr_clk; + assign mig_p0_rd_clk = p0_rd_clk; + assign mig_p0_wr_en = p0_wr_en; + assign mig_p0_rd_en = p0_rd_en; + assign mig_p0_wr_mask = p0_wr_mask[3:0]; + assign mig_p0_wr_data = p0_wr_data[31:0]; + assign p0_rd_data = mig_p0_rd_data; + assign p0_rd_full = mig_p0_rd_full; + assign p0_rd_empty = mig_p0_rd_empty; + assign p0_rd_error = mig_p0_rd_error; + assign p0_wr_error = mig_p0_wr_error; + assign p0_rd_overflow = mig_p0_rd_overflow; + assign p0_wr_underrun = mig_p0_wr_underrun; + assign p0_wr_empty = mig_p0_wr_empty; + assign p0_wr_full = mig_p0_wr_full; + assign p0_wr_count = mig_p0_wr_count; + assign p0_rd_count = mig_p0_rd_count ; + + + end + else + begin + assign mig_p0_wr_clk = 'b0; + assign mig_p0_rd_clk = 'b0; + assign mig_p0_wr_en = 'b0; + assign mig_p0_rd_en = 'b0; + assign mig_p0_wr_mask = 'b0; + assign mig_p0_wr_data = 'b0; + assign p0_rd_data = 'b0; + assign p0_rd_full = 'b0; + assign p0_rd_empty = 'b0; + assign p0_rd_error = 'b0; + assign p0_wr_error = 'b0; + assign p0_rd_overflow = 'b0; + assign p0_wr_underrun = 'b0; + assign p0_wr_empty = 'b0; + assign p0_wr_full = 'b0; + assign p0_wr_count = 'b0; + assign p0_rd_count = 'b0; + + + end + + + // Port 1 + if (C_PORT_ENABLE[1] == 1'b1) + begin + + assign mig_p1_wr_clk = p1_wr_clk; + assign mig_p1_rd_clk = p1_rd_clk; + assign mig_p1_wr_en = p1_wr_en; + assign mig_p1_wr_mask = p1_wr_mask[3:0]; + assign mig_p1_wr_data = p1_wr_data[31:0]; + assign mig_p1_rd_en = p1_rd_en; + assign p1_rd_data = mig_p1_rd_data; + assign p1_rd_empty = mig_p1_rd_empty; + assign p1_rd_full = mig_p1_rd_full; + assign p1_rd_error = mig_p1_rd_error; + assign p1_wr_error = mig_p1_wr_error; + assign p1_rd_overflow = mig_p1_rd_overflow; + assign p1_wr_underrun = mig_p1_wr_underrun; + assign p1_wr_empty = mig_p1_wr_empty; + assign p1_wr_full = mig_p1_wr_full; + assign p1_wr_count = mig_p1_wr_count; + assign p1_rd_count = mig_p1_rd_count ; + + end else + begin + + assign mig_p1_wr_clk = 'b0; + assign mig_p1_rd_clk = 'b0; + assign mig_p1_wr_en = 'b0; + assign mig_p1_wr_mask = 'b0; + assign mig_p1_wr_data = 'b0; + assign mig_p1_rd_en = 'b0; + assign p1_rd_data = 'b0; + assign p1_rd_empty = 'b0; + assign p1_rd_full = 'b0; + assign p1_rd_error = 'b0; + assign p1_wr_error = 'b0; + assign p1_rd_overflow = 'b0; + assign p1_wr_underrun = 'b0; + assign p1_wr_empty = 'b0; + assign p1_wr_full = 'b0; + assign p1_wr_count = 'b0; + assign p1_rd_count = 'b0; + + + end + + + + + +// whenever PORT 2 is in Write mode + if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[119:96] == "W32") begin : u_config1_2W + if (C_PORT_ENABLE[2] == 1'b1) + begin + assign mig_p2_clk = p2_wr_clk; + assign mig_p2_wr_data = p2_wr_data[31:0]; + assign mig_p2_wr_mask = p2_wr_mask[3:0]; + assign mig_p2_en = p2_wr_en; // this signal will not shown up if the port 5 is for read dir + assign p2_wr_error = mig_p2_error; + assign p2_wr_full = mig_p2_full; + assign p2_wr_empty = mig_p2_empty; + assign p2_wr_underrun = mig_p2_underrun; + assign p2_wr_count = mig_p2_count ; // wr port + + + end else + begin + assign mig_p2_clk = 'b0; + assign mig_p2_wr_data = 'b0; + assign mig_p2_wr_mask = 'b0; + assign mig_p2_en = 'b0; + assign p2_wr_error = 'b0; + assign p2_wr_full = 'b0; + assign p2_wr_empty = 'b0; + assign p2_wr_underrun = 'b0; + assign p2_wr_count = 'b0; + + end + assign p2_rd_data = 'b0; + assign p2_rd_overflow = 'b0; + assign p2_rd_error = 'b0; + assign p2_rd_full = 'b0; + assign p2_rd_empty = 'b0; + assign p2_rd_count = 'b0; +// assign p2_rd_error = 'b0; + + + + end else if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[119:96] == "R32") begin : u_config1_2R + + if (C_PORT_ENABLE[2] == 1'b1) + begin + assign mig_p2_clk = p2_rd_clk; + assign p2_rd_data = mig_p2_rd_data; + assign mig_p2_en = p2_rd_en; + assign p2_rd_overflow = mig_p2_overflow; + assign p2_rd_error = mig_p2_error; + assign p2_rd_full = mig_p2_full; + assign p2_rd_empty = mig_p2_empty; + assign p2_rd_count = mig_p2_count ; // wr port + + end else + begin + assign mig_p2_clk = 'b0; + assign p2_rd_data = 'b0; + assign mig_p2_en = 'b0; + + assign p2_rd_overflow = 'b0; + assign p2_rd_error = 'b0; + assign p2_rd_full = 'b0; + assign p2_rd_empty = 'b0; + assign p2_rd_count = 'b0; + + end + assign mig_p2_wr_data = 'b0; + assign mig_p2_wr_mask = 'b0; + assign p2_wr_error = 'b0; + assign p2_wr_full = 'b0; + assign p2_wr_empty = 'b0; + assign p2_wr_underrun = 'b0; + assign p2_wr_count = 'b0; + + end + if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[87:64] == "W32") begin : u_config1_3W +// whenever PORT 3 is in Write mode + + if (C_PORT_ENABLE[3] == 1'b1) + begin + + assign mig_p3_clk = p3_wr_clk; + assign mig_p3_wr_data = p3_wr_data[31:0]; + assign mig_p3_wr_mask = p3_wr_mask[3:0]; + assign mig_p3_en = p3_wr_en; + assign p3_wr_full = mig_p3_full; + assign p3_wr_empty = mig_p3_empty; + assign p3_wr_underrun = mig_p3_underrun; + assign p3_wr_count = mig_p3_count ; // wr port + assign p3_wr_error = mig_p3_error; + + end else + begin + assign mig_p3_clk = 'b0; + assign mig_p3_wr_data = 'b0; + assign mig_p3_wr_mask = 'b0; + assign mig_p3_en = 'b0; + assign p3_wr_full = 'b0; + assign p3_wr_empty = 'b0; + assign p3_wr_underrun = 'b0; + assign p3_wr_count = 'b0; + assign p3_wr_error = 'b0; + + end + assign p3_rd_overflow = 'b0; + assign p3_rd_error = 'b0; + assign p3_rd_full = 'b0; + assign p3_rd_empty = 'b0; + assign p3_rd_count = 'b0; + assign p3_rd_data = 'b0; + + + end else if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[87:64] == "R32") begin : u_config1_3R + + if (C_PORT_ENABLE[3] == 1'b1) + begin + + assign mig_p3_clk = p3_rd_clk; + assign p3_rd_data = mig_p3_rd_data; + assign mig_p3_en = p3_rd_en; // this signal will not shown up if the port 5 is for write dir + assign p3_rd_overflow = mig_p3_overflow; + assign p3_rd_error = mig_p3_error; + assign p3_rd_full = mig_p3_full; + assign p3_rd_empty = mig_p3_empty; + assign p3_rd_count = mig_p3_count ; // wr port + end else + begin + assign mig_p3_clk = 'b0; + assign mig_p3_en = 'b0; + assign p3_rd_overflow = 'b0; + assign p3_rd_full = 'b0; + assign p3_rd_empty = 'b0; + assign p3_rd_count = 'b0; + assign p3_rd_error = 'b0; + assign p3_rd_data = 'b0; + end + assign p3_wr_full = 'b0; + assign p3_wr_empty = 'b0; + assign p3_wr_underrun = 'b0; + assign p3_wr_count = 'b0; + assign p3_wr_error = 'b0; + assign mig_p3_wr_data = 'b0; + assign mig_p3_wr_mask = 'b0; + end + if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[55:32] == "W32") begin : u_config1_4W + // whenever PORT 4 is in Write mode + + if (C_PORT_ENABLE[4] == 1'b1) + begin + + assign mig_p4_clk = p4_wr_clk; + assign mig_p4_wr_data = p4_wr_data[31:0]; + assign mig_p4_wr_mask = p4_wr_mask[3:0]; + assign mig_p4_en = p4_wr_en; // this signal will not shown up if the port 5 is for read dir + assign p4_wr_full = mig_p4_full; + assign p4_wr_empty = mig_p4_empty; + assign p4_wr_underrun = mig_p4_underrun; + assign p4_wr_count = mig_p4_count ; // wr port + assign p4_wr_error = mig_p4_error; + + end else + begin + assign mig_p4_clk = 'b0; + assign mig_p4_wr_data = 'b0; + assign mig_p4_wr_mask = 'b0; + assign mig_p4_en = 'b0; + assign p4_wr_full = 'b0; + assign p4_wr_empty = 'b0; + assign p4_wr_underrun = 'b0; + assign p4_wr_count = 'b0; + assign p4_wr_error = 'b0; + end + assign p4_rd_overflow = 'b0; + assign p4_rd_error = 'b0; + assign p4_rd_full = 'b0; + assign p4_rd_empty = 'b0; + assign p4_rd_count = 'b0; + assign p4_rd_data = 'b0; + + end else if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[55:32] == "R32") begin : u_config1_4R + + if (C_PORT_ENABLE[4] == 1'b1) + begin + assign mig_p4_clk = p4_rd_clk; + assign p4_rd_data = mig_p4_rd_data; + assign mig_p4_en = p4_rd_en; // this signal will not shown up if the port 5 is for write dir + assign p4_rd_overflow = mig_p4_overflow; + assign p4_rd_error = mig_p4_error; + assign p4_rd_full = mig_p4_full; + assign p4_rd_empty = mig_p4_empty; + assign p4_rd_count = mig_p4_count ; // wr port + + end else + begin + assign mig_p4_clk = 'b0; + assign p4_rd_data = 'b0; + assign mig_p4_en = 'b0; + assign p4_rd_overflow = 'b0; + assign p4_rd_error = 'b0; + assign p4_rd_full = 'b0; + assign p4_rd_empty = 'b0; + assign p4_rd_count = 'b0; + end + assign p4_wr_full = 'b0; + assign p4_wr_empty = 'b0; + assign p4_wr_underrun = 'b0; + assign p4_wr_count = 'b0; + assign p4_wr_error = 'b0; + assign mig_p4_wr_data = 'b0; + assign mig_p4_wr_mask = 'b0; + + + + + end + + if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[23:0] == "W32") begin : u_config1_5W + // whenever PORT 5 is in Write mode + + + if (C_PORT_ENABLE[5] == 1'b1) + begin + assign mig_p5_clk = p5_wr_clk; + assign mig_p5_wr_data = p5_wr_data[31:0]; + assign mig_p5_wr_mask = p5_wr_mask[3:0]; + assign mig_p5_en = p5_wr_en; + assign p5_wr_full = mig_p5_full; + assign p5_wr_empty = mig_p5_empty; + assign p5_wr_underrun = mig_p5_underrun; + assign p5_wr_count = mig_p5_count ; + assign p5_wr_error = mig_p5_error; + + end else + begin + assign mig_p5_clk = 'b0; + assign mig_p5_wr_data = 'b0; + assign mig_p5_wr_mask = 'b0; + assign mig_p5_en = 'b0; + assign p5_wr_full = 'b0; + assign p5_wr_empty = 'b0; + assign p5_wr_underrun = 'b0; + assign p5_wr_count = 'b0; + assign p5_wr_error = 'b0; + end + assign p5_rd_data = 'b0; + assign p5_rd_overflow = 'b0; + assign p5_rd_error = 'b0; + assign p5_rd_full = 'b0; + assign p5_rd_empty = 'b0; + assign p5_rd_count = 'b0; + + + + + end else if(C_PORT_CONFIG[183:160] == "B32" && C_PORT_CONFIG[23:0] == "R32") begin : u_config1_5R + + if (C_PORT_ENABLE[5] == 1'b1) + begin + + assign mig_p5_clk = p5_rd_clk; + assign p5_rd_data = mig_p5_rd_data; + assign mig_p5_en = p5_rd_en; + assign p5_rd_overflow = mig_p5_overflow; + assign p5_rd_error = mig_p5_error; + assign p5_rd_full = mig_p5_full; + assign p5_rd_empty = mig_p5_empty; + assign p5_rd_count = mig_p5_count ; + + end else + begin + assign mig_p5_clk = 'b0; + assign p5_rd_data = 'b0; + assign mig_p5_en = 'b0; + assign p5_rd_overflow = 'b0; + assign p5_rd_error = 'b0; + assign p5_rd_full = 'b0; + assign p5_rd_empty = 'b0; + assign p5_rd_count = 'b0; + + end + assign p5_wr_full = 'b0; + assign p5_wr_empty = 'b0; + assign p5_wr_underrun = 'b0; + assign p5_wr_count = 'b0; + assign p5_wr_error = 'b0; + assign mig_p5_wr_data = 'b0; + assign mig_p5_wr_mask = 'b0; + + end + + end else if(C_PORT_CONFIG == "B32_B32_B32_B32" ) begin : u_config_2 + + + // Inputs from Application CMD Port + // ************* need to hook up rd /wr error outputs + + if (C_PORT_ENABLE[0] == 1'b1) + begin + // command port signals + assign mig_p0_arb_en = p0_arb_en ; + assign mig_p0_cmd_clk = p0_cmd_clk ; + assign mig_p0_cmd_en = p0_cmd_en ; + assign mig_p0_cmd_ra = p0_cmd_ra ; + assign mig_p0_cmd_ba = p0_cmd_ba ; + assign mig_p0_cmd_ca = p0_cmd_ca ; + assign mig_p0_cmd_instr = p0_cmd_instr; + assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ; + + // Data port signals + assign mig_p0_rd_en = p0_rd_en; + assign mig_p0_wr_clk = p0_wr_clk; + assign mig_p0_rd_clk = p0_rd_clk; + assign mig_p0_wr_en = p0_wr_en; + assign mig_p0_wr_data = p0_wr_data[31:0]; + assign mig_p0_wr_mask = p0_wr_mask[3:0]; + assign p0_wr_count = mig_p0_wr_count; + assign p0_rd_count = mig_p0_rd_count ; + + + + end else + begin + assign mig_p0_arb_en = 'b0; + assign mig_p0_cmd_clk = 'b0; + assign mig_p0_cmd_en = 'b0; + assign mig_p0_cmd_ra = 'b0; + assign mig_p0_cmd_ba = 'b0; + assign mig_p0_cmd_ca = 'b0; + assign mig_p0_cmd_instr = 'b0; + assign mig_p0_cmd_bl = 'b0; + + assign mig_p0_rd_en = 'b0; + assign mig_p0_wr_clk = 'b0; + assign mig_p0_rd_clk = 'b0; + assign mig_p0_wr_en = 'b0; + assign mig_p0_wr_data = 'b0; + assign mig_p0_wr_mask = 'b0; + assign p0_wr_count = 'b0; + assign p0_rd_count = 'b0; + + + end + + assign p0_cmd_empty = mig_p0_cmd_empty ; + assign p0_cmd_full = mig_p0_cmd_full ; + + + if (C_PORT_ENABLE[1] == 1'b1) + begin + // command port signals + + assign mig_p1_arb_en = p1_arb_en ; + assign mig_p1_cmd_clk = p1_cmd_clk ; + assign mig_p1_cmd_en = p1_cmd_en ; + assign mig_p1_cmd_ra = p1_cmd_ra ; + assign mig_p1_cmd_ba = p1_cmd_ba ; + assign mig_p1_cmd_ca = p1_cmd_ca ; + assign mig_p1_cmd_instr = p1_cmd_instr; + assign mig_p1_cmd_bl = {(p1_cmd_instr[2] | p1_cmd_bl[5]),p1_cmd_bl[4:0]} ; + // Data port signals + + assign mig_p1_wr_en = p1_wr_en; + assign mig_p1_wr_clk = p1_wr_clk; + assign mig_p1_rd_en = p1_rd_en; + assign mig_p1_wr_data = p1_wr_data[31:0]; + assign mig_p1_wr_mask = p1_wr_mask[3:0]; + assign mig_p1_rd_clk = p1_rd_clk; + assign p1_wr_count = mig_p1_wr_count; + assign p1_rd_count = mig_p1_rd_count; + + end else + begin + + assign mig_p1_arb_en = 'b0; + assign mig_p1_cmd_clk = 'b0; + assign mig_p1_cmd_en = 'b0; + assign mig_p1_cmd_ra = 'b0; + assign mig_p1_cmd_ba = 'b0; + assign mig_p1_cmd_ca = 'b0; + assign mig_p1_cmd_instr = 'b0; + assign mig_p1_cmd_bl = 'b0; + // Data port signals + assign mig_p1_wr_en = 'b0; + assign mig_p1_wr_clk = 'b0; + assign mig_p1_rd_en = 'b0; + assign mig_p1_wr_data = 'b0; + assign mig_p1_wr_mask = 'b0; + assign mig_p1_rd_clk = 'b0; + assign p1_wr_count = 'b0; + assign p1_rd_count = 'b0; + + end + + + assign p1_cmd_empty = mig_p1_cmd_empty ; + assign p1_cmd_full = mig_p1_cmd_full ; + + if (C_PORT_ENABLE[2] == 1'b1) + begin //MCB Physical port Logical Port + assign mig_p2_arb_en = p2_arb_en ; + assign mig_p2_cmd_clk = p2_cmd_clk ; + assign mig_p2_cmd_en = p2_cmd_en ; + assign mig_p2_cmd_ra = p2_cmd_ra ; + assign mig_p2_cmd_ba = p2_cmd_ba ; + assign mig_p2_cmd_ca = p2_cmd_ca ; + assign mig_p2_cmd_instr = p2_cmd_instr; + assign mig_p2_cmd_bl = {(p2_cmd_instr[2] | p2_cmd_bl[5]),p2_cmd_bl[4:0]} ; + + assign mig_p2_en = p2_rd_en; + assign mig_p2_clk = p2_rd_clk; + assign mig_p3_en = p2_wr_en; + assign mig_p3_clk = p2_wr_clk; + assign mig_p3_wr_data = p2_wr_data[31:0]; + assign mig_p3_wr_mask = p2_wr_mask[3:0]; + assign p2_wr_count = mig_p3_count; + assign p2_rd_count = mig_p2_count; + + end else + begin + + assign mig_p2_arb_en = 'b0; + assign mig_p2_cmd_clk = 'b0; + assign mig_p2_cmd_en = 'b0; + assign mig_p2_cmd_ra = 'b0; + assign mig_p2_cmd_ba = 'b0; + assign mig_p2_cmd_ca = 'b0; + assign mig_p2_cmd_instr = 'b0; + assign mig_p2_cmd_bl = 'b0; + + assign mig_p2_en = 'b0; + assign mig_p2_clk = 'b0; + assign mig_p3_en = 'b0; + assign mig_p3_clk = 'b0; + assign mig_p3_wr_data = 'b0; + assign mig_p3_wr_mask = 'b0; + assign p2_rd_count = 'b0; + assign p2_wr_count = 'b0; + + end + + assign p2_cmd_empty = mig_p2_cmd_empty ; + assign p2_cmd_full = mig_p2_cmd_full ; + + if (C_PORT_ENABLE[3] == 1'b1) + begin //MCB Physical port Logical Port + assign mig_p4_arb_en = p3_arb_en ; + assign mig_p4_cmd_clk = p3_cmd_clk ; + assign mig_p4_cmd_en = p3_cmd_en ; + assign mig_p4_cmd_ra = p3_cmd_ra ; + assign mig_p4_cmd_ba = p3_cmd_ba ; + assign mig_p4_cmd_ca = p3_cmd_ca ; + assign mig_p4_cmd_instr = p3_cmd_instr; + assign mig_p4_cmd_bl = {(p3_cmd_instr[2] | p3_cmd_bl[5]),p3_cmd_bl[4:0]} ; + + assign mig_p4_clk = p3_rd_clk; + assign mig_p4_en = p3_rd_en; + assign mig_p5_clk = p3_wr_clk; + assign mig_p5_en = p3_wr_en; + assign mig_p5_wr_data = p3_wr_data[31:0]; + assign mig_p5_wr_mask = p3_wr_mask[3:0]; + assign p3_rd_count = mig_p4_count; + assign p3_wr_count = mig_p5_count; + + + end else + begin + assign mig_p4_arb_en = 'b0; + assign mig_p4_cmd_clk = 'b0; + assign mig_p4_cmd_en = 'b0; + assign mig_p4_cmd_ra = 'b0; + assign mig_p4_cmd_ba = 'b0; + assign mig_p4_cmd_ca = 'b0; + assign mig_p4_cmd_instr = 'b0; + assign mig_p4_cmd_bl = 'b0; + + assign mig_p4_clk = 'b0; + assign mig_p4_en = 'b0; + assign mig_p5_clk = 'b0; + assign mig_p5_en = 'b0; + assign mig_p5_wr_data = 'b0; + assign mig_p5_wr_mask = 'b0; + assign p3_rd_count = 'b0; + assign p3_wr_count = 'b0; + + + + end + + assign p3_cmd_empty = mig_p4_cmd_empty ; + assign p3_cmd_full = mig_p4_cmd_full ; + + + // outputs to Applications User Port + assign p0_rd_data = mig_p0_rd_data; + assign p1_rd_data = mig_p1_rd_data; + assign p2_rd_data = mig_p2_rd_data; + assign p3_rd_data = mig_p4_rd_data; + + assign p0_rd_empty = mig_p0_rd_empty; + assign p1_rd_empty = mig_p1_rd_empty; + assign p2_rd_empty = mig_p2_empty; + assign p3_rd_empty = mig_p4_empty; + + assign p0_rd_full = mig_p0_rd_full; + assign p1_rd_full = mig_p1_rd_full; + assign p2_rd_full = mig_p2_full; + assign p3_rd_full = mig_p4_full; + + assign p0_rd_error = mig_p0_rd_error; + assign p1_rd_error = mig_p1_rd_error; + assign p2_rd_error = mig_p2_error; + assign p3_rd_error = mig_p4_error; + + assign p0_rd_overflow = mig_p0_rd_overflow; + assign p1_rd_overflow = mig_p1_rd_overflow; + assign p2_rd_overflow = mig_p2_overflow; + assign p3_rd_overflow = mig_p4_overflow; + + assign p0_wr_underrun = mig_p0_wr_underrun; + assign p1_wr_underrun = mig_p1_wr_underrun; + assign p2_wr_underrun = mig_p3_underrun; + assign p3_wr_underrun = mig_p5_underrun; + + assign p0_wr_empty = mig_p0_wr_empty; + assign p1_wr_empty = mig_p1_wr_empty; + assign p2_wr_empty = mig_p3_empty; + assign p3_wr_empty = mig_p5_empty; + + assign p0_wr_full = mig_p0_wr_full; + assign p1_wr_full = mig_p1_wr_full; + assign p2_wr_full = mig_p3_full; + assign p3_wr_full = mig_p5_full; + + assign p0_wr_error = mig_p0_wr_error; + assign p1_wr_error = mig_p1_wr_error; + assign p2_wr_error = mig_p3_error; + assign p3_wr_error = mig_p5_error; + + // unused ports signals + assign p4_cmd_empty = 1'b0; + assign p4_cmd_full = 1'b0; + assign mig_p2_wr_mask = 'b0; + assign mig_p4_wr_mask = 'b0; + + assign mig_p2_wr_data = 'b0; + assign mig_p4_wr_data = 'b0; + + assign p5_cmd_empty = 1'b0; + assign p5_cmd_full = 1'b0; + + + assign mig_p3_cmd_clk = 1'b0; + assign mig_p3_cmd_en = 1'b0; + assign mig_p3_cmd_ra = 15'd0; + assign mig_p3_cmd_ba = 3'd0; + assign mig_p3_cmd_ca = 12'd0; + assign mig_p3_cmd_instr = 3'd0; + assign mig_p3_cmd_bl = 6'd0; + assign mig_p3_arb_en = 1'b0; // physical cmd port 3 is not used in this config + + + + + assign mig_p5_arb_en = 1'b0; // physical cmd port 3 is not used in this config + assign mig_p5_cmd_clk = 1'b0; + assign mig_p5_cmd_en = 1'b0; + assign mig_p5_cmd_ra = 15'd0; + assign mig_p5_cmd_ba = 3'd0; + assign mig_p5_cmd_ca = 12'd0; + assign mig_p5_cmd_instr = 3'd0; + assign mig_p5_cmd_bl = 6'd0; + + + + //////////////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////////////// + //// + //// B64_B32_B32 + //// + ///////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////// + + + + end else if(C_PORT_CONFIG == "B64_B32_B32" ) begin : u_config_3 + + // Inputs from Application CMD Port + + + if (C_PORT_ENABLE[0] == 1'b1) + begin + assign mig_p0_arb_en = p0_arb_en ; + assign mig_p0_cmd_clk = p0_cmd_clk ; + assign mig_p0_cmd_en = p0_cmd_en ; + assign mig_p0_cmd_ra = p0_cmd_ra ; + assign mig_p0_cmd_ba = p0_cmd_ba ; + assign mig_p0_cmd_ca = p0_cmd_ca ; + assign mig_p0_cmd_instr = p0_cmd_instr; + assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ; + assign p0_cmd_empty = mig_p0_cmd_empty ; + assign p0_cmd_full = mig_p0_cmd_full ; + + assign mig_p0_wr_clk = p0_wr_clk; + assign mig_p0_rd_clk = p0_rd_clk; + assign mig_p1_wr_clk = p0_wr_clk; + assign mig_p1_rd_clk = p0_rd_clk; + + assign mig_p0_wr_en = p0_wr_en & !p0_wr_full; + assign mig_p1_wr_en = p0_wr_en & !p0_wr_full; + assign mig_p0_wr_data = p0_wr_data[31:0]; + assign mig_p0_wr_mask = p0_wr_mask[3:0]; + assign mig_p1_wr_data = p0_wr_data[63 : 32]; + assign mig_p1_wr_mask = p0_wr_mask[7 : 4]; + + assign p0_rd_empty = mig_p1_rd_empty; + assign p0_rd_data = {mig_p1_rd_data , mig_p0_rd_data}; + assign mig_p0_rd_en = p0_rd_en & !p0_rd_empty; + assign mig_p1_rd_en = p0_rd_en & !p0_rd_empty; + + + assign p0_wr_count = mig_p1_wr_count; // B64 for port 0, map most significant port to output + assign p0_rd_count = mig_p1_rd_count; + assign p0_wr_empty = mig_p1_wr_empty; + assign p0_wr_error = mig_p1_wr_error | mig_p0_wr_error; + assign p0_wr_full = mig_p1_wr_full; + assign p0_wr_underrun = mig_p1_wr_underrun | mig_p0_wr_underrun; + assign p0_rd_overflow = mig_p1_rd_overflow | mig_p0_rd_overflow; + assign p0_rd_error = mig_p1_rd_error | mig_p0_rd_error; + assign p0_rd_full = mig_p1_rd_full; + + + end else + begin + + assign mig_p0_arb_en = 'b0; + assign mig_p0_cmd_clk = 'b0; + assign mig_p0_cmd_en = 'b0; + assign mig_p0_cmd_ra = 'b0; + assign mig_p0_cmd_ba = 'b0; + assign mig_p0_cmd_ca = 'b0; + assign mig_p0_cmd_instr = 'b0; + assign mig_p0_cmd_bl = 'b0; + assign p0_cmd_empty = 'b0; + assign p0_cmd_full = 'b0; + + + assign mig_p0_wr_clk = 'b0; + assign mig_p0_rd_clk = 'b0; + assign mig_p1_wr_clk = 'b0; + assign mig_p1_rd_clk = 'b0; + + assign mig_p0_wr_en = 'b0; + assign mig_p1_wr_en = 'b0; + assign mig_p0_wr_data = 'b0; + assign mig_p0_wr_mask = 'b0; + assign mig_p1_wr_data = 'b0; + assign mig_p1_wr_mask = 'b0; + + assign p0_rd_empty = 'b0; + assign p0_rd_data = 'b0; + assign mig_p0_rd_en = 'b0; + assign mig_p1_rd_en = 'b0; + + + assign p0_wr_count = 'b0; + assign p0_rd_count = 'b0; + assign p0_wr_empty = 'b0; + assign p0_wr_error = 'b0; + assign p0_wr_full = 'b0; + assign p0_wr_underrun = 'b0; + assign p0_rd_overflow = 'b0; + assign p0_rd_error = 'b0; + assign p0_rd_full = 'b0; + + + end + + + + if (C_PORT_ENABLE[1] == 1'b1) + begin + + assign mig_p2_arb_en = p1_arb_en ; + assign mig_p2_cmd_clk = p1_cmd_clk ; + assign mig_p2_cmd_en = p1_cmd_en ; + assign mig_p2_cmd_ra = p1_cmd_ra ; + assign mig_p2_cmd_ba = p1_cmd_ba ; + assign mig_p2_cmd_ca = p1_cmd_ca ; + assign mig_p2_cmd_instr = p1_cmd_instr; + assign mig_p2_cmd_bl = {(p1_cmd_instr[2] | p1_cmd_bl[5]),p1_cmd_bl[4:0]} ; + assign p1_cmd_empty = mig_p2_cmd_empty; + assign p1_cmd_full = mig_p2_cmd_full; + + assign mig_p2_clk = p1_rd_clk; + assign mig_p3_clk = p1_wr_clk; + + assign mig_p3_en = p1_wr_en; + assign mig_p3_wr_data = p1_wr_data[31:0]; + assign mig_p3_wr_mask = p1_wr_mask[3:0]; + assign mig_p2_en = p1_rd_en; + + assign p1_rd_data = mig_p2_rd_data; + assign p1_wr_count = mig_p3_count; + assign p1_rd_count = mig_p2_count; + assign p1_wr_empty = mig_p3_empty; + assign p1_wr_error = mig_p3_error; + assign p1_wr_full = mig_p3_full; + assign p1_wr_underrun = mig_p3_underrun; + assign p1_rd_overflow = mig_p2_overflow; + assign p1_rd_error = mig_p2_error; + assign p1_rd_full = mig_p2_full; + assign p1_rd_empty = mig_p2_empty; + + end else + begin + + assign mig_p2_arb_en = 'b0; + assign mig_p2_cmd_clk = 'b0; + assign mig_p2_cmd_en = 'b0; + assign mig_p2_cmd_ra = 'b0; + assign mig_p2_cmd_ba = 'b0; + assign mig_p2_cmd_ca = 'b0; + assign mig_p2_cmd_instr = 'b0; + assign mig_p2_cmd_bl = 'b0; + assign p1_cmd_empty = 'b0; + assign p1_cmd_full = 'b0; + assign mig_p3_en = 'b0; + assign mig_p3_wr_data = 'b0; + assign mig_p3_wr_mask = 'b0; + assign mig_p2_en = 'b0; + + assign mig_p2_clk = 'b0; + assign mig_p3_clk = 'b0; + + assign p1_rd_data = 'b0; + assign p1_wr_count = 'b0; + assign p1_rd_count = 'b0; + assign p1_wr_empty = 'b0; + assign p1_wr_error = 'b0; + assign p1_wr_full = 'b0; + assign p1_wr_underrun = 'b0; + assign p1_rd_overflow = 'b0; + assign p1_rd_error = 'b0; + assign p1_rd_full = 'b0; + assign p1_rd_empty = 'b0; + + end + + if (C_PORT_ENABLE[2] == 1'b1) + begin + assign mig_p4_arb_en = p2_arb_en ; + assign mig_p4_cmd_clk = p2_cmd_clk ; + assign mig_p4_cmd_en = p2_cmd_en ; + assign mig_p4_cmd_ra = p2_cmd_ra ; + assign mig_p4_cmd_ba = p2_cmd_ba ; + assign mig_p4_cmd_ca = p2_cmd_ca ; + assign mig_p4_cmd_instr = p2_cmd_instr; + assign mig_p4_cmd_bl = {(p2_cmd_instr[2] | p2_cmd_bl[5]),p2_cmd_bl[4:0]} ; + assign p2_cmd_empty = mig_p4_cmd_empty ; + assign p2_cmd_full = mig_p4_cmd_full ; + assign mig_p5_en = p2_wr_en; + assign mig_p5_wr_data = p2_wr_data[31:0]; + assign mig_p5_wr_mask = p2_wr_mask[3:0]; + assign mig_p4_en = p2_rd_en; + + assign mig_p4_clk = p2_rd_clk; + assign mig_p5_clk = p2_wr_clk; + + assign p2_rd_data = mig_p4_rd_data; + assign p2_wr_count = mig_p5_count; + assign p2_rd_count = mig_p4_count; + assign p2_wr_empty = mig_p5_empty; + assign p2_wr_full = mig_p5_full; + assign p2_wr_error = mig_p5_error; + assign p2_wr_underrun = mig_p5_underrun; + assign p2_rd_overflow = mig_p4_overflow; + assign p2_rd_error = mig_p4_error; + assign p2_rd_full = mig_p4_full; + assign p2_rd_empty = mig_p4_empty; + + end else + begin + assign mig_p4_arb_en = 'b0; + assign mig_p4_cmd_clk = 'b0; + assign mig_p4_cmd_en = 'b0; + assign mig_p4_cmd_ra = 'b0; + assign mig_p4_cmd_ba = 'b0; + assign mig_p4_cmd_ca = 'b0; + assign mig_p4_cmd_instr = 'b0; + assign mig_p4_cmd_bl = 'b0; + assign p2_cmd_empty = 'b0; + assign p2_cmd_full = 'b0; + assign mig_p5_en = 'b0; + assign mig_p5_wr_data = 'b0; + assign mig_p5_wr_mask = 'b0; + assign mig_p4_en = 'b0; + + assign mig_p4_clk = 'b0; + assign mig_p5_clk = 'b0; + + assign p2_rd_data = 'b0; + assign p2_wr_count = 'b0; + assign p2_rd_count = 'b0; + assign p2_wr_empty = 'b0; + assign p2_wr_full = 'b0; + assign p2_wr_error = 'b0; + assign p2_wr_underrun = 'b0; + assign p2_rd_overflow = 'b0; + assign p2_rd_error = 'b0; + assign p2_rd_full = 'b0; + assign p2_rd_empty = 'b0; + + end + + + // MCB's port 1,3,5 is not used in this Config mode + assign mig_p1_arb_en = 1'b0; + assign mig_p1_cmd_clk = 1'b0; + assign mig_p1_cmd_en = 1'b0; + assign mig_p1_cmd_ra = 15'd0; + assign mig_p1_cmd_ba = 3'd0; + assign mig_p1_cmd_ca = 12'd0; + + assign mig_p1_cmd_instr = 3'd0; + assign mig_p1_cmd_bl = 6'd0; + + assign mig_p3_arb_en = 1'b0; + assign mig_p3_cmd_clk = 1'b0; + assign mig_p3_cmd_en = 1'b0; + assign mig_p3_cmd_ra = 15'd0; + assign mig_p3_cmd_ba = 3'd0; + assign mig_p3_cmd_ca = 12'd0; + + assign mig_p3_cmd_instr = 3'd0; + assign mig_p3_cmd_bl = 6'd0; + + assign mig_p5_arb_en = 1'b0; + assign mig_p5_cmd_clk = 1'b0; + assign mig_p5_cmd_en = 1'b0; + assign mig_p5_cmd_ra = 15'd0; + assign mig_p5_cmd_ba = 3'd0; + assign mig_p5_cmd_ca = 12'd0; + + assign mig_p5_cmd_instr = 3'd0; + assign mig_p5_cmd_bl = 6'd0; + + + +end else if(C_PORT_CONFIG == "B64_B64" ) begin : u_config_4 + + // Inputs from Application CMD Port + + if (C_PORT_ENABLE[0] == 1'b1) + begin + + assign mig_p0_arb_en = p0_arb_en ; + assign mig_p1_arb_en = p0_arb_en ; + + assign mig_p0_cmd_clk = p0_cmd_clk ; + assign mig_p0_cmd_en = p0_cmd_en ; + assign mig_p0_cmd_ra = p0_cmd_ra ; + assign mig_p0_cmd_ba = p0_cmd_ba ; + assign mig_p0_cmd_ca = p0_cmd_ca ; + assign mig_p0_cmd_instr = p0_cmd_instr; + assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ; + + + assign mig_p0_wr_clk = p0_wr_clk; + assign mig_p0_rd_clk = p0_rd_clk; + assign mig_p1_wr_clk = p0_wr_clk; + assign mig_p1_rd_clk = p0_rd_clk; + assign mig_p0_wr_en = p0_wr_en & !p0_wr_full; + assign mig_p0_wr_data = p0_wr_data[31:0]; + assign mig_p0_wr_mask = p0_wr_mask[3:0]; + assign mig_p1_wr_data = p0_wr_data[63 : 32]; + assign mig_p1_wr_mask = p0_wr_mask[7 : 4]; + assign mig_p1_wr_en = p0_wr_en & !p0_wr_full; + assign mig_p0_rd_en = p0_rd_en & !p0_rd_empty; + assign mig_p1_rd_en = p0_rd_en & !p0_rd_empty; + assign p0_rd_data = {mig_p1_rd_data , mig_p0_rd_data}; + + assign p0_cmd_empty = mig_p0_cmd_empty ; + assign p0_cmd_full = mig_p0_cmd_full ; + assign p0_wr_empty = mig_p1_wr_empty; + assign p0_wr_full = mig_p1_wr_full; + assign p0_wr_error = mig_p1_wr_error | mig_p0_wr_error; + assign p0_wr_count = mig_p1_wr_count; + assign p0_rd_count = mig_p1_rd_count; + assign p0_wr_underrun = mig_p1_wr_underrun | mig_p0_wr_underrun; + assign p0_rd_overflow = mig_p1_rd_overflow | mig_p0_rd_overflow; + assign p0_rd_error = mig_p1_rd_error | mig_p0_rd_error; + assign p0_rd_full = mig_p1_rd_full; + assign p0_rd_empty = mig_p1_rd_empty; + + + end else + begin + assign mig_p0_arb_en = 'b0; + assign mig_p0_cmd_clk = 'b0; + assign mig_p0_cmd_en = 'b0; + assign mig_p0_cmd_ra = 'b0; + assign mig_p0_cmd_ba = 'b0; + assign mig_p0_cmd_ca = 'b0; + assign mig_p0_cmd_instr = 'b0; + assign mig_p0_cmd_bl = 'b0; + + assign mig_p0_wr_clk = 'b0; + assign mig_p0_rd_clk = 'b0; + assign mig_p1_wr_clk = 'b0; + assign mig_p1_rd_clk = 'b0; + assign mig_p0_wr_en = 'b0; + assign mig_p1_wr_en = 'b0; + assign mig_p0_wr_data = 'b0; + assign mig_p0_wr_mask = 'b0; + assign mig_p1_wr_data = 'b0; + assign mig_p1_wr_mask = 'b0; + // assign mig_p1_wr_en = 'b0; + assign mig_p0_rd_en = 'b0; + assign mig_p1_rd_en = 'b0; + assign p0_rd_data = 'b0; + + + assign p0_cmd_empty = 'b0; + assign p0_cmd_full = 'b0; + assign p0_wr_empty = 'b0; + assign p0_wr_full = 'b0; + assign p0_wr_error = 'b0; + assign p0_wr_count = 'b0; + assign p0_rd_count = 'b0; + assign p0_wr_underrun = 'b0; + assign p0_rd_overflow = 'b0; + assign p0_rd_error = 'b0; + assign p0_rd_full = 'b0; + assign p0_rd_empty = 'b0; + + + end + + + + if (C_PORT_ENABLE[1] == 1'b1) + begin + + assign mig_p2_arb_en = p1_arb_en ; + + assign mig_p2_cmd_clk = p1_cmd_clk ; + assign mig_p2_cmd_en = p1_cmd_en ; + assign mig_p2_cmd_ra = p1_cmd_ra ; + assign mig_p2_cmd_ba = p1_cmd_ba ; + assign mig_p2_cmd_ca = p1_cmd_ca ; + assign mig_p2_cmd_instr = p1_cmd_instr; + assign mig_p2_cmd_bl = {(p1_cmd_instr[2] | p1_cmd_bl[5]),p1_cmd_bl[4:0]} ; + + + assign mig_p2_clk = p1_rd_clk; + assign mig_p3_clk = p1_wr_clk; + assign mig_p4_clk = p1_rd_clk; + assign mig_p5_clk = p1_wr_clk; + assign mig_p3_en = p1_wr_en & !p1_wr_full; + assign mig_p5_en = p1_wr_en & !p1_wr_full; + assign mig_p3_wr_data = p1_wr_data[31:0]; + assign mig_p3_wr_mask = p1_wr_mask[3:0]; + assign mig_p5_wr_data = p1_wr_data[63 : 32]; + assign mig_p5_wr_mask = p1_wr_mask[7 : 4]; + assign mig_p2_en = p1_rd_en & !p1_rd_empty; + assign mig_p4_en = p1_rd_en & !p1_rd_empty; + + assign p1_cmd_empty = mig_p2_cmd_empty ; + assign p1_cmd_full = mig_p2_cmd_full ; + + assign p1_wr_count = mig_p5_count; + assign p1_rd_count = mig_p4_count; + assign p1_wr_full = mig_p5_full; + assign p1_wr_error = mig_p5_error | mig_p5_error; + assign p1_wr_empty = mig_p5_empty; + assign p1_wr_underrun = mig_p3_underrun | mig_p5_underrun; + assign p1_rd_overflow = mig_p4_overflow; + assign p1_rd_error = mig_p4_error; + assign p1_rd_full = mig_p4_full; + assign p1_rd_empty = mig_p4_empty; + + assign p1_rd_data = {mig_p4_rd_data , mig_p2_rd_data}; + + + end else + begin + assign mig_p2_arb_en = 'b0; + // assign mig_p3_arb_en = 'b0; + // assign mig_p4_arb_en = 'b0; + // assign mig_p5_arb_en = 'b0; + + assign mig_p2_cmd_clk = 'b0; + assign mig_p2_cmd_en = 'b0; + assign mig_p2_cmd_ra = 'b0; + assign mig_p2_cmd_ba = 'b0; + assign mig_p2_cmd_ca = 'b0; + assign mig_p2_cmd_instr = 'b0; + assign mig_p2_cmd_bl = 'b0; + assign mig_p2_clk = 'b0; + assign mig_p3_clk = 'b0; + assign mig_p4_clk = 'b0; + assign mig_p5_clk = 'b0; + assign mig_p3_en = 'b0; + assign mig_p5_en = 'b0; + assign mig_p3_wr_data = 'b0; + assign mig_p3_wr_mask = 'b0; + assign mig_p5_wr_data = 'b0; + assign mig_p5_wr_mask = 'b0; + assign mig_p2_en = 'b0; + assign mig_p4_en = 'b0; + assign p1_cmd_empty = 'b0; + assign p1_cmd_full = 'b0; + + assign p1_wr_count = 'b0; + assign p1_rd_count = 'b0; + assign p1_wr_full = 'b0; + assign p1_wr_error = 'b0; + assign p1_wr_empty = 'b0; + assign p1_wr_underrun = 'b0; + assign p1_rd_overflow = 'b0; + assign p1_rd_error = 'b0; + assign p1_rd_full = 'b0; + assign p1_rd_empty = 'b0; + assign p1_rd_data = 'b0; + + end + + // unused MCB's signals in this configuration + assign mig_p3_arb_en = 1'b0; + assign mig_p4_arb_en = 1'b0; + assign mig_p5_arb_en = 1'b0; + + assign mig_p3_cmd_clk = 1'b0; + assign mig_p3_cmd_en = 1'b0; + assign mig_p3_cmd_ra = 15'd0; + assign mig_p3_cmd_ba = 3'd0; + assign mig_p3_cmd_ca = 12'd0; + assign mig_p3_cmd_instr = 3'd0; + + assign mig_p4_cmd_clk = 1'b0; + assign mig_p4_cmd_en = 1'b0; + assign mig_p4_cmd_ra = 15'd0; + assign mig_p4_cmd_ba = 3'd0; + assign mig_p4_cmd_ca = 12'd0; + assign mig_p4_cmd_instr = 3'd0; + assign mig_p4_cmd_bl = 6'd0; + + assign mig_p5_cmd_clk = 1'b0; + assign mig_p5_cmd_en = 1'b0; + assign mig_p5_cmd_ra = 15'd0; + assign mig_p5_cmd_ba = 3'd0; + assign mig_p5_cmd_ca = 12'd0; + assign mig_p5_cmd_instr = 3'd0; + assign mig_p5_cmd_bl = 6'd0; + + + + + end else if(C_PORT_CONFIG == "B128" ) begin : u_config_5 +//*******************************BEGIN OF CONFIG 5 SIGNALS ******************************** + + // Inputs from Application CMD Port + + assign mig_p0_arb_en = p0_arb_en ; + assign mig_p0_cmd_clk = p0_cmd_clk ; + assign mig_p0_cmd_en = p0_cmd_en ; + assign mig_p0_cmd_ra = p0_cmd_ra ; + assign mig_p0_cmd_ba = p0_cmd_ba ; + assign mig_p0_cmd_ca = p0_cmd_ca ; + assign mig_p0_cmd_instr = p0_cmd_instr; + assign mig_p0_cmd_bl = {(p0_cmd_instr[2] | p0_cmd_bl[5]),p0_cmd_bl[4:0]} ; + + assign p0_cmd_empty = mig_p0_cmd_empty ; + assign p0_cmd_full = mig_p0_cmd_full ; + + + + // Inputs from Application User Port + + assign mig_p0_wr_clk = p0_wr_clk; + assign mig_p0_rd_clk = p0_rd_clk; + assign mig_p1_wr_clk = p0_wr_clk; + assign mig_p1_rd_clk = p0_rd_clk; + + assign mig_p2_clk = p0_rd_clk; + assign mig_p3_clk = p0_wr_clk; + assign mig_p4_clk = p0_rd_clk; + assign mig_p5_clk = p0_wr_clk; + + + + assign mig_p0_wr_en = p0_wr_en & !p0_wr_full; + assign mig_p1_wr_en = p0_wr_en & !p0_wr_full; + assign mig_p3_en = p0_wr_en & !p0_wr_full; + assign mig_p5_en = p0_wr_en & !p0_wr_full; + + + + assign mig_p0_wr_data = p0_wr_data[31:0]; + assign mig_p0_wr_mask = p0_wr_mask[3:0]; + assign mig_p1_wr_data = p0_wr_data[63 : 32]; + assign mig_p1_wr_mask = p0_wr_mask[7 : 4]; + assign mig_p3_wr_data = p0_wr_data[95 : 64]; + assign mig_p3_wr_mask = p0_wr_mask[11 : 8]; + assign mig_p5_wr_data = p0_wr_data[127 : 96]; + assign mig_p5_wr_mask = p0_wr_mask[15 : 12]; + + assign mig_p0_rd_en = p0_rd_en & !p0_rd_empty; + assign mig_p1_rd_en = p0_rd_en & !p0_rd_empty; + assign mig_p2_en = p0_rd_en & !p0_rd_empty; + assign mig_p4_en = p0_rd_en & !p0_rd_empty; + + // outputs to Applications User Port + assign p0_rd_data = {mig_p4_rd_data , mig_p2_rd_data , mig_p1_rd_data , mig_p0_rd_data}; + assign p0_rd_empty = mig_p4_empty; + assign p0_rd_full = mig_p4_full; + assign p0_rd_error = mig_p0_rd_error | mig_p1_rd_error | mig_p2_error | mig_p4_error; + assign p0_rd_overflow = mig_p0_rd_overflow | mig_p1_rd_overflow | mig_p2_overflow | mig_p4_overflow; + + assign p0_wr_underrun = mig_p0_wr_underrun | mig_p1_wr_underrun | mig_p3_underrun | mig_p5_underrun; + assign p0_wr_empty = mig_p5_empty; + assign p0_wr_full = mig_p5_full; + assign p0_wr_error = mig_p0_wr_error | mig_p1_wr_error | mig_p3_error | mig_p5_error; + + assign p0_wr_count = mig_p5_count; + assign p0_rd_count = mig_p4_count; + + + // unused MCB's siganls in this configuration + + assign mig_p1_arb_en = 1'b0; + assign mig_p1_cmd_clk = 1'b0; + assign mig_p1_cmd_en = 1'b0; + assign mig_p1_cmd_ra = 15'd0; + assign mig_p1_cmd_ba = 3'd0; + assign mig_p1_cmd_ca = 12'd0; + + assign mig_p1_cmd_instr = 3'd0; + assign mig_p1_cmd_bl = 6'd0; + + assign mig_p2_arb_en = 1'b0; + assign mig_p2_cmd_clk = 1'b0; + assign mig_p2_cmd_en = 1'b0; + assign mig_p2_cmd_ra = 15'd0; + assign mig_p2_cmd_ba = 3'd0; + assign mig_p2_cmd_ca = 12'd0; + + assign mig_p2_cmd_instr = 3'd0; + assign mig_p2_cmd_bl = 6'd0; + + assign mig_p3_arb_en = 1'b0; + assign mig_p3_cmd_clk = 1'b0; + assign mig_p3_cmd_en = 1'b0; + assign mig_p3_cmd_ra = 15'd0; + assign mig_p3_cmd_ba = 3'd0; + assign mig_p3_cmd_ca = 12'd0; + + assign mig_p3_cmd_instr = 3'd0; + assign mig_p3_cmd_bl = 6'd0; + + assign mig_p4_arb_en = 1'b0; + assign mig_p4_cmd_clk = 1'b0; + assign mig_p4_cmd_en = 1'b0; + assign mig_p4_cmd_ra = 15'd0; + assign mig_p4_cmd_ba = 3'd0; + assign mig_p4_cmd_ca = 12'd0; + + assign mig_p4_cmd_instr = 3'd0; + assign mig_p4_cmd_bl = 6'd0; + + assign mig_p5_arb_en = 1'b0; + assign mig_p5_cmd_clk = 1'b0; + assign mig_p5_cmd_en = 1'b0; + assign mig_p5_cmd_ra = 15'd0; + assign mig_p5_cmd_ba = 3'd0; + assign mig_p5_cmd_ca = 12'd0; + + assign mig_p5_cmd_instr = 3'd0; + assign mig_p5_cmd_bl = 6'd0; + +//*******************************END OF CONFIG 5 SIGNALS ******************************** + +end +endgenerate + + MCB + # ( .PORT_CONFIG (C_PORT_CONFIG), + .MEM_WIDTH (C_NUM_DQ_PINS ), + .MEM_TYPE (C_MEM_TYPE ), + .MEM_BURST_LEN (C_MEM_BURST_LEN ), + .MEM_ADDR_ORDER (C_MEM_ADDR_ORDER), + .MEM_CAS_LATENCY (C_MEM_CAS_LATENCY), + .MEM_DDR3_CAS_LATENCY (C_MEM_DDR3_CAS_LATENCY ), + .MEM_DDR2_WRT_RECOVERY (C_MEM_DDR2_WRT_RECOVERY ), + .MEM_DDR3_WRT_RECOVERY (C_MEM_DDR3_WRT_RECOVERY ), + .MEM_MOBILE_PA_SR (C_MEM_MOBILE_PA_SR ), + .MEM_DDR1_2_ODS (C_MEM_DDR1_2_ODS ), + .MEM_DDR3_ODS (C_MEM_DDR3_ODS ), + .MEM_DDR2_RTT (C_MEM_DDR2_RTT ), + .MEM_DDR3_RTT (C_MEM_DDR3_RTT ), + .MEM_DDR3_ADD_LATENCY (C_MEM_DDR3_ADD_LATENCY ), + .MEM_DDR2_ADD_LATENCY (C_MEM_DDR2_ADD_LATENCY ), + .MEM_MOBILE_TC_SR (C_MEM_MOBILE_TC_SR ), + .MEM_MDDR_ODS (C_MEM_MDDR_ODS ), + .MEM_DDR2_DIFF_DQS_EN (C_MEM_DDR2_DIFF_DQS_EN ), + .MEM_DDR2_3_PA_SR (C_MEM_DDR2_3_PA_SR ), + .MEM_DDR3_CAS_WR_LATENCY (C_MEM_DDR3_CAS_WR_LATENCY), + .MEM_DDR3_AUTO_SR (C_MEM_DDR3_AUTO_SR ), + .MEM_DDR2_3_HIGH_TEMP_SR (C_MEM_DDR2_3_HIGH_TEMP_SR), + .MEM_DDR3_DYN_WRT_ODT (C_MEM_DDR3_DYN_WRT_ODT ), + .MEM_RA_SIZE (C_MEM_ADDR_WIDTH ), + .MEM_BA_SIZE (C_MEM_BANKADDR_WIDTH ), + .MEM_CA_SIZE (C_MEM_NUM_COL_BITS ), + .MEM_RAS_VAL (MEM_RAS_VAL ), + .MEM_RCD_VAL (MEM_RCD_VAL ), + .MEM_REFI_VAL (MEM_REFI_VAL ), + .MEM_RFC_VAL (MEM_RFC_VAL ), + .MEM_RP_VAL (MEM_RP_VAL ), + .MEM_WR_VAL (MEM_WR_VAL ), + .MEM_RTP_VAL (MEM_RTP_VAL ), + .MEM_WTR_VAL (MEM_WTR_VAL ), + .CAL_BYPASS (C_MC_CALIB_BYPASS), + .CAL_RA (C_MC_CALIBRATION_RA), + .CAL_BA (C_MC_CALIBRATION_BA ), + .CAL_CA (C_MC_CALIBRATION_CA), + .CAL_CLK_DIV (C_MC_CALIBRATION_CLK_DIV), + .CAL_DELAY (C_MC_CALIBRATION_DELAY), + .ARB_NUM_TIME_SLOTS (C_ARB_NUM_TIME_SLOTS), + .ARB_TIME_SLOT_0 (arbtimeslot0 ) , + .ARB_TIME_SLOT_1 (arbtimeslot1 ) , + .ARB_TIME_SLOT_2 (arbtimeslot2 ) , + .ARB_TIME_SLOT_3 (arbtimeslot3 ) , + .ARB_TIME_SLOT_4 (arbtimeslot4 ) , + .ARB_TIME_SLOT_5 (arbtimeslot5 ) , + .ARB_TIME_SLOT_6 (arbtimeslot6 ) , + .ARB_TIME_SLOT_7 (arbtimeslot7 ) , + .ARB_TIME_SLOT_8 (arbtimeslot8 ) , + .ARB_TIME_SLOT_9 (arbtimeslot9 ) , + .ARB_TIME_SLOT_10 (arbtimeslot10) , + .ARB_TIME_SLOT_11 (arbtimeslot11) + ) samc_0 + ( + + // HIGH-SPEED PLL clock interface + + .PLLCLK ({ioclk90,ioclk0}), + .PLLCE ({pll_ce_90,pll_ce_0}) , + + .PLLLOCK (1'b1), + + // DQS CLOCK NETWork interface + + .DQSIOIN (idelay_dqs_ioi_s), + .DQSIOIP (idelay_dqs_ioi_m), + .UDQSIOIN (idelay_udqs_ioi_s), + .UDQSIOIP (idelay_udqs_ioi_m), + + + //.DQSPIN (in_pre_dqsp), + .DQI (in_dq), + // RESETS - GLOBAl & local + .SYSRST (MCB_SYSRST ), + + // command port 0 + .P0ARBEN (mig_p0_arb_en), + .P0CMDCLK (mig_p0_cmd_clk), + .P0CMDEN (mig_p0_cmd_en), + .P0CMDRA (mig_p0_cmd_ra), + .P0CMDBA (mig_p0_cmd_ba), + .P0CMDCA (mig_p0_cmd_ca), + + .P0CMDINSTR (mig_p0_cmd_instr), + .P0CMDBL (mig_p0_cmd_bl), + .P0CMDEMPTY (mig_p0_cmd_empty), + .P0CMDFULL (mig_p0_cmd_full), + + // command port 1 + + .P1ARBEN (mig_p1_arb_en), + .P1CMDCLK (mig_p1_cmd_clk), + .P1CMDEN (mig_p1_cmd_en), + .P1CMDRA (mig_p1_cmd_ra), + .P1CMDBA (mig_p1_cmd_ba), + .P1CMDCA (mig_p1_cmd_ca), + + .P1CMDINSTR (mig_p1_cmd_instr), + .P1CMDBL (mig_p1_cmd_bl), + .P1CMDEMPTY (mig_p1_cmd_empty), + .P1CMDFULL (mig_p1_cmd_full), + + // command port 2 + + .P2ARBEN (mig_p2_arb_en), + .P2CMDCLK (mig_p2_cmd_clk), + .P2CMDEN (mig_p2_cmd_en), + .P2CMDRA (mig_p2_cmd_ra), + .P2CMDBA (mig_p2_cmd_ba), + .P2CMDCA (mig_p2_cmd_ca), + + .P2CMDINSTR (mig_p2_cmd_instr), + .P2CMDBL (mig_p2_cmd_bl), + .P2CMDEMPTY (mig_p2_cmd_empty), + .P2CMDFULL (mig_p2_cmd_full), + + // command port 3 + + .P3ARBEN (mig_p3_arb_en), + .P3CMDCLK (mig_p3_cmd_clk), + .P3CMDEN (mig_p3_cmd_en), + .P3CMDRA (mig_p3_cmd_ra), + .P3CMDBA (mig_p3_cmd_ba), + .P3CMDCA (mig_p3_cmd_ca), + + .P3CMDINSTR (mig_p3_cmd_instr), + .P3CMDBL (mig_p3_cmd_bl), + .P3CMDEMPTY (mig_p3_cmd_empty), + .P3CMDFULL (mig_p3_cmd_full), + + // command port 4 // don't care in config 2 + + .P4ARBEN (mig_p4_arb_en), + .P4CMDCLK (mig_p4_cmd_clk), + .P4CMDEN (mig_p4_cmd_en), + .P4CMDRA (mig_p4_cmd_ra), + .P4CMDBA (mig_p4_cmd_ba), + .P4CMDCA (mig_p4_cmd_ca), + + .P4CMDINSTR (mig_p4_cmd_instr), + .P4CMDBL (mig_p4_cmd_bl), + .P4CMDEMPTY (mig_p4_cmd_empty), + .P4CMDFULL (mig_p4_cmd_full), + + // command port 5 // don't care in config 2 + + .P5ARBEN (mig_p5_arb_en), + .P5CMDCLK (mig_p5_cmd_clk), + .P5CMDEN (mig_p5_cmd_en), + .P5CMDRA (mig_p5_cmd_ra), + .P5CMDBA (mig_p5_cmd_ba), + .P5CMDCA (mig_p5_cmd_ca), + + .P5CMDINSTR (mig_p5_cmd_instr), + .P5CMDBL (mig_p5_cmd_bl), + .P5CMDEMPTY (mig_p5_cmd_empty), + .P5CMDFULL (mig_p5_cmd_full), + + + // IOI & IOB SIGNals/tristate interface + + .DQIOWEN0 (dqIO_w_en_0), + .DQSIOWEN90P (dqsIO_w_en_90_p), + .DQSIOWEN90N (dqsIO_w_en_90_n), + + + // IOB MEMORY INTerface signals + .ADDR (address_90), + .BA (ba_90 ), + .RAS (ras_90 ), + .CAS (cas_90 ), + .WE (we_90 ), + .CKE (cke_90 ), + .ODT (odt_90 ), + .RST (rst_90 ), + + // CALIBRATION DRP interface + .IOIDRPCLK (ioi_drp_clk ), + .IOIDRPADDR (ioi_drp_addr ), + .IOIDRPSDO (ioi_drp_sdo ), + .IOIDRPSDI (ioi_drp_sdi ), + .IOIDRPCS (ioi_drp_cs ), + .IOIDRPADD (ioi_drp_add ), + .IOIDRPBROADCAST (ioi_drp_broadcast ), + .IOIDRPTRAIN (ioi_drp_train ), + .IOIDRPUPDATE (ioi_drp_update) , + + // CALIBRATION DAtacapture interface + //SPECIAL COMMANDs + .RECAL (mcb_recal ), + .UIREAD (mcb_ui_read), + .UIADD (mcb_ui_add) , + .UICS (mcb_ui_cs) , + .UICLK (mcb_ui_clk) , + .UISDI (mcb_ui_sdi) , + .UIADDR (mcb_ui_addr) , + .UIBROADCAST (mcb_ui_broadcast) , + .UIDRPUPDATE (mcb_ui_drp_update) , + .UIDONECAL (mcb_ui_done_cal) , + .UICMD (mcb_ui_cmd), + .UICMDIN (mcb_ui_cmd_in) , + .UICMDEN (mcb_ui_cmd_en) , + .UIDQCOUNT (mcb_ui_dqcount) , + .UIDQLOWERDEC (mcb_ui_dq_lower_dec), + .UIDQLOWERINC (mcb_ui_dq_lower_inc), + .UIDQUPPERDEC (mcb_ui_dq_upper_dec), + .UIDQUPPERINC (mcb_ui_dq_upper_inc), + .UIUDQSDEC (mcb_ui_udqs_dec), + .UIUDQSINC (mcb_ui_udqs_inc), + .UILDQSDEC (mcb_ui_ldqs_dec), + .UILDQSINC (mcb_ui_ldqs_inc), + .UODATA (uo_data), + .UODATAVALID (uo_data_valid), + .UODONECAL (hard_done_cal) , + .UOCMDREADYIN (uo_cmd_ready_in), + .UOREFRSHFLAG (uo_refrsh_flag), + .UOCALSTART (uo_cal_start) , + .UOSDO (uo_sdo), + + //CONTROL SIGNALS + .STATUS (status), + .SELFREFRESHENTER (selfrefresh_mcb_enter ), + .SELFREFRESHMODE (selfrefresh_mcb_mode ), +////////////////////////////// ////////////////// +//MUIs +//////////////////////////////////////////////// + + .P0RDDATA ( mig_p0_rd_data[31:0] ), + .P1RDDATA ( mig_p1_rd_data[31:0] ), + .P2RDDATA ( mig_p2_rd_data[31:0] ), + .P3RDDATA ( mig_p3_rd_data[31:0] ), + .P4RDDATA ( mig_p4_rd_data[31:0] ), + .P5RDDATA ( mig_p5_rd_data[31:0] ), + .LDMN ( dqnlm ), + .UDMN ( dqnum ), + .DQON ( dqo_n ), + .DQOP ( dqo_p ), + .LDMP ( dqplm ), + .UDMP ( dqpum ), + + .P0RDCOUNT ( mig_p0_rd_count ), + .P0WRCOUNT ( mig_p0_wr_count ), + .P1RDCOUNT ( mig_p1_rd_count ), + .P1WRCOUNT ( mig_p1_wr_count ), + .P2COUNT ( mig_p2_count ), + .P3COUNT ( mig_p3_count ), + .P4COUNT ( mig_p4_count ), + .P5COUNT ( mig_p5_count ), + + // NEW ADDED FIFo status siganls + // MIG USER PORT 0 + .P0RDEMPTY ( mig_p0_rd_empty), + .P0RDFULL ( mig_p0_rd_full), + .P0RDOVERFLOW ( mig_p0_rd_overflow), + .P0WREMPTY ( mig_p0_wr_empty), + .P0WRFULL ( mig_p0_wr_full), + .P0WRUNDERRUN ( mig_p0_wr_underrun), + // MIG USER PORT 1 + .P1RDEMPTY ( mig_p1_rd_empty), + .P1RDFULL ( mig_p1_rd_full), + .P1RDOVERFLOW ( mig_p1_rd_overflow), + .P1WREMPTY ( mig_p1_wr_empty), + .P1WRFULL ( mig_p1_wr_full), + .P1WRUNDERRUN ( mig_p1_wr_underrun), + + // MIG USER PORT 2 + .P2EMPTY ( mig_p2_empty), + .P2FULL ( mig_p2_full), + .P2RDOVERFLOW ( mig_p2_overflow), + .P2WRUNDERRUN ( mig_p2_underrun), + + .P3EMPTY ( mig_p3_empty ), + .P3FULL ( mig_p3_full ), + .P3RDOVERFLOW ( mig_p3_overflow), + .P3WRUNDERRUN ( mig_p3_underrun ), + // MIG USER PORT 3 + .P4EMPTY ( mig_p4_empty), + .P4FULL ( mig_p4_full), + .P4RDOVERFLOW ( mig_p4_overflow), + .P4WRUNDERRUN ( mig_p4_underrun), + + .P5EMPTY ( mig_p5_empty ), + .P5FULL ( mig_p5_full ), + .P5RDOVERFLOW ( mig_p5_overflow), + .P5WRUNDERRUN ( mig_p5_underrun), + + ////////////////////////////////////////////////////////- + .P0WREN ( mig_p0_wr_en), + .P0RDEN ( mig_p0_rd_en), + .P1WREN ( mig_p1_wr_en), + .P1RDEN ( mig_p1_rd_en), + .P2EN ( mig_p2_en), + .P3EN ( mig_p3_en), + .P4EN ( mig_p4_en), + .P5EN ( mig_p5_en), + // WRITE MASK BIts connection + .P0RWRMASK ( mig_p0_wr_mask[3:0]), + .P1RWRMASK ( mig_p1_wr_mask[3:0]), + .P2WRMASK ( mig_p2_wr_mask[3:0]), + .P3WRMASK ( mig_p3_wr_mask[3:0]), + .P4WRMASK ( mig_p4_wr_mask[3:0]), + .P5WRMASK ( mig_p5_wr_mask[3:0]), + // DATA WRITE COnnection + .P0WRDATA ( mig_p0_wr_data[31:0]), + .P1WRDATA ( mig_p1_wr_data[31:0]), + .P2WRDATA ( mig_p2_wr_data[31:0]), + .P3WRDATA ( mig_p3_wr_data[31:0]), + .P4WRDATA ( mig_p4_wr_data[31:0]), + .P5WRDATA ( mig_p5_wr_data[31:0]), + + .P0WRERROR (mig_p0_wr_error), + .P1WRERROR (mig_p1_wr_error), + .P0RDERROR (mig_p0_rd_error), + .P1RDERROR (mig_p1_rd_error), + + .P2ERROR (mig_p2_error), + .P3ERROR (mig_p3_error), + .P4ERROR (mig_p4_error), + .P5ERROR (mig_p5_error), + + // USER SIDE DAta ports clock + // 128 BITS CONnections + .P0WRCLK ( mig_p0_wr_clk ), + .P1WRCLK ( mig_p1_wr_clk ), + .P0RDCLK ( mig_p0_rd_clk ), + .P1RDCLK ( mig_p1_rd_clk ), + .P2CLK ( mig_p2_clk ), + .P3CLK ( mig_p3_clk ), + .P4CLK ( mig_p4_clk ), + .P5CLK ( mig_p5_clk) + //////////////////////////////////////////////////////// + // TST MODE PINS + + + + ); + + +////////////////////////////////////////////////////// +// Input Termination Calibration +////////////////////////////////////////////////////// +wire DONE_SOFTANDHARD_CAL; + +assign uo_done_cal = ( C_CALIB_SOFT_IP == "TRUE") ? DONE_SOFTANDHARD_CAL : hard_done_cal; +generate +if ( C_CALIB_SOFT_IP == "TRUE") begin: gen_term_calib + + + + + +mcb_soft_calibration_top # ( + + .C_MEM_TZQINIT_MAXCNT (C_MEM_TZQINIT_MAXCNT), + .C_MC_CALIBRATION_MODE(C_MC_CALIBRATION_MODE), + .SKIP_IN_TERM_CAL (C_SKIP_IN_TERM_CAL), + .SKIP_DYNAMIC_CAL (C_SKIP_DYNAMIC_CAL), + .SKIP_DYN_IN_TERM (C_SKIP_DYN_IN_TERM), + .C_SIMULATION (C_SIMULATION), + .C_MEM_TYPE (C_MEM_TYPE) + ) + mcb_soft_calibration_top_inst ( + .UI_CLK (ui_clk), //Input - global clock to be used for input_term_tuner and IODRP clock + .RST (int_sys_rst), //Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for IODRP (sub)controller + .IOCLK (ioclk0), //Input - IOCLK input to the IODRP's + .DONE_SOFTANDHARD_CAL (DONE_SOFTANDHARD_CAL), // active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete) + .PLL_LOCK (pll_lock), + + .SELFREFRESH_REQ (selfrefresh_enter), // from user app + .SELFREFRESH_MCB_MODE (selfrefresh_mcb_mode), // from MCB + .SELFREFRESH_MCB_REQ (selfrefresh_mcb_enter),// to mcb + .SELFREFRESH_MODE (selfrefresh_mode), // to user app + + + + .MCB_UIADD (mcb_ui_add), + .MCB_UISDI (mcb_ui_sdi), + .MCB_UOSDO (uo_sdo), // from MCB's UOSDO port (User output SDO) + .MCB_UODONECAL (hard_done_cal), // input for when MCB hard calibration process is complete + .MCB_UOREFRSHFLAG (uo_refrsh_flag), //high during refresh cycle and time when MCB is innactive + .MCB_UICS (mcb_ui_cs), // to MCB's UICS port (User Input CS) + .MCB_UIDRPUPDATE (mcb_ui_drp_update), // MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used during IODRP2_MCB writes). Currently just trasnparent + .MCB_UIBROADCAST (mcb_ui_broadcast), // to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) + .MCB_UIADDR (mcb_ui_addr), //to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port + .MCB_UICMDEN (mcb_ui_cmd_en), //set to take control of UI interface - removes control from internal calib block + .MCB_UIDONECAL (mcb_ui_done_cal), // + .MCB_UIDQLOWERDEC (mcb_ui_dq_lower_dec), + .MCB_UIDQLOWERINC (mcb_ui_dq_lower_inc), + .MCB_UIDQUPPERDEC (mcb_ui_dq_upper_dec), + .MCB_UIDQUPPERINC (mcb_ui_dq_upper_inc), + .MCB_UILDQSDEC (mcb_ui_ldqs_dec), + .MCB_UILDQSINC (mcb_ui_ldqs_inc), + .MCB_UIREAD (mcb_ui_read), //enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. + .MCB_UIUDQSDEC (mcb_ui_udqs_dec), + .MCB_UIUDQSINC (mcb_ui_udqs_inc), + .MCB_RECAL (mcb_recal), + .MCB_SYSRST (MCB_SYSRST), //drives the MCB's SYSRST pin - the main reset for MCB + .MCB_UICMD (mcb_ui_cmd), + .MCB_UICMDIN (mcb_ui_cmd_in), + .MCB_UIDQCOUNT (mcb_ui_dqcount), + .MCB_UODATA (uo_data), + .MCB_UODATAVALID (uo_data_valid), + .MCB_UOCMDREADY (uo_cmd_ready_in), + .MCB_UO_CAL_START (uo_cal_start), + .RZQ_Pin (rzq), + .ZIO_Pin (zio), + .CKE_Train (cke_train) + + ); + + + + + + + assign mcb_ui_clk = ui_clk; +end +endgenerate + +generate +if ( C_CALIB_SOFT_IP != "TRUE") begin: gen_no_term_calib + assign DONE_SOFTANDHARD_CAL = 1'b0; + assign MCB_SYSRST = int_sys_rst | (~wait_200us_counter[15]); + assign mcb_recal = calib_recal; + assign mcb_ui_read = ui_read; + assign mcb_ui_add = ui_add; + assign mcb_ui_cs = ui_cs; + assign mcb_ui_clk = ui_clk; + assign mcb_ui_sdi = ui_sdi; + assign mcb_ui_addr = ui_addr; + assign mcb_ui_broadcast = ui_broadcast; + assign mcb_ui_drp_update = ui_drp_update; + assign mcb_ui_done_cal = ui_done_cal; + assign mcb_ui_cmd = ui_cmd; + assign mcb_ui_cmd_in = ui_cmd_in; + assign mcb_ui_cmd_en = ui_cmd_en; + assign mcb_ui_dq_lower_dec = ui_dq_lower_dec; + assign mcb_ui_dq_lower_inc = ui_dq_lower_inc; + assign mcb_ui_dq_upper_dec = ui_dq_upper_dec; + assign mcb_ui_dq_upper_inc = ui_dq_upper_inc; + assign mcb_ui_udqs_inc = ui_udqs_inc; + assign mcb_ui_udqs_dec = ui_udqs_dec; + assign mcb_ui_ldqs_inc = ui_ldqs_inc; + assign mcb_ui_ldqs_dec = ui_ldqs_dec; + assign selfrefresh_mode = 1'b0; + + if (C_SIMULATION == "FALSE") begin: init_sequence + always @ (posedge ui_clk, posedge int_sys_rst) + begin + if (int_sys_rst) + wait_200us_counter <= 'b0; + else + if (wait_200us_counter[15]) // UI_CLK maximum is up to 100 MHz. + wait_200us_counter <= wait_200us_counter ; + else + wait_200us_counter <= wait_200us_counter + 1'b1; + end + end + else begin: init_sequence_skip +// synthesis translate_off + initial + begin + wait_200us_counter = 16'hFFFF; + $display("The 200 us wait period required before CKE goes active has been skipped in Simulation\n"); + end +// synthesis translate_on + end + + + if( C_MEM_TYPE == "DDR2") begin : gen_cketrain_a + + always @ ( posedge ui_clk) + begin + // When wait_200us_[13] and wait_200us_[14] are both asserted, + // 200 us wait should have been passed. + if (wait_200us_counter[14] && wait_200us_counter[13]) + wait_200us_done_r1 <= 1'b1; + else + wait_200us_done_r1 <= 1'b0; + + + wait_200us_done_r2 <= wait_200us_done_r1; + end + + always @ ( posedge ui_clk, posedge int_sys_rst) + begin + if (int_sys_rst) + cke_train_reg <= 1'b0; + else + if ( wait_200us_done_r1 && ~wait_200us_done_r2 ) + cke_train_reg <= 1'b1; + else if ( uo_done_cal) + cke_train_reg <= 1'b0; + end + + assign cke_train = cke_train_reg; + end + + if( C_MEM_TYPE != "DDR2") begin : gen_cketrain_b + + assign cke_train = 1'b0; + end + + +end +endgenerate + +////////////////////////////////////////////////////// +//ODDRDES2 instantiations +////////////////////////////////////////////////////// + +//////// +//ADDR +//////// + +genvar addr_ioi; + generate + for(addr_ioi = 0; addr_ioi < C_MEM_ADDR_WIDTH; addr_ioi = addr_ioi + 1) begin : gen_addr_oserdes2 +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_addr_0 +( + .OQ(ioi_addr[addr_ioi]), + .SHIFTOUT1(), + .SHIFTOUT2(), + .SHIFTOUT3(), + .SHIFTOUT4(), + .TQ(t_addr[addr_ioi]), + .CLK0(ioclk0), + .CLK1(), + .CLKDIV(), + .D1(address_90[addr_ioi]), + .D2(address_90[addr_ioi]), + .D3(), + .D4(), + .IOCE(pll_ce_0), + .OCE(1'b1), + .RST(int_sys_rst), + .SHIFTIN1(), + .SHIFTIN2(), + .SHIFTIN3(), + .SHIFTIN4(), + .T1(1'b0), + .T2(1'b0), + .T3(), + .T4(), + .TCE(1'b1), + .TRAIN(1'b0) + ); + end + endgenerate + +//////// +//BA +//////// + +genvar ba_ioi; + generate + for(ba_ioi = 0; ba_ioi < C_MEM_BANKADDR_WIDTH; ba_ioi = ba_ioi + 1) begin : gen_ba_oserdes2 +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_ba_0 +( + .OQ (ioi_ba[ba_ioi]), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .TQ (t_ba[ba_ioi]), + .CLK0 (ioclk0), + .CLK1 (), + .CLKDIV (), + .D1 (ba_90[ba_ioi]), + .D2 (ba_90[ba_ioi]), + .D3 (), + .D4 (), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1(1'b0), + .T2(1'b0), + .T3(), + .T4(), + .TCE(1'b1), + .TRAIN (1'b0) + ); + end + endgenerate + +//////// +//CAS +//////// + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_cas_0 +( + .OQ (ioi_cas), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .TQ (t_cas), + .CLK0 (ioclk0), + .CLK1 (), + .CLKDIV (), + .D1 (cas_90), + .D2 (cas_90), + .D3 (), + .D4 (), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1(1'b0), + .T2(1'b0), + .T3(), + .T4(), + .TCE(1'b1), + .TRAIN (1'b0) + ); + +//////// +//CKE +//////// + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) , // {1..8} + .TRAIN_PATTERN (15) +) ioi_cke_0 +( + .OQ (ioi_cke), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .TQ (t_cke), + .CLK0 (ioclk0), + .CLK1 (), + .CLKDIV (), + .D1 (cke_90), + .D2 (cke_90), + .D3 (), + .D4 (), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (1'b0),//int_sys_rst + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1(1'b0), + .T2(1'b0), + .T3(), + .T4(), + .TCE(1'b1), + .TRAIN (cke_train) + ); + +//////// +//ODT +//////// +generate +if(C_MEM_TYPE == "DDR3" || C_MEM_TYPE == "DDR2" ) begin : gen_ioi_odt + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_odt_0 +( + .OQ (ioi_odt), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .TQ (t_odt), + .CLK0 (ioclk0), + .CLK1 (), + .CLKDIV (), + .D1 (odt_90), + .D2 (odt_90), + .D3 (), + .D4 (), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1(1'b0), + .T2(1'b0), + .T3(), + .T4(), + .TCE(1'b1), + .TRAIN (1'b0) + ); +end +endgenerate +//////// +//RAS +//////// + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_ras_0 +( + .OQ (ioi_ras), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .TQ (t_ras), + .CLK0 (ioclk0), + .CLK1 (), + .CLKDIV (), + .D1 (ras_90), + .D2 (ras_90), + .D3 (), + .D4 (), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1 (1'b0), + .T2 (1'b0), + .T3 (), + .T4 (), + .TCE (1'b1), + .TRAIN (1'b0) + ); + +//////// +//RST +//////// +generate +if (C_MEM_TYPE == "DDR3" ) begin : gen_ioi_rst + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_rst_0 +( + .OQ (ioi_rst), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .TQ (t_rst), + .CLK0 (ioclk0), + .CLK1 (), + .CLKDIV (), + .D1 (rst_90), + .D2 (rst_90), + .D3 (), + .D4 (), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1(1'b0), + .T2(1'b0), + .T3(), + .T4(), + .TCE(1'b1), + .TRAIN (1'b0) + ); +end +endgenerate +//////// +//WE +//////// + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_we_0 +( + .OQ (ioi_we), + .TQ (t_we), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .CLK0 (ioclk0), + .CLK1 (), + .CLKDIV (), + .D1 (we_90), + .D2 (we_90), + .D3 (), + .D4 (), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1(1'b0), + .T2(1'b0), + .T3(), + .T4(), + .TCE(1'b1), + .TRAIN (1'b0) +); + +//////// +//CK +//////// + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_ck_0 +( + .OQ (ioi_ck), + .SHIFTOUT1(), + .SHIFTOUT2(), + .SHIFTOUT3(), + .SHIFTOUT4(), + .TQ (t_ck), + .CLK0 (ioclk0), + .CLK1(), + .CLKDIV(), + .D1 (1'b0), + .D2 (1'b1), + .D3(), + .D4(), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (1'b0),//int_sys_rst + .SHIFTIN1(), + .SHIFTIN2(), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1(1'b0), + .T2(1'b0), + .T3(), + .T4(), + .TCE(1'b1), + .TRAIN (1'b0) +); + +//////// +//CKN +//////// +/* +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_SLAVE), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_ckn_0 +( + .OQ (ioi_ckn), + .SHIFTOUT1(), + .SHIFTOUT2(), + .SHIFTOUT3(), + .SHIFTOUT4(), + .TQ (t_ckn), + .CLK0 (ioclk0), + .CLK1(), + .CLKDIV(), + .D1 (1'b1), + .D2 (1'b0), + .D3(), + .D4(), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (1'b0),//int_sys_rst + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3(), + .SHIFTIN4(), + .T1(1'b0), + .T2(1'b0), + .T3(), + .T4(), + .TCE(1'b1), + .TRAIN (1'b0) +); +*/ + +//////// +//UDM +//////// + +wire udm_oq; +wire udm_t; +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_udm_0 +( + .OQ (udm_oq), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .TQ (udm_t), + .CLK0 (ioclk90), + .CLK1 (), + .CLKDIV (), + .D1 (dqpum), + .D2 (dqnum), + .D3 (), + .D4 (), + .IOCE (pll_ce_90), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1 (dqIO_w_en_0), + .T2 (dqIO_w_en_0), + .T3 (), + .T4 (), + .TCE (1'b1), + .TRAIN (1'b0) +); + +//////// +//LDM +//////// +wire ldm_oq; +wire ldm_t; +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) ioi_ldm_0 +( + .OQ (ldm_oq), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .TQ (ldm_t), + .CLK0 (ioclk90), + .CLK1 (), + .CLKDIV (), + .D1 (dqplm), + .D2 (dqnlm), + .D3 (), + .D4 (), + .IOCE (pll_ce_90), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1 (dqIO_w_en_0), + .T2 (dqIO_w_en_0), + .T3 (), + .T4 (), + .TCE (1'b1), + .TRAIN (1'b0) +); + +//////// +//DQ +//////// + +wire dq_oq [C_NUM_DQ_PINS-1:0]; +wire dq_tq [C_NUM_DQ_PINS-1:0]; + +genvar dq; +generate + for(dq = 0; dq < C_NUM_DQ_PINS; dq = dq + 1) begin : gen_dq + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2), // {1..8} + .TRAIN_PATTERN (5) // {0..15} +) oserdes2_dq_0 +( + .OQ (dq_oq[dq]), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .SHIFTOUT3 (), + .SHIFTOUT4 (), + .TQ (dq_tq[dq]), + .CLK0 (ioclk90), + .CLK1 (), + .CLKDIV (), + .D1 (dqo_p[dq]), + .D2 (dqo_n[dq]), + .D3 (), + .D4 (), + .IOCE (pll_ce_90), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1 (dqIO_w_en_0), + .T2 (dqIO_w_en_0), + .T3 (), + .T4 (), + .TCE (1'b1), + .TRAIN (ioi_drp_train) +); + +end +endgenerate + +//////// +//DQSP +//////// + +wire dqsp_oq ; +wire dqsp_tq ; + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) oserdes2_dqsp_0 +( + .OQ (dqsp_oq), + .SHIFTOUT1(), + .SHIFTOUT2(), + .SHIFTOUT3(), + .SHIFTOUT4(), + .TQ (dqsp_tq), + .CLK0 (ioclk0), + .CLK1(), + .CLKDIV(), + .D1 (1'b0), + .D2 (1'b1), + .D3(), + .D4(), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1(), + .SHIFTIN2(), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1 (dqsIO_w_en_90_n), + .T2 (dqsIO_w_en_90_p), + .T3(), + .T4(), + .TCE (1'b1), + .TRAIN (1'b0) +); + +//////// +//DQSN +//////// + +wire dqsn_oq ; +wire dqsn_tq ; + + + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_SLAVE), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) oserdes2_dqsn_0 +( + .OQ (dqsn_oq), + .SHIFTOUT1(), + .SHIFTOUT2(), + .SHIFTOUT3(), + .SHIFTOUT4(), + .TQ (dqsn_tq), + .CLK0 (ioclk0), + .CLK1(), + .CLKDIV(), + .D1 (1'b1), + .D2 (1'b0), + .D3(), + .D4(), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3(), + .SHIFTIN4(), + .T1 (dqsIO_w_en_90_n), + .T2 (dqsIO_w_en_90_p), + .T3(), + .T4(), + .TCE (1'b1), + .TRAIN (1'b0) +); + +//////// +//UDQSP +//////// + +wire udqsp_oq ; +wire udqsp_tq ; + + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_MASTER), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) oserdes2_udqsp_0 +( + .OQ (udqsp_oq), + .SHIFTOUT1(), + .SHIFTOUT2(), + .SHIFTOUT3(), + .SHIFTOUT4(), + .TQ (udqsp_tq), + .CLK0 (ioclk0), + .CLK1(), + .CLKDIV(), + .D1 (1'b0), + .D2 (1'b1), + .D3(), + .D4(), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1(), + .SHIFTIN2(), + .SHIFTIN3 (), + .SHIFTIN4 (), + .T1 (dqsIO_w_en_90_n), + .T2 (dqsIO_w_en_90_p), + .T3(), + .T4(), + .TCE (1'b1), + .TRAIN (1'b0) +); + +//////// +//UDQSN +//////// + +wire udqsn_oq ; +wire udqsn_tq ; + +OSERDES2 #( + .BYPASS_GCLK_FF ("TRUE"), + .DATA_RATE_OQ (C_OSERDES2_DATA_RATE_OQ), // SDR, DDR | Data Rate setting + .DATA_RATE_OT (C_OSERDES2_DATA_RATE_OT), // SDR, DDR, BUF | Tristate Rate setting. + .OUTPUT_MODE (C_OSERDES2_OUTPUT_MODE_SE), // SINGLE_ENDED, DIFFERENTIAL + .SERDES_MODE (C_OSERDES2_SERDES_MODE_SLAVE), // MASTER, SLAVE + .DATA_WIDTH (2) // {1..8} +) oserdes2_udqsn_0 +( + .OQ (udqsn_oq), + .SHIFTOUT1(), + .SHIFTOUT2(), + .SHIFTOUT3(), + .SHIFTOUT4(), + .TQ (udqsn_tq), + .CLK0 (ioclk0), + .CLK1(), + .CLKDIV(), + .D1 (1'b1), + .D2 (1'b0), + .D3(), + .D4(), + .IOCE (pll_ce_0), + .OCE (1'b1), + .RST (int_sys_rst), + .SHIFTIN1 (), + .SHIFTIN2 (), + .SHIFTIN3(), + .SHIFTIN4(), + .T1 (dqsIO_w_en_90_n), + .T2 (dqsIO_w_en_90_p), + .T3(), + .T4(), + .TCE (1'b1), + .TRAIN (1'b0) +); + +//////////////////////////////////////////////////////// +//OSDDRES2 instantiations end +/////////////////////////////////////////////////////// + +wire aux_sdi_out_udqsp; +wire aux_sdi_out_10; +wire aux_sdi_out_11; +wire aux_sdi_out_12; +wire aux_sdi_out_14; +wire aux_sdi_out_15; + +//////////////////////////////////////////////// +//IODRP2 instantiations +//////////////////////////////////////////////// +generate +if(C_NUM_DQ_PINS == 16 ) begin : dq_15_0_data +//////////////////////////////////////////////// +//IODRP2 instantiations +//////////////////////////////////////////////// + +wire aux_sdi_out_14; +wire aux_sdi_out_15; +//////////////////////////////////////////////// +//DQ14 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ14_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (7), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive +) +iodrp2_dq_14 +( + .AUXSDO (aux_sdi_out_14), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[14]), + .DQSOUTN(), + .DQSOUTP (in_dq[14]), + .SDO(), + .TOUT (t_dq[14]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_15), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[14]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[14]), + .SDI (ioi_drp_sdo), + .T (dq_tq[14]) +); + + +///////////////////////////////////////////////// +//DQ15 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ15_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (7), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_15 +( + .AUXSDO (aux_sdi_out_15), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[15]), + .DQSOUTN(), + .DQSOUTP (in_dq[15]), + .SDO(), + .TOUT (t_dq[15]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (1'b0), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[15]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[15]), + .SDI (ioi_drp_sdo), + .T (dq_tq[15]) +); + + + +wire aux_sdi_out_12; +wire aux_sdi_out_13; +///////////////////////////////////////////////// +//DQ12 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ12_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (6), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_12 +( + .AUXSDO (aux_sdi_out_12), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[12]), + .DQSOUTN(), + .DQSOUTP (in_dq[12]), + .SDO(), + .TOUT (t_dq[12]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_13), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[12]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[12]), + .SDI (ioi_drp_sdo), + .T (dq_tq[12]) +); + + + +///////////////////////////////////////////////// +//DQ13 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ13_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (6), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_13 +( + .AUXSDO (aux_sdi_out_13), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[13]), + .DQSOUTN(), + .DQSOUTP (in_dq[13]), + .SDO(), + .TOUT (t_dq[13]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_14), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[13]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[13]), + .SDI (ioi_drp_sdo), + .T (dq_tq[13]) +); + + +wire aux_sdi_out_udqsp; +wire aux_sdi_out_udqsn; +///////// +//UDQSP +///////// +IODRP2_MCB #( +.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (UDQSP_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (14), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_udqsp_0 +( + .AUXSDO (aux_sdi_out_udqsp), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_udqs), + .DQSOUTN(), + .DQSOUTP (idelay_udqs_ioi_m), + .SDO(), + .TOUT (t_udqs), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_udqsn), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_udqsp), + .IOCLK0 (ioclk0), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (udqsp_oq), + .SDI (ioi_drp_sdo), + .T (udqsp_tq) +); + +///////// +//UDQSN +///////// +IODRP2_MCB #( +.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (UDQSN_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (14), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_udqsn_0 +( + .AUXSDO (aux_sdi_out_udqsn), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_udqsn), + .DQSOUTN(), + .DQSOUTP (idelay_udqs_ioi_s), + .SDO(), + .TOUT (t_udqsn), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_12), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_udqsp), + .IOCLK0 (ioclk0), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (udqsn_oq), + .SDI (ioi_drp_sdo), + .T (udqsn_tq) +); + + +wire aux_sdi_out_10; +wire aux_sdi_out_11; +///////////////////////////////////////////////// +//DQ10 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ10_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (5), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_10 +( + .AUXSDO (aux_sdi_out_10), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[10]), + .DQSOUTN(), + .DQSOUTP (in_dq[10]), + .SDO(), + .TOUT (t_dq[10]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_11), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[10]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[10]), + .SDI (ioi_drp_sdo), + .T (dq_tq[10]) +); + + +///////////////////////////////////////////////// +//DQ11 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ11_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (5), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_11 +( + .AUXSDO (aux_sdi_out_11), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[11]), + .DQSOUTN(), + .DQSOUTP (in_dq[11]), + .SDO(), + .TOUT (t_dq[11]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_udqsp), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[11]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[11]), + .SDI (ioi_drp_sdo), + .T (dq_tq[11]) +); + + + +wire aux_sdi_out_8; +wire aux_sdi_out_9; +///////////////////////////////////////////////// +//DQ8 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ8_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (4), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_8 +( + .AUXSDO (aux_sdi_out_8), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[8]), + .DQSOUTN(), + .DQSOUTP (in_dq[8]), + .SDO(), + .TOUT (t_dq[8]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_9), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[8]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[8]), + .SDI (ioi_drp_sdo), + .T (dq_tq[8]) +); + + +///////////////////////////////////////////////// +//DQ9 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ9_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (4), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_9 +( + .AUXSDO (aux_sdi_out_9), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[9]), + .DQSOUTN(), + .DQSOUTP (in_dq[9]), + .SDO(), + .TOUT (t_dq[9]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_10), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[9]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[9]), + .SDI (ioi_drp_sdo), + .T (dq_tq[9]) +); + + +wire aux_sdi_out_0; +wire aux_sdi_out_1; +///////////////////////////////////////////////// +//DQ0 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ0_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (0), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_0 +( + .AUXSDO (aux_sdi_out_0), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[0]), + .DQSOUTN(), + .DQSOUTP (in_dq[0]), + .SDO(), + .TOUT (t_dq[0]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_1), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[0]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[0]), + .SDI (ioi_drp_sdo), + .T (dq_tq[0]) +); + + +///////////////////////////////////////////////// +//DQ1 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ1_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (0), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_1 +( + .AUXSDO (aux_sdi_out_1), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[1]), + .DQSOUTN(), + .DQSOUTP (in_dq[1]), + .SDO(), + .TOUT (t_dq[1]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_8), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[1]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[1]), + .SDI (ioi_drp_sdo), + .T (dq_tq[1]) +); + + +wire aux_sdi_out_2; +wire aux_sdi_out_3; +///////////////////////////////////////////////// +//DQ2 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ2_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (1), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_2 +( + .AUXSDO (aux_sdi_out_2), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[2]), + .DQSOUTN(), + .DQSOUTP (in_dq[2]), + .SDO(), + .TOUT (t_dq[2]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_3), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[2]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[2]), + .SDI (ioi_drp_sdo), + .T (dq_tq[2]) +); + + +///////////////////////////////////////////////// +//DQ3 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ3_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (1), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_3 +( + .AUXSDO (aux_sdi_out_3), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[3]), + .DQSOUTN(), + .DQSOUTP (in_dq[3]), + .SDO(), + .TOUT (t_dq[3]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_0), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[3]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[3]), + .SDI (ioi_drp_sdo), + .T (dq_tq[3]) +); + + +wire aux_sdi_out_dqsp; +wire aux_sdi_out_dqsn; +///////// +//DQSP +///////// +IODRP2_MCB #( +.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (LDQSP_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (15), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dqsp_0 +( + .AUXSDO (aux_sdi_out_dqsp), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dqs), + .DQSOUTN(), + .DQSOUTP (idelay_dqs_ioi_m), + .SDO(), + .TOUT (t_dqs), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_dqsn), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dqsp), + .IOCLK0 (ioclk0), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dqsp_oq), + .SDI (ioi_drp_sdo), + .T (dqsp_tq) +); + +///////// +//DQSN +///////// +IODRP2_MCB #( +.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (LDQSN_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (15), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dqsn_0 +( + .AUXSDO (aux_sdi_out_dqsn), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dqsn), + .DQSOUTN(), + .DQSOUTP (idelay_dqs_ioi_s), + .SDO(), + .TOUT (t_dqsn), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_2), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dqsp), + .IOCLK0 (ioclk0), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dqsn_oq), + .SDI (ioi_drp_sdo), + .T (dqsn_tq) +); + +wire aux_sdi_out_6; +wire aux_sdi_out_7; +///////////////////////////////////////////////// +//DQ6 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ6_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (3), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_6 +( + .AUXSDO (aux_sdi_out_6), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[6]), + .DQSOUTN(), + .DQSOUTP (in_dq[6]), + .SDO(), + .TOUT (t_dq[6]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_7), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[6]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[6]), + .SDI (ioi_drp_sdo), + .T (dq_tq[6]) +); + +///////////////////////////////////////////////// +//DQ7 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ7_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (3), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_7 +( + .AUXSDO (aux_sdi_out_7), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[7]), + .DQSOUTN(), + .DQSOUTP (in_dq[7]), + .SDO(), + .TOUT (t_dq[7]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_dqsp), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[7]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[7]), + .SDI (ioi_drp_sdo), + .T (dq_tq[7]) +); + + + +wire aux_sdi_out_4; +wire aux_sdi_out_5; +///////////////////////////////////////////////// +//DQ4 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ4_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (2), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_4 +( + .AUXSDO (aux_sdi_out_4), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[4]), + .DQSOUTN(), + .DQSOUTP (in_dq[4]), + .SDO(), + .TOUT (t_dq[4]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_5), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[4]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[4]), + .SDI (ioi_drp_sdo), + .T (dq_tq[4]) +); + +///////////////////////////////////////////////// +//DQ5 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ5_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (2), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_5 +( + .AUXSDO (aux_sdi_out_5), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[5]), + .DQSOUTN(), + .DQSOUTP (in_dq[5]), + .SDO(), + .TOUT (t_dq[5]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_6), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[5]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[5]), + .SDI (ioi_drp_sdo), + .T (dq_tq[5]) +); + + +//wire aux_sdi_out_udm; +wire aux_sdi_out_ldm; +///////////////////////////////////////////////// +//UDM +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (0), // 0 to 255 inclusive +.MCB_ADDRESS (8), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_udm +( + .AUXSDO (ioi_drp_sdi), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_udm), + .DQSOUTN(), + .DQSOUTP(), + .SDO(), + .TOUT (t_udm), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_ldm), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN(), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (udm_oq), + .SDI (ioi_drp_sdo), + .T (udm_t) +); + + +///////////////////////////////////////////////// +//LDM +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (0), // 0 to 255 inclusive +.MCB_ADDRESS (8), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_ldm +( + .AUXSDO (aux_sdi_out_ldm), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_ldm), + .DQSOUTN(), + .DQSOUTP(), + .SDO(), + .TOUT (t_ldm), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_4), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN(), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (ldm_oq), + .SDI (ioi_drp_sdo), + .T (ldm_t) +); +end +endgenerate + +generate +if(C_NUM_DQ_PINS == 8 ) begin : dq_7_0_data +wire aux_sdi_out_0; +wire aux_sdi_out_1; +///////////////////////////////////////////////// +//DQ0 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ0_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (0), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_0 +( + .AUXSDO (aux_sdi_out_0), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[0]), + .DQSOUTN(), + .DQSOUTP (in_dq[0]), + .SDO(), + .TOUT (t_dq[0]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_1), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[0]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[0]), + .SDI (ioi_drp_sdo), + .T (dq_tq[0]) +); + + +///////////////////////////////////////////////// +//DQ1 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ1_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (0), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_1 +( + .AUXSDO (aux_sdi_out_1), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[1]), + .DQSOUTN(), + .DQSOUTP (in_dq[1]), + .SDO(), + .TOUT (t_dq[1]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (1'b0), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[1]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[1]), + .SDI (ioi_drp_sdo), + .T (dq_tq[1]) +); + + +wire aux_sdi_out_2; +wire aux_sdi_out_3; +///////////////////////////////////////////////// +//DQ2 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ2_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (1), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_2 +( + .AUXSDO (aux_sdi_out_2), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[2]), + .DQSOUTN(), + .DQSOUTP (in_dq[2]), + .SDO(), + .TOUT (t_dq[2]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_3), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[2]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[2]), + .SDI (ioi_drp_sdo), + .T (dq_tq[2]) +); + + +///////////////////////////////////////////////// +//DQ3 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ3_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (1), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_3 +( + .AUXSDO (aux_sdi_out_3), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[3]), + .DQSOUTN(), + .DQSOUTP (in_dq[3]), + .SDO(), + .TOUT (t_dq[3]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_0), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[3]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[3]), + .SDI (ioi_drp_sdo), + .T (dq_tq[3]) +); + + +wire aux_sdi_out_dqsp; +wire aux_sdi_out_dqsn; +///////// +//DQSP +///////// +IODRP2_MCB #( +.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (LDQSP_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (15), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dqsp_0 +( + .AUXSDO (aux_sdi_out_dqsp), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dqs), + .DQSOUTN(), + .DQSOUTP (idelay_dqs_ioi_m), + .SDO(), + .TOUT (t_dqs), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_dqsn), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dqsp), + .IOCLK0 (ioclk0), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dqsp_oq), + .SDI (ioi_drp_sdo), + .T (dqsp_tq) +); + +///////// +//DQSN +///////// +IODRP2_MCB #( +.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (LDQSN_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (15), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dqsn_0 +( + .AUXSDO (aux_sdi_out_dqsn), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dqsn), + .DQSOUTN(), + .DQSOUTP (idelay_dqs_ioi_s), + .SDO(), + .TOUT (t_dqsn), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_2), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dqsp), + .IOCLK0 (ioclk0), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dqsn_oq), + .SDI (ioi_drp_sdo), + .T (dqsn_tq) +); + +wire aux_sdi_out_6; +wire aux_sdi_out_7; +///////////////////////////////////////////////// +//DQ6 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ6_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (3), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_6 +( + .AUXSDO (aux_sdi_out_6), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[6]), + .DQSOUTN(), + .DQSOUTP (in_dq[6]), + .SDO(), + .TOUT (t_dq[6]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_7), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[6]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[6]), + .SDI (ioi_drp_sdo), + .T (dq_tq[6]) +); + +///////////////////////////////////////////////// +//DQ7 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ7_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (3), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_7 +( + .AUXSDO (aux_sdi_out_7), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[7]), + .DQSOUTN(), + .DQSOUTP (in_dq[7]), + .SDO(), + .TOUT (t_dq[7]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_dqsp), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[7]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[7]), + .SDI (ioi_drp_sdo), + .T (dq_tq[7]) +); + + + +wire aux_sdi_out_4; +wire aux_sdi_out_5; +///////////////////////////////////////////////// +//DQ4 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ4_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (2), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_4 +( + .AUXSDO (aux_sdi_out_4), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[4]), + .DQSOUTN(), + .DQSOUTP (in_dq[4]), + .SDO(), + .TOUT (t_dq[4]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_5), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[4]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[4]), + .SDI (ioi_drp_sdo), + .T (dq_tq[4]) +); + +///////////////////////////////////////////////// +//DQ5 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ5_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (2), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_5 +( + .AUXSDO (aux_sdi_out_5), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[5]), + .DQSOUTN(), + .DQSOUTP (in_dq[5]), + .SDO(), + .TOUT (t_dq[5]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_6), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[5]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[5]), + .SDI (ioi_drp_sdo), + .T (dq_tq[5]) +); + +//NEED TO GENERATE UDM so that user won't instantiate in this location +//wire aux_sdi_out_udm; +wire aux_sdi_out_ldm; +///////////////////////////////////////////////// +//UDM +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (0), // 0 to 255 inclusive +.MCB_ADDRESS (8), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_udm +( + .AUXSDO (ioi_drp_sdi), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_udm), + .DQSOUTN(), + .DQSOUTP(), + .SDO(), + .TOUT (t_udm), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_ldm), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN(), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (udm_oq), + .SDI (ioi_drp_sdo), + .T (udm_t) +); + + +///////////////////////////////////////////////// +//LDM +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (0), // 0 to 255 inclusive +.MCB_ADDRESS (8), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_ldm +( + .AUXSDO (aux_sdi_out_ldm), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_ldm), + .DQSOUTN(), + .DQSOUTP(), + .SDO(), + .TOUT (t_ldm), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_4), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN(), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (ldm_oq), + .SDI (ioi_drp_sdo), + .T (ldm_t) +); +end +endgenerate + +generate +if(C_NUM_DQ_PINS == 4 ) begin : dq_3_0_data + +wire aux_sdi_out_0; +wire aux_sdi_out_1; +///////////////////////////////////////////////// +//DQ0 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ0_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (0), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_0 +( + .AUXSDO (aux_sdi_out_0), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[0]), + .DQSOUTN(), + .DQSOUTP (in_dq[0]), + .SDO(), + .TOUT (t_dq[0]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_1), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[0]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[0]), + .SDI (ioi_drp_sdo), + .T (dq_tq[0]) +); + + +///////////////////////////////////////////////// +//DQ1 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ1_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (0), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_1 +( + .AUXSDO (aux_sdi_out_1), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[1]), + .DQSOUTN(), + .DQSOUTP (in_dq[1]), + .SDO(), + .TOUT (t_dq[1]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (1'b0), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[1]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[1]), + .SDI (ioi_drp_sdo), + .T (dq_tq[1]) +); + + +wire aux_sdi_out_2; +wire aux_sdi_out_3; +///////////////////////////////////////////////// +//DQ2 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ2_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (1), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_2 +( + .AUXSDO (aux_sdi_out_2), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[2]), + .DQSOUTN(), + .DQSOUTP (in_dq[2]), + .SDO(), + .TOUT (t_dq[2]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_3), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[2]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[2]), + .SDI (ioi_drp_sdo), + .T (dq_tq[2]) +); + + +///////////////////////////////////////////////// +//DQ3 +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (DQ3_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (1), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_3 +( + .AUXSDO (aux_sdi_out_3), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dq[3]), + .DQSOUTN(), + .DQSOUTP (in_dq[3]), + .SDO(), + .TOUT (t_dq[3]), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_0), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dq[3]), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dq_oq[3]), + .SDI (ioi_drp_sdo), + .T (dq_tq[3]) +); + + +wire aux_sdi_out_dqsp; +wire aux_sdi_out_dqsn; +///////// +//DQSP +///////// +IODRP2_MCB #( +.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (LDQSP_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (15), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dqsp_0 +( + .AUXSDO (aux_sdi_out_dqsp), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dqs), + .DQSOUTN(), + .DQSOUTP (idelay_dqs_ioi_m), + .SDO(), + .TOUT (t_dqs), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_dqsn), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dqsp), + .IOCLK0 (ioclk0), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dqsp_oq), + .SDI (ioi_drp_sdo), + .T (dqsp_tq) +); + +///////// +//DQSN +///////// +IODRP2_MCB #( +.DATA_RATE (C_DQS_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (LDQSN_TAP_DELAY_VAL), // 0 to 255 inclusive +.MCB_ADDRESS (15), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQS_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dqsn_0 +( + .AUXSDO (aux_sdi_out_dqsn), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_dqsn), + .DQSOUTN(), + .DQSOUTP (idelay_dqs_ioi_s), + .SDO(), + .TOUT (t_dqsn), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_2), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN (in_pre_dqsp), + .IOCLK0 (ioclk0), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (dqsn_oq), + .SDI (ioi_drp_sdo), + .T (dqsn_tq) +); + +//NEED TO GENERATE UDM so that user won't instantiate in this location +//wire aux_sdi_out_udm; +wire aux_sdi_out_ldm; +///////////////////////////////////////////////// +//UDM +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (0), // 0 to 255 inclusive +.MCB_ADDRESS (8), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_MASTER), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_udm +( + .AUXSDO (ioi_drp_sdi), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_udm), + .DQSOUTN(), + .DQSOUTP(), + .SDO(), + .TOUT (t_udm), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_ldm), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN(), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (udm_oq), + .SDI (ioi_drp_sdo), + .T (udm_t) +); + + +///////////////////////////////////////////////// +//LDM +//////////////////////////////////////////////// +IODRP2_MCB #( +.DATA_RATE (C_DQ_IODRP2_DATA_RATE), // "SDR", "DDR" +.IDELAY_VALUE (0), // 0 to 255 inclusive +.MCB_ADDRESS (8), // 0 to 15 +.ODELAY_VALUE (0), // 0 to 255 inclusive +.SERDES_MODE (C_DQ_IODRP2_SERDES_MODE_SLAVE), // "NONE", "MASTER", "SLAVE" +.SIM_TAPDELAY_VALUE (10) // 10 to 90 inclusive + +) +iodrp2_dq_ldm +( + .AUXSDO (aux_sdi_out_ldm), + .DATAOUT(), + .DATAOUT2(), + .DOUT (ioi_ldm), + .DQSOUTN(), + .DQSOUTP(), + .SDO(), + .TOUT (t_ldm), + .ADD (ioi_drp_add), + .AUXADDR (ioi_drp_addr), + .AUXSDOIN (aux_sdi_out_4), + .BKST (ioi_drp_broadcast), + .CLK (ioi_drp_clk), + .CS (ioi_drp_cs), + .IDATAIN(), + .IOCLK0 (ioclk90), + .IOCLK1(), + .MEMUPDATE (ioi_drp_update), + .ODATAIN (ldm_oq), + .SDI (ioi_drp_sdo), + .T (ldm_t) +); + +end +endgenerate + + //////////////////////////////////////////////// + //IOBs instantiations + // this part need more inputs from design team + // for now just use as listed in fpga.v + //////////////////////////////////////////////// + + +//// Address + +genvar addr_i; + generate + for(addr_i = 0; addr_i < C_MEM_ADDR_WIDTH; addr_i = addr_i + 1) begin : gen_addr_obuft + OBUFT iob_addr_inst + (.I ( ioi_addr[addr_i]), + .T ( t_addr[addr_i]), + .O ( mcbx_dram_addr[addr_i]) + ); + end + endgenerate + +genvar ba_i; + generate + for(ba_i = 0; ba_i < C_MEM_BANKADDR_WIDTH; ba_i = ba_i + 1) begin : gen_ba_obuft + OBUFT iob_ba_inst + (.I ( ioi_ba[ba_i]), + .T ( t_ba[ba_i]), + .O ( mcbx_dram_ba[ba_i]) + ); + end + endgenerate + + + +// DRAM Control +OBUFT iob_ras (.O(mcbx_dram_ras_n),.I(ioi_ras),.T(t_ras)); +OBUFT iob_cas (.O(mcbx_dram_cas_n),.I(ioi_cas),.T(t_cas)); +OBUFT iob_we (.O(mcbx_dram_we_n ),.I(ioi_we ),.T(t_we )); +OBUFT iob_cke (.O(mcbx_dram_cke),.I(ioi_cke),.T(t_cke)); + +generate +if (C_MEM_TYPE == "DDR3") begin : gen_ddr3_rst +OBUFT iob_rst (.O(mcbx_dram_ddr3_rst),.I(ioi_rst),.T(t_rst)); +end +endgenerate +generate +if((C_MEM_TYPE == "DDR3" && (C_MEM_DDR3_RTT != "OFF" || C_MEM_DDR3_DYN_WRT_ODT != "OFF")) + ||(C_MEM_TYPE == "DDR2" && C_MEM_DDR2_RTT != "OFF") ) begin : gen_dram_odt +OBUFT iob_odt (.O(mcbx_dram_odt),.I(ioi_odt),.T(t_odt)); +end +endgenerate + +// Clock +OBUFTDS iob_clk (.I(ioi_ck), .T(t_ck), .O(mcbx_dram_clk), .OB(mcbx_dram_clk_n)); + +//DQ +genvar dq_i; +generate + for(dq_i = 0; dq_i < C_NUM_DQ_PINS; dq_i = dq_i + 1) begin : gen_dq_iobuft + IOBUF gen_iob_dq_inst (.IO(mcbx_dram_dq[dq_i]),.I(ioi_dq[dq_i]),.T(t_dq[dq_i]),.O(in_pre_dq[dq_i])); + end +endgenerate + + +// DQS +generate +if(C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) begin: gen_dqs_iobuf +IOBUF iob_dqs (.IO(mcbx_dram_dqs), .I(ioi_dqs),.T(t_dqs),.O(in_pre_dqsp)); +end else begin: gen_dqs_iobufds +IOBUFDS iob_dqs (.IO(mcbx_dram_dqs),.IOB(mcbx_dram_dqs_n), .I(ioi_dqs),.T(t_dqs),.O(in_pre_dqsp)); + +end +endgenerate + +generate +if((C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) && C_NUM_DQ_PINS == 16) begin: gen_udqs_iobuf +IOBUF iob_udqs (.IO(mcbx_dram_udqs), .I(ioi_udqs),.T(t_udqs),.O(in_pre_udqsp)); +end else if(C_NUM_DQ_PINS == 16) begin: gen_udqs_iobufds +IOBUFDS iob_udqs (.IO(mcbx_dram_udqs),.IOB(mcbx_dram_udqs_n), .I(ioi_udqs),.T(t_udqs),.O(in_pre_udqsp)); + +end +endgenerate + +// DQS PULLDWON +generate +if(C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) begin: gen_dqs_pullupdn +PULLDOWN dqs_pulldown (.O(mcbx_dram_dqs)); +end else begin: gen_dqs_pullupdn_ds +PULLDOWN dqs_pulldown (.O(mcbx_dram_dqs)); +PULLUP dqs_n_pullup (.O(mcbx_dram_dqs_n)); + +end +endgenerate + +// DQSN PULLUP +generate +if((C_MEM_TYPE == "DDR" || C_MEM_TYPE =="MDDR" || (C_MEM_TYPE == "DDR2" && (C_MEM_DDR2_DIFF_DQS_EN == "NO"))) && C_NUM_DQ_PINS == 16) begin: gen_udqs_pullupdn +PULLDOWN udqs_pulldown (.O(mcbx_dram_udqs)); +end else if(C_NUM_DQ_PINS == 16) begin: gen_udqs_pullupdn_ds +PULLDOWN udqs_pulldown (.O(mcbx_dram_udqs)); +PULLUP udqs_n_pullup (.O(mcbx_dram_udqs_n)); + +end +endgenerate + + + + +//DM +// datamask generation +generate +if( C_NUM_DQ_PINS == 16) begin : gen_udm +OBUFT iob_udm (.I(ioi_udm), .T(t_udm), .O(mcbx_dram_udm)); +end +endgenerate + +OBUFT iob_ldm (.I(ioi_ldm), .T(t_ldm), .O(mcbx_dram_ldm)); + +endmodule +
xilinx/atlys/rtl/verilog/xilinx_ddr2/mcb_raw_wrapper.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xilinx/atlys/rtl/verilog/orpsoc_top/orpsoc_top.v =================================================================== --- xilinx/atlys/rtl/verilog/orpsoc_top/orpsoc_top.v (nonexistent) +++ xilinx/atlys/rtl/verilog/orpsoc_top/orpsoc_top.v (revision 627) @@ -0,0 +1,1575 @@ +////////////////////////////////////////////////////////////////////// +/// //// +/// ORPSoC top for Atlys board //// +/// //// +/// Instantiates modules, depending on ORPSoC defines file //// +/// //// +/// Julius Baxter, julius@opencores.org //// +/// Contributor(s): //// +/// Stefan Kristiansson, stefan.kristiansson@saunalahti.fi //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "orpsoc-defines.v" +`include "synthesis-defines.v" +module orpsoc_top + ( +`ifdef JTAG_DEBUG + tdo_pad_o, tms_pad_i, tck_pad_i, tdi_pad_i, +`endif +`ifdef XILINX_DDR2 + ddr2_a, ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n, + ddr2_rzq, ddr2_zio, ddr2_odt, ddr2_cke, ddr2_dm, ddr2_udm, + ddr2_dq, ddr2_dqs, ddr2_dqs_n, ddr2_udqs, ddr2_udqs_n, + ddr2_ck, ddr2_ck_n, +`endif +`ifdef XILINX_SSRAM + sram_clk, sram_clk_fb, sram_flash_addr, sram_flash_data, + sram_cen, sram_flash_oe_n, sram_flash_we_n, sram_bw, + sram_adv_ld_n, sram_mode, +`endif +`ifdef UART0 + uart0_srx_pad_i, uart0_stx_pad_o, +`ifdef UART0_EXPHEADER + uart0_srx_expheader_pad_i, uart0_stx_expheader_pad_o, +`endif +`endif +`ifdef SPI0 + spi0_mosi_o, spi0_ss_o, spi0_sck_o, spi0_miso_i, +`endif +`ifdef I2C0 + i2c0_sda_io, i2c0_scl_io, +`endif +`ifdef I2C1 + i2c1_sda_io, i2c1_scl_io, +`endif +`ifdef GPIO0 + gpio0_io, +`endif + +`ifdef ETH0 + eth0_tx_clk, eth0_tx_data, eth0_tx_en, eth0_tx_er, + eth0_rx_clk, eth0_rx_data, eth0_dv, eth0_rx_er, + eth0_col, eth0_crs, + eth0_mdc_pad_o, eth0_md_pad_io, + `ifdef ETH0_PHY_RST + eth0_rst_n_o, + `endif +`endif + + sys_clk_in, + + rst_n_pad_i + + ); + +`include "orpsoc-params.v" + + input sys_clk_in; + + input rst_n_pad_i; + +`ifdef JTAG_DEBUG + output tdo_pad_o; + input tms_pad_i; + input tck_pad_i; + input tdi_pad_i; +`endif +`ifdef XILINX_DDR2 + output [12:0] ddr2_a; + output [2:0] ddr2_ba; + output ddr2_ras_n; + output ddr2_cas_n; + output ddr2_we_n; + output ddr2_rzq; + output ddr2_zio; + output ddr2_odt; + output ddr2_cke; + output ddr2_dm; + output ddr2_udm; + + inout [15:0] ddr2_dq; + inout ddr2_dqs; + inout ddr2_dqs_n; + inout ddr2_udqs; + inout ddr2_udqs_n; + output ddr2_ck; + output ddr2_ck_n; +`endif +`ifdef UART0 + input uart0_srx_pad_i; + output uart0_stx_pad_o; + // Duplicates of the UART signals, this time to the USB debug cable +`ifdef UART0_EXPHEADER + input uart0_srx_expheader_pad_i; + output uart0_stx_expheader_pad_o; +`endif +`endif +`ifdef SPI0 + output spi0_mosi_o; + output [spi0_ss_width-1:0] spi0_ss_o; + output spi0_sck_o; + input spi0_miso_i; + +`endif +`ifdef I2C0 + inout i2c0_sda_io, i2c0_scl_io; +`endif +`ifdef I2C1 + inout i2c1_sda_io, i2c1_scl_io; +`endif +`ifdef GPIO0 + inout [gpio0_io_width-1:0] gpio0_io; +`endif +`ifdef ETH0 + input eth0_tx_clk; + output [3:0] eth0_tx_data; + output eth0_tx_en; + output eth0_tx_er; + input eth0_rx_clk; + input [3:0] eth0_rx_data; + input eth0_dv; + input eth0_rx_er; + input eth0_col; + input eth0_crs; + output eth0_mdc_pad_o; + inout eth0_md_pad_io; + `ifdef ETH0_PHY_RST + output eth0_rst_n_o; + `endif +`endif // `ifdef ETH0 + + //////////////////////////////////////////////////////////////////////// + // + // Clock and reset generation module + // + //////////////////////////////////////////////////////////////////////// + + // + // Wires + // + wire wb_clk, wb_rst; + wire ddr2_if_clk, ddr2_if_rst; + wire clk100; + wire dbg_tck; + + clkgen clkgen0 + ( + .sys_clk_in (sys_clk_in), + + .wb_clk_o (wb_clk), + .wb_rst_o (wb_rst), + +`ifdef JTAG_DEBUG + .tck_pad_i (tck_pad_i), + .dbg_tck_o (dbg_tck), +`endif +`ifdef XILINX_DDR2 + .ddr2_if_clk_o (ddr2_if_clk), + .ddr2_if_rst_o (ddr2_if_rst), + .clk100_o (clk100), +`endif + + // Asynchronous active low reset + .rst_n_pad_i (rst_n_pad_i) + ); + + + //////////////////////////////////////////////////////////////////////// + // + // Arbiter + // + //////////////////////////////////////////////////////////////////////// + + // Wire naming convention: + // First: wishbone master or slave (wbm/wbs) + // Second: Which bus it's on instruction or data (i/d) + // Third: Between which module and the arbiter the wires are + // Fourth: Signal name + // Fifth: Direction relative to module (not bus/arbiter!) + // ie. wbm_d_or12_adr_o is address OUT from the or1200 + + // OR1200 instruction bus wires + wire [wb_aw-1:0] wbm_i_or12_adr_o; + wire [wb_dw-1:0] wbm_i_or12_dat_o; + wire [3:0] wbm_i_or12_sel_o; + wire wbm_i_or12_we_o; + wire wbm_i_or12_cyc_o; + wire wbm_i_or12_stb_o; + wire [2:0] wbm_i_or12_cti_o; + wire [1:0] wbm_i_or12_bte_o; + + wire [wb_dw-1:0] wbm_i_or12_dat_i; + wire wbm_i_or12_ack_i; + wire wbm_i_or12_err_i; + wire wbm_i_or12_rty_i; + + // OR1200 data bus wires + wire [wb_aw-1:0] wbm_d_or12_adr_o; + wire [wb_dw-1:0] wbm_d_or12_dat_o; + wire [3:0] wbm_d_or12_sel_o; + wire wbm_d_or12_we_o; + wire wbm_d_or12_cyc_o; + wire wbm_d_or12_stb_o; + wire [2:0] wbm_d_or12_cti_o; + wire [1:0] wbm_d_or12_bte_o; + + wire [wb_dw-1:0] wbm_d_or12_dat_i; + wire wbm_d_or12_ack_i; + wire wbm_d_or12_err_i; + wire wbm_d_or12_rty_i; + + // Debug interface bus wires + wire [wb_aw-1:0] wbm_d_dbg_adr_o; + wire [wb_dw-1:0] wbm_d_dbg_dat_o; + wire [3:0] wbm_d_dbg_sel_o; + wire wbm_d_dbg_we_o; + wire wbm_d_dbg_cyc_o; + wire wbm_d_dbg_stb_o; + wire [2:0] wbm_d_dbg_cti_o; + wire [1:0] wbm_d_dbg_bte_o; + + wire [wb_dw-1:0] wbm_d_dbg_dat_i; + wire wbm_d_dbg_ack_i; + wire wbm_d_dbg_err_i; + wire wbm_d_dbg_rty_i; + + // Byte bus bridge master signals + wire [wb_aw-1:0] wbm_b_d_adr_o; + wire [wb_dw-1:0] wbm_b_d_dat_o; + wire [3:0] wbm_b_d_sel_o; + wire wbm_b_d_we_o; + wire wbm_b_d_cyc_o; + wire wbm_b_d_stb_o; + wire [2:0] wbm_b_d_cti_o; + wire [1:0] wbm_b_d_bte_o; + + wire [wb_dw-1:0] wbm_b_d_dat_i; + wire wbm_b_d_ack_i; + wire wbm_b_d_err_i; + wire wbm_b_d_rty_i; + + // Instruction bus slave wires // + + // rom0 instruction bus wires + wire [31:0] wbs_i_rom0_adr_i; + wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_i; + wire [3:0] wbs_i_rom0_sel_i; + wire wbs_i_rom0_we_i; + wire wbs_i_rom0_cyc_i; + wire wbs_i_rom0_stb_i; + wire [2:0] wbs_i_rom0_cti_i; + wire [1:0] wbs_i_rom0_bte_i; + wire [wbs_i_rom0_data_width-1:0] wbs_i_rom0_dat_o; + wire wbs_i_rom0_ack_o; + wire wbs_i_rom0_err_o; + wire wbs_i_rom0_rty_o; + + // mc0 instruction bus wires + wire [31:0] wbs_i_mc0_adr_i; + wire [wbs_i_mc0_data_width-1:0] wbs_i_mc0_dat_i; + wire [3:0] wbs_i_mc0_sel_i; + wire wbs_i_mc0_we_i; + wire wbs_i_mc0_cyc_i; + wire wbs_i_mc0_stb_i; + wire [2:0] wbs_i_mc0_cti_i; + wire [1:0] wbs_i_mc0_bte_i; + wire [wbs_i_mc0_data_width-1:0] wbs_i_mc0_dat_o; + wire wbs_i_mc0_ack_o; + wire wbs_i_mc0_err_o; + wire wbs_i_mc0_rty_o; + + // Data bus slave wires // + + // mc0 data bus wires + wire [31:0] wbs_d_mc0_adr_i; + wire [wbs_d_mc0_data_width-1:0] wbs_d_mc0_dat_i; + wire [3:0] wbs_d_mc0_sel_i; + wire wbs_d_mc0_we_i; + wire wbs_d_mc0_cyc_i; + wire wbs_d_mc0_stb_i; + wire [2:0] wbs_d_mc0_cti_i; + wire [1:0] wbs_d_mc0_bte_i; + wire [wbs_d_mc0_data_width-1:0] wbs_d_mc0_dat_o; + wire wbs_d_mc0_ack_o; + wire wbs_d_mc0_err_o; + wire wbs_d_mc0_rty_o; + + // i2c0 wires + wire [31:0] wbs_d_i2c0_adr_i; + wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_i; + wire [3:0] wbs_d_i2c0_sel_i; + wire wbs_d_i2c0_we_i; + wire wbs_d_i2c0_cyc_i; + wire wbs_d_i2c0_stb_i; + wire [2:0] wbs_d_i2c0_cti_i; + wire [1:0] wbs_d_i2c0_bte_i; + wire [wbs_d_i2c0_data_width-1:0] wbs_d_i2c0_dat_o; + wire wbs_d_i2c0_ack_o; + wire wbs_d_i2c0_err_o; + wire wbs_d_i2c0_rty_o; + + // i2c1 wires + wire [31:0] wbs_d_i2c1_adr_i; + wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_i; + wire [3:0] wbs_d_i2c1_sel_i; + wire wbs_d_i2c1_we_i; + wire wbs_d_i2c1_cyc_i; + wire wbs_d_i2c1_stb_i; + wire [2:0] wbs_d_i2c1_cti_i; + wire [1:0] wbs_d_i2c1_bte_i; + wire [wbs_d_i2c1_data_width-1:0] wbs_d_i2c1_dat_o; + wire wbs_d_i2c1_ack_o; + wire wbs_d_i2c1_err_o; + wire wbs_d_i2c1_rty_o; + + // spi0 wires + wire [31:0] wbs_d_spi0_adr_i; + wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_i; + wire [3:0] wbs_d_spi0_sel_i; + wire wbs_d_spi0_we_i; + wire wbs_d_spi0_cyc_i; + wire wbs_d_spi0_stb_i; + wire [2:0] wbs_d_spi0_cti_i; + wire [1:0] wbs_d_spi0_bte_i; + wire [wbs_d_spi0_data_width-1:0] wbs_d_spi0_dat_o; + wire wbs_d_spi0_ack_o; + wire wbs_d_spi0_err_o; + wire wbs_d_spi0_rty_o; + + // uart0 wires + wire [31:0] wbs_d_uart0_adr_i; + wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_i; + wire [3:0] wbs_d_uart0_sel_i; + wire wbs_d_uart0_we_i; + wire wbs_d_uart0_cyc_i; + wire wbs_d_uart0_stb_i; + wire [2:0] wbs_d_uart0_cti_i; + wire [1:0] wbs_d_uart0_bte_i; + wire [wbs_d_uart0_data_width-1:0] wbs_d_uart0_dat_o; + wire wbs_d_uart0_ack_o; + wire wbs_d_uart0_err_o; + wire wbs_d_uart0_rty_o; + + // gpio0 wires + wire [31:0] wbs_d_gpio0_adr_i; + wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_i; + wire [3:0] wbs_d_gpio0_sel_i; + wire wbs_d_gpio0_we_i; + wire wbs_d_gpio0_cyc_i; + wire wbs_d_gpio0_stb_i; + wire [2:0] wbs_d_gpio0_cti_i; + wire [1:0] wbs_d_gpio0_bte_i; + wire [wbs_d_gpio0_data_width-1:0] wbs_d_gpio0_dat_o; + wire wbs_d_gpio0_ack_o; + wire wbs_d_gpio0_err_o; + wire wbs_d_gpio0_rty_o; + + // eth0 slave wires + wire [31:0] wbs_d_eth0_adr_i; + wire [wbs_d_eth0_data_width-1:0] wbs_d_eth0_dat_i; + wire [3:0] wbs_d_eth0_sel_i; + wire wbs_d_eth0_we_i; + wire wbs_d_eth0_cyc_i; + wire wbs_d_eth0_stb_i; + wire [2:0] wbs_d_eth0_cti_i; + wire [1:0] wbs_d_eth0_bte_i; + wire [wbs_d_eth0_data_width-1:0] wbs_d_eth0_dat_o; + wire wbs_d_eth0_ack_o; + wire wbs_d_eth0_err_o; + wire wbs_d_eth0_rty_o; + + // eth0 master wires + wire [wbm_eth0_addr_width-1:0] wbm_eth0_adr_o; + wire [wbm_eth0_data_width-1:0] wbm_eth0_dat_o; + wire [3:0] wbm_eth0_sel_o; + wire wbm_eth0_we_o; + wire wbm_eth0_cyc_o; + wire wbm_eth0_stb_o; + wire [2:0] wbm_eth0_cti_o; + wire [1:0] wbm_eth0_bte_o; + wire [wbm_eth0_data_width-1:0] wbm_eth0_dat_i; + wire wbm_eth0_ack_i; + wire wbm_eth0_err_i; + wire wbm_eth0_rty_i; + + + + // + // Wishbone instruction bus arbiter + // + + arbiter_ibus arbiter_ibus0 + ( + // Instruction Bus Master + // Inputs to arbiter from master + .wbm_adr_o (wbm_i_or12_adr_o), + .wbm_dat_o (wbm_i_or12_dat_o), + .wbm_sel_o (wbm_i_or12_sel_o), + .wbm_we_o (wbm_i_or12_we_o), + .wbm_cyc_o (wbm_i_or12_cyc_o), + .wbm_stb_o (wbm_i_or12_stb_o), + .wbm_cti_o (wbm_i_or12_cti_o), + .wbm_bte_o (wbm_i_or12_bte_o), + // Outputs to master from arbiter + .wbm_dat_i (wbm_i_or12_dat_i), + .wbm_ack_i (wbm_i_or12_ack_i), + .wbm_err_i (wbm_i_or12_err_i), + .wbm_rty_i (wbm_i_or12_rty_i), + + // Slave 0 + // Inputs to slave from arbiter + .wbs0_adr_i (wbs_i_rom0_adr_i), + .wbs0_dat_i (wbs_i_rom0_dat_i), + .wbs0_sel_i (wbs_i_rom0_sel_i), + .wbs0_we_i (wbs_i_rom0_we_i), + .wbs0_cyc_i (wbs_i_rom0_cyc_i), + .wbs0_stb_i (wbs_i_rom0_stb_i), + .wbs0_cti_i (wbs_i_rom0_cti_i), + .wbs0_bte_i (wbs_i_rom0_bte_i), + // Outputs from slave to arbiter + .wbs0_dat_o (wbs_i_rom0_dat_o), + .wbs0_ack_o (wbs_i_rom0_ack_o), + .wbs0_err_o (wbs_i_rom0_err_o), + .wbs0_rty_o (wbs_i_rom0_rty_o), + + // Slave 1 + // Inputs to slave from arbiter + .wbs1_adr_i (wbs_i_mc0_adr_i), + .wbs1_dat_i (wbs_i_mc0_dat_i), + .wbs1_sel_i (wbs_i_mc0_sel_i), + .wbs1_we_i (wbs_i_mc0_we_i), + .wbs1_cyc_i (wbs_i_mc0_cyc_i), + .wbs1_stb_i (wbs_i_mc0_stb_i), + .wbs1_cti_i (wbs_i_mc0_cti_i), + .wbs1_bte_i (wbs_i_mc0_bte_i), + // Outputs from slave to arbiter + .wbs1_dat_o (wbs_i_mc0_dat_o), + .wbs1_ack_o (wbs_i_mc0_ack_o), + .wbs1_err_o (wbs_i_mc0_err_o), + .wbs1_rty_o (wbs_i_mc0_rty_o), + + // Clock, reset inputs + .wb_clk (wb_clk), + .wb_rst (wb_rst)); + + defparam arbiter_ibus0.wb_addr_match_width = ibus_arb_addr_match_width; + + defparam arbiter_ibus0.slave0_adr = ibus_arb_slave0_adr; // FLASH ROM + defparam arbiter_ibus0.slave1_adr = ibus_arb_slave1_adr; // Main memory + + // + // Wishbone data bus arbiter + // + + arbiter_dbus arbiter_dbus0 + ( + // Master 0 + // Inputs to arbiter from master + .wbm0_adr_o (wbm_d_or12_adr_o), + .wbm0_dat_o (wbm_d_or12_dat_o), + .wbm0_sel_o (wbm_d_or12_sel_o), + .wbm0_we_o (wbm_d_or12_we_o), + .wbm0_cyc_o (wbm_d_or12_cyc_o), + .wbm0_stb_o (wbm_d_or12_stb_o), + .wbm0_cti_o (wbm_d_or12_cti_o), + .wbm0_bte_o (wbm_d_or12_bte_o), + // Outputs to master from arbiter + .wbm0_dat_i (wbm_d_or12_dat_i), + .wbm0_ack_i (wbm_d_or12_ack_i), + .wbm0_err_i (wbm_d_or12_err_i), + .wbm0_rty_i (wbm_d_or12_rty_i), + + // Master 0 + // Inputs to arbiter from master + .wbm1_adr_o (wbm_d_dbg_adr_o), + .wbm1_dat_o (wbm_d_dbg_dat_o), + .wbm1_we_o (wbm_d_dbg_we_o), + .wbm1_cyc_o (wbm_d_dbg_cyc_o), + .wbm1_sel_o (wbm_d_dbg_sel_o), + .wbm1_stb_o (wbm_d_dbg_stb_o), + .wbm1_cti_o (wbm_d_dbg_cti_o), + .wbm1_bte_o (wbm_d_dbg_bte_o), + // Outputs to master from arbiter + .wbm1_dat_i (wbm_d_dbg_dat_i), + .wbm1_ack_i (wbm_d_dbg_ack_i), + .wbm1_err_i (wbm_d_dbg_err_i), + .wbm1_rty_i (wbm_d_dbg_rty_i), + + // Slaves + + .wbs0_adr_i (wbs_d_mc0_adr_i), + .wbs0_dat_i (wbs_d_mc0_dat_i), + .wbs0_sel_i (wbs_d_mc0_sel_i), + .wbs0_we_i (wbs_d_mc0_we_i), + .wbs0_cyc_i (wbs_d_mc0_cyc_i), + .wbs0_stb_i (wbs_d_mc0_stb_i), + .wbs0_cti_i (wbs_d_mc0_cti_i), + .wbs0_bte_i (wbs_d_mc0_bte_i), + .wbs0_dat_o (wbs_d_mc0_dat_o), + .wbs0_ack_o (wbs_d_mc0_ack_o), + .wbs0_err_o (wbs_d_mc0_err_o), + .wbs0_rty_o (wbs_d_mc0_rty_o), + + .wbs1_adr_i (wbs_d_eth0_adr_i), + .wbs1_dat_i (wbs_d_eth0_dat_i), + .wbs1_sel_i (wbs_d_eth0_sel_i), + .wbs1_we_i (wbs_d_eth0_we_i), + .wbs1_cyc_i (wbs_d_eth0_cyc_i), + .wbs1_stb_i (wbs_d_eth0_stb_i), + .wbs1_cti_i (wbs_d_eth0_cti_i), + .wbs1_bte_i (wbs_d_eth0_bte_i), + .wbs1_dat_o (wbs_d_eth0_dat_o), + .wbs1_ack_o (wbs_d_eth0_ack_o), + .wbs1_err_o (wbs_d_eth0_err_o), + .wbs1_rty_o (wbs_d_eth0_rty_o), + + .wbs2_adr_i (wbm_b_d_adr_o), + .wbs2_dat_i (wbm_b_d_dat_o), + .wbs2_sel_i (wbm_b_d_sel_o), + .wbs2_we_i (wbm_b_d_we_o), + .wbs2_cyc_i (wbm_b_d_cyc_o), + .wbs2_stb_i (wbm_b_d_stb_o), + .wbs2_cti_i (wbm_b_d_cti_o), + .wbs2_bte_i (wbm_b_d_bte_o), + .wbs2_dat_o (wbm_b_d_dat_i), + .wbs2_ack_o (wbm_b_d_ack_i), + .wbs2_err_o (wbm_b_d_err_i), + .wbs2_rty_o (wbm_b_d_rty_i), + + // Clock, reset inputs + .wb_clk (wb_clk), + .wb_rst (wb_rst)); + + // These settings are from top level params file + defparam arbiter_dbus0.wb_addr_match_width = dbus_arb_wb_addr_match_width; + defparam arbiter_dbus0.wb_num_slaves = dbus_arb_wb_num_slaves; + defparam arbiter_dbus0.slave0_adr = dbus_arb_slave0_adr; + defparam arbiter_dbus0.slave1_adr = dbus_arb_slave1_adr; + + // + // Wishbone byte-wide bus arbiter + // + + arbiter_bytebus arbiter_bytebus0 + ( + + // Master 0 + // Inputs to arbiter from master + .wbm0_adr_o (wbm_b_d_adr_o), + .wbm0_dat_o (wbm_b_d_dat_o), + .wbm0_sel_o (wbm_b_d_sel_o), + .wbm0_we_o (wbm_b_d_we_o), + .wbm0_cyc_o (wbm_b_d_cyc_o), + .wbm0_stb_o (wbm_b_d_stb_o), + .wbm0_cti_o (wbm_b_d_cti_o), + .wbm0_bte_o (wbm_b_d_bte_o), + // Outputs to master from arbiter + .wbm0_dat_i (wbm_b_d_dat_i), + .wbm0_ack_i (wbm_b_d_ack_i), + .wbm0_err_i (wbm_b_d_err_i), + .wbm0_rty_i (wbm_b_d_rty_i), + + // Byte bus slaves + + .wbs0_adr_i (wbs_d_uart0_adr_i), + .wbs0_dat_i (wbs_d_uart0_dat_i), + .wbs0_we_i (wbs_d_uart0_we_i), + .wbs0_cyc_i (wbs_d_uart0_cyc_i), + .wbs0_stb_i (wbs_d_uart0_stb_i), + .wbs0_cti_i (wbs_d_uart0_cti_i), + .wbs0_bte_i (wbs_d_uart0_bte_i), + .wbs0_dat_o (wbs_d_uart0_dat_o), + .wbs0_ack_o (wbs_d_uart0_ack_o), + .wbs0_err_o (wbs_d_uart0_err_o), + .wbs0_rty_o (wbs_d_uart0_rty_o), + + .wbs1_adr_i (wbs_d_gpio0_adr_i), + .wbs1_dat_i (wbs_d_gpio0_dat_i), + .wbs1_we_i (wbs_d_gpio0_we_i), + .wbs1_cyc_i (wbs_d_gpio0_cyc_i), + .wbs1_stb_i (wbs_d_gpio0_stb_i), + .wbs1_cti_i (wbs_d_gpio0_cti_i), + .wbs1_bte_i (wbs_d_gpio0_bte_i), + .wbs1_dat_o (wbs_d_gpio0_dat_o), + .wbs1_ack_o (wbs_d_gpio0_ack_o), + .wbs1_err_o (wbs_d_gpio0_err_o), + .wbs1_rty_o (wbs_d_gpio0_rty_o), + + .wbs2_adr_i (wbs_d_i2c0_adr_i), + .wbs2_dat_i (wbs_d_i2c0_dat_i), + .wbs2_we_i (wbs_d_i2c0_we_i), + .wbs2_cyc_i (wbs_d_i2c0_cyc_i), + .wbs2_stb_i (wbs_d_i2c0_stb_i), + .wbs2_cti_i (wbs_d_i2c0_cti_i), + .wbs2_bte_i (wbs_d_i2c0_bte_i), + .wbs2_dat_o (wbs_d_i2c0_dat_o), + .wbs2_ack_o (wbs_d_i2c0_ack_o), + .wbs2_err_o (wbs_d_i2c0_err_o), + .wbs2_rty_o (wbs_d_i2c0_rty_o), + + .wbs3_adr_i (wbs_d_i2c1_adr_i), + .wbs3_dat_i (wbs_d_i2c1_dat_i), + .wbs3_we_i (wbs_d_i2c1_we_i), + .wbs3_cyc_i (wbs_d_i2c1_cyc_i), + .wbs3_stb_i (wbs_d_i2c1_stb_i), + .wbs3_cti_i (wbs_d_i2c1_cti_i), + .wbs3_bte_i (wbs_d_i2c1_bte_i), + .wbs3_dat_o (wbs_d_i2c1_dat_o), + .wbs3_ack_o (wbs_d_i2c1_ack_o), + .wbs3_err_o (wbs_d_i2c1_err_o), + .wbs3_rty_o (wbs_d_i2c1_rty_o), + + .wbs4_adr_i (wbs_d_spi0_adr_i), + .wbs4_dat_i (wbs_d_spi0_dat_i), + .wbs4_we_i (wbs_d_spi0_we_i), + .wbs4_cyc_i (wbs_d_spi0_cyc_i), + .wbs4_stb_i (wbs_d_spi0_stb_i), + .wbs4_cti_i (wbs_d_spi0_cti_i), + .wbs4_bte_i (wbs_d_spi0_bte_i), + .wbs4_dat_o (wbs_d_spi0_dat_o), + .wbs4_ack_o (wbs_d_spi0_ack_o), + .wbs4_err_o (wbs_d_spi0_err_o), + .wbs4_rty_o (wbs_d_spi0_rty_o), + + // Clock, reset inputs + .wb_clk (wb_clk), + .wb_rst (wb_rst)); + + defparam arbiter_bytebus0.wb_addr_match_width = bbus_arb_wb_addr_match_width; + defparam arbiter_bytebus0.wb_num_slaves = bbus_arb_wb_num_slaves; + + defparam arbiter_bytebus0.slave0_adr = bbus_arb_slave0_adr; + defparam arbiter_bytebus0.slave1_adr = bbus_arb_slave1_adr; + defparam arbiter_bytebus0.slave2_adr = bbus_arb_slave2_adr; + defparam arbiter_bytebus0.slave3_adr = bbus_arb_slave3_adr; + defparam arbiter_bytebus0.slave4_adr = bbus_arb_slave4_adr; + + +`ifdef JTAG_DEBUG + //////////////////////////////////////////////////////////////////////// + // + // JTAG TAP + // + //////////////////////////////////////////////////////////////////////// + + // + // Wires + // + wire dbg_if_select; + wire dbg_if_tdo; + wire jtag_tap_tdo; + wire jtag_tap_shift_dr, jtag_tap_pause_dr, + jtag_tap_upate_dr, jtag_tap_capture_dr; + // + // Instantiation + // + + jtag_tap jtag_tap0 + ( + // Ports to pads + .tdo_pad_o (tdo_pad_o), + .tms_pad_i (tms_pad_i), + .tck_pad_i (dbg_tck), + .trst_pad_i (async_rst), + .tdi_pad_i (tdi_pad_i), + + .tdo_padoe_o (tdo_padoe_o), + + .tdo_o (jtag_tap_tdo), + + .shift_dr_o (jtag_tap_shift_dr), + .pause_dr_o (jtag_tap_pause_dr), + .update_dr_o (jtag_tap_update_dr), + .capture_dr_o (jtag_tap_capture_dr), + + .extest_select_o (), + .sample_preload_select_o (), + .mbist_select_o (), + .debug_select_o (dbg_if_select), + + + .bs_chain_tdi_i (1'b0), + .mbist_tdi_i (1'b0), + .debug_tdi_i (dbg_if_tdo) + + ); + + //////////////////////////////////////////////////////////////////////// +`endif // `ifdef JTAG_DEBUG + + //////////////////////////////////////////////////////////////////////// + // + // OpenRISC processor + // + //////////////////////////////////////////////////////////////////////// + + // + // Wires + // + + wire [30:0] or1200_pic_ints; + + wire [31:0] or1200_dbg_dat_i; + wire [31:0] or1200_dbg_adr_i; + wire or1200_dbg_we_i; + wire or1200_dbg_stb_i; + wire or1200_dbg_ack_o; + wire [31:0] or1200_dbg_dat_o; + + wire or1200_dbg_stall_i; + wire or1200_dbg_ewt_i; + wire [3:0] or1200_dbg_lss_o; + wire [1:0] or1200_dbg_is_o; + wire [10:0] or1200_dbg_wp_o; + wire or1200_dbg_bp_o; + wire or1200_dbg_rst; + + wire or1200_clk, or1200_rst; + wire sig_tick; + + // + // Assigns + // + assign or1200_clk = wb_clk; + assign or1200_rst = wb_rst | or1200_dbg_rst; + + // + // Instantiation + // + or1200_top or1200_top0 + ( + // Instruction bus, clocks, reset + .iwb_clk_i (wb_clk), + .iwb_rst_i (wb_rst), + .iwb_ack_i (wbm_i_or12_ack_i), + .iwb_err_i (wbm_i_or12_err_i), + .iwb_rty_i (wbm_i_or12_rty_i), + .iwb_dat_i (wbm_i_or12_dat_i), + + .iwb_cyc_o (wbm_i_or12_cyc_o), + .iwb_adr_o (wbm_i_or12_adr_o), + .iwb_stb_o (wbm_i_or12_stb_o), + .iwb_we_o (wbm_i_or12_we_o), + .iwb_sel_o (wbm_i_or12_sel_o), + .iwb_dat_o (wbm_i_or12_dat_o), + .iwb_cti_o (wbm_i_or12_cti_o), + .iwb_bte_o (wbm_i_or12_bte_o), + + // Data bus, clocks, reset + .dwb_clk_i (wb_clk), + .dwb_rst_i (wb_rst), + .dwb_ack_i (wbm_d_or12_ack_i), + .dwb_err_i (wbm_d_or12_err_i), + .dwb_rty_i (wbm_d_or12_rty_i), + .dwb_dat_i (wbm_d_or12_dat_i), + + .dwb_cyc_o (wbm_d_or12_cyc_o), + .dwb_adr_o (wbm_d_or12_adr_o), + .dwb_stb_o (wbm_d_or12_stb_o), + .dwb_we_o (wbm_d_or12_we_o), + .dwb_sel_o (wbm_d_or12_sel_o), + .dwb_dat_o (wbm_d_or12_dat_o), + .dwb_cti_o (wbm_d_or12_cti_o), + .dwb_bte_o (wbm_d_or12_bte_o), + + // Debug interface ports + .dbg_stall_i (or1200_dbg_stall_i), + //.dbg_ewt_i (or1200_dbg_ewt_i), + .dbg_ewt_i (1'b0), + .dbg_lss_o (or1200_dbg_lss_o), + .dbg_is_o (or1200_dbg_is_o), + .dbg_wp_o (or1200_dbg_wp_o), + .dbg_bp_o (or1200_dbg_bp_o), + + .dbg_adr_i (or1200_dbg_adr_i), + .dbg_we_i (or1200_dbg_we_i ), + .dbg_stb_i (or1200_dbg_stb_i), + .dbg_dat_i (or1200_dbg_dat_i), + .dbg_dat_o (or1200_dbg_dat_o), + .dbg_ack_o (or1200_dbg_ack_o), + + .pm_clksd_o (), + .pm_dc_gate_o (), + .pm_ic_gate_o (), + .pm_dmmu_gate_o (), + .pm_immu_gate_o (), + .pm_tt_gate_o (), + .pm_cpu_gate_o (), + .pm_wakeup_o (), + .pm_lvolt_o (), + + // Core clocks, resets + .clk_i (or1200_clk), + .rst_i (or1200_rst), + + .clmode_i (2'b00), + // Interrupts + .pic_ints_i (or1200_pic_ints), + .sig_tick(sig_tick), + /* + .mbist_so_o (), + .mbist_si_i (0), + .mbist_ctrl_i (0), + */ + + .pm_cpustall_i (1'b0) + + ); + + //////////////////////////////////////////////////////////////////////// + + +`ifdef JTAG_DEBUG + //////////////////////////////////////////////////////////////////////// + // + // OR1200 Debug Interface + // + //////////////////////////////////////////////////////////////////////// + + dbg_if dbg_if0 + ( + // OR1200 interface + .cpu0_clk_i (or1200_clk), + .cpu0_rst_o (or1200_dbg_rst), + .cpu0_addr_o (or1200_dbg_adr_i), + .cpu0_data_o (or1200_dbg_dat_i), + .cpu0_stb_o (or1200_dbg_stb_i), + .cpu0_we_o (or1200_dbg_we_i), + .cpu0_data_i (or1200_dbg_dat_o), + .cpu0_ack_i (or1200_dbg_ack_o), + + + .cpu0_stall_o (or1200_dbg_stall_i), + .cpu0_bp_i (or1200_dbg_bp_o), + + // TAP interface + .tck_i (dbg_tck), + .tdi_i (jtag_tap_tdo), + .tdo_o (dbg_if_tdo), + .rst_i (wb_rst), + .shift_dr_i (jtag_tap_shift_dr), + .pause_dr_i (jtag_tap_pause_dr), + .update_dr_i (jtag_tap_update_dr), + .debug_select_i (dbg_if_select), + + // Wishbone debug master + .wb_clk_i (wb_clk), + .wb_dat_i (wbm_d_dbg_dat_i), + .wb_ack_i (wbm_d_dbg_ack_i), + .wb_err_i (wbm_d_dbg_err_i), + .wb_adr_o (wbm_d_dbg_adr_o), + .wb_dat_o (wbm_d_dbg_dat_o), + .wb_cyc_o (wbm_d_dbg_cyc_o), + .wb_stb_o (wbm_d_dbg_stb_o), + .wb_sel_o (wbm_d_dbg_sel_o), + .wb_we_o (wbm_d_dbg_we_o ), + .wb_cti_o (wbm_d_dbg_cti_o), + .wb_cab_o (/* UNUSED */), + .wb_bte_o (wbm_d_dbg_bte_o) + ); + + //////////////////////////////////////////////////////////////////////// +`else // !`ifdef JTAG_DEBUG + + assign wbm_d_dbg_adr_o = 0; + assign wbm_d_dbg_dat_o = 0; + assign wbm_d_dbg_cyc_o = 0; + assign wbm_d_dbg_stb_o = 0; + assign wbm_d_dbg_sel_o = 0; + assign wbm_d_dbg_we_o = 0; + assign wbm_d_dbg_cti_o = 0; + assign wbm_d_dbg_bte_o = 0; + + assign or1200_dbg_adr_i = 0; + assign or1200_dbg_dat_i = 0; + assign or1200_dbg_stb_i = 0; + assign or1200_dbg_we_i = 0; + assign or1200_dbg_stall_i = 0; + + //////////////////////////////////////////////////////////////////////// +`endif // !`ifdef JTAG_DEBUG + +`ifdef XILINX_DDR2 + //////////////////////////////////////////////////////////////////////// + // + // Xilinx MIG DDR2 controller, Wishbone interface + // + //////////////////////////////////////////////////////////////////////// + xilinx_ddr2 xilinx_ddr2_0 + ( + .wbm0_adr_i (wbm_eth0_adr_o), + .wbm0_bte_i (wbm_eth0_bte_o), + .wbm0_cti_i (wbm_eth0_cti_o), + .wbm0_cyc_i (wbm_eth0_cyc_o), + .wbm0_dat_i (wbm_eth0_dat_o), + .wbm0_sel_i (wbm_eth0_sel_o), + .wbm0_stb_i (wbm_eth0_stb_o), + .wbm0_we_i (wbm_eth0_we_o), + .wbm0_ack_o (wbm_eth0_ack_i), + .wbm0_err_o (wbm_eth0_err_i), + .wbm0_rty_o (wbm_eth0_rty_i), + .wbm0_dat_o (wbm_eth0_dat_i), + + .wbm1_adr_i (wbs_d_mc0_adr_i), + .wbm1_bte_i (wbs_d_mc0_bte_i), + .wbm1_cti_i (wbs_d_mc0_cti_i), + .wbm1_cyc_i (wbs_d_mc0_cyc_i), + .wbm1_dat_i (wbs_d_mc0_dat_i), + .wbm1_sel_i (wbs_d_mc0_sel_i), + .wbm1_stb_i (wbs_d_mc0_stb_i), + .wbm1_we_i (wbs_d_mc0_we_i), + .wbm1_ack_o (wbs_d_mc0_ack_o), + .wbm1_err_o (wbs_d_mc0_err_o), + .wbm1_rty_o (wbs_d_mc0_rty_o), + .wbm1_dat_o (wbs_d_mc0_dat_o), + + .wbm2_adr_i (wbs_i_mc0_adr_i), + .wbm2_bte_i (wbs_i_mc0_bte_i), + .wbm2_cti_i (wbs_i_mc0_cti_i), + .wbm2_cyc_i (wbs_i_mc0_cyc_i), + .wbm2_dat_i (wbs_i_mc0_dat_i), + .wbm2_sel_i (wbs_i_mc0_sel_i), + .wbm2_stb_i (wbs_i_mc0_stb_i), + .wbm2_we_i (wbs_i_mc0_we_i), + .wbm2_ack_o (wbs_i_mc0_ack_o), + .wbm2_err_o (wbs_i_mc0_err_o), + .wbm2_rty_o (wbs_i_mc0_rty_o), + .wbm2_dat_o (wbs_i_mc0_dat_o), + + .wb_clk (wb_clk), + .wb_rst (wb_rst), + + .ddr2_a (ddr2_a[12:0]), + .ddr2_ba (ddr2_ba), + .ddr2_ras_n (ddr2_ras_n), + .ddr2_cas_n (ddr2_cas_n), + .ddr2_we_n (ddr2_we_n), + .ddr2_rzq (ddr2_rzq), + .ddr2_zio (ddr2_zio), + .ddr2_odt (ddr2_odt), + .ddr2_cke (ddr2_cke), + .ddr2_dm (ddr2_dm), + .ddr2_udm (ddr2_udm), + .ddr2_ck (ddr2_ck), + .ddr2_ck_n (ddr2_ck_n), + .ddr2_dq (ddr2_dq), + .ddr2_dqs (ddr2_dqs), + .ddr2_dqs_n (ddr2_dqs_n), + .ddr2_udqs (ddr2_udqs), + .ddr2_udqs_n (ddr2_udqs_n), + .ddr2_if_clk (ddr2_if_clk), + .ddr2_if_rst (ddr2_if_rst) + ); + +`endif + + + //////////////////////////////////////////////////////////////////////// + // + // ROM + // + //////////////////////////////////////////////////////////////////////// + + rom rom0 + ( + .wb_dat_o (wbs_i_rom0_dat_o), + .wb_ack_o (wbs_i_rom0_ack_o), + .wb_adr_i (wbs_i_rom0_adr_i[(wbs_i_rom0_addr_width+2)-1:2]), + .wb_stb_i (wbs_i_rom0_stb_i), + .wb_cyc_i (wbs_i_rom0_cyc_i), + .wb_cti_i (wbs_i_rom0_cti_i), + .wb_bte_i (wbs_i_rom0_bte_i), + .wb_clk (wb_clk), + .wb_rst (wb_rst)); + + defparam rom0.addr_width = wbs_i_rom0_addr_width; + + assign wbs_i_rom0_err_o = 0; + assign wbs_i_rom0_rty_o = 0; + + //////////////////////////////////////////////////////////////////////// + +`ifdef RAM_WB + //////////////////////////////////////////////////////////////////////// + // + // Generic RAM + // + //////////////////////////////////////////////////////////////////////// + + ram_wb ram_wb0 + ( + // Wishbone slave interface 0 + .wbm0_dat_i (wbs_i_mc0_dat_i), + .wbm0_adr_i (wbs_i_mc0_adr_i), + .wbm0_sel_i (wbs_i_mc0_sel_i), + .wbm0_cti_i (wbs_i_mc0_cti_i), + .wbm0_bte_i (wbs_i_mc0_bte_i), + .wbm0_we_i (wbs_i_mc0_we_i ), + .wbm0_cyc_i (wbs_i_mc0_cyc_i), + .wbm0_stb_i (wbs_i_mc0_stb_i), + .wbm0_dat_o (wbs_i_mc0_dat_o), + .wbm0_ack_o (wbs_i_mc0_ack_o), + .wbm0_err_o (wbs_i_mc0_err_o), + .wbm0_rty_o (wbs_i_mc0_rty_o), + // Wishbone slave interface 1 + .wbm1_dat_i (wbs_d_mc0_dat_i), + .wbm1_adr_i (wbs_d_mc0_adr_i), + .wbm1_sel_i (wbs_d_mc0_sel_i), + .wbm1_cti_i (wbs_d_mc0_cti_i), + .wbm1_bte_i (wbs_d_mc0_bte_i), + .wbm1_we_i (wbs_d_mc0_we_i ), + .wbm1_cyc_i (wbs_d_mc0_cyc_i), + .wbm1_stb_i (wbs_d_mc0_stb_i), + .wbm1_dat_o (wbs_d_mc0_dat_o), + .wbm1_ack_o (wbs_d_mc0_ack_o), + .wbm1_err_o (wbs_d_mc0_err_o), + .wbm1_rty_o (wbs_d_mc0_rty_o), + // Wishbone slave interface 2 + .wbm2_dat_i (wbm_eth0_dat_o), + .wbm2_adr_i (wbm_eth0_adr_o), + .wbm2_sel_i (wbm_eth0_sel_o), + .wbm2_cti_i (wbm_eth0_cti_o), + .wbm2_bte_i (wbm_eth0_bte_o), + .wbm2_we_i (wbm_eth0_we_o ), + .wbm2_cyc_i (wbm_eth0_cyc_o), + .wbm2_stb_i (wbm_eth0_stb_o), + .wbm2_dat_o (wbm_eth0_dat_i), + .wbm2_ack_o (wbm_eth0_ack_i), + .wbm2_err_o (wbm_eth0_err_i), + .wbm2_rty_o (wbm_eth0_rty_i), + // Clock, reset + .wb_clk_i (wb_clk), + .wb_rst_i (wb_rst)); + + defparam ram_wb0.aw = wb_aw; + defparam ram_wb0.dw = wb_dw; + + defparam ram_wb0.mem_size_bytes = (8192*1024); // 8MB + defparam ram_wb0.mem_adr_width = 23; // log2(8192*1024) + //////////////////////////////////////////////////////////////////////// +`endif // `ifdef RAM_WB + + +`ifdef ETH0 + + // + // Wires + // + wire eth0_irq; + wire [3:0] eth0_mtxd; + wire eth0_mtxen; + wire eth0_mtxerr; + wire eth0_mtx_clk; + wire eth0_mrx_clk; + wire [3:0] eth0_mrxd; + wire eth0_mrxdv; + wire eth0_mrxerr; + wire eth0_mcoll; + wire eth0_mcrs; + wire eth0_speed; + wire eth0_duplex; + wire eth0_link; + // Management interface wires + wire eth0_md_i; + wire eth0_md_o; + wire eth0_md_oe; + + + // + // assigns + + // Hook up MII wires + assign eth0_mtx_clk = eth0_tx_clk; + assign eth0_tx_data = eth0_mtxd[3:0]; + assign eth0_tx_en = eth0_mtxen; + assign eth0_tx_er = eth0_mtxerr; + assign eth0_mrxd[3:0] = eth0_rx_data; + assign eth0_mrxdv = eth0_dv; + assign eth0_mrxerr = eth0_rx_er; + assign eth0_mrx_clk = eth0_rx_clk; + assign eth0_mcoll = eth0_col; + assign eth0_mcrs = eth0_crs; + +`ifdef XILINX + // Xilinx primitive for MDIO tristate + IOBUF iobuf_phy_smi_data + ( + // Outputs + .O (eth0_md_i), + // Inouts + .IO (eth0_md_pad_io), + // Inputs + .I (eth0_md_o), + .T (!eth0_md_oe)); +`else // !`ifdef XILINX + + // Generic technology tristate control for management interface + assign eth0_md_pad_io = eth0_md_oe ? eth0_md_o : 1'bz; + assign eth0_md_i = eth0_md_pad_io; + +`endif // !`ifdef XILINX + +`ifdef ETH0_PHY_RST + assign eth0_rst_n_o = !wb_rst; +`endif + + ethmac ethmac0 + ( + // Wishbone Slave interface + .wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .wb_dat_i (wbs_d_eth0_dat_i[31:0]), + .wb_adr_i (wbs_d_eth0_adr_i[wbs_d_eth0_addr_width-1:2]), + .wb_sel_i (wbs_d_eth0_sel_i[3:0]), + .wb_we_i (wbs_d_eth0_we_i), + .wb_cyc_i (wbs_d_eth0_cyc_i), + .wb_stb_i (wbs_d_eth0_stb_i), + .wb_dat_o (wbs_d_eth0_dat_o[31:0]), + .wb_err_o (wbs_d_eth0_err_o), + .wb_ack_o (wbs_d_eth0_ack_o), + // Wishbone Master Interface + .m_wb_adr_o (wbm_eth0_adr_o[31:0]), + .m_wb_sel_o (wbm_eth0_sel_o[3:0]), + .m_wb_we_o (wbm_eth0_we_o), + .m_wb_dat_o (wbm_eth0_dat_o[31:0]), + .m_wb_cyc_o (wbm_eth0_cyc_o), + .m_wb_stb_o (wbm_eth0_stb_o), + .m_wb_cti_o (wbm_eth0_cti_o[2:0]), + .m_wb_bte_o (wbm_eth0_bte_o[1:0]), + .m_wb_dat_i (wbm_eth0_dat_i[31:0]), + .m_wb_ack_i (wbm_eth0_ack_i), + .m_wb_err_i (wbm_eth0_err_i), + + // Ethernet MII interface + // Transmit + .mtxd_pad_o (eth0_mtxd[3:0]), + .mtxen_pad_o (eth0_mtxen), + .mtxerr_pad_o (eth0_mtxerr), + .mtx_clk_pad_i (eth0_mtx_clk), + // Receive + .mrx_clk_pad_i (eth0_mrx_clk), + .mrxd_pad_i (eth0_mrxd[3:0]), + .mrxdv_pad_i (eth0_mrxdv), + .mrxerr_pad_i (eth0_mrxerr), + .mcoll_pad_i (eth0_mcoll), + .mcrs_pad_i (eth0_mcrs), + // Management interface + .md_pad_i (eth0_md_i), + .mdc_pad_o (eth0_mdc_pad_o), + .md_pad_o (eth0_md_o), + .md_padoe_o (eth0_md_oe), + + // Processor interrupt + .int_o (eth0_irq) + + /* + .mbist_so_o (), + .mbist_si_i (), + .mbist_ctrl_i () + */ + + ); + + assign wbs_d_eth0_rty_o = 0; + +`else + assign wbs_d_eth0_dat_o = 0; + assign wbs_d_eth0_err_o = 0; + assign wbs_d_eth0_ack_o = 0; + assign wbs_d_eth0_rty_o = 0; + assign wbm_eth0_adr_o = 0; + assign wbm_eth0_sel_o = 0; + assign wbm_eth0_we_o = 0; + assign wbm_eth0_dat_o = 0; + assign wbm_eth0_cyc_o = 0; + assign wbm_eth0_stb_o = 0; + assign wbm_eth0_cti_o = 0; + assign wbm_eth0_bte_o = 0; +`endif + +`ifdef UART0 + //////////////////////////////////////////////////////////////////////// + // + // UART0 + // + //////////////////////////////////////////////////////////////////////// + + // + // Wires + // + wire uart0_srx; + wire uart0_stx; + + wire uart0_irq; + + // + // Assigns + // + assign wbs_d_uart0_err_o = 0; + assign wbs_d_uart0_rty_o = 0; + + // Two UART lines coming to single one (ensure they go high when unconnected) +`ifdef UART0_EXPHEADER + assign uart0_srx = uart0_srx_pad_i & uart0_srx_expheader_pad_i; +`else + assign uart0_srx = uart0_srx_pad_i; +`endif + assign uart0_stx_pad_o = uart0_stx; + assign uart0_stx_expheader_pad_o = uart0_stx; + + + uart16550 uart16550_0 + ( + // Wishbone slave interface + .wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .wb_adr_i (wbs_d_uart0_adr_i[uart0_addr_width-1:0]), + .wb_dat_i (wbs_d_uart0_dat_i), + .wb_we_i (wbs_d_uart0_we_i), + .wb_stb_i (wbs_d_uart0_stb_i), + .wb_cyc_i (wbs_d_uart0_cyc_i), + //.wb_sel_i (), + .wb_dat_o (wbs_d_uart0_dat_o), + .wb_ack_o (wbs_d_uart0_ack_o), + + .int_o (uart0_irq), + .stx_pad_o (uart0_stx), + .rts_pad_o (), + .dtr_pad_o (), +`ifdef UART_HAS_BAUDRATE_OUTPUT + .baud_o (), +`endif + // Inputs + .srx_pad_i (uart0_srx), + .cts_pad_i (1'b0), + .dsr_pad_i (1'b0), + .ri_pad_i (1'b0), + .dcd_pad_i (1'b0)); + + //////////////////////////////////////////////////////////////////////// +`else // !`ifdef UART0 + + // + // Assigns + // + assign wbs_d_uart0_err_o = 0; + assign wbs_d_uart0_rty_o = 0; + assign wbs_d_uart0_ack_o = 0; + assign wbs_d_uart0_dat_o = 0; + + //////////////////////////////////////////////////////////////////////// +`endif // !`ifdef UART0 + +`ifdef SPI0 + //////////////////////////////////////////////////////////////////////// + // + // SPI0 controller + // + //////////////////////////////////////////////////////////////////////// + + // + // Wires + // + wire spi0_irq; + + // + // Assigns + // + assign wbs_d_spi0_err_o = 0; + assign wbs_d_spi0_rty_o = 0; + //assign spi0_hold_n_o = 1; + //assign spi0_w_n_o = 1; + + + simple_spi spi0 + ( + // Wishbone slave interface + .clk_i (wb_clk), + .rst_i (wb_rst), + .cyc_i (wbs_d_spi0_cyc_i), + .stb_i (wbs_d_spi0_stb_i), + .adr_i (wbs_d_spi0_adr_i[spi0_wb_adr_width-1:0]), + .we_i (wbs_d_spi0_we_i), + .dat_i (wbs_d_spi0_dat_i), + .dat_o (wbs_d_spi0_dat_o), + .ack_o (wbs_d_spi0_ack_o), + // SPI IRQ + .inta_o (spi0_irq), + // External SPI interface + .sck_o (spi0_sck_o), + .ss_o (spi0_ss_o), + .mosi_o (spi0_mosi_o), + .miso_i (spi0_miso_i) + ); + + defparam spi0.slave_select_width = spi0_ss_width; + + //////////////////////////////////////////////////////////////////////// +`else // !`ifdef SPI0 + + // + // Assigns + // + assign wbs_d_spi0_dat_o = 0; + assign wbs_d_spi0_ack_o = 0; + assign wbs_d_spi0_err_o = 0; + assign wbs_d_spi0_rty_o = 0; + + //////////////////////////////////////////////////////////////////////// +`endif // !`ifdef SPI0 + + +`ifdef I2C0 + //////////////////////////////////////////////////////////////////////// + // + // i2c controller 0 + // + //////////////////////////////////////////////////////////////////////// + + // + // Wires + // + wire i2c0_irq; + wire scl0_pad_o; + wire scl0_padoen_o; + wire sda0_pad_o; + wire sda0_padoen_o; + + i2c_master_slave + # + ( + .DEFAULT_SLAVE_ADDR(HV0_SADR) + ) + i2c_master_slave0 + ( + .wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .arst_i (wb_rst), + .wb_adr_i (wbs_d_i2c0_adr_i[i2c_0_wb_adr_width-1:0]), + .wb_dat_i (wbs_d_i2c0_dat_i), + .wb_we_i (wbs_d_i2c0_we_i ), + .wb_cyc_i (wbs_d_i2c0_cyc_i), + .wb_stb_i (wbs_d_i2c0_stb_i), + .wb_dat_o (wbs_d_i2c0_dat_o), + .wb_ack_o (wbs_d_i2c0_ack_o), + .scl_pad_i (i2c0_scl_io ), + .scl_pad_o (scl0_pad_o ), + .scl_padoen_o (scl0_padoen_o ), + .sda_pad_i (i2c0_sda_io ), + .sda_pad_o (sda0_pad_o ), + .sda_padoen_o (sda0_padoen_o ), + + // Interrupt + .wb_inta_o (i2c0_irq) + + ); + + assign wbs_d_i2c0_err_o = 0; + assign wbs_d_i2c0_rty_o = 0; + + // i2c phy lines + assign i2c0_scl_io = scl0_padoen_o ? 1'bz : scl0_pad_o; + assign i2c0_sda_io = sda0_padoen_o ? 1'bz : sda0_pad_o; + + + //////////////////////////////////////////////////////////////////////// +`else // !`ifdef I2C0 + + assign wbs_d_i2c0_dat_o = 0; + assign wbs_d_i2c0_ack_o = 0; + assign wbs_d_i2c0_err_o = 0; + assign wbs_d_i2c0_rty_o = 0; + + //////////////////////////////////////////////////////////////////////// +`endif // !`ifdef I2C0 + +`ifdef I2C1 + //////////////////////////////////////////////////////////////////////// + // + // i2c controller 1 + // + //////////////////////////////////////////////////////////////////////// + + // + // Wires + // + wire i2c1_irq; + wire scl1_pad_o; + wire scl1_padoen_o; + wire sda1_pad_o; + wire sda1_padoen_o; + + i2c_master_slave + # + ( + .DEFAULT_SLAVE_ADDR(HV1_SADR) + ) + i2c_master_slave1 + ( + .wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .arst_i (wb_rst), + .wb_adr_i (wbs_d_i2c1_adr_i[i2c_1_wb_adr_width-1:0]), + .wb_dat_i (wbs_d_i2c1_dat_i), + .wb_we_i (wbs_d_i2c1_we_i ), + .wb_cyc_i (wbs_d_i2c1_cyc_i), + .wb_stb_i (wbs_d_i2c1_stb_i), + .wb_dat_o (wbs_d_i2c1_dat_o), + .wb_ack_o (wbs_d_i2c1_ack_o), + .scl_pad_i (i2c1_scl_io ), + .scl_pad_o (scl1_pad_o ), + .scl_padoen_o (scl1_padoen_o ), + .sda_pad_i (i2c1_sda_io ), + .sda_pad_o (sda1_pad_o ), + .sda_padoen_o (sda1_padoen_o ), + + // Interrupt + .wb_inta_o (i2c1_irq) + + ); + + assign wbs_d_i2c1_err_o = 0; + assign wbs_d_i2c1_rty_o = 0; + + // i2c phy lines + assign i2c1_scl_io = scl1_padoen_o ? 1'bz : scl1_pad_o; + assign i2c1_sda_io = sda1_padoen_o ? 1'bz : sda1_pad_o; + + //////////////////////////////////////////////////////////////////////// +`else // !`ifdef I2C1 + + assign wbs_d_i2c1_dat_o = 0; + assign wbs_d_i2c1_ack_o = 0; + assign wbs_d_i2c1_err_o = 0; + assign wbs_d_i2c1_rty_o = 0; + + //////////////////////////////////////////////////////////////////////// +`endif // !`ifdef I2C1 + +`ifdef GPIO0 + //////////////////////////////////////////////////////////////////////// + // + // GPIO 0 + // + //////////////////////////////////////////////////////////////////////// + + gpio gpio0 + ( + // GPIO bus + .gpio_io (gpio0_io[gpio0_io_width-1:0]), + // Wishbone slave interface + .wb_adr_i (wbs_d_gpio0_adr_i[gpio0_wb_adr_width-1:0]), + .wb_dat_i (wbs_d_gpio0_dat_i), + .wb_we_i (wbs_d_gpio0_we_i), + .wb_cyc_i (wbs_d_gpio0_cyc_i), + .wb_stb_i (wbs_d_gpio0_stb_i), + .wb_cti_i (wbs_d_gpio0_cti_i), + .wb_bte_i (wbs_d_gpio0_bte_i), + .wb_dat_o (wbs_d_gpio0_dat_o), + .wb_ack_o (wbs_d_gpio0_ack_o), + .wb_err_o (wbs_d_gpio0_err_o), + .wb_rty_o (wbs_d_gpio0_rty_o), + + .wb_clk (wb_clk), + .wb_rst (wb_rst) + ); + + defparam gpio0.gpio_io_width = gpio0_io_width; + defparam gpio0.gpio_dir_reset_val = gpio0_dir_reset_val; + defparam gpio0.gpio_o_reset_val = gpio0_o_reset_val; + + //////////////////////////////////////////////////////////////////////// +`else // !`ifdef GPIO0 + assign wbs_d_gpio0_dat_o = 0; + assign wbs_d_gpio0_ack_o = 0; + assign wbs_d_gpio0_err_o = 0; + assign wbs_d_gpio0_rty_o = 0; + //////////////////////////////////////////////////////////////////////// +`endif // !`ifdef GPIO0 + + //////////////////////////////////////////////////////////////////////// + // + // OR1200 Interrupt assignment + // + //////////////////////////////////////////////////////////////////////// + + assign or1200_pic_ints[0] = 0; // Non-maskable inside OR1200 + assign or1200_pic_ints[1] = 0; // Non-maskable inside OR1200 +`ifdef UART0 + assign or1200_pic_ints[2] = uart0_irq; +`else + assign or1200_pic_ints[2] = 0; +`endif + assign or1200_pic_ints[3] = 0; +`ifdef ETH0 + assign or1200_pic_ints[4] = eth0_irq; +`else + assign or1200_pic_ints[4] = 0; +`endif + assign or1200_pic_ints[5] = 0; +`ifdef SPI0 + assign or1200_pic_ints[6] = spi0_irq; +`else + assign or1200_pic_ints[6] = 0; +`endif + assign or1200_pic_ints[7] = 0; + assign or1200_pic_ints[8] = 0; + assign or1200_pic_ints[9] = 0; +`ifdef I2C0 + assign or1200_pic_ints[10] = i2c0_irq; +`else + assign or1200_pic_ints[10] = 0; +`endif +`ifdef I2C1 + assign or1200_pic_ints[11] = i2c1_irq; +`else + assign or1200_pic_ints[11] = 0; +`endif + assign or1200_pic_ints[12] = 0; + assign or1200_pic_ints[13] = 0; + assign or1200_pic_ints[14] = 0; + assign or1200_pic_ints[15] = 0; + assign or1200_pic_ints[16] = 0; + assign or1200_pic_ints[17] = 0; + assign or1200_pic_ints[18] = 0; + assign or1200_pic_ints[19] = 0; + assign or1200_pic_ints[20] = 0; + assign or1200_pic_ints[21] = 0; + assign or1200_pic_ints[22] = 0; + assign or1200_pic_ints[23] = 0; + assign or1200_pic_ints[24] = 0; + assign or1200_pic_ints[25] = 0; + assign or1200_pic_ints[26] = 0; + assign or1200_pic_ints[27] = 0; + assign or1200_pic_ints[28] = 0; + assign or1200_pic_ints[29] = 0; + assign or1200_pic_ints[30] = 0; + +endmodule // orpsoc_top + + Index: xilinx/atlys/rtl/verilog/arbiter/arbiter_bytebus.v =================================================================== --- xilinx/atlys/rtl/verilog/arbiter/arbiter_bytebus.v (nonexistent) +++ xilinx/atlys/rtl/verilog/arbiter/arbiter_bytebus.v (revision 627) @@ -0,0 +1,1192 @@ +////////////////////////////////////////////////////////////////////// +/// //// +/// Wishbone arbiter, byte-wide data path, no bursting //// +/// //// +/// Simple arbiter, single master, multiple slave, for byte-wide //// +/// peripherals //// +/// //// +/// Julius Baxter, julius@opencores.org //// +/// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// +// Things to update when changing slave config: +// +// 1. Port list +// 2. Port specification +// 3. Slave addr select parameter +// 4. Slave addr selects +// 5. Slave input mux logic +// 6. The four different master out mux logics (dat_o mux, and ack, rty & err) +// +`include "orpsoc-defines.v" +module arbiter_bytebus + ( + + // Master in + wbm0_adr_o, + wbm0_dat_o, + wbm0_sel_o, + wbm0_we_o, + wbm0_cyc_o, + wbm0_stb_o, + wbm0_cti_o, + wbm0_bte_o, + wbm0_dat_i, + wbm0_ack_i, + wbm0_err_i, + wbm0_rty_i, + + // Slave one + // Wishbone Slave interface + wbs0_adr_i, + wbs0_dat_i, + wbs0_we_i, + wbs0_cyc_i, + wbs0_stb_i, + wbs0_cti_i, + wbs0_bte_i, + wbs0_dat_o, + wbs0_ack_o, + wbs0_err_o, + wbs0_rty_o, + + // Slave two + // Wishbone Slave interface + wbs1_adr_i, + wbs1_dat_i, + wbs1_we_i, + wbs1_cyc_i, + wbs1_stb_i, + wbs1_cti_i, + wbs1_bte_i, + wbs1_dat_o, + wbs1_ack_o, + wbs1_err_o, + wbs1_rty_o, + + // Slave three + // Wishbone Slave interface + wbs2_adr_i, + wbs2_dat_i, + wbs2_we_i, + wbs2_cyc_i, + wbs2_stb_i, + wbs2_cti_i, + wbs2_bte_i, + wbs2_dat_o, + wbs2_ack_o, + wbs2_err_o, + wbs2_rty_o, + + // Slave four + // Wishbone Slave interface + wbs3_adr_i, + wbs3_dat_i, + wbs3_we_i, + wbs3_cyc_i, + wbs3_stb_i, + wbs3_cti_i, + wbs3_bte_i, + wbs3_dat_o, + wbs3_ack_o, + wbs3_err_o, + wbs3_rty_o, + + // Slave five + // Wishbone Slave interface + wbs4_adr_i, + wbs4_dat_i, + wbs4_we_i, + wbs4_cyc_i, + wbs4_stb_i, + wbs4_cti_i, + wbs4_bte_i, + wbs4_dat_o, + wbs4_ack_o, + wbs4_err_o, + wbs4_rty_o, +/* + // Slave six + // Wishbone Slave interface + wbs5_adr_i, + wbs5_dat_i, + wbs5_we_i, + wbs5_cyc_i, + wbs5_stb_i, + wbs5_cti_i, + wbs5_bte_i, + wbs5_dat_o, + wbs5_ack_o, + wbs5_err_o, + wbs5_rty_o, + + // Slave seven + // Wishbone Slave interface + wbs6_adr_i, + wbs6_dat_i, + wbs6_we_i, + wbs6_cyc_i, + wbs6_stb_i, + wbs6_cti_i, + wbs6_bte_i, + wbs6_dat_o, + wbs6_ack_o, + wbs6_err_o, + wbs6_rty_o, + + // Slave eight + // Wishbone Slave interface + wbs7_adr_i, + wbs7_dat_i, + wbs7_we_i, + wbs7_cyc_i, + wbs7_stb_i, + wbs7_cti_i, + wbs7_bte_i, + wbs7_dat_o, + wbs7_ack_o, + wbs7_err_o, + wbs7_rty_o, + + // Slave nine + // Wishbone Slave interface + wbs8_adr_i, + wbs8_dat_i, + wbs8_we_i, + wbs8_cyc_i, + wbs8_stb_i, + wbs8_cti_i, + wbs8_bte_i, + wbs8_dat_o, + wbs8_ack_o, + wbs8_err_o, + wbs8_rty_o, + + // Slave ten + // Wishbone Slave interface + wbs9_adr_i, + wbs9_dat_i, + wbs9_we_i, + wbs9_cyc_i, + wbs9_stb_i, + wbs9_cti_i, + wbs9_bte_i, + wbs9_dat_o, + wbs9_ack_o, + wbs9_err_o, + wbs9_rty_o, + + // Slave eleven + // Wishbone Slave interface + wbs10_adr_i, + wbs10_dat_i, + wbs10_we_i, + wbs10_cyc_i, + wbs10_stb_i, + wbs10_cti_i, + wbs10_bte_i, + wbs10_dat_o, + wbs10_ack_o, + wbs10_err_o, + wbs10_rty_o, + + // Slave twelve + // Wishbone Slave interface + wbs11_adr_i, + wbs11_dat_i, + wbs11_we_i, + wbs11_cyc_i, + wbs11_stb_i, + wbs11_cti_i, + wbs11_bte_i, + wbs11_dat_o, + wbs11_ack_o, + wbs11_err_o, + wbs11_rty_o, + + // Slave thirteen + // Wishbone Slave interface + wbs12_adr_i, + wbs12_dat_i, + wbs12_we_i, + wbs12_cyc_i, + wbs12_stb_i, + wbs12_cti_i, + wbs12_bte_i, + wbs12_dat_o, + wbs12_ack_o, + wbs12_err_o, + wbs12_rty_o, + + // Slave fourteen + // Wishbone Slave interface + wbs13_adr_i, + wbs13_dat_i, + wbs13_we_i, + wbs13_cyc_i, + wbs13_stb_i, + wbs13_cti_i, + wbs13_bte_i, + wbs13_dat_o, + wbs13_ack_o, + wbs13_err_o, + wbs13_rty_o, + + // Slave fifteen + // Wishbone Slave interface + wbs14_adr_i, + wbs14_dat_i, + wbs14_we_i, + wbs14_cyc_i, + wbs14_stb_i, + wbs14_cti_i, + wbs14_bte_i, + wbs14_dat_o, + wbs14_ack_o, + wbs14_err_o, + wbs14_rty_o, + + // Slave sixteen + // Wishbone Slave interface + wbs15_adr_i, + wbs15_dat_i, + wbs15_we_i, + wbs15_cyc_i, + wbs15_stb_i, + wbs15_cti_i, + wbs15_bte_i, + + wbs15_dat_o, + wbs15_ack_o, + wbs15_err_o, + wbs15_rty_o, + + // Slave seventeen + // Wishbone Slave interface + wbs16_adr_i, + wbs16_dat_i, + wbs16_we_i, + wbs16_cyc_i, + wbs16_stb_i, + wbs16_cti_i, + wbs16_bte_i, + + wbs16_dat_o, + wbs16_ack_o, + wbs16_err_o, + wbs16_rty_o, + + + // Slave eighteen + // Wishbone Slave interface + wbs17_adr_i, + wbs17_dat_i, + wbs17_we_i, + wbs17_cyc_i, + wbs17_stb_i, + wbs17_cti_i, + wbs17_bte_i, + + wbs17_dat_o, + wbs17_ack_o, + wbs17_err_o, + wbs17_rty_o, + + // Slave nineteen + // Wishbone Slave interface + wbs18_adr_i, + wbs18_dat_i, + wbs18_we_i, + wbs18_cyc_i, + wbs18_stb_i, + wbs18_cti_i, + wbs18_bte_i, + + wbs18_dat_o, + wbs18_ack_o, + wbs18_err_o, + wbs18_rty_o, + + // Slave twenty + // Wishbone Slave interface + wbs19_adr_i, + wbs19_dat_i, + wbs19_we_i, + wbs19_cyc_i, + wbs19_stb_i, + wbs19_cti_i, + wbs19_bte_i, + + wbs19_dat_o, + wbs19_ack_o, + wbs19_err_o, + wbs19_rty_o, + + */ + + wb_clk, wb_rst + ); + + + parameter wb_dat_width = 32; + parameter wbs_dat_width = 8; + parameter wb_adr_width = 32; + + parameter wb_addr_match_width = 8; + + parameter wb_num_slaves = 20; // Currently can handle up to 20 + + // Slave addresses + + parameter slave0_adr = 8'h00; + parameter slave1_adr = 8'h00; + parameter slave2_adr = 8'h00; + parameter slave3_adr = 8'h00; + parameter slave4_adr = 8'h00; + parameter slave5_adr = 8'h00; + parameter slave6_adr = 8'h00; + parameter slave7_adr = 8'h00; + parameter slave8_adr = 8'h00; + parameter slave9_adr = 8'h00; + parameter slave10_adr = 8'h00; + parameter slave11_adr = 8'h00; + parameter slave12_adr = 8'h00; + parameter slave13_adr = 8'h00; + parameter slave14_adr = 8'h00; + parameter slave15_adr = 8'h00; + parameter slave16_adr = 8'h00; + parameter slave17_adr = 8'h00; + parameter slave18_adr = 8'h00; + parameter slave19_adr = 8'h00; + + +`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width + + input wb_clk; + input wb_rst; + + // WB Master one + input [wb_adr_width-1:0] wbm0_adr_o; + input [wb_dat_width-1:0] wbm0_dat_o; + input [3:0] wbm0_sel_o; + input wbm0_we_o; + input wbm0_cyc_o; + input wbm0_stb_o; + input [2:0] wbm0_cti_o; + input [1:0] wbm0_bte_o; + output [wb_dat_width-1:0] wbm0_dat_i; + output wbm0_ack_i; + output wbm0_err_i; + output wbm0_rty_i; + + + // Slave one + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs0_adr_i; + output [wbs_dat_width-1:0] wbs0_dat_i; + output wbs0_we_i; + output wbs0_cyc_i; + output wbs0_stb_i; + output [2:0] wbs0_cti_i; + output [1:0] wbs0_bte_i; + input [wbs_dat_width-1:0] wbs0_dat_o; + input wbs0_ack_o; + input wbs0_err_o; + input wbs0_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs1_adr_i; + output [wbs_dat_width-1:0] wbs1_dat_i; + output wbs1_we_i; + output wbs1_cyc_i; + output wbs1_stb_i; + output [2:0] wbs1_cti_i; + output [1:0] wbs1_bte_i; + input [wbs_dat_width-1:0] wbs1_dat_o; + input wbs1_ack_o; + input wbs1_err_o; + input wbs1_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs2_adr_i; + output [wbs_dat_width-1:0] wbs2_dat_i; + output wbs2_we_i; + output wbs2_cyc_i; + output wbs2_stb_i; + output [2:0] wbs2_cti_i; + output [1:0] wbs2_bte_i; + input [wbs_dat_width-1:0] wbs2_dat_o; + input wbs2_ack_o; + input wbs2_err_o; + input wbs2_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs3_adr_i; + output [wbs_dat_width-1:0] wbs3_dat_i; + output wbs3_we_i; + output wbs3_cyc_i; + output wbs3_stb_i; + output [2:0] wbs3_cti_i; + output [1:0] wbs3_bte_i; + input [wbs_dat_width-1:0] wbs3_dat_o; + input wbs3_ack_o; + input wbs3_err_o; + input wbs3_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs4_adr_i; + output [wbs_dat_width-1:0] wbs4_dat_i; + output wbs4_we_i; + output wbs4_cyc_i; + output wbs4_stb_i; + output [2:0] wbs4_cti_i; + output [1:0] wbs4_bte_i; + input [wbs_dat_width-1:0] wbs4_dat_o; + input wbs4_ack_o; + input wbs4_err_o; + input wbs4_rty_o; + +/* + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs5_adr_i; + output [wbs_dat_width-1:0] wbs5_dat_i; + output wbs5_we_i; + output wbs5_cyc_i; + output wbs5_stb_i; + output [2:0] wbs5_cti_i; + output [1:0] wbs5_bte_i; + input [wbs_dat_width-1:0] wbs5_dat_o; + input wbs5_ack_o; + input wbs5_err_o; + input wbs5_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs6_adr_i; + output [wbs_dat_width-1:0] wbs6_dat_i; + output wbs6_we_i; + output wbs6_cyc_i; + output wbs6_stb_i; + output [2:0] wbs6_cti_i; + output [1:0] wbs6_bte_i; + input [wbs_dat_width-1:0] wbs6_dat_o; + input wbs6_ack_o; + input wbs6_err_o; + input wbs6_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs7_adr_i; + output [wbs_dat_width-1:0] wbs7_dat_i; + output wbs7_we_i; + output wbs7_cyc_i; + output wbs7_stb_i; + output [2:0] wbs7_cti_i; + output [1:0] wbs7_bte_i; + input [wbs_dat_width-1:0] wbs7_dat_o; + input wbs7_ack_o; + input wbs7_err_o; + input wbs7_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs8_adr_i; + output [wbs_dat_width-1:0] wbs8_dat_i; + output wbs8_we_i; + output wbs8_cyc_i; + output wbs8_stb_i; + output [2:0] wbs8_cti_i; + output [1:0] wbs8_bte_i; + input [wbs_dat_width-1:0] wbs8_dat_o; + input wbs8_ack_o; + input wbs8_err_o; + input wbs8_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs9_adr_i; + output [wbs_dat_width-1:0] wbs9_dat_i; + output wbs9_we_i; + output wbs9_cyc_i; + output wbs9_stb_i; + output [2:0] wbs9_cti_i; + output [1:0] wbs9_bte_i; + input [wbs_dat_width-1:0] wbs9_dat_o; + input wbs9_ack_o; + input wbs9_err_o; + input wbs9_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs10_adr_i; + output [wbs_dat_width-1:0] wbs10_dat_i; + output wbs10_we_i; + output wbs10_cyc_i; + output wbs10_stb_i; + output [2:0] wbs10_cti_i; + output [1:0] wbs10_bte_i; + input [wbs_dat_width-1:0] wbs10_dat_o; + input wbs10_ack_o; + input wbs10_err_o; + input wbs10_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs11_adr_i; + output [wbs_dat_width-1:0] wbs11_dat_i; + output wbs11_we_i; + output wbs11_cyc_i; + output wbs11_stb_i; + output [2:0] wbs11_cti_i; + output [1:0] wbs11_bte_i; + input [wbs_dat_width-1:0] wbs11_dat_o; + input wbs11_ack_o; + input wbs11_err_o; + input wbs11_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs12_adr_i; + output [wbs_dat_width-1:0] wbs12_dat_i; + output wbs12_we_i; + output wbs12_cyc_i; + output wbs12_stb_i; + output [2:0] wbs12_cti_i; + output [1:0] wbs12_bte_i; + input [wbs_dat_width-1:0] wbs12_dat_o; + input wbs12_ack_o; + input wbs12_err_o; + input wbs12_rty_o; + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs13_adr_i; + output [wbs_dat_width-1:0] wbs13_dat_i; + output wbs13_we_i; + output wbs13_cyc_i; + output wbs13_stb_i; + output [2:0] wbs13_cti_i; + output [1:0] wbs13_bte_i; + input [wbs_dat_width-1:0] wbs13_dat_o; + input wbs13_ack_o; + input wbs13_err_o; + input wbs13_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs14_adr_i; + output [wbs_dat_width-1:0] wbs14_dat_i; + output wbs14_we_i; + output wbs14_cyc_i; + output wbs14_stb_i; + output [2:0] wbs14_cti_i; + output [1:0] wbs14_bte_i; + input [wbs_dat_width-1:0] wbs14_dat_o; + input wbs14_ack_o; + input wbs14_err_o; + input wbs14_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs15_adr_i; + output [wbs_dat_width-1:0] wbs15_dat_i; + output wbs15_we_i; + output wbs15_cyc_i; + output wbs15_stb_i; + output [2:0] wbs15_cti_i; + output [1:0] wbs15_bte_i; + input [wbs_dat_width-1:0] wbs15_dat_o; + input wbs15_ack_o; + input wbs15_err_o; + input wbs15_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs16_adr_i; + output [wbs_dat_width-1:0] wbs16_dat_i; + output wbs16_we_i; + output wbs16_cyc_i; + output wbs16_stb_i; + output [2:0] wbs16_cti_i; + output [1:0] wbs16_bte_i; + input [wbs_dat_width-1:0] wbs16_dat_o; + input wbs16_ack_o; + input wbs16_err_o; + input wbs16_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs17_adr_i; + output [wbs_dat_width-1:0] wbs17_dat_i; + output wbs17_we_i; + output wbs17_cyc_i; + output wbs17_stb_i; + output [2:0] wbs17_cti_i; + output [1:0] wbs17_bte_i; + input [wbs_dat_width-1:0] wbs17_dat_o; + input wbs17_ack_o; + input wbs17_err_o; + input wbs17_rty_o; + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs18_adr_i; + output [wbs_dat_width-1:0] wbs18_dat_i; + output wbs18_we_i; + output wbs18_cyc_i; + output wbs18_stb_i; + output [2:0] wbs18_cti_i; + output [1:0] wbs18_bte_i; + input [wbs_dat_width-1:0] wbs18_dat_o; + input wbs18_ack_o; + input wbs18_err_o; + input wbs18_rty_o; + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs19_adr_i; + output [wbs_dat_width-1:0] wbs19_dat_i; + output wbs19_we_i; + output wbs19_cyc_i; + output wbs19_stb_i; + output [2:0] wbs19_cti_i; + output [1:0] wbs19_bte_i; + input [wbs_dat_width-1:0] wbs19_dat_o; + input wbs19_ack_o; + input wbs19_err_o; + input wbs19_rty_o; + */ + + reg watchdog_err; + + // Master input mux output wires + wire [wb_adr_width-1:0] wbm_adr_o; + wire [wbs_dat_width-1:0] wbm_dat_o; + wire [3:0] wbm_sel_o; + wire wbm_we_o; + wire wbm_cyc_o; + wire wbm_stb_o; + wire [2:0] wbm_cti_o; + wire [1:0] wbm_bte_o; + + wire [wbs_dat_width-1:0] wbm_dat_byte_i; + wire wbm_ack_i; + wire wbm_err_i; + wire wbm_rty_i; + + + // Master input mux (not really used, only one master on this bus) + assign wbm_adr_o = wbm0_adr_o; + + // Select the right byte and put it on the data out line + // !BIG ENDIAN! + assign wbm_dat_o = wbm0_sel_o[3] ? wbm0_dat_o[31:24] : + wbm0_sel_o[2] ? wbm0_dat_o[23:16] : + wbm0_sel_o[1] ? wbm0_dat_o[15:8] : + wbm0_dat_o[7:0]; + + assign wbm_we_o = wbm0_we_o; + + assign wbm_cyc_o = wbm0_stb_o; + + assign wbm_stb_o = wbm0_stb_o; + + // Will we really need these for byte-peripherals + assign wbm_cti_o = wbm0_cti_o; + + assign wbm_bte_o = wbm0_bte_o; + + // Signals back to the master + assign wbm0_dat_i = (wbm0_sel_o[3]) ? {wbm_dat_byte_i, 24'd0} : + (wbm0_sel_o[2]) ? {8'd0, wbm_dat_byte_i, 16'd0} : + (wbm0_sel_o[1]) ? {16'd0, wbm_dat_byte_i, 8'd0} : + {24'd0, wbm_dat_byte_i}; + + assign wbm0_ack_i = wbm_ack_i; + assign wbm0_err_i = wbm_err_i; + assign wbm0_rty_i = wbm_rty_i; + +`ifdef ARBITER_BYTEBUS_WATCHDOG + reg [`ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer; + reg wbm_stb_r; // Register strobe + wire wbm_stb_edge; // Detect its edge + + always @(posedge wb_clk) + wbm_stb_r <= wbm_stb_o; + + assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r); + + // Counter logic + always @(posedge wb_clk) + if (wb_rst) watchdog_timer <= 0; + else if (wbm_ack_i) // When we see an ack, turn off timer + watchdog_timer <= 0; + else if (wbm_stb_edge) // New access means start timer again + watchdog_timer <= 1; + else if (|watchdog_timer) // Continue counting if counter > 0 + watchdog_timer <= watchdog_timer + 1; + + always @(posedge wb_clk) + watchdog_err <= (&watchdog_timer); + +`else // !`ifdef ARBITER_BYTEBUS_WATCHDOG + always @(posedge wb_clk) + watchdog_err <= 0; + +`endif // !`ifdef ARBITER_BYTEBUS_WATCHDOG + + + // Wishbone slave mux out wires + wire [wb_adr_width-1:0] wbs_adr_i; + wire [wbs_dat_width-1:0] wbs_dat_i; + wire wbs_we_i; + wire wbs_cyc_i; + wire wbs_stb_i; + wire [2:0] wbs_cti_i; + wire [1:0] wbs_bte_i; + wire [wbs_dat_width-1:0] wbs_dat_o; + wire wbs_ack_o; + wire wbs_err_o; + wire wbs_rty_o; + + + // Slave select wire + wire [wb_num_slaves-1:0] wb_slave_sel; + + // Slave out mux in wires + wire [wbs_dat_width-1:0] wbs_dat_o_mux_i [0:wb_num_slaves-1]; + wire wbs_ack_o_mux_i [0:wb_num_slaves-1]; + wire wbs_err_o_mux_i [0:wb_num_slaves-1]; + wire wbs_rty_o_mux_i [0:wb_num_slaves-1]; + + // Slave selects + assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr; + assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr; + assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr; + assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr; + assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr; + /* + assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr; + assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr; + assign wb_slave_sel[7] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave7_adr; + assign wb_slave_sel[8] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave8_adr; + assign wb_slave_sel[9] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave9_adr; + assign wb_slave_sel[10] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave10_adr; + assign wb_slave_sel[11] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave11_adr; + assign wb_slave_sel[12] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave12_adr; + assign wb_slave_sel[13] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave13_adr; + assign wb_slave_sel[14] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave14_adr; + assign wb_slave_sel[15] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave15_adr; + assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave16_adr; + assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave17_adr; + assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave18_adr; + assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave19_adr; + */ + + + // Assign master inputs to slaves and slave inputs for MUXing back to master + + // Slave 0 inputs + assign wbs0_adr_i = wbm_adr_o; + assign wbs0_dat_i = wbm_dat_o; + assign wbs0_cyc_i = wbm_cyc_o & wb_slave_sel[0]; + assign wbs0_stb_i = wbm_stb_o & wb_slave_sel[0]; + assign wbs0_we_i = wbm_we_o; + assign wbs0_cti_i = wbm_cti_o; + assign wbs0_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[0] = wbs0_dat_o; + assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel[0]; + assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0]; + assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0]; + + + // Slave 1 inputs + assign wbs1_adr_i = wbm_adr_o; + assign wbs1_dat_i = wbm_dat_o; + assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel[1]; + assign wbs1_stb_i = wbm_stb_o & wb_slave_sel[1]; + assign wbs1_we_i = wbm_we_o; + assign wbs1_cti_i = wbm_cti_o; + assign wbs1_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[1] = wbs1_dat_o; + assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel[1]; + assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1]; + assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1]; + + + // Slave 2 inputs + assign wbs2_adr_i = wbm_adr_o; + assign wbs2_dat_i = wbm_dat_o; + assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel[2]; + assign wbs2_stb_i = wbm_stb_o & wb_slave_sel[2]; + assign wbs2_we_i = wbm_we_o; + assign wbs2_cti_i = wbm_cti_o; + assign wbs2_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[2] = wbs2_dat_o; + assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel[2]; + assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel[2]; + assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel[2]; + + + // Slave 3 inputs + assign wbs3_adr_i = wbm_adr_o; + assign wbs3_dat_i = wbm_dat_o; + assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel[3]; + assign wbs3_stb_i = wbm_stb_o & wb_slave_sel[3]; + assign wbs3_we_i = wbm_we_o; + assign wbs3_cti_i = wbm_cti_o; + assign wbs3_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[3] = wbs3_dat_o; + assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel[3]; + assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel[3]; + assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel[3]; + + + // Slave 4 inputs + assign wbs4_adr_i = wbm_adr_o; + assign wbs4_dat_i = wbm_dat_o; + assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel[4]; + assign wbs4_stb_i = wbm_stb_o & wb_slave_sel[4]; + assign wbs4_we_i = wbm_we_o; + assign wbs4_cti_i = wbm_cti_o; + assign wbs4_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[4] = wbs4_dat_o; + assign wbs_ack_o_mux_i[4] = wbs4_ack_o & wb_slave_sel[4]; + assign wbs_err_o_mux_i[4] = wbs4_err_o & wb_slave_sel[4]; + assign wbs_rty_o_mux_i[4] = wbs4_rty_o & wb_slave_sel[4]; + + /* + // Slave 5 inputs + assign wbs5_adr_i = wbm_adr_o; + assign wbs5_dat_i = wbm_dat_o; + assign wbs5_cyc_i = wbm_cyc_o & wb_slave_sel[5]; + assign wbs5_stb_i = wbm_stb_o & wb_slave_sel[5]; + assign wbs5_we_i = wbm_we_o; + assign wbs5_cti_i = wbm_cti_o; + assign wbs5_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[5] = wbs5_dat_o; + assign wbs_ack_o_mux_i[5] = wbs5_ack_o & wb_slave_sel[5]; + assign wbs_err_o_mux_i[5] = wbs5_err_o & wb_slave_sel[5]; + assign wbs_rty_o_mux_i[5] = wbs5_rty_o & wb_slave_sel[5]; + + + // Slave 6 inputs + assign wbs6_adr_i = wbm_adr_o; + assign wbs6_dat_i = wbm_dat_o; + assign wbs6_cyc_i = wbm_cyc_o & wb_slave_sel[6]; + assign wbs6_stb_i = wbm_stb_o & wb_slave_sel[6]; + assign wbs6_we_i = wbm_we_o; + assign wbs6_cti_i = wbm_cti_o; + assign wbs6_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[6] = wbs6_dat_o; + assign wbs_ack_o_mux_i[6] = wbs6_ack_o & wb_slave_sel[6]; + assign wbs_err_o_mux_i[6] = wbs6_err_o & wb_slave_sel[6]; + assign wbs_rty_o_mux_i[6] = wbs6_rty_o & wb_slave_sel[6]; + + + // Slave 7 inputs + assign wbs7_adr_i = wbm_adr_o; + assign wbs7_dat_i = wbm_dat_o; + assign wbs7_cyc_i = wbm_cyc_o & wb_slave_sel[7]; + assign wbs7_stb_i = wbm_stb_o & wb_slave_sel[7]; + assign wbs7_we_i = wbm_we_o; + assign wbs7_cti_i = wbm_cti_o; + assign wbs7_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[7] = wbs7_dat_o; + assign wbs_ack_o_mux_i[7] = wbs7_ack_o & wb_slave_sel[7]; + assign wbs_err_o_mux_i[7] = wbs7_err_o & wb_slave_sel[7]; + assign wbs_rty_o_mux_i[7] = wbs7_rty_o & wb_slave_sel[7]; + + + // Slave 8 inputs + assign wbs8_adr_i = wbm_adr_o; + assign wbs8_dat_i = wbm_dat_o; + assign wbs8_cyc_i = wbm_cyc_o & wb_slave_sel[8]; + assign wbs8_stb_i = wbm_stb_o & wb_slave_sel[8]; + assign wbs8_we_i = wbm_we_o; + assign wbs8_cti_i = wbm_cti_o; + assign wbs8_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[8] = wbs8_dat_o; + assign wbs_ack_o_mux_i[8] = wbs8_ack_o & wb_slave_sel[8]; + assign wbs_err_o_mux_i[8] = wbs8_err_o & wb_slave_sel[8]; + assign wbs_rty_o_mux_i[8] = wbs8_rty_o & wb_slave_sel[8]; + + + // Slave 9 inputs + assign wbs9_adr_i = wbm_adr_o; + assign wbs9_dat_i = wbm_dat_o; + assign wbs9_cyc_i = wbm_cyc_o & wb_slave_sel[9]; + assign wbs9_stb_i = wbm_stb_o & wb_slave_sel[9]; + assign wbs9_we_i = wbm_we_o; + assign wbs9_cti_i = wbm_cti_o; + assign wbs9_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[9] = wbs9_dat_o; + assign wbs_ack_o_mux_i[9] = wbs9_ack_o & wb_slave_sel[9]; + assign wbs_err_o_mux_i[9] = wbs9_err_o & wb_slave_sel[9]; + assign wbs_rty_o_mux_i[9] = wbs9_rty_o & wb_slave_sel[9]; + + + // Slave 10 inputs + assign wbs10_adr_i = wbm_adr_o; + assign wbs10_dat_i = wbm_dat_o; + assign wbs10_cyc_i = wbm_cyc_o & wb_slave_sel[10]; + assign wbs10_stb_i = wbm_stb_o & wb_slave_sel[10]; + assign wbs10_we_i = wbm_we_o; + assign wbs10_cti_i = wbm_cti_o; + assign wbs10_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[10] = wbs10_dat_o; + assign wbs_ack_o_mux_i[10] = wbs10_ack_o & wb_slave_sel[10]; + assign wbs_err_o_mux_i[10] = wbs10_err_o & wb_slave_sel[10]; + assign wbs_rty_o_mux_i[10] = wbs10_rty_o & wb_slave_sel[10]; + + + // Slave 11 inputs + assign wbs11_adr_i = wbm_adr_o; + assign wbs11_dat_i = wbm_dat_o; + assign wbs11_cyc_i = wbm_cyc_o & wb_slave_sel[11]; + assign wbs11_stb_i = wbm_stb_o & wb_slave_sel[11]; + assign wbs11_we_i = wbm_we_o; + assign wbs11_cti_i = wbm_cti_o; + assign wbs11_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[11] = wbs11_dat_o; + assign wbs_ack_o_mux_i[11] = wbs11_ack_o & wb_slave_sel[11]; + assign wbs_err_o_mux_i[11] = wbs11_err_o & wb_slave_sel[11]; + assign wbs_rty_o_mux_i[11] = wbs11_rty_o & wb_slave_sel[11]; + + // Slave 12 inputs + assign wbs12_adr_i = wbm_adr_o; + assign wbs12_dat_i = wbm_dat_o; + assign wbs12_cyc_i = wbm_cyc_o & wb_slave_sel[12]; + assign wbs12_stb_i = wbm_stb_o & wb_slave_sel[12]; + assign wbs12_we_i = wbm_we_o; + assign wbs12_cti_i = wbm_cti_o; + assign wbs12_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[12] = wbs12_dat_o; + assign wbs_ack_o_mux_i[12] = wbs12_ack_o & wb_slave_sel[12]; + assign wbs_err_o_mux_i[12] = wbs12_err_o & wb_slave_sel[12]; + assign wbs_rty_o_mux_i[12] = wbs12_rty_o & wb_slave_sel[12]; + + + // Slave 13 inputs + assign wbs13_adr_i = wbm_adr_o; + assign wbs13_dat_i = wbm_dat_o; + assign wbs13_cyc_i = wbm_cyc_o & wb_slave_sel[13]; + assign wbs13_stb_i = wbm_stb_o & wb_slave_sel[13]; + assign wbs13_we_i = wbm_we_o; + assign wbs13_cti_i = wbm_cti_o; + assign wbs13_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[13] = wbs13_dat_o; + assign wbs_ack_o_mux_i[13] = wbs13_ack_o & wb_slave_sel[13]; + assign wbs_err_o_mux_i[13] = wbs13_err_o & wb_slave_sel[13]; + assign wbs_rty_o_mux_i[13] = wbs13_rty_o & wb_slave_sel[13]; + + + // Slave 14 inputs + assign wbs14_adr_i = wbm_adr_o; + assign wbs14_dat_i = wbm_dat_o; + assign wbs14_cyc_i = wbm_cyc_o & wb_slave_sel[14]; + assign wbs14_stb_i = wbm_stb_o & wb_slave_sel[14]; + assign wbs14_we_i = wbm_we_o; + assign wbs14_cti_i = wbm_cti_o; + assign wbs14_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[14] = wbs14_dat_o; + assign wbs_ack_o_mux_i[14] = wbs14_ack_o & wb_slave_sel[14]; + assign wbs_err_o_mux_i[14] = wbs14_err_o & wb_slave_sel[14]; + assign wbs_rty_o_mux_i[14] = wbs14_rty_o & wb_slave_sel[14]; + + + // Slave 15 inputs + assign wbs15_adr_i = wbm_adr_o; + assign wbs15_dat_i = wbm_dat_o; + assign wbs15_cyc_i = wbm_cyc_o & wb_slave_sel[15]; + assign wbs15_stb_i = wbm_stb_o & wb_slave_sel[15]; + assign wbs15_we_i = wbm_we_o; + assign wbs15_cti_i = wbm_cti_o; + assign wbs15_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[15] = wbs15_dat_o; + assign wbs_ack_o_mux_i[15] = wbs15_ack_o & wb_slave_sel[15]; + assign wbs_err_o_mux_i[15] = wbs15_err_o & wb_slave_sel[15]; + assign wbs_rty_o_mux_i[15] = wbs15_rty_o & wb_slave_sel[15]; + + + // Slave 16 inputs + assign wbs16_adr_i = wbm_adr_o; + assign wbs16_dat_i = wbm_dat_o; + assign wbs16_cyc_i = wbm_cyc_o & wb_slave_sel[16]; + assign wbs16_stb_i = wbm_stb_o & wb_slave_sel[16]; + assign wbs16_we_i = wbm_we_o; + assign wbs16_cti_i = wbm_cti_o; + assign wbs16_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[16] = wbs16_dat_o; + assign wbs_ack_o_mux_i[16] = wbs16_ack_o & wb_slave_sel[16]; + assign wbs_err_o_mux_i[16] = wbs16_err_o & wb_slave_sel[16]; + assign wbs_rty_o_mux_i[16] = wbs16_rty_o & wb_slave_sel[16]; + + + // Slave 17 inputs + assign wbs17_adr_i = wbm_adr_o; + assign wbs17_dat_i = wbm_dat_o; + assign wbs17_cyc_i = wbm_cyc_o & wb_slave_sel[17]; + assign wbs17_stb_i = wbm_stb_o & wb_slave_sel[17]; + assign wbs17_we_i = wbm_we_o; + assign wbs17_cti_i = wbm_cti_o; + assign wbs17_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[17] = wbs17_dat_o; + assign wbs_ack_o_mux_i[17] = wbs17_ack_o & wb_slave_sel[17]; + assign wbs_err_o_mux_i[17] = wbs17_err_o & wb_slave_sel[17]; + assign wbs_rty_o_mux_i[17] = wbs17_rty_o & wb_slave_sel[17]; + + // Slave 18 inputs + assign wbs18_adr_i = wbm_adr_o; + assign wbs18_dat_i = wbm_dat_o; + assign wbs18_cyc_i = wbm_cyc_o & wb_slave_sel[18]; + assign wbs18_stb_i = wbm_stb_o & wb_slave_sel[18]; + assign wbs18_we_i = wbm_we_o; + assign wbs18_cti_i = wbm_cti_o; + assign wbs18_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[18] = wbs18_dat_o; + assign wbs_ack_o_mux_i[18] = wbs18_ack_o & wb_slave_sel[18]; + assign wbs_err_o_mux_i[18] = wbs18_err_o & wb_slave_sel[18]; + assign wbs_rty_o_mux_i[18] = wbs18_rty_o & wb_slave_sel[18]; + + // Slave 19 inputs + assign wbs19_adr_i = wbm_adr_o; + assign wbs19_dat_i = wbm_dat_o; + assign wbs19_cyc_i = wbm_cyc_o & wb_slave_sel[19]; + assign wbs19_stb_i = wbm_stb_o & wb_slave_sel[19]; + assign wbs19_we_i = wbm_we_o; + assign wbs19_cti_i = wbm_cti_o; + assign wbs19_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[19] = wbs19_dat_o; + assign wbs_ack_o_mux_i[19] = wbs19_ack_o & wb_slave_sel[19]; + assign wbs_err_o_mux_i[19] = wbs19_err_o & wb_slave_sel[19]; + assign wbs_rty_o_mux_i[19] = wbs19_rty_o & wb_slave_sel[19]; + +*/ + + + + // Master out mux from slave in data + assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] : + wb_slave_sel[1] ? wbs_dat_o_mux_i[1] : + wb_slave_sel[2] ? wbs_dat_o_mux_i[2] : + wb_slave_sel[3] ? wbs_dat_o_mux_i[3] : + wb_slave_sel[4] ? wbs_dat_o_mux_i[4] : + /* + wb_slave_sel[5] ? wbs_dat_o_mux_i[5] : + wb_slave_sel[6] ? wbs_dat_o_mux_i[6] : + wb_slave_sel[7] ? wbs_dat_o_mux_i[7] : + wb_slave_sel[8] ? wbs_dat_o_mux_i[8] : + wb_slave_sel[9] ? wbs_dat_o_mux_i[9] : + wb_slave_sel[10] ? wbs_dat_o_mux_i[10] : + wb_slave_sel[11] ? wbs_dat_o_mux_i[11] : + wb_slave_sel[12] ? wbs_dat_o_mux_i[12] : + wb_slave_sel[13] ? wbs_dat_o_mux_i[13] : + wb_slave_sel[14] ? wbs_dat_o_mux_i[14] : + wb_slave_sel[15] ? wbs_dat_o_mux_i[15] : + wb_slave_sel[16] ? wbs_dat_o_mux_i[16] : + wb_slave_sel[17] ? wbs_dat_o_mux_i[17] : + wb_slave_sel[18] ? wbs_dat_o_mux_i[18] : + wb_slave_sel[19] ? wbs_dat_o_mux_i[19] : +*/ + wbs_dat_o_mux_i[0]; + // Master out acks, or together + assign wbm_ack_i = wbs_ack_o_mux_i[0] | + wbs_ack_o_mux_i[1] | + wbs_ack_o_mux_i[2] | + wbs_ack_o_mux_i[3] | + wbs_ack_o_mux_i[4] /* | + wbs_ack_o_mux_i[5] | + wbs_ack_o_mux_i[6] | + wbs_ack_o_mux_i[7] | + wbs_ack_o_mux_i[8] | + wbs_ack_o_mux_i[9] | + wbs_ack_o_mux_i[10] | + wbs_ack_o_mux_i[11] | + wbs_ack_o_mux_i[12] | + wbs_ack_o_mux_i[13] | + wbs_ack_o_mux_i[14] | + wbs_ack_o_mux_i[15] | + wbs_ack_o_mux_i[16] | + wbs_ack_o_mux_i[17] | + wbs_ack_o_mux_i[18] | + wbs_ack_o_mux_i[19] + */ + ; + + + assign wbm_err_i = wbs_err_o_mux_i[0] | + wbs_err_o_mux_i[1] | + wbs_err_o_mux_i[2] | + wbs_err_o_mux_i[3] | + wbs_err_o_mux_i[4] |/* + wbs_err_o_mux_i[5] | + wbs_err_o_mux_i[6] | + wbs_err_o_mux_i[7] | + wbs_err_o_mux_i[8] | + wbs_err_o_mux_i[9] | + wbs_err_o_mux_i[10] | + wbs_err_o_mux_i[11] | + wbs_err_o_mux_i[12] | + wbs_err_o_mux_i[13] | + wbs_err_o_mux_i[14] | + wbs_err_o_mux_i[15] | + wbs_err_o_mux_i[16] | + wbs_err_o_mux_i[17] | + wbs_err_o_mux_i[18] | + wbs_err_o_mux_i[19] | + */ + watchdog_err ; + + + assign wbm_rty_i = wbs_rty_o_mux_i[0] | + wbs_rty_o_mux_i[1] | + wbs_rty_o_mux_i[2] | + wbs_rty_o_mux_i[3] | + wbs_rty_o_mux_i[4] /*| + wbs_rty_o_mux_i[5] | + wbs_rty_o_mux_i[6] | + wbs_rty_o_mux_i[7] | + wbs_rty_o_mux_i[8] | + wbs_rty_o_mux_i[9] | + wbs_rty_o_mux_i[10] | + wbs_rty_o_mux_i[11] | + wbs_rty_o_mux_i[12] | + wbs_rty_o_mux_i[13] | + wbs_rty_o_mux_i[14] | + wbs_rty_o_mux_i[15] | + wbs_rty_o_mux_i[16] | + wbs_rty_o_mux_i[17] | + wbs_rty_o_mux_i[18] | + wbs_rty_o_mux_i[19] + */ + ; + +endmodule // arbiter_bytebus Index: xilinx/atlys/rtl/verilog/arbiter/arbiter_dbus.v =================================================================== --- xilinx/atlys/rtl/verilog/arbiter/arbiter_dbus.v (nonexistent) +++ xilinx/atlys/rtl/verilog/arbiter/arbiter_dbus.v (revision 627) @@ -0,0 +1,1268 @@ +////////////////////////////////////////////////////////////////////// +/// //// +/// Wishbone arbiter, burst-compatible //// +/// //// +/// Simple arbiter, multi-master, multi-slave with default slave //// +/// for chaining with peripheral arbiter //// +/// //// +/// Julius Baxter, julius@opencores.org //// +/// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +`include "orpsoc-defines.v" +// 2 Masters, a few slaves +module arbiter_dbus + ( + // or1200 data master + // Wishbone Master interface + wbm0_adr_o, + wbm0_dat_o, + wbm0_sel_o, + wbm0_we_o, + wbm0_cyc_o, + wbm0_stb_o, + wbm0_cti_o, + wbm0_bte_o, + + wbm0_dat_i, + wbm0_ack_i, + wbm0_err_i, + wbm0_rty_i, + + // or1200 debug master + // Wishbone Master interface + wbm1_adr_o, + wbm1_dat_o, + wbm1_sel_o, + wbm1_we_o, + wbm1_cyc_o, + wbm1_stb_o, + wbm1_cti_o, + wbm1_bte_o, + + wbm1_dat_i, + wbm1_ack_i, + wbm1_err_i, + wbm1_rty_i, + + // Slave one + // Wishbone Slave interface + wbs0_adr_i, + wbs0_dat_i, + wbs0_sel_i, + wbs0_we_i, + wbs0_cyc_i, + wbs0_stb_i, + wbs0_cti_i, + wbs0_bte_i, + + wbs0_dat_o, + wbs0_ack_o, + wbs0_err_o, + wbs0_rty_o, + + // Slave two + // Wishbone Slave interface + wbs1_adr_i, + wbs1_dat_i, + wbs1_sel_i, + wbs1_we_i, + wbs1_cyc_i, + wbs1_stb_i, + wbs1_cti_i, + wbs1_bte_i, + + wbs1_dat_o, + wbs1_ack_o, + wbs1_err_o, + wbs1_rty_o, + + + // Slave three + // Wishbone Slave interface + wbs2_adr_i, + wbs2_dat_i, + wbs2_sel_i, + wbs2_we_i, + wbs2_cyc_i, + wbs2_stb_i, + wbs2_cti_i, + wbs2_bte_i, + + wbs2_dat_o, + wbs2_ack_o, + wbs2_err_o, + wbs2_rty_o, + /* + // Slave four + // Wishbone Slave interface + wbs3_adr_i, + wbs3_dat_i, + wbs3_sel_i, + wbs3_we_i, + wbs3_cyc_i, + wbs3_stb_i, + wbs3_cti_i, + wbs3_bte_i, + + wbs3_dat_o, + wbs3_ack_o, + wbs3_err_o, + wbs3_rty_o, + + // Slave five + // Wishbone Slave interface + wbs4_adr_i, + wbs4_dat_i, + wbs4_sel_i, + wbs4_we_i, + wbs4_cyc_i, + wbs4_stb_i, + wbs4_cti_i, + wbs4_bte_i, + + wbs4_dat_o, + wbs4_ack_o, + wbs4_err_o, + wbs4_rty_o, + + // Slave six + // Wishbone Slave interface + wbs5_adr_i, + wbs5_dat_i, + wbs5_sel_i, + wbs5_we_i, + wbs5_cyc_i, + wbs5_stb_i, + wbs5_cti_i, + wbs5_bte_i, + + wbs5_dat_o, + wbs5_ack_o, + wbs5_err_o, + wbs5_rty_o, + + // Slave seven + // Wishbone Slave interface + wbs6_adr_i, + wbs6_dat_i, + wbs6_sel_i, + wbs6_we_i, + wbs6_cyc_i, + wbs6_stb_i, + wbs6_cti_i, + wbs6_bte_i, + + wbs6_dat_o, + wbs6_ack_o, + wbs6_err_o, + wbs6_rty_o, + + // Slave eight + // Wishbone Slave interface + wbs7_adr_i, + wbs7_dat_i, + wbs7_sel_i, + wbs7_we_i, + wbs7_cyc_i, + wbs7_stb_i, + wbs7_cti_i, + wbs7_bte_i, + + wbs7_dat_o, + wbs7_ack_o, + wbs7_err_o, + wbs7_rty_o, + + // Slave nine + // Wishbone Slave interface + wbs8_adr_i, + wbs8_dat_i, + wbs8_sel_i, + wbs8_we_i, + wbs8_cyc_i, + wbs8_stb_i, + wbs8_cti_i, + wbs8_bte_i, + + wbs8_dat_o, + wbs8_ack_o, + wbs8_err_o, + wbs8_rty_o, + + // Slave ten + // Wishbone Slave interface + wbs9_adr_i, + wbs9_dat_i, + wbs9_sel_i, + wbs9_we_i, + wbs9_cyc_i, + wbs9_stb_i, + wbs9_cti_i, + wbs9_bte_i, + + wbs9_dat_o, + wbs9_ack_o, + wbs9_err_o, + wbs9_rty_o, + + // Slave eleven + // Wishbone Slave interface + wbs10_adr_i, + wbs10_dat_i, + wbs10_sel_i, + wbs10_we_i, + wbs10_cyc_i, + wbs10_stb_i, + wbs10_cti_i, + wbs10_bte_i, + + wbs10_dat_o, + wbs10_ack_o, + wbs10_err_o, + wbs10_rty_o, + + // Slave twelve + // Wishbone Slave interface + wbs11_adr_i, + wbs11_dat_i, + wbs11_sel_i, + wbs11_we_i, + wbs11_cyc_i, + wbs11_stb_i, + wbs11_cti_i, + wbs11_bte_i, + + wbs11_dat_o, + wbs11_ack_o, + wbs11_err_o, + wbs11_rty_o, + + // Slave thirteen + // Wishbone Slave interface + wbs12_adr_i, + wbs12_dat_i, + wbs12_sel_i, + wbs12_we_i, + wbs12_cyc_i, + wbs12_stb_i, + wbs12_cti_i, + wbs12_bte_i, + + wbs12_dat_o, + wbs12_ack_o, + wbs12_err_o, + wbs12_rty_o, + + // Slave fourteen + // Wishbone Slave interface + wbs13_adr_i, + wbs13_dat_i, + wbs13_sel_i, + wbs13_we_i, + wbs13_cyc_i, + wbs13_stb_i, + wbs13_cti_i, + wbs13_bte_i, + + wbs13_dat_o, + wbs13_ack_o, + wbs13_err_o, + wbs13_rty_o, + + // Slave fifteen + // Wishbone Slave interface + wbs14_adr_i, + wbs14_dat_i, + wbs14_sel_i, + wbs14_we_i, + wbs14_cyc_i, + wbs14_stb_i, + wbs14_cti_i, + wbs14_bte_i, + + wbs14_dat_o, + wbs14_ack_o, + wbs14_err_o, + wbs14_rty_o, + + // Slave sixteen + // Wishbone Slave interface + wbs15_adr_i, + wbs15_dat_i, + wbs15_sel_i, + wbs15_we_i, + wbs15_cyc_i, + wbs15_stb_i, + wbs15_cti_i, + wbs15_bte_i, + + wbs15_dat_o, + wbs15_ack_o, + wbs15_err_o, + wbs15_rty_o, + + // Slave seventeen + // Wishbone Slave interface + wbs16_adr_i, + wbs16_dat_i, + wbs16_sel_i, + wbs16_we_i, + wbs16_cyc_i, + wbs16_stb_i, + wbs16_cti_i, + wbs16_bte_i, + + wbs16_dat_o, + wbs16_ack_o, + wbs16_err_o, + wbs16_rty_o, + */ + + wb_clk, + wb_rst + ); + + parameter wb_dat_width = 32; + parameter wb_adr_width = 32; + + parameter wb_addr_match_width = 8; + + parameter wb_num_slaves = 2; // must also (un)comment things if changing + + // Slave addresses - these should be defparam'd from top level + // Declare them as you need them + parameter slave0_adr = 0; + parameter slave1_adr = 0; + parameter slave2_adr = 0; + parameter slave3_adr = 0; + parameter slave4_adr = 0; + parameter slave5_adr = 0; + parameter slave6_adr = 0; + parameter slave7_adr = 0; + parameter slave8_adr = 0; + parameter slave9_adr = 0; + parameter slave10_adr = 0; + parameter slave11_adr = 0; + parameter slave12_adr = 0; + + // Select for slave 0 +`define WB_ARB_ADDR_MATCH_SEL_SLAVE0 wb_adr_width-1:wb_adr_width-4 +`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width + + input wb_clk; + input wb_rst; + + // WB Master one + input [wb_adr_width-1:0] wbm0_adr_o; + input [wb_dat_width-1:0] wbm0_dat_o; + input [3:0] wbm0_sel_o; + input wbm0_we_o; + input wbm0_cyc_o; + input wbm0_stb_o; + input [2:0] wbm0_cti_o; + input [1:0] wbm0_bte_o; + output [wb_dat_width-1:0] wbm0_dat_i; + output wbm0_ack_i; + output wbm0_err_i; + output wbm0_rty_i; + + + input [wb_adr_width-1:0] wbm1_adr_o; + input [wb_dat_width-1:0] wbm1_dat_o; + input [3:0] wbm1_sel_o; + input wbm1_we_o; + input wbm1_cyc_o; + input wbm1_stb_o; + input [2:0] wbm1_cti_o; + input [1:0] wbm1_bte_o; + output [wb_dat_width-1:0] wbm1_dat_i; + output wbm1_ack_i; + output wbm1_err_i; + output wbm1_rty_i; + + + // Slave one + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs0_adr_i; + output [wb_dat_width-1:0] wbs0_dat_i; + output [3:0] wbs0_sel_i; + output wbs0_we_i; + output wbs0_cyc_i; + output wbs0_stb_i; + output [2:0] wbs0_cti_i; + output [1:0] wbs0_bte_i; + input [wb_dat_width-1:0] wbs0_dat_o; + input wbs0_ack_o; + input wbs0_err_o; + input wbs0_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs1_adr_i; + output [wb_dat_width-1:0] wbs1_dat_i; + output [3:0] wbs1_sel_i; + output wbs1_we_i; + output wbs1_cyc_i; + output wbs1_stb_i; + output [2:0] wbs1_cti_i; + output [1:0] wbs1_bte_i; + input [wb_dat_width-1:0] wbs1_dat_o; + input wbs1_ack_o; + input wbs1_err_o; + input wbs1_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs2_adr_i; + output [wb_dat_width-1:0] wbs2_dat_i; + output [3:0] wbs2_sel_i; + output wbs2_we_i; + output wbs2_cyc_i; + output wbs2_stb_i; + output [2:0] wbs2_cti_i; + output [1:0] wbs2_bte_i; + input [wb_dat_width-1:0] wbs2_dat_o; + input wbs2_ack_o; + input wbs2_err_o; + input wbs2_rty_o; +/* + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs3_adr_i; + output [wb_dat_width-1:0] wbs3_dat_i; + output [3:0] wbs3_sel_i; + output wbs3_we_i; + output wbs3_cyc_i; + output wbs3_stb_i; + output [2:0] wbs3_cti_i; + output [1:0] wbs3_bte_i; + input [wb_dat_width-1:0] wbs3_dat_o; + input wbs3_ack_o; + input wbs3_err_o; + input wbs3_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs4_adr_i; + output [wb_dat_width-1:0] wbs4_dat_i; + output [3:0] wbs4_sel_i; + output wbs4_we_i; + output wbs4_cyc_i; + output wbs4_stb_i; + output [2:0] wbs4_cti_i; + output [1:0] wbs4_bte_i; + input [wb_dat_width-1:0] wbs4_dat_o; + input wbs4_ack_o; + input wbs4_err_o; + input wbs4_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs5_adr_i; + output [wb_dat_width-1:0] wbs5_dat_i; + output [3:0] wbs5_sel_i; + output wbs5_we_i; + output wbs5_cyc_i; + output wbs5_stb_i; + output [2:0] wbs5_cti_i; + output [1:0] wbs5_bte_i; + input [wb_dat_width-1:0] wbs5_dat_o; + input wbs5_ack_o; + input wbs5_err_o; + input wbs5_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs6_adr_i; + output [wb_dat_width-1:0] wbs6_dat_i; + output [3:0] wbs6_sel_i; + output wbs6_we_i; + output wbs6_cyc_i; + output wbs6_stb_i; + output [2:0] wbs6_cti_i; + output [1:0] wbs6_bte_i; + input [wb_dat_width-1:0] wbs6_dat_o; + input wbs6_ack_o; + input wbs6_err_o; + input wbs6_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs7_adr_i; + output [wb_dat_width-1:0] wbs7_dat_i; + output [3:0] wbs7_sel_i; + output wbs7_we_i; + output wbs7_cyc_i; + output wbs7_stb_i; + output [2:0] wbs7_cti_i; + output [1:0] wbs7_bte_i; + input [wb_dat_width-1:0] wbs7_dat_o; + input wbs7_ack_o; + input wbs7_err_o; + input wbs7_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs8_adr_i; + output [wb_dat_width-1:0] wbs8_dat_i; + output [3:0] wbs8_sel_i; + output wbs8_we_i; + output wbs8_cyc_i; + output wbs8_stb_i; + output [2:0] wbs8_cti_i; + output [1:0] wbs8_bte_i; + input [wb_dat_width-1:0] wbs8_dat_o; + input wbs8_ack_o; + input wbs8_err_o; + input wbs8_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs9_adr_i; + output [wb_dat_width-1:0] wbs9_dat_i; + output [3:0] wbs9_sel_i; + output wbs9_we_i; + output wbs9_cyc_i; + output wbs9_stb_i; + output [2:0] wbs9_cti_i; + output [1:0] wbs9_bte_i; + input [wb_dat_width-1:0] wbs9_dat_o; + input wbs9_ack_o; + input wbs9_err_o; + input wbs9_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs10_adr_i; + output [wb_dat_width-1:0] wbs10_dat_i; + output [3:0] wbs10_sel_i; + output wbs10_we_i; + output wbs10_cyc_i; + output wbs10_stb_i; + output [2:0] wbs10_cti_i; + output [1:0] wbs10_bte_i; + input [wb_dat_width-1:0] wbs10_dat_o; + input wbs10_ack_o; + input wbs10_err_o; + input wbs10_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs11_adr_i; + output [wb_dat_width-1:0] wbs11_dat_i; + output [3:0] wbs11_sel_i; + output wbs11_we_i; + output wbs11_cyc_i; + output wbs11_stb_i; + output [2:0] wbs11_cti_i; + output [1:0] wbs11_bte_i; + input [wb_dat_width-1:0] wbs11_dat_o; + input wbs11_ack_o; + input wbs11_err_o; + input wbs11_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs12_adr_i; + output [wb_dat_width-1:0] wbs12_dat_i; + output [3:0] wbs12_sel_i; + output wbs12_we_i; + output wbs12_cyc_i; + output wbs12_stb_i; + output [2:0] wbs12_cti_i; + output [1:0] wbs12_bte_i; + input [wb_dat_width-1:0] wbs12_dat_o; + input wbs12_ack_o; + input wbs12_err_o; + input wbs12_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs13_adr_i; + output [wb_dat_width-1:0] wbs13_dat_i; + output [3:0] wbs13_sel_i; + output wbs13_we_i; + output wbs13_cyc_i; + output wbs13_stb_i; + output [2:0] wbs13_cti_i; + output [1:0] wbs13_bte_i; + input [wb_dat_width-1:0] wbs13_dat_o; + input wbs13_ack_o; + input wbs13_err_o; + input wbs13_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs14_adr_i; + output [wb_dat_width-1:0] wbs14_dat_i; + output [3:0] wbs14_sel_i; + output wbs14_we_i; + output wbs14_cyc_i; + output wbs14_stb_i; + output [2:0] wbs14_cti_i; + output [1:0] wbs14_bte_i; + input [wb_dat_width-1:0] wbs14_dat_o; + input wbs14_ack_o; + input wbs14_err_o; + input wbs14_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs15_adr_i; + output [wb_dat_width-1:0] wbs15_dat_i; + output [3:0] wbs15_sel_i; + output wbs15_we_i; + output wbs15_cyc_i; + output wbs15_stb_i; + output [2:0] wbs15_cti_i; + output [1:0] wbs15_bte_i; + input [wb_dat_width-1:0] wbs15_dat_o; + input wbs15_ack_o; + input wbs15_err_o; + input wbs15_rty_o; + + + // Wishbone Slave interface + output [wb_adr_width-1:0] wbs16_adr_i; + output [wb_dat_width-1:0] wbs16_dat_i; + output [3:0] wbs16_sel_i; + output wbs16_we_i; + output wbs16_cyc_i; + output wbs16_stb_i; + output [2:0] wbs16_cti_i; + output [1:0] wbs16_bte_i; + input [wb_dat_width-1:0] wbs16_dat_o; + input wbs16_ack_o; + input wbs16_err_o; + input wbs16_rty_o; + +*/ + + reg watchdog_err; + +`ifdef ARBITER_DBUS_REGISTERING + + + // Registering setup: + // Masters typically register their outputs, so do the master selection and + // muxing before registering in the arbiter. Keep the common parts outside + // for code brevity. + + // Master ins -> |MUX> -> these wires + wire [wb_adr_width-1:0] wbm_adr_o_w; + wire [wb_dat_width-1:0] wbm_dat_o_w; + wire [3:0] wbm_sel_o_w; + wire wbm_we_o_w; + wire wbm_cyc_o_w; + wire wbm_stb_o_w; + wire [2:0] wbm_cti_o_w; + wire [1:0] wbm_bte_o_w; + // Slave ins -> |MUX> -> these wires + wire [wb_dat_width-1:0] wbm_dat_i; + wire wbm_ack_i; + wire wbm_err_i; + wire wbm_rty_i; + + // Registers after masters input mux + reg [wb_adr_width-1:0] wbm_adr_o_r; + reg [wb_dat_width-1:0] wbm_dat_o_r; + reg [3:0] wbm_sel_o_r; + reg wbm_we_o_r; + reg wbm_cyc_o_r; + reg wbm_stb_o_r; + reg [2:0] wbm_cti_o_r; + reg [1:0] wbm_bte_o_r; + + // Master input mux register wires + wire [wb_adr_width-1:0] wbm_adr_o; + wire [wb_dat_width-1:0] wbm_dat_o; + wire [3:0] wbm_sel_o; + wire wbm_we_o; + wire wbm_cyc_o; + wire wbm_stb_o; + wire [2:0] wbm_cti_o; + wire [1:0] wbm_bte_o; + + // Registers after slaves input mux + reg [wb_dat_width-1:0] wbm_dat_i_r; + reg wbm_ack_i_r; + reg wbm_err_i_r; + reg wbm_rty_i_r; + + // Master select (MUX controls) + wire [1:0] master_sel; + // priority to wbm1, the debug master + assign master_sel[0] = wbm0_cyc_o & !wbm1_cyc_o; + assign master_sel[1] = wbm1_cyc_o; + + + // Master input mux, priority to debug master + assign wbm_adr_o_w = master_sel[1] ? wbm1_adr_o : + wbm0_adr_o; + + assign wbm_dat_o_w = master_sel[1] ? wbm1_dat_o : + wbm0_dat_o; + + assign wbm_sel_o_w = master_sel[1] ? wbm1_sel_o : + wbm0_sel_o; + + assign wbm_we_o_w = master_sel[1] ? wbm1_we_o : + wbm0_we_o; + + assign wbm_cyc_o_w = master_sel[1] ? wbm1_cyc_o : + wbm0_cyc_o; + + assign wbm_stb_o_w = master_sel[1] ? wbm1_stb_o : + wbm0_stb_o; + + assign wbm_cti_o_w = master_sel[1] ? wbm1_cti_o : + wbm0_cti_o; + + assign wbm_bte_o_w = master_sel[1] ? wbm1_bte_o : + wbm0_bte_o; + + + // Register muxed master signals + always @(posedge wb_clk) + begin + wbm_adr_o_r <= wbm_adr_o_w; + wbm_dat_o_r <= wbm_dat_o_w; + wbm_sel_o_r <= wbm_sel_o_w; + wbm_we_o_r <= wbm_we_o_w; + wbm_cyc_o_r <= wbm_cyc_o_w; + wbm_stb_o_r <= wbm_stb_o_w & !wbm_ack_i & !wbm_ack_i_r; + wbm_cti_o_r <= wbm_cti_o_w; + wbm_bte_o_r <= wbm_bte_o_w; + + wbm_dat_i_r <= wbm_dat_i; + wbm_ack_i_r <= wbm_ack_i; + wbm_err_i_r <= wbm_err_i; + wbm_rty_i_r <= wbm_rty_i; + end // always @ (posedge wb_clk) + + + assign wbm_adr_o = wbm_adr_o_r; + assign wbm_dat_o = wbm_dat_o_r; + assign wbm_sel_o = wbm_sel_o_r; + assign wbm_we_o = wbm_we_o_r; + assign wbm_cyc_o = wbm_cyc_o_r; + assign wbm_stb_o = wbm_stb_o_r; + assign wbm_cti_o = wbm_cti_o_r; + assign wbm_bte_o = wbm_bte_o_r; + + // Master input mux, priority to debug master + assign wbm0_dat_i = wbm_dat_i_r; + assign wbm0_ack_i = wbm_ack_i_r & master_sel[0]; + assign wbm0_err_i = wbm_err_i_r & master_sel[0]; + assign wbm0_rty_i = wbm_rty_i_r & master_sel[0]; + + assign wbm1_dat_i = wbm_dat_i_r; + assign wbm1_ack_i = wbm_ack_i_r & master_sel[1]; + assign wbm1_err_i = wbm_err_i_r & master_sel[1]; + assign wbm1_rty_i = wbm_rty_i_r & master_sel[1]; + +`else // !`ifdef ARBITER_DBUS_REGISTERING + + // Master input mux output wires + wire [wb_adr_width-1:0] wbm_adr_o; + wire [wb_dat_width-1:0] wbm_dat_o; + wire [3:0] wbm_sel_o; + wire wbm_we_o; + wire wbm_cyc_o; + wire wbm_stb_o; + wire [2:0] wbm_cti_o; + wire [1:0] wbm_bte_o; + + // Master select + wire [1:0] master_sel; + // priority to wbm1, the debug master + assign master_sel[0] = wbm0_cyc_o & !wbm1_cyc_o; + assign master_sel[1] = wbm1_cyc_o; + + + // Master input mux, priority to debug master + assign wbm_adr_o = master_sel[1] ? wbm1_adr_o : + wbm0_adr_o; + + assign wbm_dat_o = master_sel[1] ? wbm1_dat_o : + wbm0_dat_o; + + assign wbm_sel_o = master_sel[1] ? wbm1_sel_o : + wbm0_sel_o; + + assign wbm_we_o = master_sel[1] ? wbm1_we_o : + wbm0_we_o; + + assign wbm_cyc_o = master_sel[1] ? wbm1_cyc_o : + wbm0_cyc_o; + + assign wbm_stb_o = master_sel[1] ? wbm1_stb_o : + wbm0_stb_o; + + assign wbm_cti_o = master_sel[1] ? wbm1_cti_o : + wbm0_cti_o; + + assign wbm_bte_o = master_sel[1] ? wbm1_bte_o : + wbm0_bte_o; + + + wire [wb_dat_width-1:0] wbm_dat_i; + wire wbm_ack_i; + wire wbm_err_i; + wire wbm_rty_i; + + + assign wbm0_dat_i = wbm_dat_i; + assign wbm0_ack_i = wbm_ack_i & master_sel[0]; + assign wbm0_err_i = wbm_err_i & master_sel[0]; + assign wbm0_rty_i = wbm_rty_i & master_sel[0]; + + assign wbm1_dat_i = wbm_dat_i; + assign wbm1_ack_i = wbm_ack_i & master_sel[1]; + assign wbm1_err_i = wbm_err_i & master_sel[1]; + assign wbm1_rty_i = wbm_rty_i & master_sel[1]; + + + +`endif // !`ifdef ARBITER_DBUS_REGISTERING + + + // Slave select wire + wire [wb_num_slaves-1:0] wb_slave_sel; + reg [wb_num_slaves-1:0] wb_slave_sel_r; + + // Register wb_slave_sel_r to break combinatorial loop when selecting default + // slave + always @(posedge wb_clk) + wb_slave_sel_r <= wb_slave_sel; + + // Slave out mux in wires + wire [wb_dat_width-1:0] wbs_dat_o_mux_i [0:wb_num_slaves-1]; + wire wbs_ack_o_mux_i [0:wb_num_slaves-1]; + wire wbs_err_o_mux_i [0:wb_num_slaves-1]; + wire wbs_rty_o_mux_i [0:wb_num_slaves-1]; + + // + // Slave selects + // + assign wb_slave_sel[0] = wbm_adr_o[31:28] == slave0_adr | wbm_adr_o[31:28] == 4'hf; // Special case, point all reads to ROM address to here + assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr; + + // Auto select last slave when others are not selected + assign wb_slave_sel[2] = !(wb_slave_sel_r[0] | wb_slave_sel_r[1]); + +/* + assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr; + assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr; + assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr; + assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr; + assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr; + assign wb_slave_sel[7] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave7_adr; + assign wb_slave_sel[8] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave8_adr; + assign wb_slave_sel[9] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave9_adr; + assign wb_slave_sel[10] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave10_adr; + assign wb_slave_sel[11] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave11_adr; + assign wb_slave_sel[12] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave12_adr; + assign wb_slave_sel[13] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave13_adr; + assign wb_slave_sel[14] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave14_adr; + assign wb_slave_sel[15] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave15_adr; + assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave16_adr; +*/ + +`ifdef ARBITER_DBUS_WATCHDOG + reg [`ARBITER_DBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer; + reg wbm_stb_r; // Register strobe + wire wbm_stb_edge; // Detect its edge + + always @(posedge wb_clk) + wbm_stb_r <= wbm_stb_o; + + assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r); + + // Counter logic + always @(posedge wb_clk) + if (wb_rst) watchdog_timer <= 0; + else if (wbm_ack_i) // When we see an ack, turn off timer + watchdog_timer <= 0; + else if (wbm_stb_edge) // New access means start timer again + watchdog_timer <= 1; + else if (|watchdog_timer) // Continue counting if counter > 0 + watchdog_timer <= watchdog_timer + 1; + + always @(posedge wb_clk) + watchdog_err <= (&watchdog_timer); + + +`else // !`ifdef ARBITER_DBUS_WATCHDOG + + always @(posedge wb_clk) + watchdog_err <= 0; + +`endif // !`ifdef ARBITER_DBUS_WATCHDOG + + + + // Slave 0 inputs + assign wbs0_adr_i = wbm_adr_o; + assign wbs0_dat_i = wbm_dat_o; + assign wbs0_sel_i = wbm_sel_o; + assign wbs0_cyc_i = wbm_cyc_o & wb_slave_sel_r[0]; + assign wbs0_stb_i = wbm_stb_o & wb_slave_sel_r[0]; + assign wbs0_we_i = wbm_we_o; + assign wbs0_cti_i = wbm_cti_o; + assign wbs0_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[0] = wbs0_dat_o; + assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel_r[0]; + assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel_r[0]; + assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel_r[0]; + + + // Slave 1 inputs + assign wbs1_adr_i = wbm_adr_o; + assign wbs1_dat_i = wbm_dat_o; + assign wbs1_sel_i = wbm_sel_o; + assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel_r[1]; + assign wbs1_stb_i = wbm_stb_o & wb_slave_sel_r[1]; + assign wbs1_we_i = wbm_we_o; + assign wbs1_cti_i = wbm_cti_o; + assign wbs1_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[1] = wbs1_dat_o; + assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel_r[1]; + assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel_r[1]; + assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel_r[1]; + + + // Slave 2 inputs + assign wbs2_adr_i = wbm_adr_o; + assign wbs2_dat_i = wbm_dat_o; + assign wbs2_sel_i = wbm_sel_o; + assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel_r[2]; + assign wbs2_stb_i = wbm_stb_o & wb_slave_sel_r[2]; + assign wbs2_we_i = wbm_we_o; + assign wbs2_cti_i = wbm_cti_o; + assign wbs2_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[2] = wbs2_dat_o; + assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel_r[2]; + assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel_r[2]; + assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel_r[2]; +/* + + // Slave 3 inputs + assign wbs3_adr_i = wbm_adr_o; + assign wbs3_dat_i = wbm_dat_o; + assign wbs3_sel_i = wbm_sel_o; + assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel_r[3]; + assign wbs3_stb_i = wbm_stb_o & wb_slave_sel_r[3]; + assign wbs3_we_i = wbm_we_o; + assign wbs3_cti_i = wbm_cti_o; + assign wbs3_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[3] = wbs3_dat_o; + assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel_r[3]; + assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel_r[3]; + assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel_r[3]; + + // Slave 4 inputs + assign wbs4_adr_i = wbm_adr_o; + assign wbs4_dat_i = wbm_dat_o; + assign wbs4_sel_i = wbm_sel_o; + assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel_r[4]; + assign wbs4_stb_i = wbm_stb_o & wb_slave_sel_r[4]; + assign wbs4_we_i = wbm_we_o; + assign wbs4_cti_i = wbm_cti_o; + assign wbs4_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[4] = wbs4_dat_o; + assign wbs_ack_o_mux_i[4] = wbs4_ack_o & wb_slave_sel_r[4]; + assign wbs_err_o_mux_i[4] = wbs4_err_o & wb_slave_sel_r[4]; + assign wbs_rty_o_mux_i[4] = wbs4_rty_o & wb_slave_sel_r[4]; + + + // Slave 5 inputs + assign wbs5_adr_i = wbm_adr_o; + assign wbs5_dat_i = wbm_dat_o; + assign wbs5_sel_i = wbm_sel_o; + assign wbs5_cyc_i = wbm_cyc_o & wb_slave_sel_r[5]; + assign wbs5_stb_i = wbm_stb_o & wb_slave_sel_r[5]; + assign wbs5_we_i = wbm_we_o; + assign wbs5_cti_i = wbm_cti_o; + assign wbs5_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[5] = wbs5_dat_o; + assign wbs_ack_o_mux_i[5] = wbs5_ack_o & wb_slave_sel_r[5]; + assign wbs_err_o_mux_i[5] = wbs5_err_o & wb_slave_sel_r[5]; + assign wbs_rty_o_mux_i[5] = wbs5_rty_o & wb_slave_sel_r[5]; + + + // Slave 6 inputs + assign wbs6_adr_i = wbm_adr_o; + assign wbs6_dat_i = wbm_dat_o; + assign wbs6_sel_i = wbm_sel_o; + assign wbs6_cyc_i = wbm_cyc_o & wb_slave_sel_r[6]; + assign wbs6_stb_i = wbm_stb_o & wb_slave_sel_r[6]; + assign wbs6_we_i = wbm_we_o; + assign wbs6_cti_i = wbm_cti_o; + assign wbs6_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[6] = wbs6_dat_o; + assign wbs_ack_o_mux_i[6] = wbs6_ack_o & wb_slave_sel_r[6]; + assign wbs_err_o_mux_i[6] = wbs6_err_o & wb_slave_sel_r[6]; + assign wbs_rty_o_mux_i[6] = wbs6_rty_o & wb_slave_sel_r[6]; + + + // Slave 7 inputs + assign wbs7_adr_i = wbm_adr_o; + assign wbs7_dat_i = wbm_dat_o; + assign wbs7_sel_i = wbm_sel_o; + assign wbs7_cyc_i = wbm_cyc_o & wb_slave_sel_r[7]; + assign wbs7_stb_i = wbm_stb_o & wb_slave_sel_r[7]; + assign wbs7_we_i = wbm_we_o; + assign wbs7_cti_i = wbm_cti_o; + assign wbs7_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[7] = wbs7_dat_o; + assign wbs_ack_o_mux_i[7] = wbs7_ack_o & wb_slave_sel_r[7]; + assign wbs_err_o_mux_i[7] = wbs7_err_o & wb_slave_sel_r[7]; + assign wbs_rty_o_mux_i[7] = wbs7_rty_o & wb_slave_sel_r[7]; + + + // Slave 8 inputs + assign wbs8_adr_i = wbm_adr_o; + assign wbs8_dat_i = wbm_dat_o; + assign wbs8_sel_i = wbm_sel_o; + assign wbs8_cyc_i = wbm_cyc_o & wb_slave_sel_r[8]; + assign wbs8_stb_i = wbm_stb_o & wb_slave_sel_r[8]; + assign wbs8_we_i = wbm_we_o; + assign wbs8_cti_i = wbm_cti_o; + assign wbs8_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[8] = wbs8_dat_o; + assign wbs_ack_o_mux_i[8] = wbs8_ack_o & wb_slave_sel_r[8]; + assign wbs_err_o_mux_i[8] = wbs8_err_o & wb_slave_sel_r[8]; + assign wbs_rty_o_mux_i[8] = wbs8_rty_o & wb_slave_sel_r[8]; + + + // Slave 9 inputs + assign wbs9_adr_i = wbm_adr_o; + assign wbs9_dat_i = wbm_dat_o; + assign wbs9_sel_i = wbm_sel_o; + assign wbs9_cyc_i = wbm_cyc_o & wb_slave_sel_r[9]; + assign wbs9_stb_i = wbm_stb_o & wb_slave_sel_r[9]; + assign wbs9_we_i = wbm_we_o; + assign wbs9_cti_i = wbm_cti_o; + assign wbs9_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[9] = wbs9_dat_o; + assign wbs_ack_o_mux_i[9] = wbs9_ack_o & wb_slave_sel_r[9]; + assign wbs_err_o_mux_i[9] = wbs9_err_o & wb_slave_sel_r[9]; + assign wbs_rty_o_mux_i[9] = wbs9_rty_o & wb_slave_sel_r[9]; + + + // Slave 10 inputs + assign wbs10_adr_i = wbm_adr_o; + assign wbs10_dat_i = wbm_dat_o; + assign wbs10_sel_i = wbm_sel_o; + assign wbs10_cyc_i = wbm_cyc_o & wb_slave_sel_r[10]; + assign wbs10_stb_i = wbm_stb_o & wb_slave_sel_r[10]; + assign wbs10_we_i = wbm_we_o; + assign wbs10_cti_i = wbm_cti_o; + assign wbs10_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[10] = wbs10_dat_o; + assign wbs_ack_o_mux_i[10] = wbs10_ack_o & wb_slave_sel_r[10]; + assign wbs_err_o_mux_i[10] = wbs10_err_o & wb_slave_sel_r[10]; + assign wbs_rty_o_mux_i[10] = wbs10_rty_o & wb_slave_sel_r[10]; + + + // Slave 11 inputs + assign wbs11_adr_i = wbm_adr_o; + assign wbs11_dat_i = wbm_dat_o; + assign wbs11_sel_i = wbm_sel_o; + assign wbs11_cyc_i = wbm_cyc_o & wb_slave_sel_r[11]; + assign wbs11_stb_i = wbm_stb_o & wb_slave_sel_r[11]; + assign wbs11_we_i = wbm_we_o; + assign wbs11_cti_i = wbm_cti_o; + assign wbs11_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[11] = wbs11_dat_o; + assign wbs_ack_o_mux_i[11] = wbs11_ack_o & wb_slave_sel_r[11]; + assign wbs_err_o_mux_i[11] = wbs11_err_o & wb_slave_sel_r[11]; + assign wbs_rty_o_mux_i[11] = wbs11_rty_o & wb_slave_sel_r[11]; + + + // Slave 12 inputs + assign wbs12_adr_i = wbm_adr_o; + assign wbs12_dat_i = wbm_dat_o; + assign wbs12_sel_i = wbm_sel_o; + assign wbs12_cyc_i = wbm_cyc_o & wb_slave_sel_r[12]; + assign wbs12_stb_i = wbm_stb_o & wb_slave_sel_r[12]; + assign wbs12_we_i = wbm_we_o; + assign wbs12_cti_i = wbm_cti_o; + assign wbs12_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[12] = wbs12_dat_o; + assign wbs_ack_o_mux_i[12] = wbs12_ack_o & wb_slave_sel_r[12]; + assign wbs_err_o_mux_i[12] = wbs12_err_o & wb_slave_sel_r[12]; + assign wbs_rty_o_mux_i[12] = wbs12_rty_o & wb_slave_sel_r[12]; + + + // Slave 13 inputs + assign wbs13_adr_i = wbm_adr_o; + assign wbs13_dat_i = wbm_dat_o; + assign wbs13_sel_i = wbm_sel_o; + assign wbs13_cyc_i = wbm_cyc_o & wb_slave_sel_r[13]; + assign wbs13_stb_i = wbm_stb_o & wb_slave_sel_r[13]; + assign wbs13_we_i = wbm_we_o; + assign wbs13_cti_i = wbm_cti_o; + assign wbs13_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[13] = wbs13_dat_o; + assign wbs_ack_o_mux_i[13] = wbs13_ack_o & wb_slave_sel_r[13]; + assign wbs_err_o_mux_i[13] = wbs13_err_o & wb_slave_sel_r[13]; + assign wbs_rty_o_mux_i[13] = wbs13_rty_o & wb_slave_sel_r[13]; + + + // Slave 14 inputs + assign wbs14_adr_i = wbm_adr_o; + assign wbs14_dat_i = wbm_dat_o; + assign wbs14_sel_i = wbm_sel_o; + assign wbs14_cyc_i = wbm_cyc_o & wb_slave_sel_r[14]; + assign wbs14_stb_i = wbm_stb_o & wb_slave_sel_r[14]; + assign wbs14_we_i = wbm_we_o; + assign wbs14_cti_i = wbm_cti_o; + assign wbs14_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[14] = wbs14_dat_o; + assign wbs_ack_o_mux_i[14] = wbs14_ack_o & wb_slave_sel_r[14]; + assign wbs_err_o_mux_i[14] = wbs14_err_o & wb_slave_sel_r[14]; + assign wbs_rty_o_mux_i[14] = wbs14_rty_o & wb_slave_sel_r[14]; + + + // Slave 15 inputs + assign wbs15_adr_i = wbm_adr_o; + assign wbs15_dat_i = wbm_dat_o; + assign wbs15_sel_i = wbm_sel_o; + assign wbs15_cyc_i = wbm_cyc_o & wb_slave_sel_r[15]; + assign wbs15_stb_i = wbm_stb_o & wb_slave_sel_r[15]; + assign wbs15_we_i = wbm_we_o; + assign wbs15_cti_i = wbm_cti_o; + assign wbs15_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[15] = wbs15_dat_o; + assign wbs_ack_o_mux_i[15] = wbs15_ack_o & wb_slave_sel_r[15]; + assign wbs_err_o_mux_i[15] = wbs15_err_o & wb_slave_sel_r[15]; + assign wbs_rty_o_mux_i[15] = wbs15_rty_o & wb_slave_sel_r[15]; + + + // Slave 16 inputs + assign wbs16_adr_i = wbm_adr_o; + assign wbs16_dat_i = wbm_dat_o; + assign wbs16_sel_i = wbm_sel_o; + assign wbs16_cyc_i = wbm_cyc_o & wb_slave_sel_r[16]; + assign wbs16_stb_i = wbm_stb_o & wb_slave_sel_r[16]; + assign wbs16_we_i = wbm_we_o; + assign wbs16_cti_i = wbm_cti_o; + assign wbs16_bte_i = wbm_bte_o; + assign wbs_dat_o_mux_i[16] = wbs16_dat_o; + assign wbs_ack_o_mux_i[16] = wbs16_ack_o & wb_slave_sel_r[16]; + assign wbs_err_o_mux_i[16] = wbs16_err_o & wb_slave_sel_r[16]; + assign wbs_rty_o_mux_i[16] = wbs16_rty_o & wb_slave_sel_r[16]; + +*/ + + + + // Master out mux from slave in data + assign wbm_dat_i = wb_slave_sel_r[0] ? wbs_dat_o_mux_i[0] : + wb_slave_sel_r[1] ? wbs_dat_o_mux_i[1] : + wb_slave_sel_r[2] ? wbs_dat_o_mux_i[2] : +/* wb_slave_sel_r[3] ? wbs_dat_o_mux_i[3] : + wb_slave_sel_r[4] ? wbs_dat_o_mux_i[4] : + wb_slave_sel_r[5] ? wbs_dat_o_mux_i[5] : + wb_slave_sel_r[6] ? wbs_dat_o_mux_i[6] : + wb_slave_sel_r[7] ? wbs_dat_o_mux_i[7] : + wb_slave_sel_r[8] ? wbs_dat_o_mux_i[8] : + wb_slave_sel_r[9] ? wbs_dat_o_mux_i[9] : + wb_slave_sel_r[10] ? wbs_dat_o_mux_i[10] : + wb_slave_sel_r[11] ? wbs_dat_o_mux_i[11] : + wb_slave_sel_r[12] ? wbs_dat_o_mux_i[12] : + wb_slave_sel_r[13] ? wbs_dat_o_mux_i[13] : + wb_slave_sel_r[14] ? wbs_dat_o_mux_i[14] : + wb_slave_sel_r[15] ? wbs_dat_o_mux_i[15] : + wb_slave_sel_r[16] ? wbs_dat_o_mux_i[16] : +*/ + wbs_dat_o_mux_i[0]; + + // Master out acks, or together + assign wbm_ack_i = wbs_ack_o_mux_i[0] | + wbs_ack_o_mux_i[1] | + wbs_ack_o_mux_i[2] /*| + wbs_ack_o_mux_i[3] | + wbs_ack_o_mux_i[4] | + wbs_ack_o_mux_i[5] | + wbs_ack_o_mux_i[6] | + wbs_ack_o_mux_i[7] | + wbs_ack_o_mux_i[8] | + wbs_ack_o_mux_i[9] | + wbs_ack_o_mux_i[10] | + wbs_ack_o_mux_i[11] | + wbs_ack_o_mux_i[12] | + wbs_ack_o_mux_i[13] | + wbs_ack_o_mux_i[14] | + wbs_ack_o_mux_i[15] | + wbs_ack_o_mux_i[16] */ + ; + + + assign wbm_err_i = wbs_err_o_mux_i[0] | + wbs_err_o_mux_i[1] | + wbs_err_o_mux_i[2] |/* + wbs_err_o_mux_i[3] | + wbs_err_o_mux_i[4] | + wbs_err_o_mux_i[5] | + wbs_err_o_mux_i[6] | + wbs_err_o_mux_i[7] | + wbs_err_o_mux_i[8] | + wbs_err_o_mux_i[9] | + wbs_err_o_mux_i[10] | + wbs_err_o_mux_i[11] | + wbs_err_o_mux_i[12] | + wbs_err_o_mux_i[13] | + wbs_err_o_mux_i[14] | + wbs_err_o_mux_i[15] | + wbs_err_o_mux_i[16] |*/ + watchdog_err ; + + + assign wbm_rty_i = wbs_rty_o_mux_i[0] | + wbs_rty_o_mux_i[1] | + wbs_rty_o_mux_i[2] /*| + wbs_rty_o_mux_i[3] | + wbs_rty_o_mux_i[4] | + wbs_rty_o_mux_i[5] | + wbs_rty_o_mux_i[6] | + wbs_rty_o_mux_i[7] | + wbs_rty_o_mux_i[8] | + wbs_rty_o_mux_i[9] | + wbs_rty_o_mux_i[10] | + wbs_rty_o_mux_i[11] | + wbs_rty_o_mux_i[12] | + wbs_rty_o_mux_i[13] | + wbs_rty_o_mux_i[14] | + wbs_rty_o_mux_i[15] | + wbs_rty_o_mux_i[16]*/; + +endmodule // arbiter_dbus + Index: xilinx/atlys/rtl/verilog/arbiter/arbiter_ibus.v =================================================================== --- xilinx/atlys/rtl/verilog/arbiter/arbiter_ibus.v (nonexistent) +++ xilinx/atlys/rtl/verilog/arbiter/arbiter_ibus.v (revision 627) @@ -0,0 +1,337 @@ +////////////////////////////////////////////////////////////////////// +/// //// +/// Wishbone arbiter, burst-compatible //// +/// //// +/// Simple arbiter, single master, dual slave, primarily for //// +/// processor instruction bus, providing access to one main //// +/// memory server and one ROM //// +/// //// +/// Julius Baxter, julius@opencores.org //// +/// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +`include "orpsoc-defines.v" +// One master, 2 slaves. +module arbiter_ibus + ( + // instruction bus in + // Wishbone Master interface + wbm_adr_o, + wbm_dat_o, + wbm_sel_o, + wbm_we_o, + wbm_cyc_o, + wbm_stb_o, + wbm_cti_o, + wbm_bte_o, + + wbm_dat_i, + wbm_ack_i, + wbm_err_i, + wbm_rty_i, + + + // Slave one + // Wishbone Slave interface + wbs0_adr_i, + wbs0_dat_i, + wbs0_sel_i, + wbs0_we_i, + wbs0_cyc_i, + wbs0_stb_i, + wbs0_cti_i, + wbs0_bte_i, + + wbs0_dat_o, + wbs0_ack_o, + wbs0_err_o, + wbs0_rty_o, + + // Slave two + // Wishbone Slave interface + wbs1_adr_i, + wbs1_dat_i, + wbs1_sel_i, + wbs1_we_i, + wbs1_cyc_i, + wbs1_stb_i, + wbs1_cti_i, + wbs1_bte_i, + + wbs1_dat_o, + wbs1_ack_o, + wbs1_err_o, + wbs1_rty_o, + + wb_clk, + wb_rst + ); + + + parameter wb_dat_width = 32; + parameter wb_adr_width = 32; + + parameter wb_addr_match_width = 8; + + parameter slave0_adr = 8'hf0; // FLASH ROM + parameter slave1_adr = 8'h00; // Main memory (SDRAM/FPGA SRAM) + +`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width + + input wb_clk; + input wb_rst; + + + // WB Master + input [wb_adr_width-1:0] wbm_adr_o; + input [wb_dat_width-1:0] wbm_dat_o; + input [3:0] wbm_sel_o; + input wbm_we_o; + input wbm_cyc_o; + input wbm_stb_o; + input [2:0] wbm_cti_o; + input [1:0] wbm_bte_o; + output [wb_dat_width-1:0] wbm_dat_i; + output wbm_ack_i; + output wbm_err_i; + output wbm_rty_i; + + // WB Slave 0 + output [wb_adr_width-1:0] wbs0_adr_i; + output [wb_dat_width-1:0] wbs0_dat_i; + output [3:0] wbs0_sel_i; + output wbs0_we_i; + output wbs0_cyc_i; + output wbs0_stb_i; + output [2:0] wbs0_cti_i; + output [1:0] wbs0_bte_i; + input [wb_dat_width-1:0] wbs0_dat_o; + input wbs0_ack_o; + input wbs0_err_o; + input wbs0_rty_o; + + // WB Slave 1 + output [wb_adr_width-1:0] wbs1_adr_i; + output [wb_dat_width-1:0] wbs1_dat_i; + output [3:0] wbs1_sel_i; + output wbs1_we_i; + output wbs1_cyc_i; + output wbs1_stb_i; + output [2:0] wbs1_cti_i; + output [1:0] wbs1_bte_i; + input [wb_dat_width-1:0] wbs1_dat_o; + input wbs1_ack_o; + input wbs1_err_o; + input wbs1_rty_o; + + wire [1:0] slave_sel; // One bit per slave + + reg watchdog_err; + +`ifdef ARBITER_IBUS_WATCHDOG + reg [`ARBITER_IBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer; + reg wbm_stb_r; // Register strobe + wire wbm_stb_edge; // Detect its edge + reg wbm_stb_edge_r, wbm_ack_i_r; // Reg these, better timing + + always @(posedge wb_clk) + wbm_stb_r <= wbm_stb_o; + + assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r); + + always @(posedge wb_clk) + wbm_stb_edge_r <= wbm_stb_edge; + + always @(posedge wb_clk) + wbm_ack_i_r <= wbm_ack_i; + + + // Counter logic + always @(posedge wb_clk) + if (wb_rst) watchdog_timer <= 0; + else if (wbm_ack_i_r) // When we see an ack, turn off timer + watchdog_timer <= 0; + else if (wbm_stb_edge_r) // New access means start timer again + watchdog_timer <= 1; + else if (|watchdog_timer) // Continue counting if counter > 0 + watchdog_timer <= watchdog_timer + 1; + + always @(posedge wb_clk) + watchdog_err <= (&watchdog_timer); + +`else // !`ifdef ARBITER_IBUS_WATCHDOG + + always @(posedge wb_clk) + watchdog_err <= 0; + +`endif // !`ifdef ARBITER_IBUS_WATCHDOG + + + +`ifdef ARBITER_IBUS_REGISTERING + + // Master input registers + reg [wb_adr_width-1:0] wbm_adr_o_r; + reg [wb_dat_width-1:0] wbm_dat_o_r; + reg [3:0] wbm_sel_o_r; + reg wbm_we_o_r; + reg wbm_cyc_o_r; + reg wbm_stb_o_r; + reg [2:0] wbm_cti_o_r; + reg [1:0] wbm_bte_o_r; + // Slave output registers + reg [wb_dat_width-1:0] wbs0_dat_o_r; + reg wbs0_ack_o_r; + reg wbs0_err_o_r; + reg wbs0_rty_o_r; + reg [wb_dat_width-1:0] wbs1_dat_o_r; + reg wbs1_ack_o_r; + reg wbs1_err_o_r; + reg wbs1_rty_o_r; + + wire wbm_ack_i_pre_reg; + + + + // Register master input signals + always @(posedge wb_clk) + begin + wbm_adr_o_r <= wbm_adr_o; + wbm_dat_o_r <= wbm_dat_o; + wbm_sel_o_r <= wbm_sel_o; + wbm_we_o_r <= wbm_we_o; + wbm_cyc_o_r <= wbm_cyc_o; + wbm_stb_o_r <= wbm_stb_o & !wbm_ack_i_pre_reg & !wbm_ack_i;//classic + wbm_cti_o_r <= wbm_cti_o; + wbm_bte_o_r <= wbm_bte_o; + + // Slave signals + wbs0_dat_o_r <= wbs0_dat_o; + wbs0_ack_o_r <= wbs0_ack_o; + wbs0_err_o_r <= wbs0_err_o; + wbs0_rty_o_r <= wbs0_rty_o; + wbs1_dat_o_r <= wbs1_dat_o; + wbs1_ack_o_r <= wbs1_ack_o; + wbs1_err_o_r <= wbs1_err_o; + wbs1_rty_o_r <= wbs1_rty_o; + + end // always @ (posedge wb_clk) + + // Slave select + assign slave_sel[0] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] == + slave0_adr; + + assign slave_sel[1] = wbm_adr_o_r[`WB_ARB_ADDR_MATCH_SEL] == + slave1_adr; + + // Slave out assigns + assign wbs0_adr_i = wbm_adr_o_r; + assign wbs0_dat_i = wbm_dat_o_r; + assign wbs0_we_i = wbm_dat_o_r; + assign wbs0_sel_i = wbm_sel_o_r; + assign wbs0_cti_i = wbm_cti_o_r; + assign wbs0_bte_i = wbm_bte_o_r; + assign wbs0_cyc_i = wbm_cyc_o_r & slave_sel[0]; + assign wbs0_stb_i = wbm_stb_o_r & slave_sel[0]; + + assign wbs1_adr_i = wbm_adr_o_r; + assign wbs1_dat_i = wbm_dat_o_r; + assign wbs1_we_i = wbm_dat_o_r; + assign wbs1_sel_i = wbm_sel_o_r; + assign wbs1_cti_i = wbm_cti_o_r; + assign wbs1_bte_i = wbm_bte_o_r; + assign wbs1_cyc_i = wbm_cyc_o_r & slave_sel[1]; + assign wbs1_stb_i = wbm_stb_o_r & slave_sel[1]; + + // Master out assigns + // Don't care about none selected... + assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o_r : + wbs0_dat_o_r ; + + assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o_r) | + (slave_sel[1] & wbs1_ack_o_r) + ; + + assign wbm_err_i = (slave_sel[0] & wbs0_err_o_r) | + (slave_sel[1] & wbs1_err_o_r) | + watchdog_err; + + assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o_r) | + (slave_sel[1] & wbs1_rty_o_r); + + // Non-registered ack + assign wbm_ack_i_pre_reg = (slave_sel[0] & wbs0_ack_o) | + (slave_sel[1] & wbs1_ack_o); + +`else // !`ifdef ARBITER_IBUS_REGISTERING + + // Slave select + assign slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == + slave0_adr; + + assign slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == + slave1_adr; + + // Slave out assigns + assign wbs0_adr_i = wbm_adr_o; + assign wbs0_dat_i = wbm_dat_o; + assign wbs0_we_i = wbm_we_o; + assign wbs0_sel_i = wbm_sel_o; + assign wbs0_cti_i = wbm_cti_o; + assign wbs0_bte_i = wbm_bte_o; + assign wbs0_cyc_i = wbm_cyc_o & slave_sel[0]; + assign wbs0_stb_i = wbm_stb_o & slave_sel[0]; + + assign wbs1_adr_i = wbm_adr_o; + assign wbs1_dat_i = wbm_dat_o; + assign wbs1_we_i = wbm_we_o; + assign wbs1_sel_i = wbm_sel_o; + assign wbs1_cti_i = wbm_cti_o; + assign wbs1_bte_i = wbm_bte_o; + assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1]; + assign wbs1_stb_i = wbm_stb_o & slave_sel[1]; + + // Master out assigns + // Don't care about none selected... + assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o : + wbs0_dat_o ; + + assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) | + (slave_sel[1] & wbs1_ack_o); + + + assign wbm_err_i = (slave_sel[0] & wbs0_err_o) | + (slave_sel[1] & wbs1_err_o) | + watchdog_err; + + assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) | + (slave_sel[1] & wbs1_rty_o); + + +`endif +endmodule // arbiter_ibus + Index: xilinx/atlys/rtl/verilog/gpio/gpio.v =================================================================== --- xilinx/atlys/rtl/verilog/gpio/gpio.v (nonexistent) +++ xilinx/atlys/rtl/verilog/gpio/gpio.v (revision 627) @@ -0,0 +1,159 @@ +/* + * + * Simple 24-bit wide GPIO module + * + * Can be made wider as needed, but must be done manually. + * + * First lot of bytes are the GPIO I/O regs + * Second lot are the direction registers + * + * Set direction bit to '1' to output corresponding data bit. + * + * Register mapping: + * + * For 8 GPIOs we would have + * adr 0: gpio data 7:0 + * adr 1: gpio data 15:8 + * adr 2: gpio data 23:16 + * adr 3: gpio dir 7:0 + * adr 4: gpio dir 15:8 + * adr 5: gpio dir 23:16 + * + * Backend pinout file needs to be updated for any GPIO width changes. + * + */ + +module gpio( + wb_clk, + wb_rst, + + wb_adr_i, + wb_dat_i, + wb_we_i, + wb_cyc_i, + wb_stb_i, + wb_cti_i, + wb_bte_i, + + wb_ack_o, + wb_dat_o, + wb_err_o, + wb_rty_o, + + gpio_io); + + + parameter gpio_io_width = 24; + + parameter gpio_dir_reset_val = 0; + parameter gpio_o_reset_val = 0; + + + parameter wb_dat_width = 8; + parameter wb_adr_width = 3; // 8 bytes addressable + + input wb_clk; + input wb_rst; + + input [wb_adr_width-1:0] wb_adr_i; + input [wb_dat_width-1:0] wb_dat_i; + input wb_we_i; + input wb_cyc_i; + input wb_stb_i; + input [2:0] wb_cti_i; + input [1:0] wb_bte_i; + output reg [wb_dat_width-1:0] wb_dat_o; // constantly sampling gpio in bus + output reg wb_ack_o; + output wb_err_o; + output wb_rty_o; + + inout [gpio_io_width-1:0] gpio_io; + + // Internal registers + reg [gpio_io_width-1:0] gpio_dir; + + reg [gpio_io_width-1:0] gpio_o; + + wire [gpio_io_width-1:0] gpio_i; + + // Tristate logic for IO + genvar i; + generate + for (i=0;i

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