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https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/rtl/verilog/clkgen
- from Rev 361 to Rev 362
- ↔ Reverse comparison
Rev 361 → Rev 362
/clkgen.v
91,9 → 91,8
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// An active-low synchronous reset signal (usually a PLL lock signal) |
wire sync_rst_n; |
assign sync_rst_n = async_rst_n; // Pretend it's somehow synchronous now |
|
// An active-low synchronous reset from ethernet PLL |
wire sync_eth_rst_n; |
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// Here we just assign "board" clock (really test) to wishbone clock |
assign wb_clk_o = clk_pad_i; |